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1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 1 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary document title 1mx36-bit, 2mx18-bit, 4mx8-bit ddrii cio b4 sram the attached data sheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to c hange the specifications. samsung electronics will evaluate and reply to your requests and questions on the parameters of this device. if you have any ques- tions, please contact the samsung branch office near your office, call or contact headquarters. revi sio n history rev. no. 0.0 0.1 0.2 0.3 0.4 0.5 remark advance preliminary preliminary preliminary preliminary preliminary history 1. initial document. 1. pin name change from dll to doff. 2. vddq range change from 1.5v to 1.5v~1.8v. 3. update jtag test conditions. 4. reserved pin for high density name change from nc to vss/sa 5. delete ac test condition about clock input timing reference level 6. delete clock description on page 2 and add hstl i/o comment 1. update current characteristics in dc electrical characteristics 2. change ac timing characteristics 3. update jtag instruction coding and diagrams 1. add ac electrical characteristics. 2. change ac timing characteristics. 3. change dc electrical characteristics(i sb1 ) 1. change the data setup/hold time. 2. change the access time.(tchqv, tchqx, etc.) 3. change the clock cycle time.(max value of tkhkh) 4. change the jtag instruction coding. 1. change the boundary scan exit order. 2. change the ac timing characteristics(-25, -20) 3. correct the overshoot and undershoot timing diagrams. draft date october, 22 200 1 december, 14 2001 july, 29. 2002 sep. 6. 2002 oct. 7. 2002 dec. 16, 2002
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 2 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary 1m x36-bit, 2mx18-bit, 4mx8-bit ddrii cio b4 sram features functional block diagram ? 1.8v+0.1v/-0.1v power supply. ? dll circuitry for wide output data valid window and future freguency scaling. ? i/o supply voltage 1.5v+0.1v/-0.1v for 1.5v i/o, 1.8v+0.1v/-0.1v for 1.8v i/o . ? pipelined, double-data rate operation. ? common data input/output bus . ? hstl i/o ? full data coherency, providing most current data. ? synchronous pipeline read with self timed late write. ? registered address, control and data input/output. ? ddr(double data rate) interface on read and write ports. ? fixed 4-bit burst for both read and write operation. ? clock-stop supports to reduce current. ? two input clocks(k and k ) for accurate ddr timing at clock rising edges only. ? two input clocks for output data(c and c ) to minimize clock-skew and flight-time mismatches. ? two echo clocks (cq and cq ) to enhance output data traceability. ? single address bus. ? byte write (x18, x36) and nybble(x8) write function. ? simple depth expansion with no data contention. ? programmable output impedance. ? jtag 1149.1 compatible test access port. ? 165fbga(11x15 ball aray fbga) with body size of 15x17mm organization part number cycle time access time unit x36 k7i323684m-fc25 4.0 0.45 ns k7i323684m-fc20 5.0 0.45 ns k7i323684m-fc16 6.0 0.50 ns k7i323684m-fc13 7.5 0.50 ns x18 k7i321884m-fc25 4.0 0.45 ns k7i321884m-fc20 5.0 0.45 ns k7i321884m-fc16 6.0 0.50 ns k7i321884m-fc13 7.5 0.50 ns x8 k7i320884m-fc25 4.0 0.45 ns k7i320884m-fc20 5.0 0.45 ns k7i320884m-fc16 6.0 0.50 ns K7I320884M-FC13 7.5 0.50 ns ld address r/ w c c add reg & burst logic data reg c lk gen ctrl logic 1mx36 (2mx18) memory array write driver k k bw x 4(or 2) dq select output control s e n s e a m p s w r i t e / r e a d d e c o d e o u t p u t r e g o u t p u t s e l e c t o u t p u t d r i v e r notes : 1. numbers in ( ) are for x18 device, x8 device also the same with appropriate adjustments of depth and width. 18 18 (or 19) 36 (or 18) 36 (or 18) 72 72 (echo clock out) cq, cq 36 (or 18) a0,a1 ddrii sram and double data rate comprise a new family of products developed by cypress, hitachi, idt, micron, nec and samsung te chnology. (or 19) (or 36) (or 36)
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 3 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary pin configurations (top view) k7i323684m(1mx36) notes : 1. * checked no connect(nc) pins are reserved for higher density address, i.e. 10a for 64mb, 2a for 128mb . 2. bw 0 controls write to dq0:dq8, bw 1 controls write to dq9:dq17, bw 2 controls write to dq18:dq26 and bw 3 controls write to dq27:dq35. 1 2 3 4 5 6 7 8 9 10 11 a cq v ss/ sa* sa r/ w bw 2 k bw 1 ld sa v ss/ sa* cq b nc dq27 dq18 sa bw 3 k bw 0 sa nc nc dq8 c nc nc dq28 v ss sa sa0 sa1 v ss nc dq17 dq7 d nc dq29 dq19 v ss v ss v ss v ss v ss nc nc dq16 e nc nc dq20 v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc dq32 v ddq v dd v ss v dd v ddq nc dq13 dq4 k nc nc dq23 v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc dq34 v ss v ss v ss v ss v ss nc dq11 dq1 n nc dq35 dq25 v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa c sa sa nc dq9 dq0 r tdo tck sa sa sa c sa sa sa tms tdi pin name notes: 1. c, c, k or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 3. not connected to chip pad internally. symbol pin numbers description note k, k 6b, 6a input clock c, c 6p, 6r input clock for output data 1 cq, cq 11a, 1a output echo clock doff 1h dll disable when low sa0,sa1 6c,7c burst count address inputs sa 3a,9a,4b,8b,5c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs dq0-35 2b,3b,11b,3c,10c,11c,2d,3d,11d,3e,10e,11e,2f,3f 11f,2g,3g,11g,3j,10j,11j,3k,10k,11k,2l,3l,11l 3m,10m,11m,2n,3n,11n,3p,10p,11p data inputs outputs r/ w 4a read, write control pin, read active when high ld 8a synchronous load pin, bus cycle sequence is to be defined when low bw 0 , bw 1, bw 2 , bw 3 7b,7a,5a,5b block write control pin,active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 2 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply ( 1.8 v ) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply ( 1.5v or 1.8v ) v ss 2a,10a,4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l, 4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 1b,9b,10b,1c,2c,9c,1d,9d,10d,1e,2e,9e, 1f,9f,10f,1g,9g,10g,1j,2j,9j,1k,2k,9k 1l,9l,10l,1m,2m,9m,1n,9n,10n,1p,2p,9p no connect 3
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 4 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary pin configurations (top view) k7i321884m(2mx18) notes: 1. * checked no connect(nc) pins are reserved for higher density address, i.e. 2a for 64mb. 2. bw 0 controls write to dq0:dq8 and bw 1 controls write to dq9:dq17. 1 2 3 4 5 6 7 8 9 10 11 a cq v ss/ sa* sa r/ w bw 1 k nc ld sa sa cq b nc dq9 nc sa nc k bw 0 sa nc nc dq8 c nc nc nc v ss sa sa0 sa1 v ss nc dq7 nc d nc nc dq10 v ss v ss v ss v ss v ss nc nc nc e nc nc dq11 v ddq v ss v ss v ss v ddq nc nc dq6 f nc dq12 nc v ddq v dd v ss v dd v ddq nc nc dq5 g nc nc dq13 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq4 nc k nc nc dq14 v ddq v dd v ss v dd v ddq nc nc dq3 l nc dq15 nc v ddq v ss v ss v ss v ddq nc nc dq2 m nc nc nc v ss v ss v ss v ss v ss nc dq1 nc n nc nc dq16 v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa c sa sa nc nc dq0 r tdo tck sa sa sa c sa sa sa tms tdi pin name notes: 1. c, c, k or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 3. not connected to chip pad internally. symbol pin numbers description note k, k 6b, 6a input clock c, c 6p, 6r input clock for output data 1 cq, cq 11a, 1a output echo clock doff 1h dll disable when low sa0,sa1 6c,7c burst count address inputs sa 3a,9a,10a,4b,8b,5c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs dq0-17 2b,11b,10c,3d,3e,11e,2f,11f,3g,10j,3k,11k,2l,11l 10m,3n,3p,11p data inputs outputs r/ w 4a read, write control pin, read active when high ld 8a synchronous load pin, bus cycle sequence is to be defined when low bw 0 , bw 1 7b, 5a block write control pin,active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 2 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply ( 1.8 v ) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply ( 1.5v or 1.8v ) v ss 2a,4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l,4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 7a,1b,3b,5b,9b,10b,1c,2c,3c,9c,11c,1d,2d,9d,10d,11d 1e,2e,9e,10e,1f,3f,9f,10f,1g,2g,9g,10g,11g 1j,2j,3j,9j,11j,1k,2k,9k,10k,1l,3l,9l,10l 1m,2m,3m,9m,11m,1n,2n,9n,10n,11n,1p,2p,9p,10p no connect 3
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 5 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary pin configurations (top view) k7i320884m(4mx8) notes: 1. * checked no connect(nc) pin is reserved for higher density address, i.e. 2a for 72mb. 2. nw 0 controls write to dq0:dq3 and nw 1 controls write to dq4:dq7. 1 2 3 4 5 6 7 8 9 10 11 a cq v ss/ sa* sa r/ w nw 1 k nc ld sa sa cq b nc nc nc sa nc k nw 0 sa nc nc dq3 c nc nc nc v ss sa nc sa v ss nc nc nc d nc nc nc v ss v ss v ss v ss v ss nc nc nc e nc nc dq4 v ddq v ss v ss v ss v ddq nc nc dq2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc nc dq5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc dq1 nc k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc dq6 nc v ddq v ss v ss v ss v ddq nc nc dq0 m nc nc nc v ss v ss v ss v ss v ss nc nc nc n nc nc nc v ss sa sa sa v ss nc nc nc p nc nc dq7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c sa sa sa tms tdi pin name notes: 1. c, c, k or k cannot be set to v ref voltage. 2. when zq pin is directly connected to v dd output impedance is set to minimum value and it cannot be connected to ground or left unconnected . 3. not connected to chip pad internally. 4. the x8 product does not permit random start address on the least significant address bit. symbol pin numbers description note k, k 6b, 6a input clock c, c 6p, 6r input clock for output data 1 cq, cq 11a, 1a output echo clock doff 1h dll disable when low sa 3a,9a,10a,4b,8b,5c,7c,5n-7n,4p,5p,7p,8p,3r-5r,7r-9r address inputs dq0-7 10j,11b,3e,11e,3g,2l,11l,3p data inputs outputs r/ w 4a read, write control pin, read active when high ld 8a synchronous load pin, bus cycle sequence is to be defined when low nw 0 , nw 1 7b, 5a nybble write control pin,active when low v ref 2h,10h input reference voltage zq 11h output driver impedance control input 2 v dd 5f,7f,5g,7g,5h,7h,5j,7j,5k,7k power supply ( 1.8 v ) v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply ( 1.5v or 1.8v ) v ss 2a,4c,8c,4d-8d,5e-7e,6f,6g,6h,6j,6k,5l-7l,4m-8m,4n,8n ground tms 10r jtag test mode select tdi 11r jtag test data input tck 2r jtag test clock tdo 1r jtag test data output nc 7a,1b,2b,3b,5b,9b,10b,1c,2c,3c,7c,9c,10c,11c 1d,2d,3d,9d,10d,11d,1e,2e,9e,10e,1f,2f,3f,9f,10f,11f 1g,2g,9g,10g,11g,1j,2j,3j,9j,11j,1k,2k,3k,9k,10k,11k 1l,3l,9l,10l,1m,2m,3m,9m,10m,11m,1n,2n,3n,9n,10n 11n,1p,2p,9p,10p,11p no connect 3
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 6 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary the k7i323684m,k7i321884m and k7i320884m are 37,748,736-bits ddr common i/o synchronous pipelined burst srams. they are organized as 1,048,576 words by 36bits for k7i323684m, 2,097,152 words by 18 bits for k7i321884m and 4,194,304 words by 8bits for k7i320884m. address, data inputs, and all control signals are synchronized to the input clock ( k or k ). normally data outputs are synchronized to output clocks ( c and c ), but when c and c are tied high, the data outputs are synchronized to the input clocks ( k and k ). read data are referenced to echo clock ( cq or cq ) outputs. read address and write address are registered on rising edges of the input k clocks. common address bus is used to access address both for read and write operations. the internal burst counter is fiexd to 4-bit sequential for both read and write operations. synchronous pipeline read and late write enable high speed operations. simple depth expansion is accomplished by using ld for port selection. byte write operation is supported with bw 0 and bw 1 ( bw 2 and bw 3) pins for x18 ( x36 ) device. nybble write operation is supported with nw 0 and nw 1 pins for x8 device. ieee 1149.1 serial boundary scan (jtag) simplifies monitoriing package pads attachment status with system. the k7i323684m,k7i321884m and k7i320884m are implemented with samsung's high performance 6t cmos technology and is available in 165pin fbga packages. multiple power and ground pins minimize ground bounce. general description read operations read cycles are initiated by initiating r/ w as high at the rising edge of the positive input clock k. address is presented and stored in the read address register synchronized with k clock. for 4-bit burst ddr operation, it will access four 36-bit, 18-bit or 8-bit data words with each read command. the first pipelined data is transfered out of the device triggered by c clock following next k clock rising edge. next burst data is triggered by the rising edge of following c clock rising edge. continuous read operations are initated with k clock rising edge. and pipelined data are transferred out of device on every rising edge of both c and c clocks. in case c and c tied to high, output data are triggered by k and k insted of c and c . when the ld is disabled after a read operation, the k7i323684m,k7i321884m and k7i320884m will first complete burst read operation before entering into deselect mode at the next k clock rising edge. then output drivers disabled automatically to high impedance state. e cho clock operation to assure the output tracibility, the sram provides the output echo clock, pair of compliment clock cq and cq , which are synchronized with internal data output. echo clocks run free during normal operation. the echo clock is triggered by internal output clock signal, and transfered to external through same structures as output driver.
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 7 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary write cycles are initiated by activating r/ w as low at the rising edge of the positive input clock k. address is presented and stored in the write address register synchronized with next k clock. for 4-bit burst ddr operation, it will write two 36-bit, 18-bit or 8-bit data words with each write command. the first "late writed" data is transfered and registered in to the device synchronous with next k clock rising edge. next burst data is transfered and registered synchronous with following k clock rising edge. continuous write operations are initated with k rising edge. and "late writed" data is presented to the device on every rising edge of both k and k clocks. when the ld is disabled, the k7i323684m,k7i321884m and k7i320884m will enter into deselect mode. the device disregards input data presented on the same cycle w disabled. the k7i323684m and k7i321884m support byte write operations. with activating bw 0 or bw 1 ( bw 2 or bw 3 ) in write cycle, only one byte of input data is presented. in k7i321884m, bw 0 controls write operation to d0:d8, bw 1 controls write operation to d9:d17. and in k7i323684m bw 2 controls write operation to d18:d26, bw 3 controls write operation to d27:d35. the the k7i320884m support nybble write operations. in k7i320884m, nw 0 controls write operation to d0:d3, nw 1 controls write operation to d4:d7. write operations programmable impedance output buffer operation single clock mode depth expansion the designer can program the sram's output buffer impedance by terminating the zq pin to v ss through a precision resistor(rq). the value of rq (within 15%) is five times the output impedance desired. for example, 250 w resistor will give an output impedance of 50 w . impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. in all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behav- ior in the sram. there are no power up requirements for the sram. however, to guarantee optimum output driver impedance after power up, the sram needs 1024 non-read cycles. k7i323684m, k7i321884m and k7i320884m can be operated with the single clock pair k and k , insted of c or c for output clocks. to operate these devices in single clock mode, c and c must be tied high during power up and must be maintained high during operation. after power up, this device can t change to or from single clock mode. system flight time and clock skew could not be compensated in this mode. each port can be selected and deselected independently with r/ w be shared among all srams and provide a new ld signal for each bank. before chip deselected, all read and write pending operations are completed. clock consideration k7i323684m, k7i321884m and k7i320884m utilize internal dll(delay-locked loops) for maximum output data valid window. it can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles. circuitry automatically resets the dll when absence of input clock is detected.
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 8 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary state diagram notes : 1. internal burst counter is fixed as 4-bit linear, i.e. when first address is a0+0, next internal burst address is a0+1. 2. "load" refers to read new address active status with ld =low, " load " refers to read new address inactive status with ld =high. 3. "read" refers to read active read status with r/ w =high, "write" refers to write active status with r/ w =low load load load load power-up nop load new address load read write dcount = 0 dcount = 2 dcount = 2 load read dcount = 1 always write dcount = 1 always increment read address increment write address ddr read dcount=dcount+1 ddr write dcount=dcount+1 linear burst sequence table burst sequence case 1 case 2 case 3 case 4 sa 1 sa 0 sa 1 sa 0 sa 1 sa 0 sa 1 sa 0 first address fourth address 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 1 0
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 9 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary write truth table (x18) notes: 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( - ). 3. assumes a write cycle was initiated. 4. this table illustates operation for x18 devices. x8 device operation is similar except that nw 0 controls d0:d3 and nw 0 controls d4:d7. k k bw 0 bw 1 operation - l l write all bytes ( k - ) - l l write all bytes ( k - ) - l h write byte 0 ( k - ) - l h write byte 0 ( k - ) - h l write byte 1 ( k - ) - h l write byte 1 ( k - ) - h h write nothing ( k - ) - h h write nothing ( k - ) write truth table (x36) notes: 1. x means "don t care". 2. all inputs in this table must meet setup and hold time around the rising edge of input clock k or k ( - ). 3. assumes a write cycle was initiated. k k bw 0 bw 1 bw 2 bw 3 operation - l l l l write all bytes ( k - ) - l l l l write all bytes ( k - ) - l h h h write byte 0 ( k - ) - l h h h write byte 0 ( k - ) - h l h h write byte 1 ( k - ) - h l h h write byte 1 ( k - ) - h h l l write byte 2 and byte 3 ( k - ) - h h l l write byte 2 and byte 3 ( k - ) - h h h h write nothing ( k - ) - h h h h write nothing ( k - ) truth tables synchronous truth table notes: 1. x means "don t care". 2. the rising edge of clock is symbolized by ( - ). k ld r/ w q operation q(a0) q(a1) q(a2) q(a3) stopped x x previous state previous state previous state previous state clock stop - h x high-z high-z high-z high-z no operation - l h q out at c (t+1) q out at c(t+2) q out at c (t+2) q out at c(t+3) read - l l din at k(t+1) din at k (t+1) din at k(t+2) din at k (t+2) write
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 10 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary absolute maximum ratings* *note: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stres s rating only and functional operation of the device at these or any other conditions above those indicated in the operati ng sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v ddq must not exceed v dd during normal operation. parameter symbol rating unit voltage on v dd supply relative to v ss v dd -0.5 to 2.9 v voltage on v ddq supply relative to v ss v ddq -0.5 to v dd v voltage on input pin relative to v ss v in -0.5 to v dd+ 0.3 v power dissipation p d tbd w storage temperature t stg -65 to 150 c operating temperature t opr 0 to 70 c storage temperature range under bias t bias -10 to 85 c dc electrical characteristics (v dd = 1.8 v 0.1v , t a =0 c to +70 c) notes: 1. minimum cycle. i out =0ma. 2. |i oh |=(v ddq /2)/(rq/5) for 175 w rq 350 w . 3. |i ol |=(v ddq /2)/(rq/5) for 175 w rq 350 w . 4. minimum impedance mode when zq pin is connected to v dd . 5. operating current is calculated with 50% read cycles and 50% write cycles. 6. standby current is only after all pending read and write burst opeactions are completed. 7. programmable impedance mode. 8. these are dc test criteria. dc design criteria is v ref 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 9. v il (min)dc= - 0.3v, v il (min)ac=-1.5v(pulse width 3ns). 10. v ih (max)dc= v ddq +0.3, v ih (max)ac= v ddq +0.85v(pulse width 3ns). parameter symbol test conditions min max unit notes input leakage current i il v dd =max ; v in =v ss to v ddq -2 +2 m a output leakage current i ol output disabled, -2 +2 m a operating current (x36): ddr i cc v dd =max , i out =0ma cycle time 3 t khkh min -25 - 620 ma 1,5 -20 - 520 -16 - 440 -13 360 operating current (x18): ddr i cc v dd =max , i out =0ma cycle time 3 t khkh min -25 - 560 ma 1,5 -20 - 470 -16 - 410 -13 - 350 operating current (x8): ddr i cc v dd =max , i out =0ma cycle time 3 t khkh min -25 - 540 ma 1,5 -20 - 450 -16 - 390 -13 350 standby current(nop): ddr i sb1 device deselected, i out =0ma, f=max, all inputs 0.2v or 3 v dd -0.2v -25 - 200 ma 1,6 -20 - 180 -16 - 160 -13 - 140 output high voltage v oh1 v ddq /2-0.12 v ddq /2+0.12 v 2,7 output low voltage v ol1 v ddq /2-0.12 v ddq /2+0.12 v 3,7 output high voltage v oh2 i oh =-1.0ma v ddq -0.2 v ddq v 4 output low voltage v ol2 i ol =1.0ma v ss 0.2 v 4 input low voltage v il -0.3 v ref -0.1 v 8,9 input high voltage v ih v ref +0.1 v ddq +0.3 v 8,10
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 11 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary note: for power-up, v ih v ddq +0.3v and v dd 1.7v and v ddq 1.4v t 200ms v ddq v il v ddq +0.5v 20% t khkh (min) v ss v ih v ss -0.5v 20% t khkh (min) undershoot timing overershoot timing operating conditions (0 c t a 70 c) parameter symbol min max unit supply voltage v dd 1.7 1.9 v v ddq 1.4 1.9 v reference voltage v ref 0.68 0.95 v ground v ss 0 0 v v dd q/2 50 w sram zo=50 w 0.75v v ref zq 250 w ac test output load ac test conditions note : parameters are tested with rq=250 w parameter symbol value unit core power supply voltage v dd 1.7~1.9 v output power supply voltage v ddq 1.4~1.9 v input high/low level v ih /v il 1.25/0.25 v input reference level v ref 0.75 v input rise/fall time t r /t f 0.3/0.3 ns output timing reference level v ddq /2 v ac electrical characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes: 1. this condition is for ac function test only, not for ac parameter test. 2. to maintain a valid level, the transitioning edge of the input must : a) sustain a constant slew rate from the current ac level through the target ac level, v il(ac) or v ih(ac) b) reach at least the target ac level c) after the ac target level is reached, continue to maintain at least the target dc level, v il(dc) or v ih(dc) parameter symbol min max unit notes input high voltage v ih (ac) v ref + 0.2 - v 1,2 input low voltage v il (ac) - v ref - 0.2 v 1,2 v ddq +0.25v v ss -0.25v
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 12 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary ac timing characteristics (v dd =1.8v 0.1v, t a =0 c to +70 c) notes : 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r , w , bw 0 , bw 1 and (nw 0 , nw 1 , for x8) and ( bw 2 , bw 3 , also for x36) 3. if c, c are tied high, k, k become the references for c, c timing parameters. 4. to avoid bus contention, at a given voltage and temperature tchqx 1 is bigger than tchqz. the specs as shown do not imply bus contention beacuse tchqx 1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9v) than tchqz, which is a max parameter(worst case at 70 c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 6. vdd slew rate must be less than 0.1v dc per 50 ns for dll lock retention. dll lock time begins once vdd and input clock are stable. 7. echo clock is very tightly controlled to data valid/data hold. by design, there is a 0.1 ns variation from echo clock to data. the data sheet parameters reflect tester guardbands and test setup variations. parameter symbol -25 -20 -16 -13 units notes min max min max min max min max clock clock cycle time (k, k , c, c ) t khkh 4.00 5.25 5.00 6.30 6.00 7.88 7.50 8.40 ns clock phase jitter (k, k , c, c ) t kc var 0.20 0.20 0.20 0.20 ns 5 clock high time (k, k , c, c ) t khkl 1.60 2.00 2.40 3.00 ns clock low time (k, k , c, c ) t klkh 1.60 2.00 2.40 3.00 ns clock to clock (k - ? k - , c - ? c - ) t kh k h 1.80 2.20 2.20 2.75 2.70 3.30 3.38 4.13 ns clock to data clock (k - ? c - , k -? c - ) t khch 0.00 1.80 0.00 2.30 0.00 2.80 0.00 3.55 ns dll lock time (k, c) t kc lock 1024 1024 1024 1024 cycle 6 k static to dll reset t kc reset 30 30 30 30 ns output times c, c high to output valid t chqv 0.45 0.45 0.50 0.50 ns 3 c, c high to output hold t chqx -0.45 -0.45 -0.50 -0.50 ns 3 c, c high to echo clock valid t chcqv 0.45 0.45 0.50 0.50 ns c, c high to echo clock hold t chcqx -0.45 -0.45 -0.50 -0.50 ns cq, cq high to output valid t cqhqv 0.30 0.35 0.40 0.40 ns 7 cq, cq high to output hold t cqhqx -0.30 -0.35 -0.40 -0.40 ns 7 c, high to output high-z t chqz 0.45 0.45 0.50 0.50 ns 3 c, high to output low-z t chqx1 -0.45 -0.45 -0.50 -0.50 ns 3 setup times address valid to k rising edge t avkh 0.50 0.60 0.70 0.70 ns control inputs valid to k rising edge t ivkh 0.50 0.60 0.70 0.70 ns 2 data-in valid to k, k rising edge t dvkh 0.35 0.40 0.50 0.50 ns hold times k rising edge to address hold t khax 0.50 0.60 0.70 0.70 ns k rising edge to control inputs hold t khix 0.50 0.60 0.70 0.70 ns k, k rising edge to data-in hold t khdx 0.35 0.40 0.50 0.50 ns
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 13 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary application inrormation thermal resistance note : junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounti ng site thermal impedance. t j =t a + p d x q ja prmeter symbol typ unit notes junction to ambient q ja tbd c /w junction to case q jc tbd c /w junction to pins q jb tbd c /w pin capacitance note : 1. parameters are tested with rq=250 w and v ddq =1.5v. 2. periodically sampled and not 100% tested. prmeter symbol testcondition typ max unit notes address control input capacitance c in v in =0v 4 5 pf input and output capacitance c out v out =0v 6 7 pf clock capacitance c clk - 5 6 pf 2mx18 sram#1 sa r/ w bw 0 dq 0-17 zq k c c sram#4 r vt r=50 w vt=v ref vt r r=250 w r=250 w bw 1 k sa r/ w ld 3 bw 0 dq 0-17 zq k c c bw 1 k dq address r/ w ld 0-3 bw 0-7 return clk source clk return clk source clk memory controller ld 0
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 14 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary nop k k sa t avkh t khax cq 1 2 3 4 5 6 7 8 10 12 11 ld cq dq read (burst of 4) (burst of 4) nop write (burst of 4) read 9 read (burst of 4) d 21 d 23 d 24 d 22 t ivkh t khch t chqv t chqx t dvkh t khdx t khkh undefined don t care a 1 note 1. q 01 refers to output from address a. q 02 refers to output from the next internal burst address following a, etc. 2. outputs are disabled(high-z) one clock cycle after a nop . 3. the second nop cycle is not necessary for correct device operation; however, at high clock frequencies, it may be required to prevent bus contention. t kh k h t klkh r/ w t khix q 01 q 02 q 03 q 04 q 11 q 12 q 13 q 14 c c a 0 a 2 a 3 q 31 q 32 q 33 nop t khkl t chqx 1 t cqhqx t cqhqv t khkh t khkl t klkh t kh k h t chqz t cqhqz t chcqh timing wave forms of read, write and nop (note3)
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 15 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port(tap). the package pads are monitored by the serial scan circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. internal data is not driven out of the sram under jtag control. in conformance with ieee 1149.1, the sram contains a tap controller, instruction reg- ister, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. it is possible to use this device without utilizing the tap. to disable the tap controll er without interfacing with normal operation of the sram, tck must be tied to v ss to preclude mid level input. tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. but they may also be tied to v dd through a resistor. tdo should be left unconnected. tap controller state diagram jtag block diagram sram core bypass reg. identification reg. instruction reg. control signals tap controller tdo tdi tms tck test logic reset run test idle 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 1 1 1 1 jtag instruction coding note : 1. places dqs in hi-z in order to sample all input data regardless of other sram inputs. this instruction is not ieee 1149.1 compliant. 2. places dqs in hi-z in order to sample all input data regardless of other sram inputs. 3. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 4. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when exiting the shift dr states. 5. sample instruction dose not places dqs in hi-z. 6. this instruction is reserved for future use. ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 1 0 0 1 idcode identification register 3 0 1 0 sample-z boundary scan register 2 0 1 1 reserved do not use 6 1 0 0 sample boundary scan register 5 1 0 1 reserved do not use 6 1 1 0 reserved do not use 6 1 1 1 bypass bypass register 4
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 16 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary id register definition note : part configuration /def=010 for 32mb, /wx=11 for x36, 10 for x18, 01 for x8 /t=1 for dll ver., 0 for non-dll ver. /q=1 for ddr, 0 for ddr /b=1 for 4bit burst, 0 for 2bit burst /s=1 for separat e i/o, 0 for common i/o part revision number (31:29) part configuration (28:12) samsung jedec code (11: 1) start bit(0) 1mx36 000 00def0wx0t0q0b0s0 00001001110 1 2mx18 000 00def0wx0t0q0b0s0 00001001110 1 4mx8 000 00def0wx0t0q0b0s0 00001001110 1 scan register definition part instruction register bypass register id register boundary scan 1mx36 3 bits 1 bit 32 bits 109 bits 2mx18 3 bits 1 bit 32 bits 109 bits 4mx8 3 bits 1 bit 32 bits 109 bits note : 1. nc pins are read as "x" ( i.e. don t care.) order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 10a 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 2a 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1h 85 1j 86 2j 87 3k 88 3j 89 2k 90 1k 91 2l 92 3l 93 1m 94 1l 95 3n 96 3m 97 1n 98 2m 99 3p 100 2n 101 2p 102 1p 103 3r 104 4r 105 4p 106 5p 107 5n 108 5r 109 internal order pin id 1 6r 2 6p 3 6n 4 7p 5 7n 6 7r 7 8r 8 8p 9 9r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e boundary scan exit order
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 17 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary jtag dc operating conditions note : 1. the input level of sram pin is to follow the sram dc specification . parameter symbol min typ max unit note power supply voltage v dd tbd tbd tbd v input high level v ih tbd - tbd v input low level v il tbd - tbd v output high voltage(i oh =-2ma) v oh tbd - tbd v output low voltage(i ol =2ma) v ol tbd - tbd v jtag timing diagram jtag ac characteristics parameter symbol min max unit note tck cycle time t chch tbd - ns tck high pulse width t chcl tbd - ns tck low pulse width t clch tbd - ns tms input setup time t mvch tbd - ns tms input hold time t chmx tbd - ns tdi input setup time t dvch tbd - ns tdi input hold time t chdx tbd - ns sram input setup time t svch tbd - ns sram input hold time t chsx tbd - ns clock low to output valid t clqv tbd tbd ns jtag ac test conditions note : 1. see sram ac test output load on page 11. parameter symbol min unit note input high/low level v ih /v il tbd v input rise/fall time tr/tf tbd ns input and output timing reference level tbd v 1 tck tms tdi pi t chch t mvch t chmx t chcl t clch t dvch t chdx t clqv tdo (sram) t svch t chsx
1mx36 & 2mx18 & 4mx8 ddrii cio b4 sram - 18 - rev 0.5 dec. 2002 k7i323684m k7i321884m k7i320884m preliminary 165 fbga package dimensions c side view 15mm x 17mm body, 1.0mm bump pitch, 11x15 ball array f b ? h g a bottom view top view b a d e e symbol value units note symbol value units note a 15 0.1 mm e 1.0 mm b 17 0.1 mm f 14.0 mm c 1.3 0.1 mm g 10.0 mm d 0.35 0.05 mm h 0.45 0.05 mm

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