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direct modulation/fast waveform generating, 13 ghz, fractional - n frequency synthesizer data sheet adf4159 rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. howev er, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or oth erwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com f eatures rf bandwidth to 13 ghz high and low speed fmcw r amp g eneration 25- bit fixed modulus allows sub hertz frequency resolution pfd f requencies up to 110 mhz normalized phase nois e floor of ?224 dbc/hz fsk and psk functions sawtooth, triangular , and para bolic waveform generation ramp superimposed with fsk ramp with 2 different sweep rates ramp d elay , frequency readback , and interrupt functions programmable phase control 2.7 v to 3. 45 v analog power supply 1.8 v digital power supply programmable charge pum p currents 3 - wire serial interface digital lock detect esd performance : 3000 v hbm, 1000 v cdm a pplications fmcw r adar s communications test equipment communication s in f rastructure g eneral d escription the adf4159 is a 13 ghz , fractional - n frequency synthesizer with modulation and both fast and slow waveform generation capability. the part use s a 25 - bit fixed modulus, allowing sub hertz frequency resolution . the adf4159 consists of a low noise digital phase frequency detector (pfd), a precision charge pump, and a programmable reference divider. the - - based fractional interpolator allow s programmable fractional - n division. the int and fra c registers define an overall n divider as n = int + (frac/2 25 ) . the adf4159 can be used to implement frequ ency shift keying (fsk) and phase shift keying (psk) modulation. f requency sweep modes are also available to generate various wav eforms in the frequency domain, for example, sawtooth and triangular wave - forms. the adf4159 features cycle slip reduction circuitry, which enables faster lock times without the need for modifications to the loop filter. control of all on - chip registe rs is via a simple 3 - wire inter face. the adf4159 operates with a n analog power supply in the range of 2.7 v to 3. 45 v and a digital power supply in the range of 1.6 2 v to 1.98 v . the device can be powered down when not in use. f unctional block diag ram lock detect cp data le 32-bit data register clk a g n d dv dd dgnd r div sd out n div dgnd c p g n d sdv dd dv dd av dd v p ce rf in a rf in b output mux muxout ? + high-z phase frequency detector adf4159 third-order fractional interpolator fraction value integer value charge pump tx data reference r set ref in 2 doubler 5-bit r counter 2 divider modulus 2 25 v alue n counter + ? sw2 sw1 sdgnd 10849-001 fast lock switch csr figure 1.
adf4159 data sheet rev. b | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 spec ifications ..................................................................................... 3 timing specifications .................................................................. 4 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 10 reference input section ............................................................. 10 rf input stage ............................................................................. 10 rf int divider ........................................................................... 10 25- bit fixed modulus ................................................................ 10 int, frac, and r counter relationship ................................ 10 r counter .................................................................................... 10 phase frequency detector (pfd) and ch arge pump ............ 11 muxout and lock detect ...................................................... 11 input shift register ..................................................................... 11 p rogram modes .......................................................................... 11 register maps .................................................................................. 12 frac/int register (r0) map .................................................. 14 l sb frac register (r1) map ................................................... 15 r divider register (r2) map .................................................... 16 function register (r3) map ...................................................... 18 clock register (r4) map ........................................................... 20 deviation register (r5) map .................................................... 21 step register (r6) map .............................................................. 22 delay register (r7) map ........................................................... 23 applications information .............................................................. 24 initialization sequence .............................................................. 24 rf synthesizer worked example ............................................. 24 reference doubler ...................................................................... 24 cycle slip reduction for faster lock times ........................... 24 modulation .................................................................................. 25 waveform generation ............................................................... 25 waveform deviations and timing ........................................... 26 single ramp burst ...................................................................... 26 single triangular burst .............................................................. 26 single sawtooth burst ................................................................ 26 sawtooth ramp ........................................................................... 26 triangular ramp ........................................................................ 26 fmcw radar ramp settings worked example ...................... 26 activating the ramp .................................................................. 27 other waveforms ....................................................................... 27 ramp complete signal to muxout ..................................... 30 interrupt modes and frequency readback ............................ 31 fast lo ck mode .......................................................................... 32 spur mechanisms ....................................................................... 33 filter design using adisimpll .............................................. 33 p cb design guidelines for the chip scale package .............. 33 application of the adf4159 in fmcw radar ........................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history 6/13 rev. a to rev. b change d pfd antiback lash pulse from 3 ns to 1 ns in phase frequency detector (pfd) and charge pump section ............. 1 1 c hanges to charge pump current setting section and reference doubler section ............................................................ 1 6 changes to negative bleed current enable section and loss of lock (lol) section ........................................................................ 1 8 5 /1 3 revision a : initial version
data sheet adf4159 rev. b | page 3 of 36 specifications av dd = v p = 2.7 v to 3. 45 v, dv dd = sdv dd = 1.8 v, agnd = dgnd = s dgnd = cp gnd = 0 v, f pfd = 110 mhz , t a = t min to t max , dbm referred to 50 ?, unless otherwise noted. table 1 . parameter 1 min typ max unit test conditions/comments rf characteristics rf input frequency (rf in ) 0.5 13 ghz ? 10 dbm min to 0 dbm max; for lower frequencies, ensure a slew rate 400 v/s prescaler output frequency 2 ghz for higher frequencies, use 8/9 prescaler reference characteristics ref in input frequency 10 260 mhz ? 5 dbm min to + 9 dbm max biased at 1.8/2 (ac coupling ensures 1.8/2 bias); for frequencies < 10 mhz, use a dc - coupled , cmos - compatible square wave with a slew rate > 25 v/s reference doubler enabled 10 5 0 mhz bit db20 in register r2 set to 1 ref in input capacitance 1.2 pf ref in input current 100 a phase frequency detector (pfd) phase detector frequency 2 110 mhz charge pump i cp sink/source current programmable high value 4. 8 ma r set = 5.1 k ? low value 300 a absolute accuracy 2.5 % r set = 5.1 k? r set range 4.59 5.1 5.61 k? i cp three - state leakage current 1 na sink and source current sink and source matching 2 % 0.5 v < v cp < v p ? 0.5 v i cp vs. v cp 2 % 0.5 v < v cp < v p ? 0.5 v i cp vs. temperature 2 % v cp = v p /2 logic inputs input high voltage, v inh 1.4 v input low voltage, v inl 0.4 v input current, i inh /i inl 1 a input capacitance, c in 10 pf logic outputs output high voltage, v oh d v dd ? 0.4 v cmos output selected output low voltage, v ol 0.3 v i ol = 500 a output high current, i oh 100 a power supplies av dd 2.7 3.45 v dv dd , sdv dd 1.62 1.8 1.98 v v p 2.7 3.45 v ai dd 26 40 ma supply current drawn by av dd ; f pfd = 110 mhz d i dd 7.5 10 ma supply current drawn by dv dd ; f pfd = 110 mhz i p 5.5 7 ma supply current drawn by v p ; f pfd = 110 mhz power - down mode 2 a
adf4159 data sheet rev. b | page 4 of 36 parameter 1 min typ max unit test conditions/comments noise characteristics normalized phase noise floor 3 pll loop bw = 1 mhz integer - n mode ? 224 dbc/hz frac = 0 fractional - n mode ? 217 dbc/hz normalized 1/f noise (pn 1_f ) 4 ? 120 dbc/hz measured at 10 khz offset, normalized to 1 ghz phase noise performance 5 at vco output 12, 002 mhz output 6 ? 96 dbc/hz at 50 khz offset, 100 mhz pfd frequency 1 operatin g temperature: ?40c to +125c. 2 guaranteed by design. sample tested to ensure compliance. 3 th is specification can be used to calculate phase noise for any application. use the formula ((normalized phase noise floor) + 10 log(f pfd ) + 20 logn ) to calculate in - band phase noise performance as seen at the vco output. 4 the pll phase noise is composed of flicker ( 1/f) noise plus the normalized pll noise floor. the formula for calculating the 1/f noise contribution at an rf frequency (f rf ) and at an offset frequency (f) is given by pn = pn 1_f + 10 log(10 khz/f) + 20 log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll . 5 the phas e noise is measured with the ev - adf4159eb 3 z and the rohde & schwarz fsup signal source ana lyzer. 6 f refin = 100 mhz; f pfd = 100 mhz; offset frequency = 50 khz; rf out = 12, 002 mhz; n = 120.02 ; loop bandwidth = 250 khz . timing specification s av dd = v p = 2.7 v to 3. 45 v , dv dd = sdv dd = 1.8 v , agnd = dgnd = sdgnd = cpgnd = 0 v , t a = t min to t max , dbm referred to 50 ?, unless otherwise noted . table 2 . write timing parameter limit at t min to t max unit description t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width write timing diagram clk data le le db30 db1 (control bit c2) db2 (control bit c3) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 4 t 5 t 7 t 6 10849-002 db31 (msb) figure 2. write timing diagram
data sheet adf4159 rev. b | page 5 of 36 table 3 . read timing parameter limit at t min to t max unit description t 1 1 t pfd + 20 ns min tx data setup time t 2 2 0 ns min c lk setup time to data (on m uxout) t 3 25 ns min clk high duration t 4 25 ns min clk low duration t 5 10 ns min clk to le setup time 1 t pfd is the period of the pfd frequency; for example, if the pfd frequency is 50 mhz, t pfd = 20 ns. read timing diagram clk t 4 t 3 muxout db36 db35 db1 db2 db0 tx data t 1 t 2 le t 5 notes 1. le should be kept high during readback. 10849-003 figure 3. read timing diagram to muxout pin c l 10pf 500a i ol 100a i oh 0.9v 10849-004 figure 4 . load circuit for muxout timing , c l = 10 pf
adf4159 data sheet rev. b | page 6 of 36 absolute maximum rat ings t a = 25c, gnd = agnd = dgnd = sdgnd = cpgnd = 0 v, unless otherwise noted. table 4 . parameter rating a v dd to gnd ? 0.3 v to +3. 9 v d v dd to gnd ? 0.3 v to + 2 . 4 v v p to gnd ? 0.3 v to +3.9 v v p to av dd ? 0.3 v to +0 . 3 v digital i/o voltage to gnd ? 0.3 v to d v dd + 0.3 v analog i/o voltage to gnd ? 0.3 v to a v dd + 0.3 v ref in to gnd ? 0.3 v to d v dd + 0.3 v rf in to gnd ? 0.3 v to a v dd + 0.3 v operating temperature range , industrial ? 40c to +125c storage temperature range ? 65c to +125c maximum junction temperature 150c reflow soldering peak temperature 260c time at peak temperature 40 sec esd charged device model 1000 v human body model 3000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those ind icated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance thermal impedance ( ja ) is specified for a device with the exposed pad soldered to agnd. table 5 . thermal resistance package type ja unit 24- lead lfcsp _wq 30.4 c/w esd caution
data sheet adf4159 rev. b | page 7 of 36 pin configuration and fu nction descriptions cpgnd notes 1. the lfcsp has an exposed pad that must be connected to agnd. 2 1 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 8 9 1 0 1 1 7 1 2 2 0 1 9 2 1 2 2 2 3 2 4 adf4159 top view (not to scale) agnd agnd rf in b rf in a av dd av dd av dd ref in dgnd sdgnd tx data sdv dd muxout le data clk ce cp r set v p sw2 sw1 dv dd 10849-005 figure 5. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 cpgnd charge pump ground. this pin is the ground return path for the charge pump. 2, 3 agnd analog ground. 4 rf in b complementary input to the rf prescale r. decouple this pin to the ground plane with a small bypass capacitor, typically 100 pf. 5 rf in a input to the rf prescaler. this small signal input is normally ac-coupled from the vco. 6, 7, 8 av dd positive power supply for the rf section. place decoupling capacitors to the ground plane as close as possible to these pins. 9 ref in reference input. this cmos input has a nominal threshold of dv dd /2 and an equivalent inp ut resistance of 100 k. it can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 10 dgnd digital ground. 11 sdgnd digital - modulator ground. this pin is the ground return path for the - modulator. 12 tx data transmit data pin. this pin provides the data to be transmitted in fsk or psk mode and also controls some ramping functionality. 13 ce chip enable (1.8 v logic). a logic low on this pin pow ers down the device and places the charge pump output into three-state mode. 14 clk serial clock input. this input is used to clock in the serial data to the registers. the data is latched into the input shift register on the clk rising edge. this input is a high impedance cmos input. 15 data serial data input. the serial data is loaded msb first; the three lsbs are the control bits. this input is a high impedance cmos input. 16 le load enable input. when le is high, the data stored in the input shift register is loaded into one of the eight latches; the latch is selected using the control bi ts. this input is a high impedance cmos input. 17 muxout multiplexer output. this pin allows various internal signals to be accessed externally. 18 sdv dd power supply for the digital - modulator. place decoup ling capacitors to the ground plane as close as possible to this pin. 19 dv dd positive power supply for the digital section. place deco upling capacitors to the di gital ground plane as close as possible to this pin. 20, 21 sw1, sw2 switches for fast lock. 22 v p charge pump power supply. the voltage on th is pin must be greater than or equal to av dd . 23 r set connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is as follows: i cp_max = 24.48/ r set where: i cp_max = 4.8 ma. r set = 5.1 k. 24 cp charge pump output. when the charge pu mp is enabled, this output provides i cp to the external loop filter, which, in turn, drives the external vco. 25 epad exposed pad. the lfcsp has an expo sed pad that must be connected to agnd.
adf4159 data sheet rev. b | page 8 of 36 typi cal performance char acteristics ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) frequenc y offset (hz) 10849-106 figure 6. phase noise at 12.002 ghz, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, bleed current = 11. 03 a 1 1.98 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 50 100 150 200 frequenc y (ghz) time (s) 10849-107 figure 7. sawtooth ramp, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3, clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64 1 1.98 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 50 100 150 200 frequenc y (ghz) time (s) 10849-108 figure 8. sawtooth ramp with delay, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3, clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64, delay word = 1000 1 1.98 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 20 40 60 80 100 frequenc y (ghz) time (s) 10849-109 figure 9. sawtooth burst, f pfd = 100 mhz, i cp = 2. 5 ma, loop bandwidth = 250 khz, clk 1 = 3, clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64 1 1.98 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 100 200 300 400 500 frequenc y (ghz) time (s) 10849- 1 10 figure 10 . dual sawtooth ramp, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3; first ramp: clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64; second ramp: clk 2 = 52, dev = 1024, dev_offset = 7 , number of st eps = 64 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 100 200 300 400 500 frequenc y (ghz) time (s) 10849- 11 1 figure 11 . triangle ramp, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3, clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64
data sheet adf4159 rev. b | page 9 of 36 1 1.99 12.00 12.01 12.02 12.03 12.04 12.05 12.06 0 50 100 150 200 frequenc y (ghz) time (s) 10849- 1 12 figure 12 . fast ramp (triangle ramp with different slopes), f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3; up ramp: clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64; down ramp: clk 2 = 70, dev = 16 , 384, dev_offset = 8, number of steps = 4 ?200 ?150 ?100 ?50 0 50 100 150 200 0 50 100 150 200 phase (degrees) time (s) 10849- 1 13 figure 13 . phase shift keying (psk) , loop bandwidth = 250 khz, phase value = 1024, data rate = 20 khz 1 1.996 1 1.997 1 1.998 1 1.999 12.000 12.001 12.002 12.003 12.004 0 50 100 150 200 frequenc y (ghz) time (s) 10849- 1 14 figure 14 . frequency shift keying (fsk) , loop bandwidth = 250 khz, dev = 1049, dev_offset = 9, data rate = 20 khz 1 1.994 1 1.996 1 1.998 12.000 12.002 12.004 12.006 12.008 12.010 12.012 12.014 0 100 200 300 400 500 frequenc y (ghz) time (s) 10849- 1 15 figure 15 . fsk ramp, f pfd = 100 mhz, i cp = 2.5 ma, loop bandwidth = 250 khz, clk 1 = 3, clk 2 = 26, dev = 1024, dev_offset = 8, number of steps = 64; fsk: dev = ? 512, dev_offset = 8 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 5 10 15 20 rf sensitivit y (dbm) frequenc y (ghz) prescaler 8/9 prescaler 4/5 10849- 1 16 figure 16 . rf in sensitivity at nominal temperature ?6 ?4 ?2 0 2 4 6 0 0.5 1.0 1.5 2.0 2.5 3.0 i cp (ma) v cp (v) 10849- 1 17 figure 17 . charge pump output characteristics
adf4159 data sheet rev. b | page 10 of 36 theory of operation reference input sect ion figure 18 shows the reference input stage. the sw1 and sw2 switches are normally closed (nc in figure 18 ) . the sw3 switch is normally open (no in figure 18). when power - down is initiated, sw3 is closed , and sw1 and sw2 are opened. in this way, no loading of the ref in pin occurs during power - down. bu ff er t o r c o un t er r ef i n 100 k ? n c s w 2 s w 3 n o n c s w 1 p o w e r - d o w n c o n t r o l 10849-013 figure 18 . reference input stage rf input stage figur e 19 shows the rf input stage. the input stage is followed by a two - stage limiting amplifier to generate the current - mode logic (cml) clock levels required for the prescaler. b i a s g e n er a t o r 1 . 6 v a g n d a v d d 2k ? 2k ? r f i n b r f i n a 10849-014 figure 19 . rf input stage rf int divider the rf int c mos divider allows a division ratio in the pll feedback counter. division ratios from 23 to 4095 are allowed. t h i rd - o rd er f rac t io n a l i n t e r p o l a t o r f ra c v a l u e m o d value i n t value r f int d i v i d er n = i n t + f rac / m o d f r o m r f i n p u t s t a g e t o p f d n c o un t er 10849-015 figure 20 . rf int divider 25- bit fixed modulus the adf4159 ha s a 25 - bit fixed modulus. this modulus allows output frequencies to be spaced with a resolution of f res = f pfd /2 25 (1) where f pfd is the frequency of the phase frequency detector (pfd). for example, with a pfd frequency of 10 0 mhz, frequency steps of 2 .98 hz are possible. int, frac , and r counter relationship the int and frac values , in conjunction with the r counter , make it possible to generate output frequencies that are spaced by fractions of the pfd frequency . the rf vco frequency (rf out ) equation is rf out = ( int + ( frac /2 25 )) f pfd (2) where: rf out is the output frequency of the external voltage controlled oscillator (vco). int is the preset divide ratio of the binary 12 - bit counter (23 to 4095). frac is the numerator of the fractional division ( 0 to ( 2 25 ? 1 ) ). the pfd frequency (f pfd ) equation is f pfd = ref in [(1 + d )/( r (1 + t ))] (3) where: ref in is the reference input frequency. d is the ref in doubler bit (0 or 1). r is the preset divide ratio of the binary 5 - bit programmable reference (r) counter (1 to 32). t is the ref in divide - by - 2 bit (0 or 1). r counter the 5 - bit r counter allows the input reference frequency (ref in ) to be divided down to supply the reference clock to the pfd. division ratios from 1 to 32 are allowed.
data sheet adf4159 rev. b | page 11 of 36 phase frequency dete ctor (pfd) and charge pump the pfd takes inputs from the r counter and n counter and produces an output proportional to the phase and frequency difference between them. figure 21 s hows a simplified sche - matic of the pfd . u 3 c l r 2 q 2 d 2 u 2 d o w n u p h ig h h ig h c p ? i n + i n char g e p u m p d el a y c l r 1 q 1 d 1 u 1 10849-016 figure 21 . pfd simplified schematic the pfd includes a fixed delay element that sets the width of the antiback lash pulse, which is typically 1 ns. this pulse ensures that there is no dead zone in the pfd transfer function and g ives a consistent reference spur level. m uxout and lock detect the multiplexer output on the adf4159 allows the user to access various internal points on the chip. the state of muxout is controlled by the m4, m3, m2, and m1 bits in register r0 (see figure 25 ). figure 22 shows the muxout section in block diagram form. muxout t hr ee-s t a t e o u t p u t n divider output dgnd dgnd r divider output digi t al lock detect readback t o muxout clk divider output seria l d at a output r divider/2 n divider/2 contro l mux 10849-017 dv dd dv dd figure 22 . muxout schem atic input shift register the adf4159 digita l section includes a 5 - bit r counter, a 12 - bit int counter, and a 25 - bit frac counter. data is clocked into the 32- bit input shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the input shift register to one of eight la tches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2, and c1) in the input shif t register. as shown in figure 2 , t he control bits are the three lsbs ( db2, db1, and db0 , respectively). table 7 shows t he truth table for these bits . figure 23 and figure 24 provide a summary of how the latches are programmed. table 7 . truth table for the c3, c2, and c1 control bits control bits register c3 c2 c1 0 0 0 r0 0 0 1 r1 0 1 0 r2 0 1 1 r3 1 0 0 r4 1 0 1 r5 1 1 0 r6 1 1 1 r7 program modes table 7 and figure 25 through figure 32 show how the program modes are set up in the adf4159 . the following settings in the adf4159 are double buffered: lsb fractional value, phas e value, charge pump current setting, reference divide - by - 2 , reference doubler, r counter value, and clk 1 divider value . before the part uses a new value for any double - buffered setting, the following two events must occur: 1. the new value is latched into th e device by writing to the appropriate register. 2. a new write is performed to register 0 ( r0 ) . for example, updating the fractional value involve s a write to the 13 lsb bits in r1 and the 12 msb bits in r0. r1 must be written to first, followed by the write to r0. the frequency change begin s after the write to r0. double - buffering ensures that the bits written to r1 do not take effect until after the write to r0.
adf4159 data sheet rev. b | page 12 of 36 register maps d b 3 1 control bits 12-bit msb fractional value (frac) 13-bit lsb fractional value (frac) 12-bit integer value (int) muxout control d b 3 0 d d b 2 9 b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 r 1 m 4 m 3 m 2 m 1 n 1 2 n 1 1 n 1 0 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 f 2 5 f 2 4 f 2 3 f 2 2 f 2 1 f 2 0 f 1 9 f 1 8 f 1 7 f 1 6 f 1 5 f 1 4 c 3 ( 0 ) c 2 ( 0 ) c 1 ( 0 ) ramp on frac/int register (r0) d b 3 1 12-bit phase value reserved d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 p1 f 1 3 f 1 2 f 1 1 f 1 0 f 9 f 8 f 7 f 6 f 5 f 4 f 3 f 2 f 1 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 c 3 ( 0 ) c 2 ( 0 ) c 1 ( 1 ) lsb frac register (r1) d b 3 1 reserved neg bleed current power-down pd polarity ldp psk counter reset cp three-state d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 0 0 0 0 nb3 nb2 nb1 0 0 0 0 1 l 1 n s 1 u 1 2 0 0 0 0 r m 2 r m 1 u 1 1 u 1 0 u 9 u 8 u 7 c 3 ( 0 ) c 2 ( 1 ) c 1 ( 1 ) function register (r3) d b 3 1 5-bit r counter reserved reserved phase adjust prescaler csr rdiv2 dbb d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 cr1 c p i 4 c p i 3 c p i 2 c p i 1 0 p 1 u 2 u 1 r 5 r 4 r 3 r 2 r 1 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 c 3 ( 0 ) c 2 ( 1 ) c 1 ( 0 ) r divider register (r2) dbb dbb dbb dbb dbb sd reset ramp mode reserved rese r ved rese r ved neg bleed enable fsk n sel lol notes 1. dbb = double-buffered bits. control bits control bits control bits 12-bit clk 1 divider value cp current setting reference doubler dbb 10849-018 figure 23 . register summary 1
data sheet adf4159 rev. b | page 13 of 36 reserved d b 3 1 20-bit step word d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 0 0 0 0 0 s s e 1 s 2 0 s 1 9 s 1 8 s 1 7 s 1 6 s 1 5 s 1 4 s 1 3 s 1 2 s 1 1 s 1 0 s 9 s 8 s 7 s 6 s 5 s 4 s 3 s 2 s 1 c 3 ( 1 ) c 2 ( 1 ) c 1 ( 0 ) step register (r6) d b 3 1 12-bit delay start word ramp delay fl d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 0 0 0 0 0 0 0 t d 1 s t 1 t r 1 f r 1 r d 1 d c 1 d s e 1 d s 1 2 d s 1 1 d s 1 0 d s 9 d s 8 d s 7 d s 6 d s 5 d s 4 d s 3 d s 2 d s 1 c 3 ( 1 ) c 2 ( 1 ) c 1 ( 1 ) delay register (r7) reserved del start en del clk sel ramp delay fast ramp tx data trigger tx data trigger delay sing full tri tri delay reserved reserved reserved d b 3 1 12-bit clk 2 divider value d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 l s 1 0 0 0 0 0 r5 r4 r3 r2 r1 c2 c1 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 0 ) clock register (r4) clk div mode c s 1 0 0 0 d b 3 1 16-bit deviation word d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 0 0 t r 1 i 2 i 1 d s 1 d o 4 d o 3 d o 2 d o 1 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 1 ) deviation register (r5) d 4 d 3 d 2 d 1 4-bit deviation offset word dev sel step sel interrupt tx ramp clk tx dat a invert parabolic ramp dual ramp fsk ramp le sel clk div sel control bits control bits control bits control bits control bits notes 1. dbb = double-buffered bits. 10849-019 ramp status figure 24 . register summary 2
adf4159 data sheet rev. b | page 14 of 36 frac/int register (r 0) map when bits db[2:0] are set to 000 , the on - chip frac/int register (register r 0 ) is programmed (see figure 25). ramp o n when bit db31 is set to 1 , th e ramp function is enabled . when bit db31 is set to 0, the ramp function is disabled . muxout control the on - chip multiplexer o f the adf4159 is controlled by bits db[30:27] . see figure 25 for the truth table. 12- bit integer value (int) bits db[26:15] set the int value , which forms part of the overall feedback division factor. for more information , s ee the int, f rac, and r counter relationship section . 12- bit msb fractional value (frac) bits db[14:3] , along with bits db[27:15] in the lsb frac register ( register r1), set the frac value that is loaded into the fractional interpolator. th e frac value forms part of the overa ll feedback division factor. these 12 bits are the most significant bits (msb s) of the 25 - bit frac value; bits db[27:15] in the lsb frac register ( register r1) are the least significant bits (lsb s ). for more infor - mation, s ee the rf synthesizer worked example section. db31 control bits 12-bit msb fractional value (frac) 12-bit integer value (int) muxout control db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r1 m4 m3 m2 m1 n12 n11 n10 n9 n8 n7 n6 n5 n4 n3 n2 n1 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 f15 f14 c3(0) c2(0) c1(0) ramp on m 4 m 3 m 2 m 1 output 0 0 0 0 t hr ee - s t a te o u t p u t 0 0 0 1 d v dd 0 0 1 0 d gn d 0 0 1 1 r di v i d e r out p u t 0 1 0 0 n di v i d e r out p u t 0 1 0 1 reserved 0 1 1 0 digi t a l lock detect 0 1 1 1 ser i a l d a t a out p ut 1 0 0 0 r ese r ve d 1 0 0 1 r ese r ve d 1 0 1 0 clk di v i d e r output 1 0 1 1 r ese r ve d 1 1 0 0 reserved 1 1 0 1 r d iv i d e r /2 1 1 1 0 n d iv i d e r /2 1 1 1 1 r eadback to muxout r1 ramp on 0 ramp disabled ramp enabled 1 f25 f24 ... f15 f14 msb fractional value (frac)* 0 1 2 3 . . . 4092 4093 4094 4095 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 n 12 n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 integer v a lue ( i nt) 0 0 0 0 0 0 0 1 0 1 1 1 23 0 0 0 0 0 0 0 1 1 0 0 0 24 0 0 0 0 0 0 0 1 1 0 0 1 25 0 0 0 0 0 0 0 1 1 0 1 0 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 1 1 1 1 1 1 1 0 1 40 9 3 1 1 1 1 1 1 1 1 1 1 1 0 40 9 4 1 1 1 1 1 1 1 1 1 1 1 1 40 9 5 *the frac value is made up of the 12-bit msb stored in register r0 and the 13-bit lsb stored in register r1. frac value = 13-bit lsb + 12-bit msb 2 13 . 10849-020 figure 25 . frac/int register (r0) map
data sheet adf4159 rev. b | page 15 of 36 lsb frac register (r 1) map when bits db[2:0] are set to 001 , the on - chip lsb frac register (register r 1 ) is programmed (see figure 26). reserved bits all reserved bits must be set to 0 for normal operation. phase adj ust ment b it db28 enables and disables phase adjustment. the p hase shift is generated by the value programmed in bits db[14:3]. 13- bit lsb fractional value (frac) bits db[27:15] , alo ng with bits db[14:3] in the frac /int register ( register r0), set the frac value that is loaded into the fractional interpolator. th e frac value forms part of the overall feedback division factor . these 13 bits are the least significant bits (lsb s) of the 25 - bit frac value ; bits db[14:3] in the frac/int register are the most significant bits (msb s ) . for more information , s ee the rf synthesizer worked example secti on. 12- bit phase value bits db[14:3] control the p hase word. the phase word is used to increase the rf output phase relative to the current phase. the phase change occurs after a write to register r0. phase shift = ( phase value 360)/2 12 for example, pha se value = 512 increase s the phase by 45. to us e p hase a djust ment , bit db28 must be set to 1 . if p hase a djustment is not used, it is recommended that the p hase v alue be set to 0. db31 control bits 12-bit phase value 13-bit lsb fractional value (frac) reserved db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 p1 f13 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 c3(0) c2(0) c1(1) p12 p 1 1 ... p2 p1 phase value 0 1 ... 1 1 2047 . . ... . . . 0 0 ... 1 1 3 0 0 ... 1 0 2 0 0 ... 0 1 1 0 0 ... 0 0 0 (recommended) 1 1 ... 1 1 ?1 1 1 ... 1 0 ?2 1 1 ... 0 1 ?3 . . ... . . . 1 0 ... 0 0 ?2048 *the frac value is made up of the 12-bit msb stored in register r0 and the 13-bit lsb stored in register r1. frac value = 13-bit lsb + 12-bit msb 2 13 . dbb dbb notes 1. dbb = double-buffered bits. 10849-021 phase adj p1 phase adj 0 di s a bl e d 1 en a b le d f13 f12 ... f2 f1 lsb fractional value (frac)* 0 1 2 3 . . . 8188 8189 8190 8191 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 figure 26 . lsb frac register (r1) map
adf4159 data sheet rev. b | page 16 of 36 r div ider register (r2) m ap when bits db[2:0] are set to 010 , the on - chip r divider register (register r 2 ) is programmed (see figure 27). reserved bits all reserved bits must be set to 0 for normal operation. csr enable when bit db28 is set to 1, cycle slip reduction (csr) is enabled . c ycle slip reduction is a method for improving lock times. note that the signal at the pfd must have a 50% duty cycle for cycle slip reduction to work. in addition, the charge pump current setting must be set to its minimum value . for more information, s ee the cycle slip reduction for faster lock times section. t he cycle slip reduction feature can be used only when the phase detector polarity setting is positive ( bit db6 = 1 in register r3). csr cannot be used if the phase detector polarity setting is nega - tive (bit db6 = 0 in register r3) . charge pump current setting bits db[27 :2 4 ] set the charge pump current (see figure 27 ). s et these bits to the charge pump current that th e loop filter is designed with. best practice is to design the loop filter for a charge pump current of 2.5 ma or 2.81 ma and then use the programmable charge pump current to tweak the fr equency response. see the reference doubler section for information on setting the charge pump current when the doubler is enabled. prescaler (p/p + 1) the dual - modulus prescaler (p/p + 1), a long with the int, frac, and fixed modu lus values , determine s the overall division ratio from rf in to the pfd input. bit db22 set s the prescaler value. operating at cml levels, the prescaler takes the clock from the rf input stage and divides it down for the counters. the prescaler is based on a synchronous 4/5 core. when the prescaler is set to 4/5, the m aximum rf frequency allowed is 8 ghz. therefore, when operating the adf4159 at frequencies greater than 8 ghz, the prescaler must be set to 8/9. the prescaler limits the int value as follows: ? prescaler = 4/5: n min = 23 ? prescaler = 8/9 : n min = 75 rdiv2 when bit db 2 1 is set to 1 , a divide - by - 2 toggle flip - flop is inserted between the r counter and the pfd. this feature can be used to provid e a 50% duty cy cle signal at the pfd. reference doubler when bit db 20 is set to 0 , the reference doubler is disabled, and the ref in si gnal is fed directly to the 5 - bit r counter . when bit db20 is set to 1 , the reference doubler is enabled, and the ref in f requency is multipl ied by a factor of 2 before the signal is fed into the 5 - bit r counter . when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edge s of ref in become active edges at the pfd input . when the reference doubler is enabled, for optimum phase noise performance, it is recommended to only use charge pump current settings 0b0000 to 0b0111, that is, 0.31 ma to 2.5 ma. in this ca se, best practice is to design the loop filter to for a charge pump current of 1.25 ma or 1.57 ma and then use the programmable charge pump current to tweak the frequency response. 5 - bit r counter the 5 - bit r counter (bits db[19:15]) allows the input refer ence frequency (ref in ) to be divided down to supply the reference clock to the pfd. division ratios from 1 to 32 are allowed. 12- bit clk 1 divider value bits db[14:3] program the clk 1 divider value , which determines the duration of the time step in ramp mod e.
data sheet adf4159 rev. b | page 17 of 36 db31 12-bit clk 1 divider value 5-bit r counter reserved reserved csr prescaler cp current setting control bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 cr1 cpi4 cpi3 cpi2 cpi1 0 p1 u2 u1 r5 r4 r3 r2 r1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(0) u 1 reference doubler 0 di s a bl e d 1 en a b le d cr1 cycle slip reduction 0 di s a bl e d 1 en a b le d r 5 r 4 r 3 r 2 r 1 r count e r di vi de r a tio 0 0 0 0 1 1 0 0 0 1 0 2 0 0 0 1 1 3 0 0 1 0 0 4 . . . . . . . . . . . . . . . 1 1 1 0 1 2 9 1 1 1 1 0 3 0 1 1 1 1 1 3 1 0 0 0 0 0 3 2 u 2 r divi d er 0 di s a bl e d 1 en a b le d p1 p r esc a le r 0 4/5 1 8/9 i cp ( m a ) cp i4 cp i3 cp i2 cp i1 5.1 k ? 0 0 0 0 0.3 1 0 0 0 1 0.6 3 0 0 1 0 0.9 4 0 0 1 1 1.2 5 0 1 0 0 1.5 7 0 1 0 1 1.8 8 0 1 1 0 2.1 9 0 1 1 1 2.5 1 0 0 0 2.8 1 1 0 0 1 3.1 3 1 0 1 0 3.4 4 1 0 1 1 3.7 5 1 1 0 0 4.0 6 1 1 0 1 4.3 8 1 1 1 0 4.6 9 1 1 1 1 5.0 dbb dbb dbb rdiv2 dbb reference doubler dbb d12 d11 ... d2 d1 0 0 0 0 . . . 1 1 1 1 0 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... 0 0 1 1 . . . 0 0 1 1 0 1 0 1 . . . 0 1 0 1 0 1 2 3 . . . 4092 4093 4094 4095 notes 1. dbb = double-buffered bits. clk 1 divider value 10849-022 figure 27 . r divider register (r2) map
adf4159 data sheet rev. b | page 18 of 36 function register (r 3) map when bits db[2:0] are set to 01 1, the on - chip function register (register r 3 ) is programmed (see figure 28). res erved bits all reserved bits except bit db17 must be set to 0 for normal operation. bit db17 must be set to 1 for normal operation. negative bleed current bits db[24:22] set the negative bleed current value (i bleed ). calculate i bleed using the following fo rmula , and then select the value of bits db[24:22] that is closest to the calculated value. i bleed = (4 i cp )/ n where: i cp is the charge pump current . n is the n counter value. negative bleed current enable db21 enables a negative bleed current in the cha rge pump. when the charge pump is operating in a nonlinear region, phase noise and spurious performance can degrade. negative bleed current operates by pushing the charge pump operation region away from this nonlinear region. the programmability feature co ntrols how far the region of operation is moved. if the current is too little, the charge pump will remain in the non - linear region; if the current is too high, the charge pump will become unstable or degrade the maximum pfd frequency. it is necessary to experiment with various charge pump currents to find the optimum. the formula for calculating the optimum negative bleed current is shown in the negative bleed current section; however, exper - imentation may show a different curren t gives the optimum result. loss of lock (lol) bit db16 enables or disables the loss of lock indication. when this bit is set to 0 (loss of lock enabled), the part indicates loss of lock even when the reference is remov ed. t his feature provides an advantag e over the standard implementation of lock detect. the loss of lock feature may not operate as expected when negative bleed current is enabled. n sel bit db15 can be used to circumvent the issue of pipeline dela y between update s of the integer and fraction al values in the n c ounter. typically, the int value is loaded first, followed by the frac value. this can cause the n counter value to be incor - rect for a brief period of time equal to the pipeline delay (about four pfd cycles ) . this delay has no effect i f the int value was not updated. however , if the int value has changed , this incorrect n counter value can cause the pll to overshoot in frequency while it tries to lock to the temporarily incorrect n counter value . after the correct fractional value is lo aded, the pll quickly lock s to the correct frequency. introducing an additional delay to the loading of the int value using the n sel bit cause s th e int and frac value s to be loaded at the same time , preventing frequency overshoot. the delay is t urned on b y setting bit db 15 to 1. - reset for most applications, bit db14 should be set to 0. when this bit is set to 0, the - modulator is reset on each write to register r 0. if it is not required that the - modulator be reset on each write to register r 0, s et this bit to 1. ramp mode bits db [ 11 :10] determine the type of generated waveform (see figure 28 and the waveform generation section) . psk enable when bit db9 is set to 1, psk modulation is enabled. whe n this bit is set to 0, psk modulation is disabled. f or more infor - mation , see the phase shift keying (psk) section . fsk enable when bit db8 is set to 1, fsk modulation is enabled. when this bit is set to 0, fsk modulation is disa bled. for more infor - mation, s e e th e frequency shift keying (fsk) section . lock detect precision (ldp) t he digital lock detect circuit monitors the pfd up and down pulses ( logical or of the up and down pulses ; see figure 21 ). every 32 nd pulse is measured. the ldp bit ( bit db7) specifies the length of each lock detect reference cycle. ? ldp = 0: if five consecutive pulses of less than 14 ns are measured, digital lock detect is asserted. ? ldp = 1: if five consec utive pulses of less than 6 ns are measured, digital lock detect is asserted. digital lock detect remains asserted until the pulse width exceeds 22 ns , a write to register r0 occurs , or the part is powered down . phase detector (pd) polarity bit db6 sets th e phase detector polarity. when the vco characteristics are positive, set this bit to 1. when the vco characteristics are negative, set this bit to 0. power - down bit db5 provides the programmable power - down mode. setting this bit to 1 performs a power - down . setting this bit to 0 returns the synthesizer to normal operation. wh en the part is in software power - down mode, it retains all information in its registers. t he register contents are lost only when the supplies are removed. when power - down is activated, the following events occur: ? all active dc current paths are removed. ? the rf synthesizer counters are forced to their load state conditions. ? the charge pump is forced into three - state mode. ? the digital lock detect circuitry is reset. ? the rf in input is deb iased. ? the input shift register remains active and capable of loading and latching data.
data sheet adf4159 rev. b | page 19 of 36 charge pump three - state when bit db 4 is set to 1, the charge pump is placed in to three - state mode . for normal charge pump operation, set this bit to 0 . counter reset bit db3 is the rf counter reset bit . when this bit is set to 1, the rf synthesizer counters are held in reset. for normal operation, set this bit to 0. db31 rese r ved pd polarit y ld p counter reset c p three-s ta te contro l bits db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db 1 1 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 nb3 nb2 nb1 0 0 0 0 1 l1 ns1 u12 0 0 rm2 rm1 0 0 u 1 1 u10 u9 u8 u7 c3(0) c2(1) c1(1) u9 power-down 0 disabled 1 enabled u10 pd polarit y 0 neg a tive 1 positive u 1 1 ld p 0 14ns 1 6ns ns1 n se l 0 n word load on - clock 1 n word load del a yed 4 cycles rm2 ram p mode 0 continuous s a w t ooth 1 rm1 0 1 single ram p burst 1 0 single s a w t ooth burst 0 1 continuous triangular nb2 neg a tive bleed current (a) 0 3.73 1 1.03 25.25 53.1 109.7 224.7 454.7 916.4 1 nb1 0 1 1 0 0 nb3 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 1 u7 counter reset 0 disabled 1 enabled u8 c p three-s ta te 0 disabled 1 enabled - reset n se l lo l rese r ved rese r ved rese r ved neg bleed current neg bleed en u12 - reset 0 enabled 1 disabled l1 lo l 0 enabled 1 disabled 0 neg bleed en 0 disabled 1 enabled ram p mode psk fsk 10849-023 0 fsk 0 disabled 1 enabled 0 psk 0 disabled 1 enabled power-down figure 28 . function register (r3) map
adf4159 data sheet rev. b | page 20 of 36 clock register (r4) map when bit s db[2:0] are set to 1 00 , the on - chip clock register (register r 4 ) is programmed (see figure 29). le sel in some applications, it is necessary to synchronize the le pin with the r eference signal . to do t his, bit db 31 must be set to 1. synchronization is done internally on the part. reserved bits all reserved bits must be set to 0 for normal operation. ramp status bits db[25: 2 1] provide access to the following advanced features (see figure 29) : ? readback to muxout option: the synthesizer frequency at the moment of interruption can be read back (see the interrupt modes and frequency readback section) . ? ramp c omplete to muxout option: a logic high pulse is output on the muxout pin at the end of each ramp. ? charge p ump u p and c harge p ump d own options: the charge pump is forced to constantly output up or down pulse s, respectively . when using the r eadback to muxout or ramp complete to muxout option, the muxout bits in regis ter r0 ( bits db[30:27]) must be set to 1111. clock d ivider mode bits db[20:19] specify whether the 12 - bit clock divider func - tions as a counter for the ramp functions (clk 2 ) or is turned off. these bits are also used to enable the fast lock divider (see t he fast lock mode section). 12- b it clk 2 divider value bits db[ 18:7] program the clo ck divider ( the clk 2 timer ) when the part operat es in ramp mode (see the timeout interval section ) . the clk 2 timer also determines how long the loop remains in wideband mode wh en fast lo ck mode is used ( s ee the fast lock mode section ) . clock divider sel ect bit db 6 selects the clo ck divider that is load ed with the 12- b it c lock d ivider v alue . when bit db6 is set to 0, clk 1 is loaded; when bit db6 is set to 1, clk 2 for ramp 1 or ramp 2 is loaded. for more information, s ee the waveform deviations and timing section . 12-bit clk 2 divider value reserved reserved control bits ls1 0 0 0 0 0 r2 r3 r4 r5 r1 r2 r3 r4 r5 r1 c 2 c 1 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 1 2 d 1 1 . . . d2 d 1 clk 2 divider value 0 0 . . . 0 0 0 0 0 . . . 0 1 1 0 0 . . . 1 0 2 0 0 . . . 1 1 3 . . . . . . . . . . . . . . . . . . . . . . . . 1 1 . . . 0 0 4 0 9 2 1 1 . . . 0 1 4 0 9 3 1 1 . . . 1 0 4 0 9 4 1 1 . . . 1 1 4 0 9 5 c2 c1 clock divider mode 0 0 clock divider off 0 1 cs1 0 0 0 clk div mode 1 0 1 1 le sel ls1 le sel 0 1 ramp status 0 normal operation 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1 1 0 c s 1 clk div sel 0 1 clk div sel db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3(1) c2(0) c1(0) readback to muxout ramp complete to muxout charge pump up charge pump down fast lock divider reserved ramp divider le from pin le synch with ref in load clk div 1 load clk div 2 10849-024 ramp status figure 29 . clock register (r4) map
data sheet adf4159 rev. b | page 21 of 36 d eviation register (r5) map when bits db[2:0] are set to 1 0 1, the on - chip deviation register (register r 5 ) is programmed (see figure 30). rese rved bit the reserved bit must be set to 0 for normal operation. tx data invert when bit db30 is set to 0, events triggered by tx data occ u r on the rising edge of the tx data pulse. when bit db30 is set to 1, events triggered by tx data occur on the falling edge of the tx data pulse. t x data ramp clock when bit db29 is set to 0 , t he clock divider clock is used to clock the ramp. when bit db29 is set to 1 , the t x data clock is used to clock the ramp. parabolic ramp when bit db28 is set to 1 , the parabolic ramp is enabled . when bit db28 is set to 0 , the parabolic ramp is disabled. for more information, s ee the parabolic (nonlinear) ramp mode section . interrupt bits db[27:26] determine which type of interrupt is used. th is feature is used for reading back the int and f r ac value of a ramp at a given moment in time ( a rising edge on the tx data pin triggers the interrupt). from the int and frac bits, the frequency can be obtained. after readback , the sweep can continue or st op at the read back frequency. for more information, see the interrupt modes and frequency readback section. fsk ramp enable when bit db25 is set to 1 , the fsk ramp is enabled . when bit db25 is set to 0 , the fsk ra mp is disabled . dual ramp enable when bit db2 4 is set to 1 , the second ramp is enabled . when bit db2 4 is set to 0 , the second ramp is disabled . deviation select when bit db23 is set to 0 , the first deviation word is selected . when bit db23 is set to 1 , the second deviation word is selected . 4 - bit deviation offset word bits db[22:19] determine the deviation offset word . the devia - tion offset word affects the deviation resolution. 16- bit deviation word bits db[18:3] determine the signed deviation word. the de viation w ord defines the deviation step. 16-bit deviation word control bits 0 0 0 0 0 t r 1 i 2 i 1 d s 1 d o 4 d o 3 d o 2 d o 1 d 1 6 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 c 3 ( 1 ) c 2 ( 0 ) c 1 ( 1 ) i2 i1 interrupt 0 0 interrupt off 1 1 d16 d15 ... ... ... ... ... ... ... ... ... ... ... ... d2 d1 deviation word 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 1 1 1 1 ? 1 1 1 1 0 ? 2 1 1 0 1 ? 3 1 0 0 0 ?32,768 d 4 d 3 d 1 d 2 4-bit deviation offset word dev sel 0 1 0 1 do4 do3 do2 do1 dev offset word 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . 1 1 0 1 7 1 1 1 0 0 0 0 0 8 9 ds1 dev sel 0 dev word 1 1 dev word 2 0 dual ramp 0 disabled 1 enabled 0 0 disabled 1 enabled 0 fsk ramp 0 disabled 1 enabled 0 parabolic ramp 0 disabled 1 enabled tr1 tx dat a ramp clk 0 clk div 1 tx data 0 1 1 1 32,767 . . . . . . . . . . dua l ram p fsk ram p rese r ved parabolic ramp tx dat a ram p clk tx dat a invert interrupt load channel continue sweep not used load channel stop sweep db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10849-025 tx dat a invert figure 30 . dev iation register (r5) map
adf4159 data sheet rev. b | page 22 of 36 step register (r6) map when bits db[2:0] are set to 11 0 , the on - chip step register (register r 6 ) is programmed (see figure 31). reserved bits all reserved bits must be set to 0 for normal operation . step select when bit db23 is set to 0 , ste p word 1 is selected . when bit db23 is set to 1 , step word 2 is selected . 20- bit step word bits db[22:3] determine t he step word. the s tep word is the number of steps in the ramp. db 3 1 20 -b i t st ep w o r d r ese r ved c o n t r o l b i t s db 3 0 db 2 9 db 2 8 db 2 7 db 2 6 db 2 5 db 2 4 db 2 3 db 2 2 db 2 1 db 2 0 db 1 9 db 1 8 db 1 7 db 1 6 db 1 5 db 1 4 db 1 3 db 1 2 db 1 1 db 1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 0 0 0 0 0 0 0 sse 1 s 2 0 s 1 9 s 1 8 s 1 7 s 1 6 s 1 5 s 1 4 s 1 3 s 1 2 s 1 1 s 1 0 s 9 s 8 s 7 s 6 s 5 c 3 ( 1 ) c 2 ( 1 ) c 1 ( 0 ) s2 0 s1 9 ... s2 s1 step word 0 0 ... 0 0 0 0 0 ... 0 1 1 0 0 ... 1 0 2 0 0 ... 1 1 3 . . ... . . . . . ... . . . . . ... . . . 1 1 ... 0 0 1 ,048,572 1 1 ... 0 1 1 ,048,573 1 1 ... 1 0 1 ,048,574 1 1 ... 1 1 1 ,048,575 s 4 s 3 s 1 s 2 st ep sel s t ep se l sse 1 0 s t ep w o rd 1 1 s t ep w o rd 2 10849-026 figure 31 . step register (r6) map
data sheet adf4159 rev. b | page 23 of 36 d elay register (r7) map when bits db [ 2: 0] are set to 111, the on - chip delay register (register r7) is programm ed (see figure 32). reserved bits all reserved bits must be set to 0 for normal operation. tx data trigger delay w hen bit db23 is set to 0, there is no delay before th e start of the ramp when using tx data to trigger a ramp. w hen bit db23 is set to 1 , a delay is enabled before th e start of the ramp if the d elayed s tart is enabled via bit db15 . tri angular del ay w hen bit db22 is set to 1 , a delay is enabled between each section of a triangular ramp, resulting in a clipp ed ramp. this setting works only for triangular ramps and when the r amp d elay is activated. w hen bit db22 is set to 0 , the delay between triangular ramps is disable d . single full tri angle w hen bit db21 is set to 1 , the single full triangle function is enab led . w hen bit db21 is set to 0 , this function is disabled . for more information, see the waveform generation section . tx data trigger when bit db20 is set to 1 , a logic high on tx data activates the ramp. when bit db 20 is set to 0 , this function is disabled . fast ramp w hen bit db19 is set to 1 , the triangular waveform is activated with two different slopes. this waveform can be used as an alter - native to the sawtooth ramp because it mitigates the overshoot at the end of the ramp in a waveform . fast ramp is achieved by changing the top frequency to the bottom frequency in a series of small steps instead of one big step. w hen bit db19 is set to 0, the fast ramp function is disable d (see the fast ramp mode section ) . ramp delay fast lock w hen bit db18 is set to 1 , the ramp delay fast lock function is enabled . w hen bit db18 is set to 0 , th is function is disabled . ramp delay w hen bit db17 is set to 1 , the delay between ramps function is enabled . w hen bit db17 is set to 0 , this function is disabled . delay clock select w hen bit db 1 6 is set to 0 , the pfd clock is selected as the delay clock . w hen bit db16 is set to 1 , pfd clock clk 1 is selected as the delay clock. ( clk 1 is set by bits d b[14:3] in register r 2 .) delayed start enable w hen bit db1 5 is set to 1 , the delayed start is enabled . w hen bit db1 5 is set to 0 , the delayed start is disable d. 12- bit delay start word bits db[14:3] determine the delay start word. the delay start word affe cts the duration of the ramp start delay. d b 3 1 12-bit delay start word reserved ramp delay fl d b 3 0 d b 2 9 d b 2 8 d b 2 7 d b 2 6 d b 2 5 d b 2 4 d b 2 3 d b 2 2 d b 2 1 d b 2 0 d b 1 9 d b 1 8 d b 1 7 d b 1 6 d b 1 5 d b 1 4 d b 1 3 d b 1 2 d b 1 1 d b 1 0 d b 9 d b 8 d b 7 d b 6 d b 5 d b 4 d b 3 d b 2 d b 1 d b 0 0 0 0 0 0 0 0 0 0 0 t d 1 s t 1 t r 1 f r 1 r d 1 d c 1 d s e 1 d s 1 2 d s 1 1 d s 1 0 d s 9 d s 8 d s 7 d s 6 d s 5 c 3 ( 1 ) c 2 ( 1 ) c 1 ( 1 ) ds12 ds11 . . . ds2 ds1 delay start word 0 0 . . . 0 0 0 0 0 . . . 0 1 1 0 0 . . . 1 0 2 0 0 . . . 1 1 3 . . . . . . . . . . . . . . . . . . . . . . . . 1 1 . . . 0 0 4092 1 1 . . . 0 1 4093 1 1 . . . 1 0 4094 1 1 . . . 1 1 4095 d s 4 d s 3 d s 1 d s 2 dse1 del start en 0 disabled 1 enabled del start en del clk sel ramp delay dc1 del clk sel 0 pfd clk 1 pfd clk clk 1 rd1 ramp delay fast ramp tx data trigger tx data trigger delay sing full tri tri delay fr1 fast ramp tr1 tx dat a trigger st1 sing full tri 0 disabled 1 enabled 0 disabled 1 0 1 enabled 0 disabled 1 enabled disabled enabled 0 ramp delay fl 0 1 disabled enabled 0 tx dat a trigger delay 0 1 disabled enabled td1 tri delay 0 disabled 1 enabled control bits 10849-027 figure 32 . delay register (r7) map
adf4159 data sheet rev. b | page 24 of 36 applications informa tion initialization seque nce after powering up the adf4159 , initialize the part by program - ming the registers in the following sequence: 1. delay register (r7) . 2. step register (r6) . l oad the step register twice, first with step sel = 0 and then with step sel = 1 . 3. dev iation register (r5) . l oad the deviation register twice, first with dev sel = 0 and then with dev sel = 1 . 4. clock register (r4) . l oad the clock register twice, first with clk div sel = 0 and then with clk div sel = 1 . 5. function register (r3) . 6. r divider register (r2) . 7. lsb frac register (r1) . 8. frac/int register (r0) . rf synthesizer worke d example the following equation governs how the synthesizer must be programmed. rf out = ( int + ( frac/ 2 25 ) ) f pfd ( 4 ) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. the pfd frequency (f pfd ) equation is f pfd = ref in [(1 + d )/( r (1 + t ))] ( 5 ) where: ref in is the reference frequency input. d is the rf ref in doubler bit , bit db20 in register r2 (0 or 1) . r is the rf reference division factor (1 to 3 2). t is the reference divide - by - 2 bit , bit db21 in register r2 (0 or 1). fo r example, in a system where a 12.102 ghz rf frequency output (rf out ) is required and a 10 0 mhz reference frequency input (ref in ) is available, the frequency resolution is f res = r ef in / 2 25 (6) f res = 10 0 mhz / 2 25 = 2 . 98 hz from equation 5 , f pfd = [1 0 0 mhz (1 + 0)/1] = 10 0 mhz 12.102 ghz = 1 0 0 mhz ( n + frac/ 2 25 ) calculating the n and frac values, n = int ( rf out / f pfd ) = 121 frac = f msb 2 13 + f lsb f msb = int (((rf out / f pfd ) ? n ) 2 1 2 ) = 81 f lsb = int (((((rf out / f pfd ) ? n ) 2 12 ) ? f msb ) 2 13 ) = 7536 where: f msb is the 12 - bit msb frac value in register r0. f lsb is the 13 - bit lsb frac value in register r1. int () makes an integer of the argument in parentheses . reference doubler the on - chip reference doubler allows the input reference signal to be doubled. this doubling is useful for increasing the pfd compar - ison frequency. doubling the pfd frequency usually improves the noise performance of the system by 3 db. it is important to note t hat the pfd cannot be operated above 110 mhz due to a limitation in the speed of the - circuit of the n divider . cycle slip r eduction f or faster lock times in fast lo cking applications, a wide loop filter bandwidth is required for fast frequency acquisition, resulting in increased integrated phase noise and reduced s pur attenuation. using cycle slip reduction, the loop bandwidth can be kept narrow to reduce integrated phase noise and attenuate spurs while still realizing fast lock times. cycle slips cycle slips occur in integer - n/fractional - n synthesizers when the loo p bandwidth is narrow compared with the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction, slowing down the loc k time dramatically. the adf4159 contains a cycle slip reduction circuit to extend the linear range of the pfd, allowing faster lock times without loop filter changes. when the adf415 9 detects that a cycle slip is about to occur, it turns on an extra charge pump current cell. this outputs a constant current to the loop filter or removes a constant current from the loop filter (depending on whether the vco tuning voltage must increase or decrease to acquire the new frequency). the effect is that the linear range of the pfd is increased. stability is maintained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle s lip is likely, the adf4159 turns on another charge pump cell. this continues until the adf4159 detects that the vco frequency has exceeded the desired frequency. it then begins to turn off the extra charge pump cells one by one until they are all turned off and the frequency is settled. up to seven extra charge pump cells can be turned on. in most applications, seven cells is enough to eliminate cycle slips alto - gether, giving much faster lock times. when bit db28 in the r divider register (register r2) is set to 1 , cycle slip reduction is enabled . note that a 45% to 55% duty cycle is needed on the signal at the pfd in order for csr to operate co rrectly. the reference divide - by - 2 flip - flop can help to provide a 50% duty cycle at the pfd. for example, if a 100 mhz reference frequency is available and the user wants to run t he pfd at 10 mhz, setting the r divide factor to 10 results in a 10 mhz pfd signal that is not 50% duty cycle. by setting the r divide factor to 5 and enabling the reference divide - by - 2 bit, a 50% duty cycle 10 mhz signal can be achieved.
data sheet adf4159 rev. b | page 25 of 36 note that the cycle slip reduction feature can only be operated when the phase detector pola rity setting is positive ( bit db6 in register r3 is set to 1 ). it cannot be used if the phase detector polarity is negative. modulation the adf4159 can operate in frequency shift keying (fsk) or phas e shift keying (psk) mode. frequency shift keying (fsk) fsk is im plemented by configuring the adf4159 n divider for the center frequency and then toggling the tx data pin. the deviation from the cen ter frequency is set by f dev = ( f pfd /2 25 ) ( dev 2 dev_offset ) (7) where: f pfd is the pfd frequency. dev is a 16 - bit word (bits db[18:3] in register r5) . dev_offset is a 4 - bit word (bits db[22:19] in register r5) . the adf4159 implements f dev by incrementing or decrementing the configured n divide r value by dev 2 dev_offset . fsk settings worked example in this example, an fsk system operat es at 5.8 ghz with a 25 m hz f pfd , requiring 250 khz deviation (f dev ) . rearrange equation 7 as follows: ( dev 2 dev_offset ) = f dev /( f pfd / 2 25 ) ( dev 2 dev_offset ) = 250 khz/(25 mhz/2 25 ) ( dev 2 dev_offset ) = 335 , 544.32 if dev_offset is set to 6 , dev = 335 , 544.32 /(2 6 ) = 5242.88 5243 due to the rounding of dev, f dev = 250.005722 khz . toggling the tx data pin causes the frequency to hop between 250 khz from the programmed center frequency . phase shift keying (psk) when the adf4159 is configured for psk mode, the ou tput phase of the adf4159 is equal to ( phase value 360)/ 2 12 the p hase v alue is set in register 1 , bits db[14:3] . the psk modulation is controlled by the tx data pin. for example, if the phase value is 1024, a logic high on the tx data pin results in a 90 increase of the output phase. a logic low on the tx data pin results in a 90 decrease of the output phase . the polarity can be inverted by negating the p hase v alue. waveform generation the adf4159 is capable of generating f ive types of waveforms in the frequency domain : single ramp burst , single triangular burst, single sawtooth burst, continuous sawtooth ramp, and continuous triangular ram p . figure 33 through figure 37 show the types of waveforms available. frequency time 10849-028 figure 33 . single ramp burst frequenc y time 10849-029 figure 34 . single triangular burst time frequency 10849-030 figure 35 . single sawtooth burst frequency time 10849-031 figure 36 . continuous sawtooth ramp frequency time 10849-032 figure 37 . continuous triangular ramp
adf4159 data sheet rev. b | page 26 of 36 waveform deviations and timing figure 38 shows a version of a ramp. time r f dev frequency time 10849-033 figure 38. waveform timing the key parameters that define a ramp are ? frequency deviation ? timeout interval ? number of steps frequency deviation the frequency deviation for each frequency hop is set by f dev = ( f pfd /2 25 ) ( dev 2 dev_offset ) (7) where: f pfd is the pfd frequency. dev is a 16-bit word (bits db[18:3] in register r5). dev_offset is a 4-bit word (bits db[22:19] in register r5). timeout interval the time between each frequency hop is set by timer = clk 1 clk 2 (1/ f pfd ) (8) where: clk 1 and clk 2 are the 12-bit clock values (12-bit clk 1 divider in register r2 and 12-bit clk 2 divider in register r4). bits db[20:19] in register r4 must be set to 11 for ramp divider. f pfd is the pfd frequency. number of steps a 20-bit step value (bits db[22:3] in register r6) defines the number of frequency hops that take place. the int value cannot be incremented by more than 2 8 = 256 from its starting value. single ramp burst the most basic waveform is the single ramp burst. all other waveforms are variations of this waveform. in the single ramp burst, the adf4159 is locked to the frequency defined in the frac/int register (r0). when the ramp mode is enabled, the adf4159 increments the n divider value by dev 2 dev_offset , causing a frequency shift, f dev , on each timer interval. this shift is repeated until the set number of steps has taken place. the adf4159 then retains the final n divider value. single triangular burst the single triangular burst is similar to the single ramp burst. however, when the steps are completed, the adf4159 begins to decrement the n divider value by dev 2 dev_offset on each timeout interval. single sawtooth burst in the single sawtooth burst, the n divider value is reset to its initial value on the next timeout interval after the number of steps has taken place. the adf4159 retains this n divider value. sawtooth ramp the sawtooth ramp is a repeated version of the single sawtooth burst. the waveform is repeated until the ramp is disabled. triangular ramp the triangular ramp is a repeated version of the single triangu- lar burst. however, when the steps are completed, the adf4159 begins to decrement the n divider value by dev 2 dev_offset on each timeout interval. when the number of steps has again been completed, the part reverts to incrementing the n divider value. repeating this pattern creates a triangular waveform. the wave- form is repeated until the ramp is disabled. fmcw radar ramp settings worked example this example describes a frequency modulated continuous wave (fmcw) radar system that requires the rf lo to use a sawtooth ramp over a 50 mhz range every 2 ms. the pfd frequency is 25 mhz, and the rf output range is 5800 mhz to 5850 mhz. the frequency deviation for each hop in the ramp is set to ~250 khz. the frequency resolution of the adf4159 is calculated as follows: f res = f pfd /2 25 (9) using equation 9, f res is calculated as follows: f res = 25 mhz/2 25 = 0.745 hz dev_offset is calculated after rearranging equation 7. dev_offset = log 2 ( f dev / ( f res dev max )) (10) expressed in log 10 (x), equation 10 can be rearranged into the following equation: dev_offset = log 10 ( f dev /( f res dev max ))/log 10 (2) (11) where: f dev is the frequency deviation. dev max = 2 15 (maximum value of the deviation word). dev_offset is a 4-bit word. using equation 11, dev_offset is calculated as follows: dev_offset = log 10 (250 khz/(0.745 hz 2 15 ))/log 10 (2) = 3.356 after rounding, dev_offset = 4. from dev_offset, the resolution of the frequency deviation can be calculated as follows: f dev_res = f res 2 dev_offset (12) f dev_res = 0.745 hz 2 4 = 11.92 hz
data sheet adf4159 rev. b | page 27 of 36 t o calculate the dev word , use equation 1 3 . dev = f dev / ( f res 2 dev_offset ) (1 3 ) 52 . 971 , 20 2 2 mhz 25 z kh 250 4 25 = = dev rounding this value to 20 , 972 and recalculating using equation 7 to obtain the actual deviation frequency , f dev , thus produces the followin g: f dev = (25 mhz/2 25 ) (20 , 972 2 4 ) = 250.006 khz the number of f dev steps required to cover the 50 mhz range is 50 mhz/250.006 khz = 200. to cover the 50 mhz range in 2 ms, the adf4159 must hop every 2 ms/200 = 10 s. rearrang e equation 8 to set the timer value (and set clk 2 to 1): clk 1 = timer f pfd / clk 2 = 10 s 25 mhz/1 = 250 to summarize the settings, ? dev = 20 ,972 ? n umber of steps = 200 ? clk 1 = 250 ? clk 2 = 1 ( bits db[20:19] = 11 , ramp divider , in register r4 ) using these settings, program the adf4159 to a cent e r frequency of 5800 mhz and enabl e the sawtooth ramp to produce the required waveform. if a triangular ramp is used with the same settings, the adf4159 sweep s from 5800 mhz to 5850 mhz and back down again , taking 4 ms for t he entire sweep. activating the ramp after setting all required parameters , the ramp must be activated by choosing the desired type of ramp ( bits db[11:10] in register r 3) and starting the ramp ( bit db 31 = 1 in reg ister r 0) . ramp programming sequence the setting of parameters described in the fmcw radar ramp settings w orked example section and the activation of the ramp described in the activating the ramp section must be completed in the following register write order: 1. delay register (r7) 2. step register (r6) 3. deviation register (r5) 4. clock register (r4) 5. function register (r3) 6. r divider register (r2) 7. lsb frac register (r1) 8. frac/int register (r0) other waveforms dual ramp s with different ramp rates t he adf4159 can be configu red for two ramps with different step and deviation settings. it also allows the ramp rate to be reprogrammed while another ramp is running. example in this example, the pll is locked to 5790 mhz and f pfd = 25 mhz . two ramps are configured, as follows: ? ra mp 1 jumps 10 0 steps ; each step lasts 10 s and has a frequency deviation of 100 khz. ? ramp 2 jumps 80 steps; each step lasts 10 s and has a frequency deviation of 125 khz. to enable the two ramp rates , follow these steps : 1. a ctivate the dual ramp rates mode by set ting bit db24 in register r5 to 1 . 2. p rogram the ramp rate for ramp 1 by set ting the following values: ? register r5 : set bit db23 = 0, bits db[18:3] = 16, 777, and bits db[22:19] = 3 ? register r 6: set bit db2 3 = 0 and bits db[22:3] = 100 3. program the ram p rate for ramp 2 by set ting the following values: ? register r5 : set bit db23 = 1 , bits db[18:3] = 20, 972, and bits db[22:19] = 3 ? register r 6: set bit db23 = 1 and bits db[22:3] = 80 figure 39 shows t he resulting r amp with two ramp rates . t o activate t he ramp, see the activating the ramp section. frequency time sweep rate set by other register sweep rate set by one register 10849-134 figure 39 . dual ramp with two sweep rate s
adf4159 data sheet rev. b | page 28 of 36 ramp mode with superimposed fs k signal in tradition al approaches , fmcw radars use either linear frequency modulation (lfm ) or fsk modulation. used sepa - rately, these modu lations introduce ambiguity between measured distance and velocity, especially in multitarget situations. to over - come this issue and ena ble unambiguous ( distance and velocity) multitarget detection, use a ramp with fsk superimposed on it. example in this example, the pll is locked to 5790 mhz and f pfd = 25 mhz . the ramp with superimposed fsk is configured as follows: ? the number of steps is set to 100; each step lasts 10 s and has a deviation of 100 khz. ? the fsk signal is 25 khz. to enable ramp mode with fsk superimposed on it , follow these steps : 1. set bit db23 in register r5 and bit db23 in register r6 to 0. 2. program the ramp as described in the fmcw radar ramp settings worked example section . 3. p rogram fsk on the ramp to 25 khz by setting the bits in register r5 as follows: ? db [18:3] = 4194 (deviation word) ? db [22:19] = 3 (deviation offset word ) ? db23 = 1 (deviation word for fsk on the ramp) ? db 25 = 1 (ramp with fsk e nabled) figure 40 shows a n example of a ramp with fsk superimposed on it. t o activate t he ramp, see the activating the ram p section . 10849-135 frequency 0 ramp end frequency sweep time fsk shift lfmstep = frequency sweep/number of steps figure 40 . combined fsk and lfm waveform delayed start a delayed start can be used with two different parts to control the start time. figure 41 shows t he theory of del ayed start. f r e q u e nc y t i me ra mp w i t h d e l a ye d s t ar t ra mp w i t h o u t d e l a ye d s t ar t 10849-034 figure 41 . delayed start of sawtooth ramp example for example, to program a delayed start with two different parts to control the start time, follow these steps: 1. e nable the delayed start of ramp option by s et ting bit db15 in register r 7 to 1. 2. d elay the ramp on the first part by 5 s by s et ting bit db16 in register r 7 to 0 a nd set ting the 12 - bit delay start word ( bits db[ 14:3 ] in register r 7) to 125 ( f pfd = 25 mhz ) . the delay is calculated as follows: delay = t pfd del ay start word delay = 40 ns 125 = 5 s 3. delay the ramp on the second part by 125 s by s e tting bit db16 in register r 7 to 1 and setting the 12 - bit delay start word ( bits db[ 14:3 ] in register r 7) to 125. the delay is calculated as follows: delay = t pfd clk 1 delay start word delay = 40 ns 25 125 = 125 s t o activate t he ramp, see the activating the ramp section .
data sheet adf4159 rev. b | page 29 of 36 delay between ramps the adf4159 can be configured to add a delay between bursts in ramps. figure 42, figure 43, and figure 44 show a delay between ramps in sawtooth, triangular, and clipped triangular mode, respectively. frequency delay time 10849-035 figure 42. delay between ramps for sawtooth mode frequency time 10849-036 figure 43. delay between ramps for triangular mode frequenc y time delay 10849-037 figure 44. delay between ramps for clipped triangular mode example for example, to add a delay between bursts in a ramp, follow these steps: 1. enable the delay between ramps option by setting bit db17 in register r7 to 1. 2. delay the ramp by 5 s by setting bit db16 in register r7 to 0 and setting the 12-bit delay start word (bits db[14:3] in register r7) to 125 (f pfd = 25 mhz). the delay is calculated as follows: delay = t pfd delay start word delay = 40 ns 125 = 5 s if a longer delay is needed, for example, 125 s, set bit db16 in register r7 to 1, and set the 12-bit delay start word (bits db[14:3] in register r7) to 125. the delay is calculated as follows: delay = t pfd clk 1 delay start word delay = 40 ns 25 125 = 125 s it is also possible to activate fast lock operation for the first period of delay by setting bit db18 in register r7 to 1. this feature is useful for sawtooth ramps to mitigate the frequency overshoot on the transition from one sawtooth to the next. to activate the ramp, see the activating the ramp section. dual ramp rates mode with delay this mode combines the modes described in the dual ramps with different ramp rates section and the delay between ramps section (see figure 45). 10849-140 time frequency figure 45. dual ramp rates mode with delay to enable this configuration, 1. program the two ramp rates mode as described in the dual ramps with different ramp rates section. 2. program the delay as described in the delay between ramps section. parabolic (nonlinea r) ramp mode the adf4159 is capable of generating a parabolic ramp (see figure 46). frequency time 10849-141 figure 46. parabolic ramp the output frequency is generated according to the following equation: f out ( n + 1) = f out ( n) + n f dev (14) where: f out is the output frequency. n is the step number. f dev is the frequency deviation.
adf4159 data sheet rev. b | page 30 of 36 example this example describes how to set up and use the parabolic ramp mode with the following parameters : ? f ou t = 5790 mhz ? f dev = 100 khz ? number of steps = 50 ? duration of a single step = 10 s to set up the parabolic ramp mode , follow these steps : 1. configure one of the following r amp mode s: ? continuous triangular ramp (set register r3, bits db[11:10] to 01 ) . ? single ramp burst (set register r3, bits db[11:10] to 1 1 ) . for the continuous triangular ramp , the generated frequency range is calculated as follows: f = f dev ( number of steps + 2) ( number of steps + 1)/2 = 132.6 mhz for the s ingle ramp burst , the generated frequency range is calculated as follows: f = f dev ( number of steps + 1) number of steps /2 = 127.5 mhz 2. set t he timer as described for the linear ramps in the timeout interval section. 3. a ctivat e the parabolic ramp by set ting bit db28 in register r5 to 1. 4. set the counter reset ( bit db3 in register r3) to 1 and then set it to 0. t o activate t he ramp, see the activating the ramp section . fast ramp mode the adf4159 is capable of generating a f ast r amp. the fast r amp is a triangular ramp with two different slopes (see figure 47) . the number of steps, time per step , and deviation per step are programmable for both the up and down ramp s. frequency time 10849-038 figure 47 . fast ramp mode to activate th e fast ramp waveform , follow these steps : 1. select the continuous triangular wa veform by setting bits db[11:10] in register r3 to 01 . 2. enable the f ast r amp by setting bit db19 in register r7 to 1 . 3. program the u p ramp as follows. a. set bit db6 in register r4 ( clk div sel ), bit db23 in reg ister r5 ( dev sel ) , and bit db23 in register r6 ( step sel ) to 0 for ramp 1. b. calculate and program the timer, dev, dev_offset , and the step word as described in the fmcw radar ramp settings worked example section. 4. program the down ramp as follows. a. set bit db6 in register r4 (clk div sel), bit db23 in register r5 (dev sel), and bit db23 in register r6 ( step sel) to 1 for ramp 2. b. calculate and program the timer, dev, dev_offset, and the step word as described in the fmcw radar ramp settings worked example section. 5. sta rt the ramp by setting bit db31 = 1 in register r0. note that the total frequency chang e of the up and down ramps must be equal for stability. ramp complete signal to muxout figure 48 shows the r amp c omplete signal on muxout. frequency time voltage time 10849-039 figure 48 . ramp complete signal on muxout to activate this function, set bits db[30:27] in register r0 to 1111, and set bits db[2 5 :21] in re gister r4 to 00011.
data sheet adf4159 rev. b | page 31 of 36 interrupt modes and frequency readback interrupt modes are triggered from the rising edge of tx data . to activate this function, set bits db[30:27] in register r0 to 1111, and set bits db[25:21] in register r4 to 00010. to select and enable the interrupt mode, set bits db[27:26] in register r5 as shown in table 8. table 8. interrupt modes (register r5) bits db[27:26] interrupt mode 00 interrupt is off 01 interrupt on tx data , sweep continues 11 interrupt on tx data , sweep stops figure 49 shows the theory of frequency readback. frequenc y logic level time time time of interrupt frequency at which interrupt took place interrupt signal logic high logic low 1. sweep continues mode 2. sweep stops mode 12 10849-040 figure 49. interrupt and frequency readback when an interrupt takes place, the data, consisting of the int and frac values, can be read back via muxout. the data comprises 37 bits: 12 bits represent the int value and 25 bits represent the frac value. figure 50 shows how single bits are read back. msb lsb muxout clk le 12-bit integer word 0000 1110 0111 0x0e7 231 25-bit frac word 1 0110 0010 0011 1010 0111 1000 0x1623a78 23,214,712 rf = f pfd (231 + 23,214,712/2 25 ) = 1.7922963ghz tx data data clocked out on positive edge of clk and read on negative edge of clk readback word (37 bits) 0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (0x1cf623a78) 10849-041 figure 50. reading back single bits to determine the output frequency at the moment of interrupt for continuous frequency readback, the following sequence must be used (see figure 51). 1. register 0 write 2. le high 3. pulse on tx data 4. frequency readback 5. pulse on tx data 6. register r4 write 7. frequency readback 8. pulse on tx data figure 51 shows the continuous frequency readback sequence. clk muxout le tx data data r0 write r4 write r4 write frequency readback frequency readback frequency readback 37 clk pulses 37 clk pulses 37 clk pulses 32 clk pulses 32 clk pulses 32 clk pulses 10849-042 figure 51. continuous frequency readback
adf4159 data sheet rev. b | page 32 of 36 fast lock mode the adf4159 c an operate in fast lo ck mode. in this mode , the charge pump current is boosted and additional resistors are connected to m aintain the stability of the loop. fast lock timer and register sequences if the fast lo ck mode is used, a timer value must be loaded into the pll to determine the time spent in wide bandwidth mode. when bits db[20:19] in register r4 are set to 01 ( fast lo ck divider), the timer value is loaded via the 12 - bit clock divider value. before fast lock is enabled, the i nitialization sequence must be performed after the part is first powered up (see the initialization sequence section). n o te that the fast lo ck feature does n o t work in ramp mode. to use fast lock, the pll must be written to in the following sequence: 1. set bits db[20:19] = 01 in register r4 and set the fast lo ck timer value ( bits db[18:7]). 2. i f a longer time in wide loop bandwi dth is required , set the clk 1 divider value ( bits db[14:3]) in register r2 . note that the length of time that the pll remains in wi de band - width mode is equal to clk 1 fast lo ck timer/f pfd , where clk 1 is the 12 - bit clk 1 divider programmed in register r2. fast lock example in this example, the pll has a reference frequency of 13 mhz ( f pfd = 13 mhz ) and a required lock time of 50 s with clk 1 = 10 (12 - bit clk 1 divider in register r2) . in this case, the pll is set to wide bandwidth mode for 40 s. if the time period set for wide bandwidth mode is 40 s, then fast lock timer value = time in wide bandwidth f pfd /clk 1 fast lock timer value = 40 s 13 mhz / 10 = 52. therefore, 52 must be loaded into the clock divide r value in register r4 ( step 1 in the fast lock timer and register sequences section ) . fast lock loop filter topology to us e fast lo ck mode, an extra connection from the pll to the loop filter is needed. the damping resistor in the loop filter must be reduced to ? of its value in wide bandwidth mode. this reduc - tion is required because the charge pump current is increased by 16 in wide ban d width mode, and stability must be ensured. to further enhance stability and mitigate frequency overshoot during a frequency cha nge in wide bandwidth mode, resistor r3 is connected (see figure 52) . during fast lock, the sw1 pin is shorted to ground , and the sw2 pin is connected to cp (set bits db[2 0:19] in register r4 to 01 for fast lo ck divider ). the fol lowing two topologies can be used: ? divide the damping resistor (r1) into two values (r1 and r1a) that have a ratio of 1:3 (see figure 52 ). ? connect an extra resistor (r1a) directly from sw1 (see figure 53). the extra resistor must be selected such that the parallel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the original value of r1. for both to pologies, the ratio r3:r2 must equal 1:4. 10849-047 adf4159 sw2 sw1 cp c1 c2 r1 r1a r3 r2 c3 vco figure 52 . fast lock loop filter topology 1 10849-048 adf4159 sw2 sw1 cp c1 c2 r1 r1a r3 r2 c3 vco figure 53 . fast lock loop filter topology 2
data sheet adf4159 rev. b | page 33 of 36 s pur m echanisms the fractional interpolator in the adf4159 is a third - order - modulator with a 25 - bit fixed modulus (mod). the - modu - lator is clocked at the pfd reference rate (f pfd ) , which allows pll output frequencies to be synthesized at a channel step resolution of f pfd /clk 1 . t his section describes the vari ous spur mechanisms that are possible with fractional - n synthesizers and how they affect the adf4159 . fractional spurs in most fractional synthesizers, fractional spurs can appear at the set channel spacing of the synthesizer. in the adf4159 , these spurs do not appear. the high value of the fixed modulus in the adf4159 makes the - modulator quantization error spectrum look like broadband noise, effectively spreading the fractional spurs into noise. integer boundary spurs interactions between the rf vco frequency and the pfd frequency can lead to spurs known as integer boundary s purs. when these frequencies are not integer related (which is the purpose of a fractional - n synthesizer), spur sidebands appear on the vco output spectrum at an offset frequency that corre - sponds to the beat note , or difference frequency , between an integ er multiple of the pfd and the vco frequency. these spurs are called integer boundary spurs because they are more noticeable on channels close to integer multiples of the pfd , where the difference frequency can be inside the loop bandwidth. these spurs are attenuated by the loop filter on channels far from integer multiples of the pfd . reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth. however, any refer ence feedthrough mechanism that bypasses the loop can cause a problem. one such mecha - n ism is the feedthrough of low levels of on - chip reference switching noise out through the rf in x pin s back to the vco, resulting in reference spur levels as high as ? 90 dbc. take c are in the pcb layout to ensure that the vco is well separated from the input reference to avoid a possible feedthrough path on the board. low frequency applications the specification o f the rf input is 0.5 ghz minimum; however, rf frequenci es lower than 0.5 ghz can be used if the minimum slew rate specification of 400 v /s is met. an appropriate driver for example, the adcmp553 c an be used to accelerate the edge transitions of the rf signal before it is fed back to the adf4159 rf input. filter design using adi sim pll a filter design and analysis program is available to help the user implement pll design. visit http://www.analog.com/pll to down - load the free adisimpll ? software. this software designs, s imulates, and analyzes the entire pll frequency domain and time domain response. various passive and active fi lter arch i - tectures are allowed. pcb design guideline s for the chip scale package the lands on the chip scale package (cp - 24- 10 ) are rectangular. the printed circuit board (pcb) pad for thes e lands must be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. center t he land on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central exposed thermal pad. the thermal pad on the pcb must be at least as large as this exposed pad. on the pcb , there must be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that sh orting is avoided. thermal vias can be used on the pcb thermal pad to improve the thermal performance of the package. if vias are used, incor - porate them into the thermal pad at the 1.2 mm pitch grid. the via dia m eter must be between 0.3 mm and 0.33 mm, an d the via barrel must be plated with 1 ou nce of copper to plug the via. c onnect the pcb thermal pad to agnd.
adf4159 data sheet rev. b | page 34 of 36 application of the adf4159 in f mcw ra dar figure 54 shows the application of the adf4159 in a frequency modulated continuous wave (fmcw) radar system . in the fmcw radar system, t he adf4159 is used to generate the sawtooth or triangle ramps that are necessary for this type of radar t o operate. traditionally, the pll was driven directly by a direct digital synthesizer (dds) to gen erate the re quired type of wave form. due to the waveform generating mechanism that is implemented on the adf4159 , a dds is no lon ger needed, which reduces cost. t he pll solution also has advantages over another method for generating fmcw ramps: a dac driving the vco directly ; this method suffer s from nonlinearities of the vco tuning character - istics , requiring compensation. the pll method produces highly linear ramps without the need for calibration. adsp-bf531 ad8283 adc 10 bits to 12 bits 16 bits : . . mult 2 adf4159 vco baseband pa reference oscillator hpf mux : 2 no dds required with adf4159 linear frequenc y swee p micro- controller dsp bus can/flexray frequency modulated continuous wave long range radar range compensation mixer tx antenna rx antennas 10849-043 figure 54 . fmcw radar with the adf4159
data sheet adf4159 rev. b | page 35 of 36 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd-8. 06-11-2012-a bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.20 2.10 sq 2.00 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.05 max 0.02 nom figure 55. 24-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-24-10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4159ccpz ?40c to +125c 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 adf4159ccpz-rl7 ?40c to +125c 24-lead lead frame chip scale package [lfcsp_wq] cp-24-10 EV-ADF4159EB2Z evaluation board (blank pads for analog devices vco; filter unpopulated) ev-adf4159eb3z evaluation board (set up for external, sma connected vco board; filter unpopulated) 1 z = rohs compliant part.
adf4159 data sheet rev. b | page 36 of 36 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10849 - 0- 6/13(b)

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