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20 v, 6 a, synchronous step - down dc - to - dc regulator data sheet adp2386 rev. a document feedback information furnished by analog devices is believed to be accurate and reli able. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implica tion or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features input voltage: 4.5 v to 20 v integrated mosfet: 4 4 m?/11 m? reference voltage: 0.6 v 1% contin u ous output current: 6 a programmable switching frequency: 200 khz to 1.4 mhz sy nchronizes to external clock: 20 0 khz to 1.4 mhz 180 out of phase clo ck synchronization precision enable and power good external compensation internal soft start with external adjustable option s tartup into a precharged output supported by adisimpower design tool applications communications infrastructure networking and ser vers industrial and instrumentation healthcare and medical intermediate power rail conversion dc - to - dc point - of - load applications typical applications circuit adp2386 bst fb comp pgood gnd vreg rt sync ss l c vreg r t sw pgnd en pvin c in v in c bst c out v out r top r bot c c r c c ss 102 1 1-001 figure 1. 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficienc y (%) output current (a) v out = 5.0v v out = 3.3v v out = 1.2v 102 1 1-002 figure 2. efficiency vs . output current, v in = 12 v, f sw = 300 khz general description the adp2386 is a synchronous step - down, dc - to - dc regulator with an integrate d 4 4 m? , high - side p ower mosfet and a n 1 1 m? , synchronous rectifier mosfet to provide a high efficiency solution in a compact 4 mm 4 mm lfcsp package . this device uses a peak current mode, constant frequency pulse - width modulation (pwm) control scheme for excellent stability and transient response. the switching frequency of th e adp2386 can be programmed from 2 0 0 khz to 1. 4 m hz . to minimize system noise, the synchronization function allows the switching frequency to be synchronized to an external clock. the adp2386 requires minimal external component s and operates from an input voltage of 4.5 v to 20 v . the o utput voltage can be adjust ed from 0.6 v to 90% of the input voltage and deliver s up to 6 a of continuous current. each ic draws le ss than 11 0 a current from the input source when it is disabled. this regulator targets high performance application s that require high efficiency and design flexibility. external compensation and an adjustable soft start function provide design flexibility. the powe r - good output and precision enable input provide simple and reliable power sequencing. other key features include under voltage lockout (uvlo) , over voltage protection ( ovp ) , over current protection ( ocp ) , short - circuit protection (scp) , and thermal shutdown (tsd) . t he adp2386 operates over the ? 40 c to +125 c junction temperature range and is available in a 24- lead , 4 mm 4 mm lfcsp package.
adp2386 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 a pplications ....................................................................................... 1 typical applications circuit ............................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 11 theory of operation ...................................................................... 12 control scheme .......................................................................... 12 precision enable/shutdown ...................................................... 12 internal regulator (vreg) ....................................................... 12 bootstrap circuitry .................................................................... 12 oscillator ..................................................................................... 12 synchronization .......................................................................... 12 soft start ...................................................................................... 13 power good ................................................................................. 13 peak current - limit and short - circuit protection ................. 13 overvoltage protection (ovp) ................................................. 14 undervoltage lockout (uvlo) ............................................... 14 th ermal shutdown .................................................................... 14 applications information .............................................................. 15 input capacitor selection .......................................................... 15 output voltage setting .............................................................. 15 voltage conversion limitations ............................................... 15 inductor selection ...................................................................... 15 output capacitor selection ....................................................... 16 programming the input voltage uvlo .................................. 17 compensation design ............................................................... 17 adisimpower design tool ....................................................... 17 design example .............................................................................. 18 output voltage setting .............................................................. 18 frequency setting ....................................................................... 18 inductor selection ...................................................................... 18 output capacitor selec tion ....................................................... 19 compensation components ..................................................... 19 soft start time program ........................................................... 19 in put capacitor selection .......................................................... 19 recommended external components .................................... 20 circuit board layout recommendations ................................... 21 typical applications circuits ........................................................ 22 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 4/13 rev. 0 to rev. a changes to figure 4 and figure 7 .................................................... 7 updated outline dimensions ........................................................ 23 changes to ordering guide ........................................................... 23 1 1 /12 revision 0: initial version
data sheet adp2386 rev. a | page 3 of 24 specifications v pvin = 12 v, t j = ? 40 c to +125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit pvin pvin voltage range v pvin 4.5 20 v quiescent current i q no s witchi ng 2. 4 2.9 3.6 ma shutdown current i shdn en = gnd 50 80 110 a pvin undervoltage lockout threshold uvlo p vin rising 4.3 4. 4 v p vin falling 3.6 3.8 v fb fb regulation voltage v fb ? 40c < t j < 85 c 0.59 4 0.6 0.60 6 v ? 40 c < t j < 125 c 0.59 1 0.6 0.60 9 v fb bias current i fb 0.01 0.1 a error amplifier (ea) transc onductance g m 380 480 580 s ea source current i source 4 5 60 75 a ea sink current i sink 4 5 6 0 75 a int ernal regulator (vreg) vreg voltage v vreg v pvin = 12 v, i vreg = 5 0 ma 7.6 8 8 .4 v dropout voltage v pvin = 12 v, i vreg = 50 ma 340 mv regulator current l imit 6 2 100 137 ma sw high - side on resistance 1 v bst ? v sw = 5 v 44 70 m ? low -si de on resistance 1 v vreg = 8 v 11 18 m ? high - side peak current limit 7.2 9.6 11.5 a low - side negative current - limit 2 2 .5 a sw min imum on time t min_on 125 165 ns sw minimum off time t min_o ff 200 260 ns bst bootstrap voltage v b oot 4. 6 5 5. 4 v oscillator (rt pin) switching frequency f sw r t = 100 k ? 540 600 660 khz switching frequency range f sw 200 1 4 0 0 khz sync synchronization range 2 0 0 1 4 0 0 k hz sync minimum pulse width 100 n s sync positive pulse maximum duty cycle d max_sync 50 % sync input high voltage 1.3 v sync input low voltage 0.4 v ss internal soft start 1600 clock cycles ss pin p ull - up current i ss_up 2. 3 3.2 3.9 a
adp2386 data sheet rev. a | page 4 of 24 parameter symbol test conditions/comments min typ max unit pgood power - good rang e fb r ising t hreshold pgood from low to high 95 % fb rising hysteresis pgood from high to low 5 % fb f alling t hreshold pgood from low to high 105 % fb falling hysteresis pgood from high to low 11.7 % power - good deglitch time pgood f rom low to high 1024 clock cycle s pgood from high to low 16 clock cycle s power - good leakage current v pgood = 5 v 0.01 0.1 a p ower - good output low voltage i pgood = 1 ma 125 190 mv en en rising threshold 1. 17 1.2 5 v en falling thres hold 0.97 1.07 v en source current en v oltage below falling threshold 5 a en v oltage above rising threshold 1 a thermal shutdown thermal shutdown threshold 150 c thermal shutdown hysteresis 2 5 c 1 pin - to - pin measurement. 2 guaranteed by design .
data sheet adp2386 rev. a | page 5 of 24 absolute maximum rat ings table 2 . parameter rating p vin, en, pgood ? 0.3 v to + 2 2 v sw ? 1 v to + 22 v bst v sw + 6 v fb , ss , c o m p, sync, rt ? 0.3 v to +6 v vreg ? 0.3 v to + 12 v pgnd to gnd ? 0.3 v to +0.3 v operating junction temperature range ? 40 c to +125c storage temperature range ? 65c to +150c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device a t these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified fo r the worst - case conditions, that is , a device soldered in a 4 - l ayer, jedec s tandard circuit b oard for surface - mount packages. table 3 . thermal resistance package type ja unit 24-l ead lfcsp _wq 42.6 c/w esd caution
adp2386 data sheet rev. a | page 6 of 24 pi n configuration and function description s 2 1 3 4 5 6 18 17 16 15 14 13 sw sw gnd vreg fb com p pgnd 25 gnd 26 sw sw bst pvin pvin pvin notes 1. the exposed gnd pad must be soldered to a large, external, copper gnd plane to reduce thermal resistance. 2. the exposed sw pad must be connected to the sw pins of the adp2386 by using short, wide traces, or else soldered to a large, external, copper sw plane to reduce thermal resistance. 8 9 10 1 1 7 pgnd pgnd pgnd pgnd 12 pgnd sw 20 19 21 en pvin pgood 22 rt 23 sync 24 ss adp2386 t o p view 102 1 1-003 figure 3. pin configuration table 4 . pin function descriptions pin o. nemonic description 1 comp error amplifier o utput. connect an rc network from comp to gnd . 2 fb feedback voltage sense i nput. connect to a resistor divider from the output voltage, v out . 3 vreg output of the i nternal 8 v r egulator. the control circuits are powered from this voltage . p lace a 1 f , x7r or x5r c eramic capacitor between this pin and gnd . 4 gnd analog g round. return of internal control circuit. 5, 6, 7, 14 sw switch node o utput. connect to the output inductor. 8, 9, 10, 11, 12, 13 pgnd power g round. return of low - side power mosfet. 15 bst supply r ail for the high - side g ate d ri ve. p lace a 0.1 f , x7r or x5r capacitor between sw and bst . 16, 17, 18, 19 pvin power input. connect to the input power source and connect a bypass capacitor between this pin and pgnd. 20 en precision enable p in. an e xternal resistor divider can be used to set the turn - on threshold. to enable the part automatically , connect the en pin to the pvin pin . 21 pgood power - g ood output (open drain). a pull - up resistor of 10 k? to 100 k? is recommended. 22 rt frequency setting. connect a resi s tor between rt and gnd to program the switching frequency from 2 0 0 khz to 1.4 m hz . 23 sync synchronization i nput. connect this pin to an external clock to synchronize the switching frequency within a range from 200 khz to 1.4 mhz . s ee the oscillato r section and synchronization section for more information . 24 ss soft start c ontrol. connect a capacitor from ss to gnd to program the soft start time. if this pin is open, the regulator uses the internal soft start time. 25 e p, g n d the exposed gnd pad must b e soldered to a large, external, copper gnd plane to reduce thermal resistance. 26 e p, s w the exposed sw pad must be connecte d to the sw pins of the adp2386 by using short, wi de traces, or else soldered to a large , external , copper sw plane to reduce thermal resistance.
data sheet adp2386 rev. a | page 7 of 24 typical performance characteristics t a = 25 c, v in = 12 v, v out = 3.3 v, l = 2.2 h, c out = 100 f + 47 f, f sw = 600 khz, unless otherwise noted . 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficienc y (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 102 1 1-007 figure 4 . efficiency at v in = 12 v, f sw = 600 khz 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficienc y (%) output current (a) v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 102 1 1-005 figure 5. efficiency at v in = 18 v, f sw = 600 khz 50 60 70 80 90 100 4 6 8 10 12 14 16 18 20 shutdown current (a) input vo lt age (v) t j = ?40c t j = +25c t j = +125c 102 1 1-006 figure 6. shutdown current vs. input voltage ( v in ) 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficienc y (%) output current (a) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 102 1 1-004 figure 7 . efficiency at v in = 12 v, f sw = 300 khz 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 efficienc y (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 102 1 1-008 figure 8. efficiency at v in = 5 v, f sw = 600 khz 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4 6 8 10 12 14 16 18 20 quiescent current (ma) input voltage (v) t j = ?40c t j = +25c t j = +125c 102 1 1-009 figure 9. quiescent current vs. v in
adp2386 data sheet rev. a | page 8 of 24 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 ? 40 ?20 0 20 40 60 80 100 120 pvin uvlo threshold (v) temper a ture (c) rising falling 102 1 1-010 figure 10 . pvin uvlo threshold vs. temperature 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 ?40 ?20 0 20 40 60 80 100 120 ss pull-u p current (a) temper a ture (c) 102 1 1-0 1 1 figure 11 . ss pin p ul l - u p current vs. temperature 570 580 590 600 610 620 630 ?40 ?20 0 20 40 60 80 100 120 frequenc y (khz) temper a ture (c) r t = 100k? 102 1 1-012 figure 12 . frequency vs. temperature 0.95 1.00 1.05 1.10 1.15 1.20 1.25 ? 40 ? 20 0 20 40 60 80 100 120 en threshold (v) rising falling temper a ture (c) 102 1 1-013 figure 13 . en threshold vs. temperature 594 596 598 600 602 604 606 ?40 ?20 0 20 40 60 80 100 120 feedback vo lt age (mv) temper a ture ( c) 102 1 1-014 figure 14 . feedback voltage vs. temperature 7.7 7.8 7.9 8.0 8.1 8.2 8.3 8.4 ?40 ?20 0 20 40 60 80 100 120 vreg vo lt age (v) temperature (c) 102 1 1-015 figure 15 . vreg voltage vs. temperature
data sheet adp2386 rev. a | page 9 of 24 temper a ture (c) 5 15 25 35 45 55 65 ?40 ?20 0 20 40 60 80 100 120 mosfet resis t or (m?) high-side r dson low-side r dson 102 1 1-016 figure 16 . mosfet r dson vs. temperature ch1 10mv ch2 10v m2.00 s a ch2 6v 1 3 2 t 50.2% b w ch3 2 a ? 102 1 1-017 v out (ac) i l sw figure 17 . working mode waveform ch1 2v ch2 5v m2.00 ms a ch2 2v 4 1 2 3 t 50% b w ch3 5a ch4 10v ? 102 1 1-018 en v out pgood i l fi gure 18 . voltage pre charged output temper a ture (c) 7.5 8.0 8.5 9.0 9.5 10.0 10.5 ?40 ?20 0 20 40 60 80 100 120 peak curren t -limit threshold (a) 102 1 1-019 figure 19 . current - limit threshold vs. temperature m2.00 m s a ch2 5.8v 4 1 2 3 t 50% 102 1 1-020 ? ch1 2v ch2 5v b w ch3 10v ch4 5a en v out pgood i out figure 20 . soft start with full load ch2 5v ch4 10v m1.00 s a ch4 7.8v 4 2 t 50% 102 1 1-021 sync sw figure 21 . external s ynchronization
adp2386 data sheet rev. a | page 10 of 24 ch1 100mv m200 s a ch4 2.8 a 1 4 t 70.4% b w ch4 2 a ? 102 1 1-022 v out (ac) i out figure 22 . load transient response, 1 a to 5 a ? ch1 2v ch2 10v m4.00 ms a ch1 2.12v 4 1 2 t 30.2% b w ch4 5 a 102 1 1-023 v out sw i l figure 23 . output short entry 0 1 2 3 4 5 6 7 25 40 55 70 85 100 load current (a) ambient temper a ture (c) v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 102 1 1-024 figure 24 . load current vs. ambient temperature at v in = 12 v, f sw = 600 khz ch1 20mv ch2 10v m1.00 m s a ch3 12.4v 1 2 3 t 20% b w b w b w ch3 5v 102 1 1-025 sw v in v out (ac) figure 25 . line transient response, v in from 8 v to 14 v, i out = 6 a ? ch2 10v ch4 5 a ch1 2v b w m4.00ms a ch1 2.12v 4 1 2 t 70.4% 102 1 1-026 v out sw i l figure 26 . output short recovery 0 1 2 3 4 5 6 7 25 40 55 70 85 100 load current (a) ambient temper a ture (c) v out = 1v v out = 1.2v v out = 1.8v v out = 2.5v v out = 3.3v v out = 5v 102 1 1-027 figure 27 . load current vs. ambient temperature at v in = 12 v, f sw = 3 00 khz
data sheet adp2386 rev. a | page 11 of 24 functional block dia gram + ? + 0.6v i ss ss fb comp amp control logic and mosfet driver with anticross protection bst sw v i_max hiccup mode nfet nfet v i_neg vreg pgnd 0.7v 0.54v ovp pvin vreg uvlo en en_buf slope ramp clk ? + neg current cmp + ? + ? 1.17v 4a 1a ocp cmp + ? + ? driver driver boost regulator bias and driver regulator a cs osc clk slope ramp deglitch sync rt pgood gnd 102 1 1-028 figure 28 .
adp2386 data sheet rev. a | page 12 of 24 theory of operation the adp2386 is a synchronous step - down, dc - to - dc regulator that uses a current - mode architecture w ith an integrated high - side power switch and a low - side synchronous rectifier. the regulator targets high performance applications that require high efficiency and design flexibility. the adp2386 operate s fro m an input voltage that ranges from 4.5 v to 20 v and regulate s the output voltage from 0.6 v to 90% of the input voltage . additional features that maximize design flexibility include the following : programmable switching frequency, programmable soft start , external compensation, precision enable, and a power - good output . control scheme the adp2386 uses a fixed frequency, peak current - mode pwm control architecture. at the start of each oscillator cycle, the hig h - side n - mosfet is turned on, putting a positive voltage across the inductor. when the inductor current crosses the peak inductor current th reshold , the high - side n - mosfet is turned off and the low - side n - mosfet is turned on . this puts a negative voltage a cross the inductor, causing the inductor current to decrease. the low - side n - mosfet stays on for the rest of the cycle (see figure 17) . precision enable/shu tdown the en input pin has a precision analog threshold of 1 .17 v (typical ) with 100 mv of hysteresis. whe n the enable voltage exceeds 1.17 v, the regulator turns on ; when it falls to less than 1.07 v (typical), the regulator turns off. to force the regulator to automatically start when input power is applied, connect en to pvin . the precision en pin has an internal pull - down current source (5 a) that provides a default turn - off when the en pin is open . when t he en pin voltage exceeds 1. 17 v (typical ), the adp2386 is enabled and the internal pull - down current source at the en pin decreases to 1 a , which allows user s to program the pvin uvlo and hysteresis. internal regulator ( vreg) the on - board regulator provides a stable supply for the internal circuits. it is recommended that a 1 f ceramic capacitor be placed between the vreg and gnd pins . the internal regulator includes a current - limit circuit to protect the output if the maximum external load current is exceeded. bootstrap circuitry the adp2386 includes a regulator to provide the gate drive voltage for the high - side n - mo sf et. it uses differential sensing to generate a 5 v bootstrap voltage between the bst and sw pins . it is recommended that a 0.1 f, x7r or x5r ceramic capacitor be placed between the bst pin and the sw pin. oscillator t he adp2386 switching frequency is controlled by the rt pin. a resistor from rt to gnd can program the switching frequency according to the following equat ion: f sw (khz) = 15 ) (k 69120 + ? t r a 100 k resistor sets the frequency to 600 khz, and a 42.2 k resistor sets the frequency to 1.2 m hz . figure 29 shows the typical relationship between f sw and r t . 1400 20 60 100 140 180 220 260 300 r t (k 1200 1000 800 600 400 200 0 freuenc y (khz) 102 1 1-029 figure 29 . switching frequency vs. r t s ynchronization t o synchro nize the adp2386 , connect an external clock t o the sync pin. t he external clock frequency can be in the range of 200 k hz to 1.4 mhz. during synchronization , the regulator operates in c ontinuous conduction mode (ccm) , and the rising edge of the switching wave form runs 180 out of phase to the rising edge of the external clock. when the adp2386 operates in synchronization mode, a resistor mus t be connected from the rt pin to gnd to program the internal oscillator to run at 90% to 110% of the external synchronization clock.
data sheet adp2386 rev. a | page 13 of 24 soft start the adp2386 has integrated soft start circuitry to limit the output voltage rising time and reduce inrush current at startup. the internal soft start time is calculated using the following equation: t ss_int = (ms) (khz) 1600 sw f a slower soft start time can be programmed by using the ss pin. when a capacitor is connected between the ss pin and gnd, an internal current charges the capacitor to establish the soft start ramp. the soft start time is calculated using the following equation: t ss_ext = upss ss i c _ v6.0 ? where: c ss is the soft start capacitance. i ss_up is the soft start pull-up current (3.2 a). the internal error amplifier includes three positive inputs: the internal reference voltage, the internal digital soft start voltage, and the ss pin voltage. the error amplifier regulates the fb voltage to the lowest of the three voltages. if the output voltage is charged prior to turn-on, the adp2386 prevents reverse inductor current that would discharge the output capacitor. this function remains active until the soft start voltage exceeds the voltage on the fb pin. power good the power-good pin (pgood) is an active high, open-drain output that requires an external resistor to pull it up to a voltage. a logic high on the pgood pin indicates that the voltage on the fb pin (and, therefore, the output voltage) is within regulation. the power-good circuitry monitors the output voltage on the fb pin and compares it to the rising and falling thresholds that are specified in table 1. if the rising output voltage exceeds the target value, the pgood pin is held low. the pgood pin continues to be held low until the falling output voltage returns to the target value. if the output voltage falls below the target output voltage, the pgood pin is held low. the pgood pin continues to be held low until the rising output voltage returns to the target value. the power-good rising and falling thresholds are shown in figure 30. there is a 1024-cycle waiting period (deglitch) before the pgood pin is pulled from low to high, and there is a 16-cycle waiting period (deglitch) before the pgood pin is pulled from high to low. 100% 116.7% 105% 90% 95% v out (%) pgood v out rising v out fallin g 1024 cycle deglitch 16 cycle deglitch 1024 cycle deglitch 16 cycle deglitch 10211-130 figure 30. pgood rising and falling thresholds peak current-limit and short-circuit protection the adp2386 has a peak current-limit protection circuit to prevent current runaway. during the initial soft start, the adp2386 uses frequency foldback to prevent output current runaway. the switching frequency is reduced according to the voltage on the fb pin, which allows more time for the inductor to discharge. the correlation between the switching frequency and the fb pin voltage is shown in table 5. table 5. fb pin voltage and switching frequency fb pin voltage switching frequency v fb 0.4 v f sw 0.4 v > v fb 0.2 v f sw /2 v fb < 0.2 v f sw /4 for protection against heavy loads, the adp2386 uses a hiccup mode for overcurrent protection. when the inductor peak current reaches the current-limit value, the high-side mosfet turns off and the low-side mosfet turns on until the next cycle. the overcurrent counter increments during this process. if the overcurrent counter reaches 10, or the fb pin voltage falls to 0.4 v after the soft start, the regulator enters hiccup mode. the high-side and low-side mosfets are both turned off. the regulator remains in hiccup mode for 4096 clock cycles and then attempts to restart. if the current-limit fault has cleared, the regulator resumes normal operation. otherwise, it reenters hiccup mode. the adp2386 also provides a sink current limit to prevent the low-side mosfet from sinking a lot of current from the load. when the voltage across the low-side mosfet exceeds the sink current-limit threshold, which is typically 2.5 a, the low-side mosfet turns off immediately for the rest of the cycle. both high- side and low-side mosfets turn off until the next clock cycle. in some cases, the input voltage (v pvin ) ramp rate is too slow or the output capacitor is too large for the output to reach regulation during the soft start process, which causes the regulator to enter the hiccup mode. to avoid such occurrences, use a resistor divider at the en pin to program the input voltage uvlo, or use a longer soft start time.
adp2386 data sheet rev. a | page 14 of 24 over v oltage protection (o vp) the adp23 86 includes an ov ervoltage protection feature to protect the regulator against an output short to a higher volta ge supply or when a strong load disconnect transient occurs. if the feedback voltage increases to 0.7 v, the in ternal high - side and low - side mo sfet s are turned off until the voltage at the fb pin decreases to 0.63 v . a t that time , the adp2386 resumes normal operation. under v oltage lockout (uvlo ) undervoltage lockout circuitry is integrated in the adp2386 to prevent the occurrence of power - on glitches. if the v pvin voltage fall s to less than 3.8 v typical, the part shuts down , and both the power switch and synchronous rectifier turn off. when the v pvin vo ltage rises to greater than 4. 3 v typical, the soft start period is initiated , and the part is enabled. thermal shutdown if the adp2386 junction temperatures rises to greater than 150 c, the internal thermal s hutdown circuit turns off the regulator for self - protection. extreme junction temperatures can be the result of high current operation, poor circuit board thermal design, and/o r high ambient temperature. a 2 5 c hysteresis is included in the thermal shut - do wn circuit so that , if an over temperature event occurs, the adp2386 does not return to normal operation until the on - chip temperature falls to less than 125 c. upon recovery, a soft start is initiated before n ormal operation begins .
data sheet adp2386 rev. a | page 15 of 24 applications information input capacitor sele ction the input capacitor reduces the input voltage ripple caused by the switch current on pvin. place the input capacitor as close as possible to the pvin pin. a ceramic capacitor in the 10 f to 47 f r ange is recommended. the loop that is composed of this i nput capacitor, the high - side n - mosfet, and the low - side n - mosfet must be kept as small as possible. the voltage rating of the input capacitor must be greater t han the maximum inp ut voltage. ensure that t he rms current rating of the input capacitor is larger than the value calculated from the following equation: i c in _ rms = i o ut ) 1 ( d d ? output voltage setti ng the output voltage of the adp2386 is set by an external resistive divider. the resistor values are calculated using v out = 0.6 ? ? ? ? ? ? ? ? + bot top r r 1 to lim it the output voltage accuracy degradation due to the fb bias current (0.1 a maximum) to less than 0.5% ( maximum), ensure that r bot < 30 k?. table 6 lists the recommended resistor divider values for the various output voltage s. table 6 . resistor divider values for various output voltage s v out (v) r top 1 % ( k? ) r bot 1 % ( k? ) 1.0 1.2 1.5 1.8 2.5 3.3 5.0 10 10 15 20 47.5 10 22 15 10 10 10 15 2.21 3 voltage conversion l imitations the minimum output voltage for a given input voltage and switching frequency is constrained by the minimum on time. the minimum on time of the adp2386 is typically 12 5 ns. the minimum output voltage for a given input voltage and switching frequency can be calculated using the following: v out_min = v in t min_on f sw ? ( r dson_hs ? r dso n_ls ) i out_min t min_on f sw ? ( r dson_ls + r l ) i out_min (1) where: v out_min is the minimum output voltage. v in is the input voltage. t min_on is the minimum on time. f sw is the switching frequency. r dson_hs is the high - side mosfet on resistance. r dso n_ls is the low - side mosfet on resistance. i out_min is the minimum output current. r l is the series resistance of the output inductor. the maximum output voltage for a given input voltage and switching frequency is constrained by the minimum off time and t he maximum duty cycle. the minimum off time is typically 200 ns, and the maximum duty cycle of the adp2386 is typically 90%. the maximum output voltage , limited by the minimum off time at a given input voltag e and switching frequency , can be calculated using the following equation: v out_max = v in (1 ? t min_off f sw ) ? ( r dson_hs ? r dson_ls ) i out_max (1 ? t min_off f sw ) ? ( r dson_ls + r l ) i out_max (2) where: v out_max is the maximum output voltage. v in i s the input voltage. t min_off is the minimum off time. f sw is the switching frequency. r dson_hs is the high - side mosfet on resistance. r dson_ls is the low - side mosfet on resistance. i out_max is the maximum output current. r l is the series resistance of the output inductor. the maximum output voltage , limited by the maximum duty cycle at a given input voltage , can be calculated using the following equation: v out_max = d max v in (3) where d max is the maximum duty cycle; v in is the input voltage. as shown in equation 1 to equation 3 , reducing the switching frequency alleviates the minimum on time and minimum off time limitation. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and inductor ripple cu rrent. using a small inductor value leads to a faster transient response ; however, it degrades efficiency, due to a larger inductor ripple current. u sing a large inductor value leads to smaller ripple current and better efficiency , but it results in a slow er transient response. as a guideline, the inductor ripple current, i l , is typically set to one - third of the maximum load curre nt. the inductor value is calcu lated using the following equation: l = sw l out in f i d v v ? ? ) ( where: v in is the input voltage. v out is the output voltage. d is the duty cycle (d = v out /v in ) . i l is the inductor current ripple. f sw is the switching frequency. the adp2386 uses adaptive sl ope compensation in the current l oop to prevent sub harmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value.
adp2386 data sheet rev. a | page 16 of 24 for a duty cycle that is larger than 50%, the minimum inductor value is determined using the following e quation: l (minimum) = sw out f d v ? 2 ) 1 ( the peak induc tor current is calculated by i peak = i o ut + 2 l i ? the saturation current of the inductor must be larger than the peak inductor current. for ferrite core inductors with a quick saturation characteri stic, the saturation current rating of the inductor must be higher than the current - limit threshold of the switch. this prevents the inductor from reaching saturation. the rms current of the inductor is calculated as follows: i rms = 12 2 2 l out i i ? + shielded ferrite core materials are recommended for low core loss and low emi. table 7 lists some recommended inductors. output capacitor sel ection the output capacitor selection affects the output ripple voltage load step tran sient and the loop stability of the regulator. for example , during a load step transient where the load is suddenly increased, the output capacitor supplies the load until the control loop can ra mp up the inductor current. the delay caused by the control l oop causes output undershoot. the output capacitance that is required to satisfy the voltage droop requirement can be calculated using the following equation: c out_uv = uv out out in step uv v v v l i k _ 2 ) ( 2 ? ? ? where: k uv is a factor, with a typical setting of k uv = 2. i step is the load step. v out_uv is the allowable undershoot on the output voltage. another example occurs when a load is suddenly removed from the output , and the energy stored in the inductor rushes into the output capacitor, causing the output to overs hoot. the output capacitance that is required to meet the overshoot requirement can be calculated using the following equation: c out_o v = 2 2 _ 2 ) ( out ov out out step ov v v v l i k ? ? + ? where: v out_ov is the allowable overshoot on the output voltage. k ov is a factor, with a typ ical setting of k ov = 2. the output ripple is determi ned by the esr and the value of the capacitance. use the following equation s to select a capacitor that can meet the output ri pple requirements: c out_ripple = ripple out sw l v f i _ 8 ? ? r esr = l ripple out i v ? ? _ where: i l is the inductor current ripple. v out_ripple is the allowable output ripple voltage. r esr is the equivalent series resista nce of the output capacitor in o hms (?) . select the largest output capacitance given by c out_uv , c out_ov , and c out_ripple to meet both load transient and output ripple performance. table 7 . recommended inductors vendor part no. value (h) i sat (a) i rms (a) dcr (m?) toko fdve0630 - r47m 0.47 15.6 14.1 3.7 fdve0630 - r75m 0.75 10.9 10.7 6.2 fdve0630 - 1r0m 1.0 9 .5 9.5 8.5 fdve1040 - 1r5m 1.5 13.7 14.6 4.6 fdve1040 - 2r2m 2.2 11.4 11.6 6.8 fdve1040 - 3r3m 3.3 9.8 9.0 10.1 fdve1040 - 4r7m 4.7 8.2 8.0 13.8 vishay ihlp3232dz - r47m - 11 0.47 14 25 2.38 ihlp3232dz - r68m - 11 0.68 14.5 22.2 3.22 ihlp3232dz - 1r0m - 11 1.0 12 18.2 4.63 ihlp4040dz - 1r5m - 01 1.5 27.5 15 5.8 ihlp4040dz - 2r2m - 01 2.2 25.6 12 9 ihlp4040dz - 3r3m - 01 3.3 18.6 10 14.4 ihlp4040dz - 4r7m - 01 4.7 17 9.5 16.5 wurth elektronik 744 325 120 1.2 25 20 1.8 744 325 180 1.8 18 16 3.5 744 325 240 2.4 17 14 4. 75 744 325 330 3.3 15 12 5.9 744 325 420 4.2 14 11 7.1
data sheet adp2386 rev. a | page 17 of 24 the selected output capacitor voltage rating must be greater than the output voltage. the rms current rating of the output capacitor must be larger than the value that is calculated by using th e following equation: i c out _ rms = 12 l i ? programming the input voltage uvlo the adp2386 has a precision enable input that can be used to program the uvlo threshold of the input voltage (see figure 31) . en en cmp adp2386 1.17v 4a 1a pvin r top_en r bot_en 102 1 1-030 figure 31 . programming the input v oltage uvlo use the following equation s to calculate r top_en and r bot_en : r top_en = a 1 v 17 . 1 a 5 v 07 . 1 v 17 . 1 v 07 . 1 _ _ ? ? falling in rising in v v r bot _en = v 17 . 1 a 5 v 17 . 1 _ _ _ ? ? en top rising in en top r v r where: v in_risin g is the v in rising threshold. v in_falling is the v in falling threshold. compensation design for peak current - mode control, the power stage can be simplified as a voltage controlled current source supplying current to the output capacitor and load resistor . it is composed of one domain pole and a zero that is contributed by the output capacitor esr. the control - to - output transfer function is based on the following : g vd ( s ) = ) ( ) ( s v s v comp out = a vi r ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + p z f s f s 2 1 2 1 f z = out esr c r 2 1 f p = out esr c r r + ) ( 2 1 where: a vi = 8.7 a/v. r is the load resistance. c out is the output capacitance. r esr is the equivalent series resistance of the output capacitor. the adp2386 uses a transcond uctance amplifier for the error amplifier and to compensate the system. figure 32 sho ws the simplified, peak current - mode control, small signal circuit. r esr r + ? g m r c c cp c out c c r top r bot ? + a vi v out v comp v out 102 1 1-031 figure 32 . simplified peak current mode c ontrol , s mall signal c ircuit the compensation components, r c and c c , contribute a zero , and r c and the optional c cp contribute an optional pole. the closed - loop transfer equation is as follows: t v ( s ) = + ? + cp c m top bot bot c c g r r r 1 () (1 ) cc vd cccp c cp rcs gs rcc ss cc + + + the following design guideline shows how to select the r c , c c , and c cp compensation components for ceramic output capacitor applications: 1. determine the cross frequency , f c . generally, f c is between f sw /12 and f sw /6. 2. calculate r c , using the following equation: r c = vi m c out out a g f c v v 6 . 0 2 3. place the compensation zero at the domain pole , f p ; then determine c c by using the following equation: c c = c out esr r c r r + ) ( 4. c cp is optional. it can be used to cancel the zero caused by the esr of the output capacitor. c cp = c out esr r c r adi sim power design tool the adp2386 is supported by the adisimpower ? design tool set. adisimpower is a collection of tools that produce complete power designs that are optimized for a speci fic design goal. the tools enable the user to generate a full schematic and bill of materials and calculate performance in minutes. adisimpower can optimize designs for c ost, area, efficiency, and part count, while taking into consideration the operating c onditions and limitations of the ic and all real external components. for more information about theadisimpower design tools, refer to www.analog.com/adisimpower . the tool set is available from this websit e, and users can request an unpopulated board.
adp2386 data sheet rev. a | page 18 of 24 design example adp2386 bst fb comp pgood gnd rt sync vreg ss sw pgnd en pvin v in = 12v c ss 22nf c out1 100 f 6.3v c out2 47 f 6.3v c vreg 1f c bst 0.1f r t 100k? l1 2.2f v out = 3.3v c c 1.2nf c cp 4.7pf r c 44.2k? r top 2.21k? 1% 102 1 1-033 r top 10k? 1% c in 10f 25v figure 33 . schematic for design e xample this section describes the procedures for selecting the external components , based on the example specifications that are li sted in table 8 . see figure 33 for the schematic of this design example. table 8 . step - down dc -to - dc regulator requirements parameter specification input voltage v in = 12.0 v 10 % output voltage v out = 3.3 v output current i out = 6 a output voltage ripple ? v out_ripple = 33 mv load transient 5%, 1 a to 5 a, 2 a/s switching frequency f sw = 600 khz output voltage setti ng choose a 10 k? resistor as the top feedback resistor (r top ) , and calculate the bottom feedback resistor (r bot ) by using the following eq uation: r bot = r top ? ? ? ? ? ? ? ? ? 6 . 0 6 . 0 out v to set the output voltage to 3.3 v, the resistors values are as follows: r top = 10 k?, and r bot = 2.21 k? . frequency setting to set the switching frequency to 600 khz, connect a 100 k? resistor from the rt pin to gnd. inductor selection the peak - to - peak inductor ripple current, ?i l , is set to 30% of the maximum output current. use the following equation to estimate the inductor value: l = sw l out in f i d v v ? ? ) ( where: v in = 12 v . v out = 3.3 v . d = 0.275 . ?i l = 1.8 a . f s w = 600 khz . this calculation results in l = 2.215 h. choose the standard inductor value of 2.2 h. the peak - to - peak inductor ripple current can be calculated by using the following equation: i l = sw out in f l d v v ? ) ( this calculation results in ?i l = 1.81 a. use the following equation to calculate t he peak induc tor current : i peak = i out + 2 l i ? this calculation results in i peak = 6.905 a. use the following equation to calculate t he rms current flowing through t he inductor : i rms = 12 2 2 l out i i ? + this calculation results in i rms = 6.023 a. based on th e calculated current value, select an inductor with a minimum rms current rating of 6.03 a and a minimum saturation current rating of 6.91 a. however, to protect the induc tor from reaching its sat uration point under the current - limit condition, the inductor should be rated for at least a 9 .6 a saturation current for reliable operation. based on the requirements described previously , select a 2.2 h induct or, such as the fdve1040 - 2r2m from toko , which has a 6. 8 m? dcr and a 11.4 a saturation current.
data sheet adp2386 rev. a | page 19 of 24 output capacitor sel ection the output capacitor is required to meet both the output voltage ripple and load transient response requirement s. to meet the output voltage ripple requirement, use the following equation to calculate the esr and capacitance value of the output capacitor: c out_ripple = ripple out sw l v f i _ 8 ? ? r esr = l ripple out i v ? ? _ this calculation results in c out_ripple = 11.4 f, an d r esr = 18 m?. to meet the 5% overshoot and undershoot transient requirements, use the following equations to calculate the capacitance: c out_ov = 2 2 _ 2 ) ( out ov out out step ov v v v l i k ? ? + ? c out_u v = uv out out in step uv v v v l i k _ 2 ) ( 2 ? ? ? where: k ov = k uv = 2 are the coefficients for est imation purpose s. ? i step = 4 a is the load transient step. ? v out_ov = 5% v out is the overshoot voltage. ? v out_uv = 5% v out is the undershoot voltage. this calculation results in c out_ov = 63.1 f, and c out_uv = 24.5 f. according to the calculation, the ou tput capacitance must be greater than 63 f, and the esr of the output capacitor must be smaller than 18 m?. it is recommended that one 100 f/x5r/ 6.3 v ceramic capacitor and one 47 f/x5r/6.3 v ceramic capacitor be used, such as the grm32er60j107me20 and grm32er60j476me20 from murata, with an esr of 2 m?. compensation compone nts for better load transient and stability performance, set the cross frequency, f c , to f sw /10. in this case, f sw is running at 600 khz; therefore, the f c is set to 60 khz. the 100 f and 47 f c eramic output capacitors have a derated value of 62 f and 32 f. r c = 2 3.3v 94 f 60 khz 0.6 v 480 s 8.7 a/ v = 4 6.7 k? c c = (0.55 0.002 ) 94 f 46.7 k ?+ ? = 11 11 pf c c p = 0.002 94 f 46.7 k ? = 4.0 pf cho ose standard components, as follows: r c = 44.2 k?, c c = 1200 p f, and c cp = 4.7 p f. figure 34 s hows the bode plot at 6 a. t he cross frequency is 58 khz, and the phase margin is 61 . 1k 10k 100k frequenc y (hz) 1m 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 180 144 108 72 36 0 ?36 ?72 ?108 ?144 ?180 phase (degrees) magnitude (db) 102 1 1-134 figure 34 . bode plot at 6 a soft start time prog ram the soft start feature all ows the output voltage to ramp up in a controlled manner, eliminating output volt age overshoot during soft start and limiting the inrush current. set the soft start time to 4 ms. c ss = v 6 . 0 a 2 . 3 ms 4 6 . 0 _ _ = up ss ext ss i t = 2 1.3 nf choose a standard component value , as follows: c ss = 22 n f. input capacitor sele ction place a minimum 10 f ceramic capacitor near the pvin pin. in this application, it is recommended that one 10 f, x5r, 25 v ceramic capacitor be used .
adp2386 data sheet rev. a | page 20 of 24 recommended external components table 9 . recommended external components for typical applications with 6 a output current f sw (khz) v in (v) v out (v) l (h) c out (f) 1 r top (k?) r bot (k?) r c (k?) c c (pf) c cp (pf) 300 12 1 1.5 680 + 2 100 10 15 57.6 2200 150 12 1.2 2.2 680 + 2 1 00 10 10 68.1 2200 120 12 1.5 2.2 680 15 10 73.2 2200 100 12 1.8 3.3 680 20 10 88.7 2200 82 12 2.5 3.3 470 47.5 15 84.5 2200 47 12 3.3 4.7 3 100 10 2.21 44.2 2200 8.2 12 5 4.7 100 + 47 22 3 33 2200 4.7 5 1 1.5 680 + 2 100 10 15 57.6 2200 150 5 1.2 1.5 680 10 10 57.6 2200 120 5 1.5 2.2 680 15 10 73.2 2200 100 5 1.8 2.2 470 20 10 61.9 2200 82 5 2.5 2.2 3 100 47.5 15 33 2200 10 5 3.3 2.2 3 100 10 2.21 44.2 2200 8.2 600 12 1.5 1 3 100 15 10 39 1200 10 12 1.8 1.5 3 100 20 1 0 47 1200 8.2 12 2.5 2.2 2 100 47.5 15 44.2 1200 4.7 12 3.3 2.2 100 + 47 10 2.21 44.2 1200 4.7 12 5 3.3 100 22 3 44.2 1200 2.2 5 1 1 680 10 15 97.6 1200 68 5 1.2 1 470 10 10 82 1200 47 5 1.5 1 3 100 15 10 39 1200 10 5 1.8 1 2 100 20 10 33 1200 8.2 5 2.5 1 100 47.5 15 22 1200 4.7 5 3.3 1 100 + 47 10 2.21 44.2 1200 4.7 1000 12 2.5 1 100 47.5 15 37.4 680 3.3 12 3.3 1.5 100 10 2.21 47 680 2.2 12 5 1.5 100 22 3 73.2 680 2.2 5 1 0.47 3 100 10 15 44.2 680 8.2 5 1.2 0.47 2 100 1 0 10 34.8 680 6.8 5 1.5 0.68 100 + 47 15 10 33 680 4.7 5 1.8 0.68 100 + 47 20 10 39 680 4.7 5 2.5 0.68 100 47.5 15 37.4 680 3.3 5 3.3 0.68 100 10 2.21 47 680 2.2 1 680 f: 4 v, sanyo 4tp f 680m ; 470 f: 6.3 v, sanyo 6tp f 470m ; 100 f: 6.3 v, x5r, murata grm32er60j107me20; 47 f: 6.3 v, x5r, murata grm32er60j476me20 .
data sheet adp2386 rev. a | page 21 of 24 circuit board layout recommendations good printed circuit board (pcb) layout is essential for obtaining the best performance from the adp2386 . poor pcb layout can degrade the output regulation, as well as the electromagnetic interference (emi) and electromagnetic compatibility (emc) performance. figure 36 shows an example of a good pcb layout for the adp2386 . for optimum layout, refer to the following guidelines: ? use separate analog ground planes and power ground planes. connect the ground reference of sensitive analog circuitry, such as output voltage divider components, to analog ground. in addition, connect the ground reference of power components, such as input and output capacitors, to power ground. connect both ground planes to the exposed gnd pad of the adp2386 . ? place the input capacitor, inductor, and output capacitor as close as possible to the ic, and use short traces. ? ensure that the high current loop traces are as short and as wide as possible. make the high current path from the input capacitor through the inductor, the output capacitor, and the power ground plane back to the input capacitor as short as possible. to accomplish this, ensure that the input and output capacitors share a common power ground plane. in addition, ensure that the high current path from the power ground plane through the inductor and output capacitor back to the power ground plane is as short as possible by tying the pgnd pins of the adp2386 to the pgnd plane as close as possible to the input and output capacitors. ? connect the exposed gnd pad of the adp2386 to a large, external copper ground plane to maximize its power dissipation capability and minimize junction temperature. in addition, connect the exposed sw pad to the sw pins of the adp2386 , using short, wide traces; or connect the exposed sw pad to a large copper plane of the switching node for high current flow. ? place the feedback resistor divider network as close as possible to the fb pin to prevent noise pickup. minimize the length of the trace that connects the top of the feedback resistor divider to the output while keeping the trace away from the high current traces and the switching node to avoid noise pickup. to further reduce noise pickup, place an analog ground plane on either side of the fb trace and ensure that the trace is as short as possible to reduce the parasitic capacitance pickup. adp2386 bst fb comp pgood gnd rt sync vreg ss sw pgnd en pvin v in c vreg c in c out r t l c bst v out r top r bot c ss c c r c 10211-033 figure 35. high current path in the pcb circuit s w sw pow er ground plane pvin vout output capacitor input bulk cap input bypass cap inductor sw gnd vreg c v r e g c b s t fb comp pgnd g n d s w sw bst pvin pv in pvin p g n d p g n d p g n d p g n d p g n d s w e n p v i n r t o p p g o o d r t s y n c s s c s s c c c c p r t r c r b o t p u l l u p + via bottom layer trace analog ground plane copper plane 10211-034 figure 36. recommended pcb layout
adp2386 data sheet rev. a | page 22 of 24 typical application s circuit s adp2386 bst fb comp pgood gnd sync sw pgnd en pvin v in = 12v c in 10f 25v c out1 470f 6.3v c out2 10f 6.3v l1 1h c bst 0.1f v out = 1.2v r top 10k? 1% r bot 10k? 1% c cp 68pf c c 1.5nf r c 66.5k? vreg rt ss c ss 22nf c vreg 1f r t 124k? 102 1 1-035 figure 37 . typical a pplication s c ircuit, v in = 12 v, v out = 1.2 v, i out = 6 a, f s w = 500 khz adp2386 bst fb comp pgood gnd sync sw pgnd en pvin v in = 12v c in 10f 25v c out1 100f 6.3v c out2 100f 6.3v c out3 100f 6.3v l1 1.5h c bst 0.1f v out = 1.8v r top 20k? 1% r bot 10k? 1% c cp 8.2pf c c 1.2nf r c 47k? rt vreg ss c vreg 1f r pgood 100k? r t 100k? 102 1 1-038 figure 38 . typical applications circuit using internal soft s tart, v in = 12 v, v out = 1.8 v, i out = 6 a, f s w = 600 khz adp2386 bst fb comp pgood gnd sync sw pgnd en pvin v in = 12v c in 10f 25v c out 100f 6.3v l1 3.3h c bst 0.1f v out = 5v r top 22k? 1% r bot 3k? 1% c cp 2.2pf c c 1.2nf r c 44.2k? rt vreg ss c vreg 1f c ss 22nf r bot_en 2k? r top_en 16.9k? r t 100k? 102 1 1-039 figure 39 . programming input voltage uvlo rising threshold at 11 v, falling threshold at 10 v , v in = 12 v, v out = 5 v, i out = 6 a, f s w = 600 khz
data sheet adp2386 rev. a | page 23 of 24 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.25 0.20 0.15 compliant to jedec standards mo-220-wggd . bot t om view top view pin 1 indic a t or 4.10 4.00 sq 3.90 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref 0.20 min 0.20 min 0.20 min 0.20 min coplanarity 0.08 pin 1 indic a t or 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 2.80 2.70 2.60 1.05 0.95 0.85 0.45 0.35 0.25 1.50 1.40 1.30 01-14-2013-b exposed pa d exposed pa d figure 40 . 24 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 24 - 12) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adp2386acpzn -r 7 ? 40 c to +12 5 c 24- lead lfcsp_wq, 7 tape and reel cp -24-12 adp2386 - evalz ev aluation board adp2386bb - evalz inverting buck - boost evaluation board 1 z = rohs compliant part.
adp2386 data sheet rev. a | page 24 of 24 notes ? 2012 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10211 - 0 - 4/13(a)

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