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specifications (yoo= +5v :t5%, vss= -15v ::1:5%, fclk=1.28mhz. all specifications tmin to tmax unless othelwlse noted.) parameter accuracy resolution integral nonlinearity @ 25c t,run to t=x differential nonlinearity unipolaroffseterror@ + 25c tmintot=x unipolarfullscaleerror@ + 25c bipolar zero error@ + 25c tmintot=x bipolar full scale error2 @ + 25c full scale tc3,4 k,b versions' 12 :d :!:i :!:i :!:8 :!:8 :!: 15 :!:9 :!: 15 :!:io :!:45 analog inputs input ranges unipolar 0'0 +5 oto + 10 -5to+5 -10'0+10 bipolar input current unipolar bipolar internal reference voltage vrefoutput@ +25c vref output tc output current sink capability' 3 :!:0.4 -5.2/-5.3 :!:40 550 power supply rejection vddonly :!: 1/2 vssonly :!: 1/2 loglc inputs cs,nor/cmp,bin/2sc convst, clkin vinl, input low voltage vinh, input high voltage cin" input capacitance cs, nor/cmp, bin/2sc convst iin,inputcurrent clkin iin,inputcurrent logic outputs sdo, sclk, clkosc, sync vol, output low voltage v oh, output high voltage floating state leakage current sdo floating state output capacitance' +0.8 +2.4 10 :!:io :!:20 +0.4 +4.0 :!:io 15 10.2 conversion time power requirements vdd vss 100' iss' power dissipation +5 -15 7 12 135 215 l versionl 12 :!: 1/2 :!: 1/2 :!:i :!:4 :!:4 :!:io :!:5 :!:9 :!:7 :!:35 oto +5 oto + 10 -5to +5 -loto +10 3 :!:0.4 - 5.2/- 5.3 :!:25 550 :!: 1/2 :!: 1/2 +0.8 +2.4 10 :!:io :!:20 +0.4 +4.0 :!:io 15 10.2 +5 -is 7 12 135 215 notes 'temperature range as follows: k, l versions: 0 to + 70c b, c versions: - 25c to + 85"<: 'lncludes internal voltage reference error. - 'full scale tc = 6fs/6 t, where 6fs is full scale change from t a = + 2s"c to t m;o or t m..' 'includes internal voltage reference drift. 'sample tested to ensure compliance. 'power supply current is measured when ad7772 is inactive, i.e., cs= convst = sync = high. specifications suhject to change without notice. c version' 12 :!: 1/2 :!:3/4 :!:i :!:4 :!:4 :!:io :!:5 :!:9 :!:7 :!:35 oto +5 oto +10 -5to +5 -loto+1o 3 :!:0.4 -5.2/-5.3 :!:25 550 :!: 1/2 :!:1/2 +0.8 +2.4 10 :!:io :!:20 +0.4 +4.0 :!:io is 10.2 +5 -is 7 12 135 215 -2- units bits lsbmax lsbmax lsbmax lsbmax lsbmax lsbmax lsbmax lsb max ppmrc max volts volts volts volts mamax mamax v,ruoly =x ppm/oc typ ",amax lsbtyp lsbtyp vmax v min pfmax ",amax ",amax vmax vmin ",amax pfmax ",smax vnom vnom mamax ma max mwtyp mwmax test conditions/comments tested range: oto + 5v no missing codes guaranteed t min to t max input range: ot05v oroto 10v typical tc is 2ppmrc input range: ot05v oroto 10v input range: :!: 5v or:!: 10v input range: :!: 5v or :!: iov input range: 0 to 5v or 0 to iov inputrange: :!: 5vto:!: 10v -5.2sv:!:i% (external load should not change during conversion.) fschange, vss = -15v vdd= +4.75vto +5.25v fschange, vdd = +5v vss= -14.25vto -15.75v vdd = 5v:!:5% vin = otovdd vin = otovdd isink = 1.6ma isource = 200",a fclk = 1.28mhz. see control inputs synchronization. :!: 5% for specified performance :!: 5% for specified performance cs = convst = voo,ain = sv cs = convst = vdd,ain = 5v obsolete
) timing characteristlcs1 (voo= +5v, vss= -15v) limit at + 25c limit at t min, t max parameter (all grades) (k, l, b, c grades) units conditions/comments t,2 780 780 nsmin clkincycletime t2 40 50 ns max propagation delay between clkin and clkosc t3 545 560 nsmax propagationdelaybetweenclkinandsclk t/ 780 780 ns mill sclk cycle time t5 45 45 nsmin cstoconvstsetuptime t63 0 0 ns mill cs to sync hold time t7 40 50 ns mill convst pulse width t8 50 50 nsmax sclkj: to sync t. delay t9 60 65 ns max sclk j: to sync j: delay tlo4 50 50 nsmax sclkj: tosdot. delay,cl = 20pf 100 125 nsmax sclkj: tosdt. delay,cl= 1o0pf tll4 115 145 nsmax sclkj: to data valid, cl =20pf 190 235 nsmax sclkj: to data valid, cl = 1o0pf tl/ 10 10 nsmin sclk~ to sdo high impedance 65 80 nsmax notes ltiming specifications are sample tested at + 25c to ensure compliance. all input control signals are specified with tr = tf = 5ns (10% to 90% of + 5v) and timed from a voltage level of 1.6v. 'clkin mark/space ratio range is 55/45 to 45/55. 3sclk and sync are loaded with the circuit of figure i. 4tlo and tll are measured with the load circuit of figure 2 and defined as the time required for an output to cross o.8v or 2av. 't" is defined as the time required for the data lines to change o.5v when loaded with the circuit of figure 3. specifications subject to change without notice. +5v 3k!l ~ 25pf 3k!l cl ogno ~ *. + 5v3k!l sod cl ~ ogno sod 3k!l t 20pf ogno \7 ~ + 5v3k!l sod 20pf ~ ogno 3k!l ) sclk, sync sod figure 1. sclk, sync load circuit a. to voh (t71) b. to vol (t1o' t71) figure 2. load circuits for t1o' t71 test a. voh to high-z b. vol to high-z figure 3. load circuits for bus relinquish time test (ti2). clkin 5v ov clkdsc sclk cs 1 1 &. t5.1 ~ i 1 i+t7+1 ~ fj t6 j,." i i 5v ov i i -., ~t11 :sy 1 i 1 i 1 --t t9 l+- i y i --+j 5v ov cdnvst sod high impedance i i i -+i 14- t8 i"l 1 t10 1 i4-+t 1 1 \ ) sync 0 i4-t'2 } high impedance 11 ~t:d l figure 4. ad7772 timing diagram. -3- - -~ obsolete
absolute maximum ra tings* (ta = +2socunlessotherwisenoted) vddtodgnd -0.3vto+7v vsstodgnd. . . . . . . . . . . . . . . . . +o.3vto -17v agnd to dgnd . . . . . . . . . .. -o.3v to vdd +o.3v analog input voltage to agnd (bofs, :tiov, :t 5v, sum, +iov,+5v) -isvto+15v digital input voltage to dgnd (clk in, cs, convst, nor/cmp, bin/2sc) . . . . . . . . . . . . . . -o.3v to vdd +o.3v digital output voltage to dgnd (sdo, sclk, sync, ckosc) -o.3v to vdd +o.3v operating temperature range commercial (k, l versions) . . . . . . . . .. 0 to + 70c industrial (b, c versions) -25c to +85c storage temperature. . . . . . . . . . . . - 65c to + 150c power dissipation (any package) to + 75c. . . .. 450mw derates above + 75c by . . . . . . . . . . . . . . . 6mwjdc ( .stress above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other condition above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any onetime. caution: esd (electro-static-discharge) sensitive device. the digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electro- static fields. unused devices must be stored in conductive foam or shunts. the foam should be dis- charged to the destination socket before devices are removed. warning! ~ ~~device ordering information i ( notes i analog devices reserves the right to ship either ceramic or cerdip hermetic packages. 2plcc: plastic leaded chip carrier. pricing u.s. 100 + ad7772kn$35.00 ad7772ln $40.00 ad7772kp $40.00 ad7772lp $46.00 ad7772BQ $40.00 ad7772cq $45.00 ( -4- accuracy fun scale tc grade oto + 70c - 25c to + 85c -- - plastic dip hermetic 45ppmjdc :t ilsb ad7772kn ad7772BQ 35ppmjdc :t l/2lsb ad7772ln ad7772cq plcc2 45ppmjdc :t ilsb ad7772kp 35ppmjdc :t l/2lsb ad7772lp obsolete
pin configurations dip plcc . ~~g:s~ ~ g en ~ ~ u 181sync ad7772 top view (not to scale) ad7772 top view (not to scale) oofs i 8 141 clkin pin function description ) description analog input pin. this is connected as in figure 9 to provide a + 5v analog input range. analog input pin. this is connected as in figure ii to provide a + jov analog input range. voltage reference output. the ad7772 has its own internal - 5 .25v reference. analog ground analog input pin. this is connected to the inverting terminal of an op amp for::!: 5v to ::!: 10v analog input ranges. see figure 13. analog input pin. figure 13 shows how this is connected for a ::!: 5v analog input range. analog input pin. for::!: jov analog input range see figure 13. bipolar offset pin. this is tied to v ref for either ofthe bipolar analog input ranges. see figure 13. - nor/cmp and bin/2sc determine the format ofthe output data. see table i. digital ground serial data output continuously running serial clock output. clock oscillator pin. an inverted clkin signal appears at clkosc when external clock is used. see clkin (pin 14) description for crystal (resonator). clock input pin. an external ttl compatible clock may be applied to this pin. alternatively a crystal or ceramic resonator may be applied between clkin and clkosc. see figure 7. bin/2sc and nor/cmp determine the output data format. see table i. conversion start input. this signal starts a conversion on its rising edge when cs is low. chip select input. this active low signal, in conjunction with convst, starts a conversion. this is the framing signal for the serial data output. it goes low on the first rising edge of sclk after conversion begins and goes high when conversion is complete. negativesupply, -15v positive supply, + 5v table i. ad7772 output coding -5- pin mnemonic i +5v 2 +iov 3 vref 4 agnd 5 sum ) 6 ::!:5v 7 ::!:iov 8 bofs 9 nor/cmp 10 dgnd 11 sdo 12 sclk 13 clkosc 14 clkin is bin/2sc 16 convst 17 cs 18 sync 19 vss 20 vdd unipolar bipolar nor/cmp bin/2sc data format data format 0 0 2s complement complementary 2s complement 0 i straight binary complementary offset binary i 0 complementary 2s complement 2s complement i i complementary binary offset binary obsolete
20-pin ceramic dip (suffix q) d~~~~u~::' i- 1.000 ".0" -i 125." ".25' i ~,.. :om ~ ~~o"...oo, j ~ l ~ =..- io."";po'" 0." iwi tvp "."".131 - 0.'" .0.- "'.06 ".131 tol non accum 0.'" ".0" it." ...", 0."0".'" (u,::: ) ' -0.03 10tes. lead number 1 ident~ied bt dot or notch. leads will be either gold or tin plated in accordance with mil.m."'" reouirements. terminology mechanical information outline dimensions dimensions shown in inches and (mrn). 20-pin cerdip (suffix q) 20-pin plastic dip (suffix n) ( c:::::::i~ i 0.935 123.751 0.20 150lf~ 014 13.561-j u . 015 13.8' '. -i ~ o:m--rrm u -11-- 0.11 12.791 -,- 007 1.78 ..o~~ i~::\i 0.0912.28' 0:05 1.271 . c:::::::jf~ i 1.07127.181 i max .,."~~ 0.125 13.1751 u u min -,- -j i-- i-- 0.06511.6610.02110.533 0.1112.79' o:d45lti5f 0.015 0.381 0.09 12.28' lead no.1 identified by dot or notch leads are solder or tln.plated kovar or alloy 42 20-terminal plastic leaded chip carrier (suffix p) ~ '~:~~~:~~iso ~ 0.353 ad.do3 l- -~ ib."6 a:"6i so.~ ~- " 0.04' .0.do3 no.1 pin 11.143 .00161 'dentirer 0.020 10.511 max l- r-:! ~ ' 0.02 max 10.511 tdp view -.j j.- o.oso 11.271 least significant bit an adc with 12-bit resolution can resolve one part in 212 (1/4096 of full scale). for the ad7772 operating in the 0 to + 5v range, llsb is 1.22mv. no missing codes a specification which guarantees no missing codes requires that every code combination appear in a monotonic increasing sequence as the analog input level is increased. thus every code must have a finite width. for all grades of the ad7772, all 4096 codes are present over the entire operating temperature ranges. unipolar offset error for the unipolar analog input range, the first transition should occur at a level 1/2lsb above agnd. unipolar offset error is defined as the deviation of the actual transition from that point. this error can be adjusted as explained further on in this data sheet. bipolar zero error in the bipolar analog input ranges, bipolar zero is defined as the middle of code 2048. bipolar zero error is the actual deviation from that point. the circuit diagram on page 9 shows how to adjust this. o 173 ".dob ' [q: 4:3b5 ao.'85' 0105 ao.o1' li665 ao.3751 ~ ro~2,~ m'n ~ r ~s': :::.\ l3 ~~~min 0.060 11.'3im'n unipolar full scale error the last transition in the adc (from 111 . . .110 to 111 . . .111 when using straight binary coding) should occur for an analog value 1 1/2lsb below the nominal full scale (4.99816 for 5.000 volts full scale). the full scale error is the deviation of the actual level at the last transition from the ideal level with unipolar offset error adjusted to zero. this error can be trimmed out as shown in figure 12. the temperature coefficients for each grade indicate the maximum change in the full scale gain from the initial value using the internal - 5.25 volts reference. bipolar full scale error in the bipolar mode, the adc has a positive full scale error and a negative full scale error. positive full scale error is the deviation of the actual level at the last transition from the ideal level, with bipolar zero error adjusted to zero. negative full scale error is the deviation of the actual level at the first transition from the ideal level, with bipolar zero error adjusted to zero. full scale error is defined as either positive full scale error or negative full scale error, whichever is largest. -6- obsolete
1 circuit information converter details conversion start on the ad7772 is controlled by the cs and convst inputs. figure 5 shows the operating signals of interest. with cs held permanently low, a positive-going edge on convst starts the conversion cycle. the successive approximation register (sar) is reset at this stage. on the next rising edge of sclk, the sync output goes low and the three-state data output (sdo) is enabled. during conversion, the internal 12-bit dac is sequenced by the sar from the most significant bit (msb) to the least significant bit (lsb). bit decisions are made by the comparator (zero crossing detector) which checks the addition of each successive weighted bit from the dac output against the analog input. the msb decision is made and latched to the serial data output 90ns (typically) after the second rising edge of sclk following the conversion start. similarly, the succeeding bit decisions are made and latched approximately 90ns after the sclk rising edges. when conversion is complete, the sdo output is latched to the high impedance state and the sync output goes high. ) sclk ~{lf1..fl i if convst --u i 13 clock cycles1~ ,- i ' : :,(~ ~ 149011s typ high-z \ idb11~;:::xdbox high-z sync sdo figure 5. operating waveforms using an external clock source for clkin control inputs synchronization conversion time for the ad7772 is defined as the time for which the sync output is low. this is always 13 clock cycles. however, there is a delay between convst going high and sync going low. without synchronization this delay can vary from zero to an entire clock period. if a constant delay is required here, then the following approach can be used: when starting a conversion convst must go high on either the rising edge of clkin or the falling edge of clkosc. bofs ;o10v +10v rc 20kl! re ski! rf ski! 2.skl! oj ad7772 figure 6. ad7772 analog input stage n__- _n driving the analog input figure 6 shows the analog input stage for the ad7772. there are four application resistors (ra, rb, rc and rn). these can be used with one external op amp to implement::':: 5v and::':: jov analog input ranges. ra is always connected to vref for these ranges and offsets the input signal by + 2.5v. rc and rn provide an attenuation of 2 for the::':: 5v input while ri!> rc and rf) attenuate the::':: jov input by 4. the external op amp is connected as an inverting amplifier with its output driving pins i and 2 and rf) as the feedback resistor. figure 13 shows the circuit configuration. the + 5v and + lov inputs on the ad7772 connect to the comparator input via the 5ki! resistors re and rf. the dac which has 2.5ki! output impedance also connects to this point. during conversion, current from the analog input is modulated by the dac output current at a rate equal to the clkin frequency (1.28mhz maximum). this causes voltage spikes (glitches) to appear at the analog input. the magnitude and settling time of these glitches depends on the open-loop output impedance and small signal bandwidth of the amplifier or sample-and-hold driving the input. these devices must have sufficient drive to ensure that the glitches have settled within one clock period. an example of a suitable op amp is the ad op-27. the magnitude of the largest glitch when using this device to drive the analog input is typically ilmv with a 200ns settling time. suitable devices capable of driving the ad7772 analog inputs are the ad op-27 and ad7ll op amps and the ad585 sample-and- hold. internal clock oscillator figure 7 shows the ad7772 internal clock circuit. a crystal or ceramic resonator may be connected as in figure 7 to provide a clock oscillator for the adc timing. resistors ri and r2 ensure that the clkin mark/space ratio stays between 45/55 and 55/45. alternatively, the crystal/resonator may be omitted and an external clock source connected to clkin. the mark/space ratio of the external clock must be in the range 45/55 to 55/45. an inverted clkin signal will appear at the clkosc output pin. ad7772 clock notes *1.28mhz crystal/ceramic resonator. hcl and c2 capacitance values depend on crystal/ceramic resonator manufacturer. typical values are from 30pf to 100pf. figure 7. ad7772 internal clock circuit -7- obsolete
internal reference the ad7772 has an on-chip, buffered, temperature compensated, buried zener reference, which is factory trimmed to - 5.25v :!:: 1%. it is internally connected to the dac and is also available at pin 3 to sink up to 550fj..a current from an external load. for minimum code transition noise, the reference output should be decoupled with a capacitor to filter out wideband noise from the reference diode (lofj..f tantalum in parallel with 1o0nf ceramic). however, large values of decoupling capacitors can affect the dynamic response and stability ofthe reference amplifier. a ion resistor in series with the decoupling capacitors will eliminate this problem without adversely affecting the filtering effect of the capacitors. a simplified schematic of the reference with its recommended decoupling components is shown in figure 8. ad7772 figure 8. ad7772 internal - 5.25v reference appl ying the ad7772 the ad7772. has a flexible input stage with application resistors which can be configured for various analog input ranges. the following sections show the ad7772 configured for these ranges. unipolar opera non figure 9 shows the ad7772 connected for the unipolar 0 to + 5v input range. the ideal input/output characteristic for this range is given in figure 10. the designed code transitions occur midway between successive integer lsb values (i.e., 1/2lsb, 3/2lsbs, s/2lsbs . . .fs - 3/2lsbs). the output code is straight binary (see table i) with an lsb size of fs/4096 = s/4096v = 1.22mv. to change to complementary binary coding, nor/cmp should be tied to + sv. ad7772* ra 21k oto +5v analog input note 'additional pins omitted for clarity figure 9. unipolar 0 to + 5v input range -- output code full scale 11 (st:~:g i ht binary) tr 7 ansition 11...110 11...101 , , 1'1' i i' fs = 5v , i' fs 1'/ 1lsb = 4096 00. .011 tl ' / 00. .010 00. .001 00. .000 -------- 0 1 2 3 lsb lsbs lsbs ( +--of t fs fs -1lsb ain, input voltage (in terms of lsbs) figure 10. ideal input/output transfer characteristic for figure 9 figure 11 shows how the ad7772 can be connected for a 0 to + iov input range. the + sv pin is now connected to ov, thereby attenuating the input by 2 and effectively doubling the analog input range. the analog input is applied to the + iov pin. for this circuit, the lsb size is fs/4096 = 1o/4096v = 2.44mv and the coding is straight binary. ra 21k ( ad7772* 0 to +10v analog. input note 'additional pins omitted for clarity figure ". ad7772 in 0 to + 10v analog input range unipolar offset and full scale error adjustment if absolute accuracy is an application requirement, then offset and full scale error can be adjusted to zero. offset error must be adjusted before full scale error. figure 12 shows the extra com- ponents required for full scale error adjustment. the analog input range is 0 to + sv and the coding is straight binary. zero offset is achieved by adjusting the offset of the op amp driving the analog input (le., al in figure 12). for zero offset error apply 0.6imv (+ 1/2lsb) to vin and adjust the op amp offset voltage until the adc output code flickers between 0000 . . . 0000 and 000 . . . 0001. l to adjust the full scale error, apply an analog input of 4. 99817v (fs - 3/2lsbs) to vin and adjust ri until the adc output code flickers between 1111 . . . illo and 1111 . . . 1111. -8- obsolete
-- ) ad7772* r. 21k ad711 adop-27 0 to +sv analog input rl 200 r3 10 r2 20k note "additional pins omitted for clarity figure 12. unipolar 0 to +5v operation with full-scale error adjust ) bipolar opera non figure 13 shows the circuit configuration for implementing :t sv and :t iov analog input voltages on the ad7772. ra and rd offset the input signal by a constant + 2.sv while rc and ro provide attenuation for the :t sv input. rb; re and ro provide attenuation for the :t iov input. if a :t sv input range is needed, the input signal should be applied to pin 6 (:t sv) and pin 7 left unconnected. for a :t iov input range, apply the signal to pin 7 (:t lov) and leave pin 6 open circuit. the output code format is offset binary. figure 14 shows the ideal input/output characteristic for the :t sv input range. ad7772* :10v input r. 21k :5v input note "additional pins omitted for clarity figure 13. ad7772 connected for .:t-5v/.:t-10v input range ) output code (offset binary) 111 . . . 111 111. .110 100. .010 100...001 100. . 000 i 011. ..111 +1 i 011...110 +1 ~ ' l! 1 ~ - r-. fs = 10v i 000 . . .001 i 000. . .000 i llsb = 4~:6 ov s yon. input voltage -in terms of lsbs figure 14. ideal input/output transfer characteristic for the bipolar circuit of figure 13 bipolar offset and full scale error adjustment in measurement applications where absolute accuracy is required, offset and full scale error can be adjusted to zero. figure is shows how the :t sv input range circuit is modified to do this. by placing r3 in parallel with the op amp feedback resistance ro and the rl, r2 combination in parallel with re, an adjustment range of :t 16lsbs is possible. bipolar zero error must be adjusted before full scale error. this is achieved by applying an analog input of + 1.22mv (+ 1i2lsb) at the :t sv input pin and adjusting the op amp offset until the adc output code flickers between 1000 . . . 0000 and 1000 . . . 0001. for full scale error adjustment, the analog input must be at 4.99878 volts (i.e., fs/2 - 1i2lsb or last transition point). then rl is adjusted until the output code flickers between 1111 . . . 1110 and 1111 . . . 1111. ad7772* von (:sv) r. 21k note "additional pins omitted for clarity figure 15. ad7772 connected for .:t-5v input range with full-scale error adjust -9- obsolete
interfacing the ad7772 is a serial output device, making it suitable for use with digital signal processors which have a serial port (tms32020, dsp56000, etc.) as well as microcontrollers (8051, 6803) and shift registers. see figure 4 for the timing diagram. the serial data is placed on the sdo pin as conversion is taking place. each data bit is valid on the falling edge of sclk, and the complete word is framed by the sync pulse. tms32020/tms320c25 interface figure 16 shows the circuit for interfacing the ad7772 to the tms32020/tms320c25 serial port. the ad7772 has cs tied permanently low. in a sampling system, the sample timer would control the start of conversion. when the system is non- sampling, this convst pulse could be software-controlled by the processor. when conversion begins, the sync output goes low. this enables the serial input of the tms32020/tms320c25 which now accepts the data appearing at dr on each negative-going edge of clkr. after sixteen clkr pulses the internal interrupt (rint) is automatically set. the service routine for this interrupt then reads the conversion result from the drr (data receive register) into the accumulator or memory. note that the word in the drr must be shifted right three times in order to get the address bus tms32020 tms320c25 ad7772* clkin clkr dr sclk sdo fsr sync *llnear circuitry omitted for clarity figure 16. ad7772 to tms32020/tms320c25 interface standard right-justified data format. this is also the case in the other processor interfaces which follow. nec pd7720/ pd77230 interface figure 17 shows an interface circuit for the nec /lpd7720 digital signal processor. unlike the fsr input on the tms320 processors, the sien input on the /lpd77201/lpd77230 is level sensitive rather than edge sensitive. because the processor can only be configured for either 8-bit or 16-bit data transfers, the sien input to the /lpd77201/lpd77230 must be at least 16 clock pulses wide to receive the 12-bit conversion result from the ad7772. the circuitry of figure 17 accomplishes this by using the convst and sync signals as the set and reset controls on an s-r flip-flop. in figure 17 the processor controls the start of conversion. cs is tied low, and the output of the address decoder drives convst. data bits are shifted into the /lpd7720 on the rising edge of sck when sien is asserted. this means that sclk from the ad7772 must be inverted before connecting to the sck input. the internal shift register converts the serial data to parallel and transfers it to the si register when 16 bits have been received. the internal acknowledge flag, slack, is also set at this time. when the parallel data is read from the si register, this slack flag is reset. it is important to read the data from the si register before the next conversion is complete and the data bits transferred; otherwise the original data will be lost. when interfacing to the /lpd77230, the inverter for sclk shown in figure 17 is not needed, since data on si is synchronized with the falling edge of sick (the serial input clock). thus, sclk from the ad7772 is connected directly to sick on the [.lpd77230. all other connections are as in figure 17. ( clock "pd7720 convst sck si sclk sdo sien ad7772* sync *llnear circuitry omitted for clarity figure 17. ad7772 to nec /.j.pd7720 interface dsp56000 interface the dsp56000 has a very versatile serial interface which can be configured to suit various applications. figure 18 shows an interface circuit for the ad7772 to dsp56000. the dsp56000 is configured for normal mode, asynchronous operation. this means that the dsp56000 serial transmitter and receiver have their own separate clock and synchronization signals. the pro- cessor is set up for 16-bit word and continuous clock with sco and sci configured as inputs. the fsl control bit, which selects the type of frame synchronization to be recognized, should be set to o. all of these conditions are programmable in the dsp56000. (/ addressibus dsp56000 gs sco ad7772 sclk sdo srd sci sync figure 18. ad7772 to dsp56000 interface l -10- obsolete
) when the receiver is enabled, a l6-bit data word will be clocked in each time the frame synchronization signal is detected. once received, the data word will be transferred from the ssi receive shift register to the receive data register (rx). the rdf flag (receive data register full flag) will be set to indicate that the receiver is full and the receive interrupt will occur if it has been enabled. the dsp program should read the data from rx before a new data word is transferred from the receive shift register, otherwise the receive overrun error (roe) will be set. ad7772 in remote control applica nons figure 19 shows a serial interface between the ad7772 and a remote controller. the digital signals are transmitted differentially along twisted pairs while optocouplers sense the signals at the receiving end. the ds8830 is a dual differential line driver, designed to drive long lengths of coaxial cable, strip line or twisted pair transmission lines. the optocouplers used are hcpl- 260ls, which have sufficient speed (looov/f.ls slew rate) to handle the maximum data transfer rate of 1.28m bits/sec. the ad7772 is set up so that only one signal (convst) is needed to start conversion. three twisted pairs are needed to transfer the data back to the controller. these take the sclk, sdo and sync signals. figure 19. using optocouplers with the ad7772 j -11- obsolete
ad7772 - ad585 sample-hold interface figure 20 shows a typical sampling application for the ad7772 with an ad585 sample-and-hold amplifier driving the adc analog input. the ad585 is configured as 11 unity gain buffer. the :t iov input signal is successively sampled and held and this signal is then fed to pin 7 of the ad7772 which is connected for an analog input range of :t lov. for the circuit of figure 20 to function properly, it is necessary to have the convst signal for the adc synchronized with clkin as discussed previously. this ensures that the analog input is always held at a fixed point in time after the convst signal goes high and equal interval sampling is achieved. without this synchronization, the holding point would not be exactly defined and the data acquisition system performance would suffer accordingly. the maximum throughput rate of the system shown in figure 20 is 76khz. iofls is required for conversion while a further 3fls must be allowed for the ad585 to acquire the signal. this yields a total time of 13fls. thus, the maximum sampling rate is 76khz and the analog input bandwidth is 38khz. +15v +5v analog input -10v to +10v note "additional pins omitted for clarity figure 20. ad7772 sample-and-hold interface applica non hints good printed circuit board (pcb) layout is as important as the circuit design itself in achieving high speed aid performance. the ad7772's comparator is required to make bit decisions on an lsb size of 1.22mv. to achieve this, the designer has to be conscious of noise both in the adc itself and the preceding analog circuitry. switching mode power supplies are not recom- mended as the switching spikes will feed through to the comparator causing noisy code transitions. other causes of concern are ground loops and digital feedthrough from microprocessors. these are factors which influence any adc, and a proper pcb layout which minimizes these effects is essential for best performance. (' layout hints ensure that the layout for the printed circuit board has the digital and analog signal lines separated as much as possible. take care not to run any digital track alongside an analog signal track. guard (screen) the analog input with agnd. establish a single point analog ground (star ground) separate from the logic system ground at pin 4 (agnd) or as close as possible to the ad7772 as shown in figure 21. connect all other grounds and pin 10 (ad7772 dgnd) to this single analog ground point. do not connect any other digital grounds to this analog ground point. low impedance analog and digital power supply common returns are essential to low noise operation of the adc so make the foil width for these tracks as wide as possible. the use of ground planes minimizes impedance paths while guarding the analog circuitry from digital noise. the circuit layout of figures 24 and 25 have both analog and digital ground planes which are kept separate and only joined together at the ad7772 agnd pin. noise: keep the input signal leads to the analog input and signal return leads from agnd (pin 4) as short as possible to minimize input noise coupling. in applications where this is not possible use a shielded cable between the source and the adc. reduce the ground circuit impedance as much as possible, since any potential difference in grounds between the signal source and the adc appears as an error voltage in series with the input signal. (/ analog supply digital supply ad7772 digital circuitry figure 21. power supply grounding practice l., -12- obsolete
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@) ) @j ) ... 000000000000 0 0000000 0 0000000 0000000 0000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 0000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 0000000000000. 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 00000000000000 0 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 ooooooooooo~oooo 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 figure 25. pcb solder side layout for figure 22 -15- @) obsolete
c z z 0 s;;;:: c.::i o..j c > u ~ (i) o~~~ @&1~8!3 ) c a: !::i ( (.) il) ~ q co u., 6 o~ - (.) 0 <.oil) ~ " ..j ..j 8+ x~u ~ ~~+e~ ~ i ~~ + ~ n a o ~=00" \; m+ '" u - ~ c u i- :2 a a c z c.::i ? > il) 'i ~+o (.) 0 u ~c::> 0 0+ 130 (.) !3~ + ~ figure 26. component overlay for circuit of figure 22 - --~- ,) obsolete

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