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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local elpida memory, inc. for availability and additional information. mos integrated circuit pd45v128421, 45v128821, 45v128161 128m-bit virtualchannel tm dram data sheet document no. e0025n10 (1st edition) (previous no. m15076ej2v0ds00) date published january 2001 cp (k) printed in japan elpida memory, inc. is a joint venture dram company of nec corporation and hitachi, ltd. description the 128m-bit virtualchannel dram is implemented to be 100% pin and package compatible to the industry standard sdram. it uses the same command protocol and interface as sdram. it also follows the same electrical and timing specifications of the sdram, such that it is possible for one product platform to be used with the virtualchannel dram and non-virtualchannel dram part. features ? fully standard synchronous dynamic ram, with all signals referenced to a positive clock edge ? dual internal banks controlled by bank select address ? sixteen channels controlled by channel select address ? quad segments controlled by segment select address ? byte control (x16) by ldqm and udqm ? wrap sequence (interleave) ? burst length (4) ? read latency (2) ? prefetch read latency (4) : for x4 bits organization( pd45v128421), prefetch read operation can not be used. ? auto precharge and without auto precharge ? auto refresh and self refresh ? x4, x8, x16 organization ? single 3.3 v 0.3 v power supply ? interface: lvttl ? refresh cycle: 4 k cycles / 64 ms
data sheet e0025n10 2 pd45v128421, 45v128821, 45v128161 ordering information part number organization clock read prefetch channel package (word x bit x bank) frequency latency read and mhz (max.) latency interface pd45v128421g5-a75-9jf 16m x 4 x 2 133 2 ? note 16 channels 54-pin plastic pd45v128821g5-a75-9jf 8m x 8 x 2 2 4 and tsop(ii) pd45v128161g5-a75-9jf 4m x 16 x 2 2 4 lvttl (10.16 mm (400)) note for x4 bits organization, prefetch read operation can not be used.
data sheet e0025n10 3 pd45v128421, 45v128821, 45v128161 part number pd4 5 v 128 8 2 1 g5 - a75 [ x4, x8 ] interface 1 : lvttl number of banks and channel 1 : 2 banks and 8 channels 2 : 2 banks and 16 channels 3 : 2 banks and 32 channels 4 : 4 banks and 8 channels 5 : 4 banks and 16 channels 6 : 4 banks and 32 channels organization 4 : x4 8 : x8 dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v minimum cycle time 75 : rl=2 : 7.5 ns (133 mhz) 10 : rl=2 : 10 ns (100 mhz) v : virtualchannel memory memory density 64m bits 128m bits : : 64 128 note note note note note no letter : single data rate sdram category
data sheet e0025n10 4 pd45v128421, 45v128821, 45v128161 pd4 5 v 128 16 1 g5 - a75 [ x16 ] number of banks and interface 1 : 2 banks and lvttl word and number of channel memory density dram nec memory package g5 : tsop(ii) low voltage a : 3.3 0.3 v category 64m bits 128m bits : : 64 128 note note 15 : x16 bits and 8 channels 16 : x16 bits and 16 channels 17 : x16 bits and 32 channels no letter : single data rate sdram minimum cycle time 75 : rl=2 : 7.5 ns (133 mhz) 10 : rl=2 : 10 ns (100 mhz) v : virtualchannel memory
data sheet e0025n10 5 pd45v128421, 45v128821, 45v128161 pin configurations /xxx indicates active low signal. [ pd45v128421] 54-pin plastic tsop (ii) (10.16 mm (400)) 16m words x 4 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc nc v cc q nc dq0 v ss q nc nc v cc q nc dq1 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss nc v ss q nc dq3 v cc q nc nc v ss q nc dq2 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7, a10 dq0 - dq3 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address.
data sheet e0025n10 6 pd45v128421, 45v128821, 45v128161 [ pd45v128821] 54-pin plastic tsop (ii) (10.16 mm (400)) 8m words x 8 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q nc dq1 v ss q nc dq2 v cc q nc dq3 v ss q nc v cc nc /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq7 v ss q nc dq6 v cc q nc dq5 v ss q nc dq4 v cc q nc v ss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a7 dq0 - dq7 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable dqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address.
data sheet e0025n10 7 pd45v128421, 45v128821, 45v128161 [ pd45v128161] 54-pin plastic tsop (ii) (10.16 mm (400)) 4m words x 16 bits x 2 banks 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 v cc dq0 v cc q dq1 dq2 v ss q dq3 dq4 v cc q dq5 dq6 v ss q dq7 v cc ldqm /we /cas /ras /cs bank address(a13) a12 auto precharge(a10) a0 a1 a2 a3 v cc 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 v ss dq15 v ss q dq14 dq13 v cc q dq12 dq11 v ss q dq10 dq9 v cc q dq8 v ss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 v ss a0 - a13 a0 - a12 a0 - a6 dq0 - dq15 /cs /ras /cas /we : : : : : : : : address inputs row address inputs column address inputs data inputs / outputs chip select row address strobe column address strobe write enable udqm ldqm cke clk v cc v ss v cc q v ss q nc : : : : : : : : : upper dq mask enable lower dq mask enable clock enable system clock input supply voltage ground supply voltage for dq ground for dq no connection remark refer to 1. input / output pin function for bank address, channel address and segment address.
data sheet e0025n10 8 pd45v128421, 45v128821, 45v128161 virtualchannel dram architecture the virtualchannel dram is a memory core technology designed to improve memory data throughput efficiency and initial latency of memories. intended for use in next generation memory systems, the virtualchannel dram technology is ideal memory for a wide range of application such as multimedia pc, game machine, internet server etc?. the slow core operation memory such as dram, flash memory and mask rom can get very significant performance improvements with virtualchannel dram technology. today's memory subsystems are accessed by multiple tasks/sources (memory masters), working in multitasking mode. each memory master accesses memory with an address locality with a time locality, a block size and a number of contiguous accesses. virtualchannel dram architecture is designed for this multitasking, multiple masters, interleaving access scenarios. the virtualchannel dram provides memory masters with virtualchannels. each channel is a set of resources that constitute a fast dedicated path for each memory masters to access the memory. the virtualchannels will minimize the overhead resulting from other memory master's accesses, reduce the access latency and facilitate automatic data sharing. each channel is equipped with a data row buffer and its own independent operating modes. to the memory masters, this looks like its own very fast memory. the system memory controller associates these channels to the memory masters for their accesses. thus, the channels are made to track the accesses of these memory masters. the system memory controller has complete controls over the operations of the channels. it can schedule and issue commands that causes segments of memory rows to be loaded into the channels or for data from the channels to be written back to the memory rows. any channels can store the data from any rows, can be written to any rows and hence are fully associative. then the read and write operations will be occurring as much as possible with these high speed channels, minimizing all overheads associated with the dram bank operations. the read/write operations of the channels (foreground operations) can operate independently with the dram bank operations (background operations) of activate, precharge, prefetch (loading row data to channel) and restore (writing channel data to row). then virtualchannel dram also further enhances performance by allowing the system memory controller to schedule the foreground and background operations to operate concurrently. virtualchannel dram architecture offers the following features and benefits: 1. multiplies the effective data throughput performance of conventional dram core. 2. achieving close to full data bus bandwidth with low latency, interleaved random row, random column read/write through the channels. 3. transparent dram bank operations through the concurrent foreground and background operations 4. very wide (256 bytes wide) internal data transfer bus between channel and memory core 5. equivalence of tens of multiple memory banks by using only a fraction of the frequency of row activate and precharge of conventional dram core.
data sheet e0025n10 9 pd45v128421, 45v128821, 45v128161 block diagram channel bank b sense amp. memory cell array row decoder segment decoder dqm control logic command decoder clock generator cke clk bank a column decoder latch circuit data control circuit input and output buffer dq dq address buffer and refresh counter address address channel control channel selector /we /cas /ras /cs
data sheet e0025n10 10 pd45v128421, 45v128821, 45v128161 conceptual schematic 1 foreground read operation write operation row decoder bank b row decoder bank a one segment : 1/4 row one segment means one data transfer size at the background operations. background prefetch operation restore operation prefetch operation (from segment of memory core to channel) restore operation (from channel to segment of memory core) write operation ( to channel ) read operation ( from channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment
data sheet e0025n10 11 pd45v128421, 45v128821, 45v128161 conceptual schematic 2 prefetch operation the data is fetched from a segment to any channel buffer. segment segment segment segment segment segment segment segment 16 channels row decoder bank b row decoder bank a restore operation the data is transferred from a channel buffer to any segment. 16 channels row decoder bank b row decoder bank a segment segment segment segment segment segment segment segment must select one channel must select one segment
data sheet e0025n10 12 pd45v128421, 45v128821, 45v128161 data size of segment and channel memory cell 8 k (8192) bits 1 row 2 k (2048) bits 4 segments 16 channels 2 k (2048) bits 2 1 3 45 16 input and output buffer 0 1 2 3 x 4 bits organization 512 bits 2048 (2k) bits / 4 column selector one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 7 6 x 8 bits organization column selector 256 bits 2048 (2k) bits / 8 one channel density 2048 (2k) bits input and output buffer 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 x 16 bits organization column selector 128 bits 2048 (2k) bits / 16 one channel density 2048 (2k) bits one segment means one data transfer size at the prefetch and restore operation.
data sheet e0025n10 13 pd45v128421, 45v128821, 45v128161 1. input / output pin function (1/3) pin name input/output function clk input clk is the master clock input. other inputs signals for all commands are referenced to the clk rising edge. cke input cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the virtualchannel dram suspends operation. when the virtualchannel dram is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs input chip select. /cs low starts the command input cycle, which occurs on rising edge of clk. during /cs high, commands are ignored but operations continue. /ras, /cas, /we input command inputs. the combination of these signals defines the command being entered. for details, refer to the command table in command functions. the symbol names (/ras, /cas, /we) do not refer to the functional meanings used for conventional dram. dqm for x8,x4 devices udqm ldqm for x16 device input for x4, x8 devices dqm controls i/o buffers. for x16 device udqm and ldqm control upper byte and lower byte i/o buffers, respectively. in read mode dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clocks. in write mode dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. dq0 - dq3 dq0 - dq7 dq0 - dq15 input / output dq pins have the same function as i/o pins on a standard synchronous dram. dq0 - dq3 (for x 4 bits device) dq0 - dq7 (for x 8 bits device) dq0 - dq8 (for x 16 bits device) nc ? no connection. leave these pins unconnected. v cc v ss (power supply) v cc and v ss are power supply pins for internal circuits. v cc q v ss q (power supply) v cc q and v ss q are power supply pins for the output buffers.
data sheet e0025n10 14 pd45v128421, 45v128821, 45v128161 (2/3) pin name input / output function a0 - a13 input address specification. these pins provide memory source and target addresses (bank, row, column, etc.), and channel addresses. row address row address is determined by a0 - a12 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address column address is determined by a0 - a7 and a10 at the clk rising edge in the read or write command cycle. it depends on the bit organization. : a0 - a7, a10 for x4 device : a0 - a7 for x8 device : a0 - a6 for x16 device. bank address(a13) a13 is the bank select signal. in command cycle, a13 low select bank a, and a13 high select bank b. channel address(a8, a9, a11, a12) a8, a9, a11, a12 are the channel select signals. channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 a11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 a12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 segment address(a0, a1, a10, a13) a0, a1, a10, a13 are the segment select signals. in prefetch and restore operations, column address in channel is determined by a0, a1. in prefetch read operation, segment is determined by a10, a13.
data sheet e0025n10 15 pd45v128421, 45v128821, 45v128161 (3/3) pin name input / output function a0 - a13 input auto precharge address(a10) a10 defines the precharge mode. in the precharge command cycle high level: all banks are precharged. low level: only the bank selected by a13 is precharged. in the prefetch or restore command cycle high level: auto precharge low level: without auto precharge
data sheet e0025n10 16 pd45v128421, 45v128821, 45v128161 2. truth table 2.1 command execution all commands are executed with the signal combination at the rising edge of the clock (clk), /cs (chip select) must be low at the command input cycle. cke (clock enable) must be high at one clock before the command input cycle as shown in below. the state of the /ras, /cas, and /we signals specifies the command function to be executed. some commands have the same signal combination for /ras, /cas, and /we and are distinguished by some of address input signals. when /cs becomes high, operations continue as specified in the command, but further commands (signal states that would specify a command) are not registered until /cs becomes low. this state is device deselect. /ras /cas /we address cke clk h n - 1 n n + 1 command l /cs
data sheet e0025n10 17 pd45v128421, 45v128821, 45v128161 2.2 command truth table function symbol /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 device deselect desl h x x x x x x x x x x x x x x x x x no operation nop l h h h x x x x x x x x x x x x x x prefetch without auto precharge pfc l h h l ba cha. cha. l cha. cha. l l l x x x seg. seg. prefetch with auto precharge pfca l h h l ba cha. cha. h cha. cha. l l l x x x seg. seg. restore without auto precharge rst l h h l ba cha. cha. l cha. cha. h x x x x x seg. seg. restore with auto precharge rsta l h h l ba cha. cha. h cha. cha. h x x x x x seg. seg. channel read read l h l h x cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. channel write writ l h l l l cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. bank activate act l l h h ba row row row row row row row row row row row row row prefetch read with auto precharge pfr n ote l l h l seg. cha. cha. seg. cha. cha. col. col. col. col. col. col. col. col. precharge selected bank pre l l l l ba x x l x x x x l x x x x x precharge all banks pall l l l l x x x h x x x x l x x x x x reset rest l l l l l l l l l l l l h x x x x x note for x4 bits organization, this command is illegal. remark abbreviations in the table mean as follows. h : high level l : low level x : high or low level (don' t care) row : row address col. : column address ba : bank address cha. : channel address seg. : segment address
data sheet e0025n10 18 pd45v128421, 45v128821, 45v128161 2.3 cke truth table current state function symbol cke /cs /ras /cas /we address n ? 1 n activating clock suspend mode entry ? h l x x x x x any clock suspend ? l l x x x x x clock suspend clock suspend mode exit ? l h x x x x x idle auto refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit ? l h l h h h x l h h x x x x idle power down entry ? h l x x x x x power down power down exit ? l h h x x x x l h h h x remark h: high level, l: low level, x: high or low level (don' t care)
data sheet e0025n10 19 pd45v128421, 45v128821, 45v128161 3. commands device deselect (desl) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 high x x x x x x x x x x x x x x x x x remark x: high or low level (don' t care) the device is deselected state by this command. clk cke h /ras /we /cas a0 to a13 /cs
data sheet e0025n10 20 pd45v128421, 45v128821, 45v128161 no operation (nop) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high high x x x x x x x x x x x x x x remark x: high or low level (don' t care) this command is not a execution command. no operations begin or terminate by this command. /cs clk cke h /ras /we /cas a0 to a13
data sheet e0025n10 21 pd45v128421, 45v128821, 45v128161 prefetch without auto precharge (pfc) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. low cha. cha. low low low x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer which is chosen by channel address. the segment and bank fields specify the source segment and bank. in addition, the channel address field specifies the destination channel. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. in case of a10: high, with auto precharge operation occurs after data fetch operation. (please refer to pfca command.) (bank precharge is necessary after data fetch.) this fetched command can be issued continuously without any precharge operation. for instance, when the first operation has been done from one of segment on activated row area to one of channel, if the second prefetch operation is required from same activated row, but different channel, the second prefetch command can be issued without any precharge operation. t ppd (pfc to pfc/pfca command period) is required between first and second prefetch command. when the new row address area need to be activated on same bank, bank precharge is necessary after this pfc command. t ppl (pfc to pre command period) is required between pfc and pre. fetched data into the channel buffer remains available for channel read and channel write operations. /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a4 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid a6 a5
data sheet e0025n10 22 pd45v128421, 45v128821, 45v128161 prefetch with auto precharge (pfca) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. high cha. cha. low low low x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer, and precharge operation is performed automatically, which closes the activated row after data fetch operation. the segment and bank fields specify the source segment and bank. in addition, the channel address field specifies the destination channel. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. (please refer to pfc command.) in case of a10: high, with auto precharge operation occurs after data fetch operation. fetched data into the channel buffer remains available for channel read and channel write operations. /cs clk cke h /we /cas a13 valid a12 valid a1 valid /ras a2 to a4 bank select channel address a11 valid a9 valid channel address a8 valid a7 segment address a0 valid a6 a5 a10
data sheet e0025n10 23 pd45v128421, 45v128821, 45v128161 restore without auto precharge (rst) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. low cha. cha. high x x x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command transfers data from a channel buffer to a segment of a row which is going to be activated by following act command. the command bank address field specifies the destination bank. the channel address fields specify the source channel. the segment number field specifies the destination segment. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. in case of a10: high, with auto precharge operation occurs after data fetch operation. (please refer to rsta command.) /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid
data sheet e0025n10 24 pd45v128421, 45v128821, 45v128161 restore with auto precharge (rsta) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high high low ba cha. cha. high cha. cha. high x x x x x seg. seg. remark ba: bank address, cha.: channel address, x: high or low level (don' t care), seg.: segment address this command transfers data from a channel buffer to a segment of a row which is going to be activated by following act command. in addition, precharge operation is performed automatically which closes the active row after data restore operation. the command bank address field specifies the destination bank. the channel address fields specify the source channel. the segment number field specifies the destination segment. a10 specify the optional precharge operation. in case of a10: low, without auto precharge operation occurs. (please refer to rst command.) in case of a10: high, with auto precharge operation occurs after data fetch operation. /cs clk cke h /ras /we /cas a13 valid a12 valid a1 valid a2 to a6 bank select channel address a11 valid a10 a9 valid channel address a8 valid a7 segment address a0 valid
data sheet e0025n10 25 pd45v128421, 45v128821, 45v128161 channel read (read) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high low high x cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. remark x: high or low level (don' t care), cha.: channel address, col.: column address channel read (read) reads data words from a channel buffer onto the data bus (dq). the channel address field specifies the source channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8, or 16 bits.). /cs clk cke h /ras /we /cas a13 a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address
data sheet e0025n10 26 pd45v128421, 45v128821, 45v128161 channel write (writ) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low high low low low cha. cha. col. cha. cha. col. col. col. col. col. col. col. col. remark x: high or low level (don' t care), cha.: channel address, col.: column address channel write(writ) writes data from the data bus (dq) into a channel buffer. the channel address field specifies the destination channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8 or 16 bits.). /cs clk cke h /ras /we /cas a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address a10 valid column address a13
data sheet e0025n10 27 pd45v128421, 45v128821, 45v128161 bank activate (act) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low high high ba row row row row row row row row row row row row row remark ba: bank address, row: row address activation causes row contents to be placed into the bank's sense amplifier. the command bank address and row address fields specify bank and row. this device has two banks, each with 8,192 rows. this command activates the bank selected by bank address(a13) and a row address selected by a0 through a12. the row remains active for access until a precharge command is issued to the bank. a precharge command must be issued before another row can be activated in that bank. each bank can have one row active. this command corresponds to a conventional dram ? s /ras falling. /cs clk cke h /ras /we /cas a13 a0 to a12 valid valid bank select row address
data sheet e0025n10 28 pd45v128421, 45v128821, 45v128161 prefetch read with auto precharge (pfr) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low high low seg. cha. cha. seg. cha. cha. col. col. col. col. col. col. col. col. remark seg.: segment address, cha.: channel address, col.: column address this command needs to follow bank activate (act) command. this command fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (dq). in addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. the segment fields specify the source segment. in addition, the channel address field specifies the destination channel. the column address field specifies the starting location of the data word in the buffer (data words may be 4, 8, or 16 bits.). for x4 bits organization, this command is illegal. /cs clk cke h /we a0 to a7 valid a12 valid channel address a11 valid a9 valid channel address a8 valid column address /ras /cas segment address a13 valid segment address a10 valid
data sheet e0025n10 29 pd45v128421, 45v128821, 45v128161 precharge selected bank (pre) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low ba x x low x x x x low x x x x x remark ba: bank address, x: high or low level (don' t care) this command closes (deactivates) an activated row in a bank, in order to prepare the bank for an activate or restore command to activate a new row. after precharging, a bank is in the idle state. the bank field specifies the bank to precharge and a10 low specifies the command. after this command, t rp (precharge to activate command period) must be satisfied for next activate command to precharging bank. this command corresponds to a conventional dram ? s /ras rising. /cs clk cke h /we /ras a6 to a9 a11,a12 a10 a13 valid bank select /cas a0 to a4 a5
data sheet e0025n10 30 pd45v128421, 45v128821, 45v128161 precharge all banks (pall) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low x x x high x x x x low x x x x x remark x: high or low level (don' t care) the signal combination is reserved (with command modifier a10 high). the pall command is typically used during auto refresh operation and initialization. replace with precharge commands for each bank. /cs clk cke h /we /ras a6 to a9 a11 to a13 /cas a0 to a4 a5 a10
data sheet e0025n10 31 pd45v128421, 45v128821, 45v128161 reset (rest) /cs /ras /cas /we a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 low low low low low low low low low low low low high x x x x x remark x: high or low level (don ? t care) this command is used to initialize virtualchannel dram. /cs clk cke h /ras /we /cas a6 to a13 a5 a0 to a4
data sheet e0025n10 32 pd45v128421, 45v128821, 45v128161 auto refresh (ref) cke /cs /ras /cas /we address n?1 n high high low low low high x remark x: high or low level (don ? t care) this command is a request to begin the auto refresh operation. the refresh address is generated internally. before executing auto refresh, all banks must be in the idle state. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during t rc period (from refresh command to refresh or activate command), the virtualchannel dram cannot accept any other command. clk cke h n ? 1n /ras /cas a0 to a13 h /we /cs
data sheet e0025n10 33 pd45v128421, 45v128821, 45v128161 self refresh (self) cke /cs /ras /cas /we address n?1 n high low low low low high x remark x: high or low level (don ? t care) after the command execution, self refresh operation continues while cke remains low. during self refresh mode, the internal refresh controller takes care of refresh interval and refresh operation. there is no need for external control. before executing self refresh, both banks must be in the idle state. during self refresh mode, both background and foreground operation can not be executed. /cs clk cke /ras n ? 1n /cas a0 to a13 hl /we
data sheet e0025n10 34 pd45v128421, 45v128821, 45v128161 4. simplified state diagram active stand by active power down prefetch with auto precharge auto refresh precharge restore with auto precharge self refresh power down reset channel read channel write automatic sequence manual input background operation foreground operation restore without auto precharge prefetch without auto precharge prefetch read write suspend read suspend idle stand by power on cke:low cke:high cke:low cke:high writ read cke:low cke:high self self exit pre rest ref pfc row active cke:high cke:low read read act read read read read read read pfr pre pre pre pre rst rst rst rsta rsta rsta act act act writ writ writ writ writ writ writ pfc pfca pfca pfca pfca pfc pfc act read writ
data sheet e0025n10 35 pd45v128421, 45v128821, 45v128161 5. prefetch read operation ( ( ( ( optional ) ) ) ) this operation fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (dq). in addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. for x4 bits organization, prefetch read operation can not be used (pfr command is illegal). row decoder bank b row decoder bank a read operation 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment prefetch read operation prefetch operation clk command dq act pfc read q2 q1 q0 0 2345678 1 hi-z ( burst length = 4 ) q3 command act pfr dq q1 q0 hi-z q2 q3 read latency = 2 prefetch read latency = 4 t apd t aprd the relationship between clock frequency and read latency, prefetch read latency clock frequency mhz(max.) read latency prefetch read latency 133 2 4
data sheet e0025n10 36 pd45v128421, 45v128821, 45v128161 6. write operation and restore operation write command proceeds write operation to the channel. when the system needs to refill the channel with new data, restore operation may be necessary. the restore operation needs both restore command and active command. restore command must be first command. restore operation is also fully associative operation. the data in the channel can be transferred to anywhere on memory core array. another write and read operation to another channel can proceed during this restore operation. the another background operation is illegal while t rad (rst/rsta to act(r) command delay time). in addition, the foreground operation to the same channel set by rst command is illegal too. row decoder bank b row decoder bank a restore operation (from channel to segment) write operation ( to channel ) 16 channels input and output buffer dq dq segment segment segment segment segment segment segment segment clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-1 d1-0 0 2345678 1 t ras t rcd hi-z ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge col. 1 banka channel 1 with auto precharge q1-1 d1-2 d1-3 9 10 read
data sheet e0025n10 37 pd45v128421, 45v128821, 45v128161 7. basic settings after initialization, it automatically sets read latency, burst length and wrap sequence as followed. item value read latency 2 prefetch read latency 4 burst length 4 wrap sequence interleave it cannot be set other value. 7.1 burst length and sequence [burst of four] starting address addressing sequence (column address a1,a0) interleave (binary) (decimal) 00 0, 1, 2, 3 01 1, 0, 3, 2 10 2, 3, 0, 1 11 3, 2, 1, 0
data sheet e0025n10 38 pd45v128421, 45v128821, 45v128161 8. initialization the virtualchannel dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) after the pause, both banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum t rp is satisfied, the reset command is executed one or more times (16 times execution also possible). (4) after the reset cycle, t rsc (2clk minimum) pause must be satisfied as well. two or more auto refresh must be performed. remarks 1. the reset command and refresh above may be transposed. 2. cke and dqm must be held high until the precharge command is issued to ensure data-bus hi-z.
data sheet e0025n10 39 pd45v128421, 45v128821, 45v128161 9. electrical specifications ? all voltages are referenced to v ss (gnd). ? after power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc , v cc q ? 0.5 to +4.6 v voltage on input pin relative to gnd v t ? 0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 1 w operating ambient temperature t a 0 to 70 c storage temperature t stg ? 55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc , v cc q 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 note1 v low level input voltage v il ? 0.3 note2 +0.8 v operating ambient temperature t a 0 70 c notes 1. v ih (max.) = v cc + 1.5 v (pulse width 5 ns) 2. v il (min.) = ? 1.5 v (pulse width 5 ns) capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 clk 2.5 3.5 pf c i2 a0 - a13, cke, /cs, /ras, /cas, /we, 2.5 3.8 dqm, udqm, ldqm data input/output capacitance c i/o dq 4.0 6.5 pf
data sheet e0025n10 40 pd45v128421, 45v128821, 45v128161 dc characteristics 1 (recommended operating conditions unless otherwise noted) parameter symbol test condition maximum. unit notes x4 x8 x16 operating current i cc1 p t rc t rc(min.) 150 ma 1 ( prefetch mode at one prefetch is executed one time during t rc . bank active ) operating current i cc1 r t rc t rc(min.) 150 ma 1 ( restore mode at one bank active ) precharge standby current i cc2 p cke v il(max.) , t ck = 15 ns 1.2 ma in power down mode i cc2 ps cke v il(max.) , t ck = 1.2 precharge standby current i cc2 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) 20 ma in non power down mode input signals are changed one time during 30 ns. i cc2 ns cke v ih(min.) , t ck = , input signals are stable. 10 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 6 ma power down mode i cc3 ps cke v il(max.) , t ck = 6 active standby current in i cc3 n cke v ih(min.) , t ck = 15 ns, /cs v ih(min.) 30 ma non power down mode input signals are changed one time during 30 ns. i cc3 ns cke v ih(min.) ,t ck = , input signals are stable. 20 operating current i cc4 t ck t ck(min.) , i o = 0 ma, 60 65 75 ma 2 (burst mode) background: precharge standby auto refresh current i cc5 t rcf t rcf(min.) 230 ma 3 self refresh current i cc6 cke 0.2 v 2 ma notes 1. i cc1 depends on cycle rates. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 . i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . dc characteristics 2 (recommended operating conditions unless otherwise noted) parameter symbol test condition min. typ. max. unit note input leakage current i i(l) 0 v i v cc q, v cc q = v cc all other pins not under test = 0 v ? 1.0 ? + 1.0 a output leakage current i o(l) 0 v o v cc q, d out is disabled. ? 1.5 ? + 1.5 a high level output voltage v oh i o = ? 4 ma 2.4 ? ? v low level output voltage v ol i o = + 4 ma ? ? 0.4 v
data sheet e0025n10 41 pd45v128421, 45v128821, 45v128161 ac characteristics (recommended operating conditions unless otherwise noted) test conditions ? ac measurements assume t t = 1 ns. ? reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . ? if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih(min.) and v il(max.) . ? an access time is measured at 1.4 v. t ck2 t s t h t ds valid valid valid valid valid t ac2 hi-z hi-z t ac2 t lz t oh2 t hz t dh t ds t dh t ch t ch t cl clk (input) command address dqm data (input) data (output) cke t cks t ckh t ck2 t cl
data sheet e0025n10 42 pd45v128421, 45v128821, 45v128161 ac characteristics parameter symbol -a75 unit note min. max. clock cycle time t ck2 7.5 ? ns access time from clk t ac2 ? 5.4 ns 1 clk high level width t ch 2.5 ? ns clk low level width t cl 2.5 ? ns data-out hold time t oh 2.7 ? ns 1 data-out low-impedance time t lz 0 ? ns data-out high-impedance time t hz2 2.5 5.4 ns data-in setup time t ds 1.5 ? ns data-in hold time t dh 0.8 ? ns address, command, dqm setup time t s 1.5 ? ns address, command, dqm hold time t h 0.8 ? ns cke setup time t cks 1.5 ? ns cke hold time t ckh 0.8 ? ns cke setup time (power down exit) t cksp 1.5 ? ns transition time t t 0.5 30 ns refresh time (4,096 refresh cycle) t ref ? 64 ms reset cycle time t rsc 2 ? clk note1 output load. output z = 50 ? 50 pf
data sheet e0025n10 43 pd45v128421, 45v128821, 45v128161 ac characteristics (background to background operation) parameter symbol -a 75 unit notes min. max. same bank operation act to act / ref command period t rc 67.5 ? ns ref to ref / act command period t rcf 67.5 ? ns act to pre command period t ras 52.5 120,000 ns pre to act / ref command period t rp 20 ? ns act to pfc / pfca command delay time t apd 15 ? ns act to pfr command delay time (prefetch read operation) t aprd 15 ? ns 2 pfc to pre command delay time t ppl 22.5 ? ns pfca / pfr to act / ref command delay time t pal 45 ? ns rst / rsta to act(r) note1 command delay time t rad 7.5 30 ns 3 same,other bank operation act(r) note1 to pfc/pfca/pfr command delay time t rpd 37.5 ? ns pfc to pfc / pfca command delay time t ppd 22.5 ? ns other bank operation act to act / act(r) or act(r) to act command delay time t rrd 15 ? ns act(r) to act(r) command delay time t rrdr 30 ? ns pfc / pfca to rst / rsta command delay time t prd 22.5 ? ns notes 1. act(r) command is act command after rst command. 2. for x4 bits organization, prefetch read operation can not used. 3. the another background operation and same channel foreground operation are illegal while t rad period.
data sheet e0025n10 44 pd45v128421, 45v128821, 45v128161 ac characteristics (foreground to foreground operation) parameter symbol -a 75 unit note min. max. read / write to read / write command delay time t ccd 7.5 ? ns ac characteristics (background to foreground operation) (after same channel prefetch/restore) parameter symbol -a 75 unit note min. max. pfc / pfca to read / write command delay time t pcd 15 ? ns act(r) to read / write command delay time t rcd 30 ? ns 1 note1 act(r) command is act command after rst command.
data sheet e0025n10 45 pd45v128421, 45v128821, 45v128161 cccccc clk 41213 22 21 command address a10 t rp pall h ref row 1 act banka t rsc ref a5 l t rcf t rcf dq dqm hi-z 0123 rest remark rest command can be executed one or more times.
data sheet e0025n10 46 pd45v128421, 45v128821, 45v128161 ]ccfc]ccccccccec clk ( read latency = 2, burst length = 4 ) 0 2345678 1 9 111213141516 10 command act pfc read writ cke /ras /cas /we /cs dq dqm l hi-z q1-0 q1-1 d1-0 d1-1 a8,a9,a11,a12 row channel channel channel a13 bank bank a10 row a5,a6,a7 row column column a2,a3,a4 row column column a0,a1 row segment column column h q1-2 q1-3 d1-2 d1-3
data sheet e0025n10 47 pd45v128421, 45v128821, 45v128161 cccccfcce clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z q1-3 t pcd cke q1-0 q1-1 q1-2 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend
data sheet e0025n10 48 pd45v128421, 45v128821, 45v128161 cccccfccec clk command channel address a13 a10 dq dqm ( burst length = 4 ) 0 2345678 1 t apd l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 writ channel 1 hi-z t pcd cke d1-0 auto precharge without 1 clock suspend 2 clocks suspend 3 clocks suspend d1-1 d1-2 d1-3
data sheet e0025n10 49 pd45v128421, 45v128821, 45v128161 ccc clk command channel address a13 a10 dq dqm ( read latency = 2, burst length = 4 ) 0 2345678 1 l row 0 act banka 9 111213141516 10 segment 1 pfc banka channel 1 col. 0 read channel 1 hi-z cke q1-0 q1-1 auto precharge without power down mode entry power down mode exit power down mode entry power down mode exit t cksp t cksp pre banka l active standby precharge standby q1-2 q1-3
data sheet e0025n10 50 pd45v128421, 45v128821, 45v128161 ccc read 0234 1 clk command dq dqm q0 q1 q2 hi-z l q3 ( burst length = 4 ) read latency = 2 (( writ 023 1 clk command dq dqm d1 d2 d3 l ( burst length = 4 ) write latency = 0 d0
data sheet e0025n10 51 pd45v128421, 45v128821, 45v128161 cccc clk dq dqm q0 q1 q3 hi-z hi-z read mask latency = 2 mask ( burst length = 4 ) (((( clk dq dqm mask mask ( burst length = 4 ) d1 d3 write mask latency = 0
data sheet e0025n10 52 pd45v128421, 45v128821, 45v128161 cccc clk command channel address dq dqm read col. 0 col. 0 read 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 q1-3 q3-0 q3-1 q3-2 channel 1 channel 3 ( read latency = 2, burst length = 4 ) q3-3 (((( clk command channel address dq dqm writ col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l d1-0 d1-1 d1-2 d1-3 d3-0 d3-1 d3-2 d3-3 ( burst length = 4 ) channel 1 channel 3
data sheet e0025n10 53 pd45v128421, 45v128821, 45v128161 cccc clk command channel address dq dqm read col. 0 col. 0 writ 0 2345678 1 t ccd hi-z l q1-0 q1-1 q1-2 d3-0 d3-1 d3-2 ( burst length = 4 ) channel 1 channel 3 d3-3 (((( clk command channel address dq dqm writ col. 0 col. 0 read 0 2345678 1 t ccd hi-z hi-z l d1-0 d1-1 d1-2 q3-0 q3-1 q3-2 ( burst length = 4 ) channel 1 channel 3 q3-3
data sheet e0025n10 54 pd45v128421, 45v128821, 45v128161 ccccccccfccec clk command channel address a13 a10 dq dqm act pfc read pre act row 0 banka row 1 banka col. 0 banka banka l q1-2 q1-1 q1-0 0 2345678 1 t apd t ras t rc t rp t pcd hi-z l ( read latency = 2, burst length = 4 ) channel 1 channel 1 segment without auto precharge q1-3 (((((((a((9( clk command channel address a13 a10 dq dqm act pfc read read pre row 0 banka col. 7 col. 0 banka banka l q4-2 q5-7 q4-1 q4-0 0 2345678 1 t ppl hi-z l ( read latency = 2, burst length = 4 ) channel 1 segment channel 4 channel 5 without auto precharge
data sheet e0025n10 55 pd45v128421, 45v128821, 45v128161 cccccccfccec clk command channel address a13 a10 dq dqm act act pfc writ pre row 0 banka row 1 col. 0 banka banka banka l d1-2 d1-3 d1-1 d1-0 0 2345678 1 t apd t ras t rc t pcd t rp hi-z l ( burst length = 4 ) channel 1 segment channel 1 without auto precharge (((((((a((9( clk command channel address a13 a10 dq dqm pfc act writ pre writ row 0 banka col. 7 col. 0 banka banka l d4-2 d3-7 d3-8 d4-1 d4-0 0 2345678 1 t ppl hi-z l ( burst length = 4 ) channel 1 segment channel 4 channel 3 d3-9 without auto precharge
data sheet e0025n10 56 pd45v128421, 45v128821, 45v128161 cccccccccfccec clk command channel address a13 a10 dq dqm pfc read act read pre row 0 banka col. 7 col. 0 banka banka l q1-2 q1-1 q1-0 q1-7 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination ( read latency = 2, burst length = 4 ) channel 1 segment channel 1 channel 1 without auto precharge q1-9 q1-8 (((((((((a((9( clk command channel address a13 a10 dq dqm pfc read act writ pre row 0 banka col. 3 col. 0 banka banka l d1-3 q1-1 q1-0 d1-5 d1-4 0 2345678 1 t apd t pcd t ppl hi-z prefetch termination channel 1 segment channel 1 channel 1 ( read latency = 2, burst length = 4 ) without auto precharge d1-6
data sheet e0025n10 57 pd45v128421, 45v128821, 45v128161 cccccccccfccec clk command channel address a13 a10 dq dqm act writ writ pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-1 d1-0 d1-2 d1-3 0 2345678 1 t apd t ppl t pcd hi-z mask pfc ( burst length = 4 ) segment channel 1 channel 1 channel 1 d1-4 without auto precharge d1-3 ( (((((((((a((9( clk command channel address a13 a10 dq dqm act writ read pre row 0 banka col. 1 col. 0 banka banka l d1-2 d1-1 d1-0 q1-2 d1-3 q1-1 0 2345678 1 t apd t ppl t pcd hi-z mask pfc ( read latency = 2, burst length = 4 ) segment channel 1 channel 1 channel 1 without auto precharge
data sheet e0025n10 58 pd45v128421, 45v128821, 45v128161 restore to read operation without auto precharge (same channel read) clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q1-1 q1-0 0 2345678 1 t rcd t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 1 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge q1-2 (((((((a((9( clk command channel address a13 a10 dq dqm read pre row 0 col. 0 banka l q7-3 q7-2 q7-1 q7-0 0 2345678 1 t ras hi-z l ( read latency = 2, burst length = 4 ) segment channel 7 channel 1 t rad rst act (r) banka banka remark act(r) command is act command after rst command. without auto precharge
data sheet e0025n10 59 pd45v128421, 45v128821, 45v128161 cccccccfccec clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d1-3 d1-2 d1-1 d1-0 0 2345678 1 t ras t rcd hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 remark act(r) command is act command after rst command. without auto precharge (((((((a((9( clk command channel address a13 a10 dq dqm writ pre row 0 col. 0 banka l d3-3 d3-2 d3-1 d3-0 0 2345678 1 t ras hi-z l ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 3 remark act(r) command is act command after rst command. without auto precharge
data sheet e0025n10 60 pd45v128421, 45v128821, 45v128161 cccccccccfccec clk command channel address a13 a10 dq dqm read read pre row 0 col. 4 col. 0 banka l q1-4 q1-1 q1-0 0 2345678 1 t ras t rcd hi-z l restore termination ( read latency = 2, burst length = 4 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge t rad (((((((((a((9( clk command channel address a13 a10 dq dqm read writ pre row 0 col. 5 col. 0 banka l q1-1 q1-0 d1-6 d1-5 0 2345678 1 t ras t rcd hi-z restore termination ( read latency = 2, burst length = 4 ) segment channel 1 rst act (r) banka banka channel 1 channel 1 d1-7 remark act(r) command is act command after rst command. without auto precharge t rad
data sheet e0025n10 61 pd45v128421, 45v128821, 45v128161 cccccccccfccec clk command channel address a13 a10 dq dqm writ writ pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 d1-2 d1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 d1-3 remark act(r) command is act command after rst command. without auto precharge (((((((((a((9( clk command channel address a13 a10 dq dqm writ read pre row 0 col. 1 col. 0 banka l d1-1 d1-2 d1-0 q1-1 0 2345678 1 t ras t rcd hi-z restore termination mask ( read latency = 2, burst length = 4 ) segment channel 1 t rad rst act (r) banka banka channel 1 channel 1 remark act(r) command is act command after rst command. without auto precharge
data sheet e0025n10 62 pd45v128421, 45v128821, 45v128161 cccccccc clk command channel address a13 a10 dq dqm act act pfc row 0 row 1 banka bankb bankb 0 2345678 1 t rrd t apd t ppd hi-z l segment 1 channel 1 without auto precharge 910 pfc bankb segment 2 channel 8 without auto precharge pfc banka segment 3 channel 2 without auto precharge t ppd ( (((((((a((9( clk command channel address a13 a10 dq dqm act pfc row 0 banka row 0 banka 0 2345678 1 t apd t prd hi-z l segment 1 channel 1 t rad rst act (r) bankb bankb channel 2 segment 1 remark act(r) command is act command after rst command. without auto precharge without auto precharge
data sheet e0025n10 63 pd45v128421, 45v128821, 45v128161 ccccc clk command channel address a13 a10 dq dqm act act pfc a row 0 banka row 0 banka banka 0 23456789 1 t apd t pal t rc hi-z l auto precharge segment 1 channel 1
data sheet e0025n10 64 pd45v128421, 45v128821, 45v128161 ccccccc clk command channel address a13 a10 dq dqm pfc pre row 0 bankb row 1 l banka 0 2345678 1 t ras t rrdr t rpd hi-z l segment 1 channel 2 t rad rst act (r) banka banka rst act (r) bankb bankb channel 1 channel 1 segment 3 segment 2 remark act(r) command is act command after rst command. t rad without auto precharge without auto precharge without auto precharge ( (((((( clk command channel address a13 a10 dq dqm row 0 banka 0 23456789 1 t rc hi-z l row 0 row 1 auto precharge segment 1 channel 2 t rad rsta act (r) banka banka t rad bankb bankb segment 3 channel 1 t rrdr act rst act (r) remark act(r) command is act command after rst command. without auto precharge
data sheet e0025n10 65 pd45v128421, 45v128821, 45v128161 ccccccccc clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 q1-8 q1-9 q1-10 q1-11 q1-0 q1-1 q1-2 q1-3 read col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. read will be interrupted by pfr. prl=4 (prefetch read latency) 13 t pal (read latency = 2, prefetch read latency = 4, burst length = 4) write to prefetch read with auto precharge operation clk command channel address a13 a10 dq dqm 0 2345678 1 t rc t aprd hi-z l row 0 channel 1 act banka 91112 10 d1-8 d1-9 d1-10 q1-0 q1-1 q1-2 q1-3 writ col. 8 col. 0 pfr segment channel 1 segment row 1 act banka illegal to input any other background operation. writ will be interrupted by pfr. prl=4 (prefetch read latency) l t pal (read latency = 2, prefetch read latency = 4, burst length = 4)
data sheet e0025n10 66 pd45v128421, 45v128821, 45v128161 ccc clk command address a10 dq dqm h pall ref act 0 2349101112 1 t rp t rcf hi-z l self refresh operation (entry and exit) 109 clk command address a10 dq dqm 0 23456 1 t rp l pall h 96 98 99 100 101 108 97 ref t rcf act cke self refresh entry self refresh exit
data sheet e0025n10 67 pd45v128421, 45v128821, 45v128161 mccc 1. each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. 2. dimension "a" does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. m p a g c n b m d l k j h i e f detail of lead end s 54 28 127 s item b c i l m n 54-pin plastic tsop ( ii ) (10.16 mm (400)) a d e f g h j p millimeters 0.80 (t.p.) 0.91 max. 0.13 0.50 0.10 10.16 0.10 0.10 22.22 0.05 0.10 0.05 0.32 1.1 0.1 11.76 0.20 1.00 + 0.08 ? 0.07 0.80 0.20 3 + 7 ? 3 k 0.145 + 0.025 ? 0.015 s54g5-80-9jf-2
data sheet e0025n10 68 pd45v128421, 45v128821, 45v128161 mccccc please consult with our sales offices for soldering conditions of the pd45v128 . type of surface mount device pd45v128421g5 : 54-pin plastic tsop (ii) (10.16mm (400)) pd45v128821g5 : 54-pin plastic tsop (ii) (10.16mm (400)) pd45v128161g5 : 54-pin plastic tsop (ii) (10.16mm (400))
data sheet e0025n10 69 pd45v128421, 45v128821, 45v128161 12. cc c edition / page description date this edition previous edition type of revision location nec corporation (m15076e) 1st edition / ? ? ? ? sep. 2000 2nd edition / p. 2 p. 2 deletion -a10 sep.2000 p. 9 p. 9 modification block diagram p. 35 p. 35 deletion 100 mhz p. 39, 40, p. 39, 40, deletion -a10 specs 42, 43, 44 42, 43, 44 elpida memory, inc. (e0025n) 1st edition / ? ? ? republished by elpida memory, inc. jan. 2001
data sheet e0025n10 70 pd45v128421, 45v128821, 45v128161 [memo]
data sheet e0025n10 71 pd45v128421, 45v128821, 45v128161 c ccc cccc note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd45v128421, 45v128821, 45v128161 [memo] the names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company. m8e 00. 4 the information in this document is current as of november, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of elpida's data sheets or data books, etc., for the most up-to-date specifications of elpida semiconductor products. not all products and/or types are available in every country. please check with an elpida memory, inc. for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of elpida. elpida assumes no responsibility for any errors that may appear in this document. elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of elpida semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while elpida endeavours to enhance the quality, reliability and safety of elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. elpida semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of elpida semiconductor products is "standard" unless otherwise expressly specified in elpida's data sheets or data books, etc. if customers wish to use elpida semiconductor products in applications not intended by elpida, they must contact an elpida memory, inc. in advance to determine elpida's willingness to support a given application. (note) (1) "elpida" as used in this statement means elpida memory, inc. and also includes its majority-owned subsidiaries. (2) "elpida semiconductor products" means any semiconductor product developed or manufactured by or for elpida (as defined above). ? ? ? ? ? ?

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