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ltc4556 1 4556f the ltc ? 4556 provides all necessary power control, level translation and supervisory functions for a smart card or s.a.m. card interface. the part contains a low noise charge pump** plus ldo for generating v cc power, as well as all necessary level shifting circuitry. the card voltage can be set to either 1.8v, 3v or 5v. the ltc4556 includes a card detection channel with automatic debounce circuitry. to reduce wiring costs, the ltc4556 interfaces to a microcontroller via a simple 4-wire serial interface. multiple devices may be connected in daisy- chain fashion so that the number of wires to the card socket board is independent of the number of sockets. status data is returned over the same interface. extensive security features ensure proper deactivation sequencing in the event of a supply fault or a smart card electrical fault. the smart card pins can withstand greater than 10kv esd in-situ with no additional components. the ltc4556 is available in a small, low profile (0.75mm), 4mm 4mm qfn package. n handheld payment terminals n pay telephones n atm machines n pos terminals n computer keyboards n multiple s.a.m. sockets , ltc and lt are registered trademarks of linear technology corporation. n electrical specifications are iso7816-3 and emv compatible n control/status serial port may be daisy-chained for multicard applications n automatic shutdown on electrical faults n buck boost charge pump generates 5v, 3v or 1.8v outputs (smart card classes a, b and c) n automatic level translation n dynamic pull-ups deliver fast signal rise times* n supervisory functions prevent smart card faults n low operating current: 250 m a typical n v in : 2.7v to 5.5v n ultralow shutdown current n >10kv esd on smart card pins n small 24-pin 4mm 4mm qfn package smart card interface with serial control 4-wire command interface 4-wire card interface smart card c8 c4 i/o rst clk v cc 18 17 16 15 14 13 19 20 12 9 11 6 1 10 8 2 3 4 5 21 22 23 24 dv cc v batt gnd fault d in d out sclk ld data r in sync async pres underv 240k ltc4556 1 f 1 f 4556 ta01 1 f 1 f 0.1 f c + c cpo 180k input power rst 5v/div 10 m s/div 4556 g11.eps deactivation sequence i/o 5v/div v cc 5v/div clk 5v/div *u.s. patent no. 6,356,140 **u.s. patent no. 6,411,531 features descriptio u applicatio s u typical applicatio u
ltc4556 2 4556f v batt , dv cc , cpo, fault, underv to gnd ....................................... C0.3v to 6.0v pres, data, r in , sync, async, ld, d in , sclk to gnd ............... C0.3v to (dv cc + 0.3v) i/o, clk ....................................... C0.3v to (v cc + 0.3v) order part number t jmax = 125 c, q ja = 37 c/w exposed pad (pin 25) is sgnd. must be soldered to pcb consult ltc marketing for parts specified with wider operating temperature ranges. ltc4556euf absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v batt = 3.3v, dv cc = 3.3v unless otherwise noted. i cc (note 5) .......................................................... 65ma v cc short-circuit duration ............................... indefinite operating temperature range (note 4) .. C 40 c to 85 c storage temperature range ................. C 65 c to 125 c parameter conditions min typ max units input power supply v batt operating voltage l 2.7 5.5 v i vbatt operating current v cc = 5v, i cc = 0 m a l 250 400 m a i vbatt shutdown current no card present, v cpo = 0v l 0.5 1.75 m a dv cc operating voltage l 1.7 5.5 v i dvcc operating current l 525 m a i dvcc shutdown current l 0.2 1.5 m a charge pump r olcp 5v mode open-loop v batt = 3.075v, i cpo = i cc = 60ma, (note 3) l 8.2 17 w output resistance cpo turn on time i cc = 0ma, 10% to 90% l 0.6 1.5 ms 25 top view uf package 24-lead (4mm 4mm) plastic qfn dv cc data r in sync async fault c8 c4 i/o rst clk v cc ld sclk d out d in underv pres nc gnd c C v batt c + cpo 24 23 22 21 20 19 7 8 9 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 uf part marking 4556
ltc4556 3 4556f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v batt = 3.3v, dv cc = 3.3v unless otherwise noted. symbol conditions min typ max units smart card supply v cc output voltage 5v mode, 0 < i cc < 60ma l 4.65 5.0 5.35 v 3v mode, 0 < i cc < 50ma l 2.75 3.0 3.25 v 1.8v mode, 0 < i cc < 30ma l 1.65 1.8 1.95 v v cc turn on-time i cc = 0ma, 10% to 90% l 0.8 1.5 ms undervoltage detection relative to nominal output l C9 C5 C2.5 % overcurrent detection l 60 110 150 ma smart card detection debounce time ( pres to d7) l 15 32 60 ms pres pull-up current v pres = 0 l 1 2.5 m a deactivation time ( rst to v cc = 0.4v) i cc = 0ma, c vcc = 1 m f l 100 250 m s clk (non-bidirectional modes) low level output voltage (v ol ), (note 2) sink current = C 200 m a l 0.2 v high level output voltage (v oh ), (note 2) source current = 200 m a l v cc C 0.2 v rise/fall time, (note 2) loaded with 50pf, 10% to 90% l 16 ns clk frequency, (note 2) l 10 mhz rst, c4, c8 low level output voltage (v ol ), (note 2) sink current = C 200 m a l 0.2 v high level output voltage (v oh ), (note 2) source current = 200 m a l v cc C 0.2 v rise/fall time, (note 2) loaded with 50pf, 10% to 90% l 100 ns i/o, clk (clk specifications in bidirectional mode only) low level output voltage (v ol ), (note 2) sink current = C1ma (v data = 0v or v sync = 0v) l 0.3 v high level output voltage (v oh ), (note 2) source current = 20 m a (v data = v dvcc or l 0.85 ? v cc v v sync = v dvcc ) rise/fall time, (note 2) loaded with 50pf, 10% to 90% l 500 ns short circuit current, (note 2) v data = 0v or v sync = 0v l 510ma data, sync (sync specifications in bidirectional mode only) low level output voltage (v ol ) sink current = C 500 m a (v i/o = 0v or v clk = 0v) l 0.3 v high level output voltage (v oh ) source current = 20 m a (v i/o = v cc or v clk = v cc ) l 0.8 ? dv cc v rise/fall time loaded with 50pf l 500 ns r in , d in , sclk, ld, sync, async (sync specifications for non-bidirectional mode) low input threshold (v il ) l 0.15 ? dv cc v high input threshold (v ih ) l 0.85 ? dv cc v input current (i ih /i il ) l C1 1 m a d out low level output voltage (v ol ) sink current = C 200 m a l 0.3 v high level output voltage (v oh ) source current = 200 m a l dv cc C 0.3 v underv threshold l 1.17 1.23 1.29 v leakage current v underv = 3.3v l 50 na
ltc4556 4 4556f electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v batt = 3.3v, dv cc = 3.3v unless otherwise noted. parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: this specification applies to all three smart card voltage classes: 1.8v, 3v and 5v. note 3: r olcp o (2v batt C v cpo )/i cpo ; v cpo will depend upon total load (i cc ) and minimum supply voltage v batt . see figure 6. note 4: the ltc4556e is guaranteed to meet performance specifications from 0 c to 70 c. specifications over the C 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. note 5: based on long term current density limitation. typical perfor a ce characteristics uw v batt supply voltage (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply current ( a) 4556 g01 500 400 300 200 100 0 t a = 25 c i cc = 0 a v cc = 5v v cc = 1.8v v cc = 3v temperature ( c) C40 C15 10 35 60 85 short-circuit current (ma) 4556 g02 6.0 5.5 5.0 4.5 4.0 3.5 dv cc = v batt = 3.3v v cc = 5v clk i/o temperature ( c) ?0 ?5 10 35 60 85 output resistance ( ) 4556 g03 10 9 8 7 6 v batt = 2.7v v cpo = 4.9v no load supply current vs v batt i/o and clk short-circuit current vs temperature (clk in bidirectional mode) charge pump open-loop output resistance vs temperature (2v batt C v cpo ) / i cpo fault low level output voltage (v ol ) sink current = C 200 m a l 0.005 0.3 v leakage current v fault = 5.5v l 1 m a serial port timing t ds d in valid to sclk setup 8 ns t dh d in valid to sclk hold 8 ns t dd d out output delay c load = 15pf 15 60 ns t l sclk low time 50 ns t h sclk high time 50 ns t lw ld pulse width 50 ns t cl sclk to ld 50 ns t lc ld to sclk 0ns
ltc4556 5 4556f typical perfor a ce characteristics uw temperature ( c) C40 C15 10 35 60 85 load current (ma) 4556 g04 140 130 120 110 100 90 80 v batt = 3.3v v cc = 1.8v, cpo = 4v v cc = 3v, cpo = 5.5v v cc = 5v, cpo = 5.5v v batt supply voltage (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 debounce time (ms) 4556 g05 50 45 40 35 30 25 t a = 85 c t a = 25 c t a = C40 c temperature ( c) C40 C15 10 35 60 85 i/o low output voltage (mv) 4556 g06 200 175 150 125 100 v data = v sync = 0v i ol = C1ma v batt = 3v v cc = 1.8v v cc = 3v, 5v load current (ma) extra input current (ma) 6 5 4 3 2 1 0 0.01 1 10 4556 g07 0.1 100 v batt = 3.3v t a = 25 c v cc overcurrent shutdown threshold vs temperature card detection debounce time vs v batt supply voltage bidirectional channel (i/o) low output level vs temperature extra input current vs load current (i batt C 2i cc ) v batt shutdown current vs supply voltage dv cc shutdown current vs supply voltage charge pump and ldo activation deactivation sequence data C i/o channel v cpo 5v/div v cc 5v/div i/o 5v/div 1ms/div 4556 g10 10 m s/div 4556 g11.eps i/o 2v/div data 2v/div 100ns/div 4556 g12 rst 5v/div i/o 5v/div v cc 5v/div clk 5v/div v batt supply voltage (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply current ( a) 4556 g08 3.0 2.5 2.0 1.5 1.0 0.5 0 t a = 85 c t a = 25 c t a = 40 c v dvcc = v batt v dvcc supply voltage (v) 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 supply current ( a) 4556 g09 1.0 0.8 0.6 0.4 0.2 0 t a = 25 c t a = 85 c t a = C40 c v batt = v dvcc
ltc4556 6 4556f cpo (pin 12): charge pump. cpo is the output of the charge pump. when the smart card requires power, the charge pump will charge cpo to either 3.7v or 5.35v depending on what smart card voltage is required. a low impedance 1 m f x5r or x7r ceramic capacitor is required on cpo. v cc (pin 13): card socket. the v cc pin should be con- nected to the v cc pin of the smart card socket. the activation of the v cc pin is controlled by the serial port (see tables 1 and 2) and can be set to 0v, 1.8v, 3v or 5v. clk (pin 14): card socket. the clk pin should be con- nected to the clk pin of the smart card socket. the clk signal can be derived from either the sync input or the async input depending on which type of card is being accessed. the card type is selected via the serial port (see tables 1 and 3). in bidirectional mode, the clk pin be- comes an input/output with the microcontroller side sync pin. rst (pin 15): card socket. this pin should be connected to the rst pin of the smart card socket. the rst signal is derived from the r in pin. when the card is selected, its rst pin follows r in . when the card is deselected, the rst pin holds the current value on r in . i/o (pin 16): card socket. the i/o pin connects to the i/o pin of the smart card socket. when the smart card is selected, its i/o pin connects to the data pin. when the smart card is deselected, its i/o pin returns to the idle state (h). c4, c8 (pins 17, 18): card socket. these pins connect to the c4 and c8 pins of synchronous memory cards on the smart card socket. the signal for these pins is unidirec- tional and can only be sent to the card. data for c4 and c8 is transmitted via the data pin and may be selected in place of i/o via the serial port (see table 4). when either c4 or c8 is selected, it will follow the data pin. when it is deselected, it will remain latched at its current state. pres (pin 19): card socket. the pres pin is used to detect the presence of a smart card. it should be connected to a normally open detection switch on the smart card acceptors socket. this pin has a pull-up current source on-chip so no external components are required. pi fu ctio s uuu dv cc (pin 1): power. reference voltage for the control logic. data (pin 2): input/output. microcontroller side data i/o pin. the data pin provides the bidirectional communica- tion path to the smart card. the card may be selected to communicate via the data pin. if several ltc4556s are connected in parallel, the data pin can be made high impedance by selecting neither card socket. the c4 and c8 synchronous card pins can be selected to connect to the data pin via the serial port (see table 4). r in (pin 3): input. the r in pin supplies the rst signal to the smart card. it is level shifted and transmitted directly to the rst pin of a selected card. when the card is deselected, the rst pin is latched at its current state. sync (pin 4): input-input/output. the sync pin provides the clock input for synchronous smart cards. when a synchronous card is selected, its clk pin follows sync directly. when a synchronous card is deselected, the clk pin is latched at its current state. in bidirectional mode, the sync pin becomes an input/output with the smart card clk pin. async (pin 5): input. the async pin provides the clock input for asynchronous cards and should be connected to a free running clock. the clock signal to the smart card can be a ? 1, ? 2, ? 4 or ? 8 version of the signal on async. asynchronous cards can also be placed in clock stop mode with the clock stopped either high or low. fault (pin 6): output. the fault pin can be used as an interrupt to a microcontroller to indicate when a fault has occurred. it is an open drain output, which is logically equivalent to d4 . (see table 1) nc (pin 7): no connection to chip. may be grounded. gnd (pin 8): ground. power ground for the chip. this pin should be connected directly to a low impedance ground plane. c C , c + (pins 9, 11): charge pump. charge pump flying capacitor pins. a 1 m f x5r or x7r ceramic capacitor should be connected from c + to c C . v batt (pin 10): power. supply voltage for analog and power sections of the ltc4556.
ltc4556 7 4556f sclk. d out can be connected directly to a microcontroller or the d in pin of another ltc4556 or ltc1955 for daisy chained operation. sclk (pin 23): input. the sclk pin clocks the serial port. each new data bit is received on the rising edge of sclk. sclk should be left high during idle times and should not be clocked when ld is low. ld (pin 24): input. the falling edge of this pin loads the current state of the shift register into the command regis- ter. command changes to the smart card will be updated on the falling edge of ld. the rising edge of ld latches status information into the shift register for the next read/ write cycle. sgnd (pin 25): exposed pad. must be soldered to pcb ground. underv (pin 20): input. the underv pin provides security by supplying a precision undervoltage threshold for external supply monitoring. an external resistive volt- age divider programs the desired undervoltage threshold. once underv falls below 1.23v, the ltc4556 automati- cally begins the deactivation sequence. if external supply monitoring is not required, the underv pin should be connected to either v batt or dv cc . d in (pin 21): input. input for the serial port. command data is shifted into d in synchronously with sclk. d in can be connected directly to a microcontroller or the d out pin of another ltc4556 or ltc1955 for daisy chained operation. d out (pin 22): output. output for the serial port. smart card status data is shifted out of d out synchronously with pi fu ctio s uuu block diagra w c4 c8 i/o rst clk v cc v batt dv cc gnd charge pump fault underv 1.23v pres 4556 bd smart card socket digital supply smart card communications serial port command/status data c + c C cpo + C reset control logic status data command latch shift register + C t d in d out sclk ld clock control logic charge pump data async sync r in 24 23 22 21 3 4 5 2 6 1 20 19 15 14 18 17 13 11 9 8 10 12 ldo 16
ltc4556 8 4556f serial port the microcontroller compatible serial port provides all of the command and control inputs for the ltc4556 as well as the status of the smart card. data on the d in input is loaded on the rising edge of sclk. d7 is loaded first and d0 last. at the same time the command bits are being shifted into the d in input, the status bits are being shifted out of the d out output. the status bits are presented to d out on the rising edge of sclk. once all bits have been clocked into the shift register, the command data is loaded into the command latch by bringing ld low. at this time the command latch is updated and the ltc4556 will begin to act on the new command set. when ld is low, the shift register is transparent to the status data of the smart card channel. the status data is latched into the shift register on the rising edge of ld. sclk should be held in the high state when idle and should only be clocked when ld is high. likewise ld should only be brought high when sclk is high. figure 2 shows the operation of the serial port. multiple ltc4556s may be daisy chained together by connecting the d out pin of one ltc4556 to the d in pin of another. figure 7 shows an example of an ltc4556 daisy chained together with ltc1955s. the maximum clock rate for the serial port is 10mhz. the serial port controls the following parameters of the smart card socket: ? selection/deselection of the smart card ?v cc voltage level of the card (5v/3v/1.8v/0v) ? clock mode of the card (synchronous, asynchronous or bidirectional) ? operating mode of asynchronous cards (clock stop high, low, ? 1, ? 2, ? 4 or ? 8) ? selection of the i/o, c4 or c8 pins the serial port provides the following status data: ? it indicates the presence or absence of the smart card. ? it indicates the readiness of the smart card v cc supply. communication with the smart card is disabled until its power supply voltage has reached the final value. ? it indicates fault status. in the event of an electrical or atr fault, the fault is reported. for electrical faults, the ltc4556 will automatically deactivate the smart card. table 1 illustrates the command inputs and status outputs associated with each bit of the serial data word. three voltage options are available from the ltc4556: 5v, 3v and 1.8v. bits d0, d1 determine which voltage is selected. setting both control bits to 0 deactivates the card and sets the smart card supply voltage to 0v. table 2 shows the operation of the supply control bits. the clk pin to the smart card can be programmed for various modes. both synchronous and asynchronous cards are supported. there are several options available with asynchronous cards. table 3 shows how all clock options are obtained using bits d5Cd7. figure 2. serial port timing diagram d in sclk ld x d0 d7 xd1 d out d7 from input d0 d7 4556 f02 d6 d5 d7 d1 t lc t dh t dd t ds t h t l t lw t cl d6 d2 operatio u
ltc4556 9 4556f to receive status data from the serial port, a read/write operation must be performed. when polling for the pres- ence of a smart card, the input word may be set to $00 since this is the shutdown command for the ltc4556. data channel the data channel is level shifted to the appropriate v cc voltages at the i/o pin. an nmos pass transistor performs the level shifting. the gate of the nmos transistor is biased such that the transistor is completely off when both sides have relin- quished the channel. if one side of the channel asserts an l, then the transistor will convey the l to the other side. operatio u table 3. clock options d7 d6 d5 clock mode 0 0 0 synchronous mode 0 0 1 bidirectional mode 0 1 0 asynchronous stop low 0 1 1 asynchronous stop high 1 0 0 asynchronous ? 1 1 0 1 asynchronous ? 2 1 1 0 asynchronous ? 4 1 1 1 asynchronous ? 8 table 2. v cc and shutdown options d1 d0 status 00v cc = 0v (shutdown) 01v cc = 1.8v 10v cc = 3v 11v cc = 5v table 1. serial port commands status output bit command input 0d0v cc options 0 d1 (see table 2) 0 d2 card select/deselect 0 d3 card communications card electrical fault d4 options (see table 4) card atr fault d5 card clock options card v cc ready d6 (see table 3) card present d7 table 4. communications options d4 d3 communication mode 0 0 nothing selected 0 1 c4 connected to data pin 1 0 c8 connected to data pin 1 1 i/o connected to data pin note that current passes from the receiving side of the channel to the transmitting side. the low output voltage of the receiving side will be dependent upon the voltage at the transmitting side plus the ir drop of the pass transistor. when a card socket is selected, it becomes a candidate to drive data on the data pin and likewise receive data from the data pin. when a card socket is deselected, the voltage on its i/o pin will return to the idle state (h) and the data side of that channel will become high impedance. the ltc4556 includes provision for unidirectional com- munication with the c4 and c8 pins of the smart card. the c4, c8 and i/o pins are individually multiplexed to the data pin using bits d3 and d4 as shown in table 4. dynamic pull-up current sources the current sources on the bidirectional pins (data, i/o) are dynamically activated to achieve a fast rise time with a relatively small static current. once a bidirectional pin is relinquished, a small start up current begins to charge the node. an edge rate detector determines if the pin is released by comparing its slew rate with an internal reference value. if a valid transition is detected, a large pull-up current enhances the edge rate on the node. the higher slew rate corroborates the decision to charge the node thereby affecting a dynamic form of hysteresis. figure 3. dynamic pull-up current sources + dv dt v ref local supply bidirectional pin 4556 f03 i start
ltc4556 10 4556f clock channel as described in the section serial port, the ltc4556 supports both synchronous and asynchronous smart cards. when bits d5-d7 are set to 0s, the clock channel is in synchronous mode. in synchronous mode, the clk pin follows the sync pin for a channel that is selected. if the channel is deselected (via the serial port) the clk line is latched at its current value. when control bits d7, d6 and d5 are set to 0, 0 and 1 respectively, the clock channel is in bidirectional mode. this mode permits clock stretching when communicating with bidirectional cards. the bidirectional level translation circuit is identical to the i/o-data circuit. a low can be asserted from either the sync pin or the clk pin and the other pin will follow. the low can be handed off to affect clock stretching if both sides assert at the same time. it will not run as fast as the unidirectional synchronous or asynchronous modes but does employ accelerating pull- up sources on both sides for maximum clock rate. in asynchronous mode the clk pin follows either the async pin ( ? 1 mode) or a divided version of this pin. the clk pin can also be stopped high or low. the available divider ratios include ? 2, ? 4 and ? 8. when switching between divider ratios, the internal selection circuitry ensures that no spikes or glitches appear on the clk pin. consequently, it may take up to 8 clock pulses for the clock frequency change command to take affect. synchroniza- tion circuitry ensures that no glitches occur when entering or exiting one of the stop modes. for example, when entering stop low mode, the selection circuitry waits for the next falling edge of the clk signal to make the change. likewise if stop high is selected it will occur on the next rising edge. deselection of an asynchronous card does not affect its clk pin. its clock can be started, stopped or its divider ratio changed at any time. to clean up the duty cycle of the incoming clock in asynchronous applications, any of the clock divider modes ? 2, ? 4 or ? 8 will yield a very nearly 50% duty cycle. additional synchronization circuitry prevents glitches from occurring when switching between synchronous mode and asynchronous mode. because of this circuitry, two edges (a falling edge followed by a rising edge) are necessary at the clk pin to switch modes from asynchro- nous to synchronous. for example, if clock stop mode is engaged, the clock channel will not change modes until clock stop mode is disengaged. both sync and async inputs are independently level shifted to the appropriate voltage for the clk pin (5v, 3v, 1.8v). reset channel when the card is selected, the reset channel provides a level shifted path from the r in pin to the rst pin. when the card is deselected its rst pin is latched at the current value of r in . smart card detection circuit the pres pin is used to detect the presence of a smart card. an automatic debounce circuit waits until a smart card has been present for a continuous period of typically 32ms. once a valid card indication exists, the status bit is updated and may be polled by cycling data through the serial port. the d out pin (equivalent to d7) of the serial port can be used to indicate the presence of a card in real time if ld is held low. the pres pin has a built-in pull-up current source so no external components are required for switch detection. the pull-up current source is designed to have a small current when the pin voltage is below approximately 1v but somewhat higher current when the pin voltage reaches 1v. this helps maintain low power dissipation when a card is present and yet fast response time to a card removal. activation/deactivation for maximum flexibility, the activation sequencing of the smart card is left to the application programmer. however, deactivation can be achieved either manually or automati- cally. an electrical fault condition will trigger the automatic deactivation. operatio u
ltc4556 11 4556f the built-in deactivation sequence can be executed via the serial port simply by setting the control bits d0 and d1 to 0. the deactivation sequence is outlined below. 1. the rst pin is immediately brought low. 2. the deactivation of the clk pin depends upon which type of card is used: if the smart card was set to asynchronous mode then the clk pin will be latched low on its next falling edge. if no falling edges occur within 5 m s (min) then the clk line is forced low. if the smart card was set to synchronous mode then the clk pin is immediately latched at its current value (either high or low) and then forced low after a duration of 5 m s (min). during the 5 m s timeout period, changes on sync will be ignored. 3. the i/o, c4 and c8 pins are brought low. 4. the v cc pin is brought low. upon activation, to comply with relevant smart card stan- dards, none of the smart card signal pins will be allowed to go high before the smart card supply voltage (v cc ) has reached its final value. electrical fault detection several types of faults are detected by the ltc4556. they include v cc undervoltage, v cc overcurrent, clk, rst, c8, c4 short circuit, card removal during a transaction, failed answer to reset (atr), supply undervoltage or underv and chip overtemperature. to prevent false errors from plaguing the microcontroller, the electrical faults are acted upon only after a 5 m s (min) timeout period. card removal during transaction faults initiate the deactivation sequence immediately. v cc undervoltage faults are determined by comparing the actual output voltage with the internal reference voltage. if the output is more than ~5% below its set point for the entire timeout period, the fault is reported and the deacti- vation sequence is initiated. v cc overcurrent faults are detected by comparing the output current of the ldos with an internal reference level. if the current of the ldo is more than 110ma (typ) for the entire timeout period, the fault is reported and the deacti- vation sequence is initiated. clk and rst faults are detected by comparing the outputs of these pins with their expected signals. if the signal on a pin is incorrect for the entire timeout period, the fault is reported and the deactivation sequence is initiated. the clock channel is a special case. since it can have a free running clock, the error indication is accumulated over a longer period of time without being cleared. even though the clock may be running, an error will still be detected. an overtemperature fault is detected by sensing the junc- tion temperature of the ic. if the junction temperature exceeds approximately 150 c for the entire timeout period, the fault is reported by setting the fault bit (d4) and the deactivation sequence is initiated. a card removal fault is determined as soon as the pres pin is high. once this occurs the fault is reported and the deactivation sequence is initiated. if no card is present, and the application software attempts to power up a card socket, an automatic fault will result. short circuits on the i/o line will not be detected by the fault detection hardware; however, a short circuit from i/o to v cc will be compliant with the maximum current limits set by applicable standards (<15ma). the same is true of the clk pin when it is set to bidirectional mode. answer to reset (atr) fault detection answer to reset faults are detected by an internal counter that is started once the rst line goes high. if the data pin remains high for 40,000 clock cycles, the atr fault bit is set in the serial ports status register (see table 1). an atr fault can not occur if the clock mode is set to synchronous. atr faults will only occur for asynchronous smart cards. operatio u
ltc4556 12 4556f atr faults are cleared by bringing the rst pin low via r in . an atr fault will not automatically deactivate the smart card. it is the application programmers responsibility to check the status register for atr faults and deactivate the smart card in accordance with smart card standards. generally, the application has 50ms (emv 2.1.3.1, 2.1.3.2) from the 40,000th clock pulse to deactivate the card. once the ltc4556 receives the deactivation command, it will shut down the smart card in less than 250 m s. operatio u using the fault pin the fault pin can be used as an interrupt to a microcon- troller. it is an open-drain output and generally requires a pull-up resistor. the fault pin will go low when an electrical fault occurs. the fault pin is logically equiva- lent to d4 (see table 1).
ltc4556 13 4556f 10kv esd protection all smart card pins (clk, rst, i/o, c4, c8 and v cc ) can withstand over 10kv of human body model esd in-situ. in order to ensure proper esd protection, careful board layout is required. the gnd pin should be tied directly to a ground plane. the multilayer ceramic chip v cc capaci- tor should be located very close to the v cc pin and tied immediately to the ground plane. capacitor selection warning: a polarized capacitor such as tantalum or alumi- num should never be used for the flying capacitor since its voltage can reverse upon start up of the ltc4556. low esr ceramic capacitors should always be used for the flying capacitor. a total of four capacitors are required to operate the ltc4556. an input bypass capacitor is required at v batt and dv cc . an output bypass capacitor is required on the smart card v cc pin. a charge pump flying capacitor is required from c + to c C and a charge storage capacitor is required on the charge pump out pin cpo. to prevent excessive noise spikes due to charge pump operation, low esr (equivalent series resistance) multi- layer ceramic chip capacitors are strongly recommended. there are several types of ceramic capacitors available each having considerably different characteristics. for example, x7r/x5r ceramic capacitors have excellent volt- age and temperature stability but relatively low packing density. y5v ceramic capacitors have apparently higher packing density but poor performance over their rated voltage or temperature ranges. under certain voltage and temperature conditions y5v and x7r/x5r ceramic ca- pacitors can be compared directly by case size rather than specified value for a desired minimum capacitance. placement of the capacitors is critical for correct operation of the ltc4556. because the charge pump generates large current steps, all of the capacitors should be placed as close to the ltc4556 as possible. the low impedance applicatio s i for atio wu u u nature of multilayer ceramic chip capacitors will minimize voltage spikes but only if the power path is kept very short (i.e., minimum inductance). the v batt node should be especially well bypassed. the capacitor for this node should be directly adjacent to the qfn package. the cpo and flying capacitors should be very close as well. the ltc4556 can tolerate more distance between the ldo capacitor and the v cc pin. figure 4 shows an example of a tight printed circuit board layout using single layer copper. for best performance a multilayer board can be used and should employ a solid ground plane on at least one layer. the following capacitors are recommended for use with the ltc4556: type value case size murata p/n batt, cpo, x5r 1 m f 0603 grm39 x5r 105k 6.3 c fly , v cc cdv cc x5r 0.1 m f 0402 grm36 x5r 104k 10 v cc gnd v batt cpo 4556 f04 figure 4. optimum single layer pcb layout
ltc4556 14 4556f daisy-chained operation for applications requiring more than one card socket, the serial port of the ltc4556 is designed to be easily daisy- chained. the d out pin of one ltc4556 can be connected directly to the d in pin of another ltc4556 or ltc1955. rather than sending one 8-bit byte before asserting ld, the microcontroller should send one 8-bit byte per device. ld should only be asserted after all devices have been updated. figure 7 shows an ltc4556 cascaded in daisy chain fashion with two ltc1955s. in this case the microcontroller would write five 8-bit bytes before assert- ing the ld pin. interfacing to a microcontroller the serial port of the ltc4556 can be connected directly to a 68hc11 style microcontrollers serial port. the micro- controller should be configured as the master device and its clocks idle state should be set to high (mstr = 1, cpol = 1 and cpha = 0 for the mc68hc11 family). figure 5 shows the recommended configuration and di- rection of data flow. note that an additional i/o line is necessary for ld to load the data once it has shifted around the loop. command data is latched into the command register on the falling edge of the ld signal. the ltc4556 will begin to act on new command data as soon as ld goes low. any general purpose microcontroller i/o line can be configured to control the ld pin. the status of the ltc4556 is returned over the serial port. status data is latched into the shift register on the rising edge of the ld pin. whenever the system is waiting for status data from the ltc4556, its ld pin should be held low. figure 5. microcontroller interface card 4556 f05 d in d out sclk ld ltc4556 mosi miso sck i/o controller applicatio s i for atio wu u u
ltc4556 15 4556f asynchronous card detection since the shift register is transparent when ld is held low, d out is the same as d7. recall from table 1 that d7 indicates the status of the card detection channel. thus it is not necessary to perform an entire read/write opera- tion to determine the card detection status. with ld low, d out can be used to generate a real time card detection interrupt. using the underv pin the underv pin can be used to add protection against a supply undervoltage fault. by using two external program- ming resistors, the undervoltage detection can be set to an arbitrary level (figure 8). to ensure that the smart card is properly shut down, there must be sufficient energy available in the input bypass capacitor to run it until the deactivation cycle begins. it can take approximately 30 m s from the detection of a fault until the deactivation se- quence begins. it is desirable to maintain the v batt supply at 2.7v or greater during this period. consider the following (worst-case) example: 1) the underv pin is programmed to trip below 3.1v. 2) it is possible to have the card activated at 5v and drawing 60ma. since the output voltage is programmed to 5v, the charge pump will be acting as a voltage doubler. with the card drawing 60ma, the input current will be 2 ? (60ma) or about 120ma. allowing the v batt supply to droop from 3.1v to 2.7v during the 30us timeout period the input capacitance would need to be at least 120ma/[(3.1v C 2.7v)/30 m s] or 9 m f. zero shutdown current although the ltc4556 is designed to have very low shutdown current it can still draw over a microampere on both dv cc and v batt when in shutdown. for applications that require virtually zero shutdown current, the dv cc pin can be grounded. this will reduce the v batt current to well under a single microampere. internal logic ensures that the ltc4556 is in shutdown when dv cc is grounded. note, however, that all of the logic signals that are refer- enced to dv cc (d in , sclk, ld, data, r in , sync and async) will have to be at 0v as well to prevent esd diodes to dv cc from being forward biased. operation at higher supplies if a 5.5v to 6v supply voltage is available, it is possible to achieve some power savings by overriding the charge pump. the higher supply can be connected directly to the cpo pin. as long as the voltage on cpo is higher than that at which it ordinarily regulates (5.35v or 3.7v depending on voltage selections) the charge pumps oscillator will not run. this configuration can give considerable power savings since the charge pump is not being used. applicatio s i for atio wu u u
ltc4556 16 4556f a voltage source is still needed on both dv cc and v batt in this configuration. recall that dv cc sets the logic refer- ence level for all the control and smart card communica- tion pins. the voltage on v batt can be any convenient level that meets the parameters in the electrical characteristics table. the 5.5v to 6v supply can be left permanently connected to cpo but there will be approximately 5 m a of current flow into cpo when the ltc4556 is in shutdown. charge pump strength under low v batt conditions, the amount of current avail- able to the smart card is limited by the charge pump. figure 6 shows how the ltc4556 can be modeled as a thevenin equivalent circuit to determine the amount of current available given the effective input voltage, 2v batt and the effective open-loop output resistance, r olcp . from figure 6, the available current is given by: i vv r cc batt cpo olcp 2 r olcp is dependent on a number of factors including the switching term, 1/(f osc ? c fly ), internal switch resis- tances and the nonoverlap period of the switching circuit. however, for a given r olcp , the minimum cpo voltage can be determined from the following expression: vvir cpo batt cc olcp 3 2() the ldo has been designed to meet all applicable smart card standards for v cc with v cpo as low as 5.13v. given this information, trade-offs can be made by the user with regard to total consumption (i cc ) and minimum supply voltage. changing the smart card supply voltage although the ltc4556 control system will allow the smart card voltage to be changed from one value to the next without an interim power down, this is not recommended. when changing from a higher voltage to a lower voltage there will generally not be a problem; however, changing from a lower voltage to a higher voltage can result in both an undervoltage condition or an overcurrent condition. the likely result is that the ltc4556 will automatically deactivate. applicable smart card standards specify that the smart card supply be powered to zero before applying a new voltage. compliance testing inductance due to long leads on type approval equipment can cause ringing and overshooot that leads to testing problems. small amounts of capacitance and damping resistors can be included in the application without com- promising the normal electrical performance of the ltc4556 or smart card system. generally a 100 w resistor and a 20pf capacitor will accomplish this as shown in figure 9. applicatio s i for atio wu u u + ldo 2v batt 4556 f06 cpo r olcp v cc figure 6. equivalent open-loop circuit
ltc4556 17 4556f figure 7. an ltc4556 and two ltc1955s daisy chained together 4-wire command interface 4-wire card interface smart card ltc4556 1 f 1 f 1 f d in d out sclk ld data r in sync async cpo input power fault v batt gnd dv cc underv fault pres c + c vendor card vendor card ltc1955 4.7 f d in d out sclk ld data r in sync async cpo v batt gnd dv cc underv fault vendor card vendor card 4556 f07 ltc1955 4.7 f d in d out sclk ld data r in sync async cpo v batt gnd dv cc underv fault 4.7 f 4.7 f 10 8 12, 13 9, 10 12, 13 9, 10 1 19 6 20 24 23 24 23 1 21 22 23 24 2 3 4 5 1 27 28 26 25 29 30 32 31 911 1 f pres a pres b c + c 21 2 11 14 1 f pres a pres b c + c 21 2 11 14 27 28 26 25 29 12 15 15 30 32 31 applicatio s i for atio wu u u
ltc4556 18 4556f applicatio s i for atio wu u u smart card socket i/o clk rst v cc c7 c3 c2 c1 c5 ltc4556 100 100 100 1 f 0.1 f 20pf 4556 f09 20pf 20pf fiugre 9. additional components for improved compliance testing 20 ltc4556 4556 f08 r2 r1 main supply v trip = 1.23v (1 + r1/r2) underv figure 8. setting the undervoltage trip point
ltc4556 19 4556f package descriptio u uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?o be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.38 0.10 24 0.23 typ (4 sides) 23 1 2 bottom view?xposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uf24) qfn 1103 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline
ltc4556 20 4556f part number description comments ltc1555l/ltc1555l-1.8 1mhz, sim power supply and level translator v in : 2.6v to 6.6v, v out = 1.8v/3v/5v, i q = 32 m a, for 1.8v/3v/5v sim cards i sd < 1 m a, ssop16 ltc1555/ltc1556 650khz, sim power supply and level translator v in : 2.7v to 10v, v out = 3v/5v, i q = 60 m a, i sd < 1 m a, for 3v/5v sim cards ssop16, ssop20 ltc1755/ltc1756 850khz, smart card interface with serial control for 3v/5v v in : 2.7v to 7v, v out = 3v/5v, i q = 60 m a, i sd < 1 m a, smart card applications ssop16, ssop24 ltc1955 dual smart card interface with serial control for 1.8v/3v/5v v in : 3v to 5.5v, v out = 1.8v/3v/5v, i q = 200 m a, smart card applications i sd < 1 m a, qfn32 ltc1986 900khz, sim power supply for 3v/5v sim cards v in : 2.6v to 4.4v, v out = 3v/5v, i q = 14 m a, i sd < 1 m a, thinsot ltc4555 sim power supply and level translator v in : 3v to 6v, v out = 1.8v/3v, i q = 40 m a, i sd < 1 m a, for 1.8v/3v sim cards qfn16 ltc4557 dual sim/smart card power supply and level translator v in : 2.7v to 5.5v, v out = 1.8v/3v, i q = 250 m a, i sd < 1 m a, for 1.8v/3v cards qfn16 thinsot is a trademark of linear technology corporation. linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0604 1k ? printed in usa related parts typical applicatio u smart card ltc4556euf 1 f d in dv cc v cc underv v batt async d out sclk r in ld data i/o c4 c8 rst clk v cc cpo v gnd c 911 12 c + fault 4556 ta02 6 20 1 4 10 21 22 23 24 5 3 2 42 41 43 44 24 9 1 16 17 18 15 14 13 pres 19 c7 c4 c8 c2 c3 c1 8 1 f 28 15 0.1 f v + 1 5 0.1 f 1 f 0.1 f c5 rd td gnd db9 0.1 f 1k 0.1 f xirq 19 37 0.1 f 180k li-ion 4.7 f 262k + rst 2 1 36 v cc18 45 v cc3 3 v cca gnd ltc1728es5-1.8 dren 17 rxen 16 mod b 21 v dd v rh 45 22 26 27 18 20 xtal extal v rl v ss gnd moda 47k rst 47k reset fault (mosi) pd3 38 irq (2mhz) e (miso) pd2 25 24 40 39 dr1in rx1out 7 8 2 3 dr1out rx1in pd1 (txd) pd0 (rxd) (sck) pd4 pb0 (ss) pd5 (ic3) pa0 28 pc0 sync 4 46 pa7 29 pc1 0.1 f 3 c2 2 c2 + 0.1 f 6 c1 5 c1 + 0.1 f 26 c3 27 c3 + 10m 8.000mhz 27pf 27pf mc68l11e9pb2 ltc1348cg battery-powered rs232 to smart card interface

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