View AD5111BCPZ10-RL7_6520304.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

single-channel, 128-/64-/32-position, up/down, 8% resistor tolerance, nonvolatile digital potentiometer data sheet ad5111 / ad5113 / ad5115 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011C2012 analog devices, inc. all rights reserved. features nominal resistor tolerance error: 8% maximum wiper current: 6 ma rheostat mode temperature coefficient: 35 ppm/c low power consumption: 2.5ma max @ 2.7 v and 125c wide bandwidth: 4 mhz (5 k option) power-on eeprom refresh time < 50 s 50-year typical data retention at 125c 1 million write cycles 2.3 v to 5.5 v supply operation chip select enable multiple device operation wide operating temperature: ?40c to +125c thin, 2 mm 2 mm 0.55 mm 8-lead lfcsp package applications mechanical potentiometer replacement portable electronics level adjustment audio volume control low resolution dac lcd panel brightness and contrast control programmable voltage to current conversion programmable filters, delays, time constants feedback resistor programmable power supply sensor calibration functional block diagram gnd rdac register up/down control logic power-on reset v dd u/d clk cs eeprom data data a w b en ad5111/ ad5113/ ad5115 09654-001 figure 1. table 1. 8% resistance tolerance family model resistance (k) position interface ad5110 10, 80 128 i 2 c ad5111 10, 80 128 up/down ad5112 5, 10, 80 64 i 2 c ad5113 5, 10, 80 64 up/down ad5116 5, 10, 80 64 push-button ad5114 10, 80 32 i 2 c ad5115 10, 80 32 up/down general description the ad5111 / ad5113/ ad5115 provide a nonvolatile solution for 128-/64-/32-position adjustment applications, offering guaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the a, b, and w pins. the low resistor tolerance, low nominal temperature coefficient, and high bandwidth simplify open-loop applications, as well as tolerance matching applications. the new low wiper resistance feature minimizes the wiper resistance in the extremes of the resistor array to only 45 , typical. a simple 3-wire up/down interf ace allows manual switching or high speed digital control with clock rates up to 50 mhz. the ad5111 / ad5113/ ad5115 are available in a 2 mm 2 mm lfcsp package. the parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c.
ad5111/ad5113/ad5115 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characte risticsad5111 .......................................... 3 electrical characte risticsad5113 .......................................... 5 electrical characte risticsad5115 .......................................... 7 interface timing specifications .................................................. 9 timing diagram ........................................................................... 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 12 test circuits ..................................................................................... 17 theory of operation ...................................................................... 18 rdac register and eeprom .................................................. 18 basic operation .......................................................................... 18 low wiper resistance feature ................................................. 18 shutdown mode ......................................................................... 18 eeprom write operation ....................................................... 18 rdac architecture .................................................................... 19 programming the variable resistor ......................................... 19 programming the potentiometer divider ............................... 20 terminal voltage operating range ......................................... 20 power-up sequence ................................................................... 21 layout and power supply biasing ............................................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 4/12rev. 0 to rev. a changes to features section............................................................ 1 changes to positive supply current, table 2 ................................ 3 changes to positive supply current, table 3 ................................ 5 changes to positive supply current, table 4 ................................ 7 updated outline dimensions ....................................................... 22 10/11revision 0: initial version
data sheet ad5111/ad5113/ad5115 rev. a | page 3 of 24 specifications electrical characteristics ad5111 10 k and 80 k versions: v dd = 2.3 v to 5.5 v, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 2. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 7 bits resistor integral nonlinearity 2 r-inl r ab = 10 k, v dd = 2.3 v to 2.7 v ?2.5 0.5 +2.5 lsb r ab = 10 k, v dd = 2.7 v to 5.5 v ?1 0.25 +1 lsb r ab = 80 k ?0.5 0.1 +0.5 lsb resistor differential nonlinearity 2 r-dnl ?1 0.25 +1 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.5 0.15 +0.5 lsb differential nonlinearity 4 dnl ?0.5 0.15 +0.5 lsb full-scale error v wfse r ab = 10 k ?2.5 lsb r ab = 80 k ?1.5 lsb zero-scale error v wzse r ab = 10 k 1.5 lsb r ab = 80 k 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 , 6 c a , c b f = 1 mhz, measured to gnd, code = half scale 20 pf capacitance w 3 , 6 c w f = 1 mhz, measured to gnd, code = half scale 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh 2 v low v inl 0.8 v input current 3 i n 1 a input capacitance 3 c in 5 pf power supplies single-supply power range 2.3 5.5 v positive supply current i dd v ih = v dd or v il = gnd, v dd = 5 v 0.75 3.5 ma v ih = v dd or v il = gnd, v dd = 2.7 v 2.5 ma v ih = v dd or v il = gnd, v dd = 2.3 v 2.4 ma eemem store current 3 , 7 i dd_nvm_store 2 ma eemem read current 3 , 8 i dd_nvm_read 320 a power dissipation 9 p diss v ih = v dd or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 10 k ?50 db r ab = 80 k ?64 db
ad5111/ad5113/ad5115 data sheet rev. | page 4 of 24 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 3 , 10 bandwidth bw code = half scale, ?3 db r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd / 2, f = 1 khz, code = half scale r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 10 k 3 s r ab = 80 k 12 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 10 k 9 nv/hz r ab = 80 k 20 nv/hz flash/ee memory reliability 3 endurance 11 t a = 25c 1 mcycles 100 kcycles data retention 12 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 r-inl is the deviation from an ideal value measured between the maximum resistance and the min imum resistance wiper positions. r-dnl measures the relative step change from ideal between succes sive tap positions. the maximum wi per current is limited to 0.8 v dd /r ab . 3 guaranteed by design and characterization; not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor termin al w have no limitations on current direction with respect to eac h other. 6 c a is measured with v w = v a = 2.5 v, c b is measured with v w = v b = 2.5 v, and c w is measured with v a = v b = 2.5 v. 7 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 8 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 9 p diss is calculated from (i dd v dd ). 10 all dynamic characteristics use v dd = 5.5 v and v logic = 5 v. 11 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 12 retention lifetime equivalent at junction temperature (t j ) is 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory. a
data sheet ad5111/ad5113/ad5115 rev. a | page 5 of 24 electrical characteristics ad5113 5 k, 10 k, and 80 k versions: v dd = 2.3 v to 5.5 v, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 3. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 6 bits resistor integral nonlinearity 2 r-inl r ab = 5 k, v dd = 2.3 v to 2.7 v ?2.5 0.5 +2.5 lsb r ab = 5 k, v dd = 2.7 v to 5.5 v ?1 0.25 +1 lsb r ab = 10 k ?1 0.25 +1 lsb r ab = 80 k ?0.25 0.1 +0.25 lsb resistor differential nonlinearity 2 r-dnl ?1 0.25 +1 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.5 0.15 +0.5 lsb differential nonlinearity 4 dnl ?0.5 0.15 +0.5 lsb full-scale error v wfse r ab = 5 k ?2.5 lsb r ab =10 k ?1.5 lsb r ab = 80 k ?1 lsb zero-scale error v wzse r ab = 5 k 1.5 lsb r ab =10 k 1 lsb r ab = 80 k 0.25 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 5 k, 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 , 6 c a , c b f = 1 mhz, measured to gnd, code = half scale 20 pf capacitance w 3 , 6 c w f = 1 mhz, measured to gnd, code = half scale 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh 2 v low v inl 0.8 v input current 3 i n 1 a input capacitance 3 c in 5 pf power supplies single-supply power range 2.3 5.5 v positive supply current i dd v ih = v dd or v il = gnd, v dd = 5 v 0.75 3.5 ma v ih = v dd or v il = gnd, v dd = 2.7 v 2.5 ma v ih = v dd or v il = gnd, v dd = 2.3 v 2.4 ma eemem store current 3 , 7 i dd_nvm_store 2 ma eemem read current 3 , 8 i dd_nvm_read 320 a power dissipation 9 p diss v ih = v dd or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 5 k ?43 db r ab =10 k ?50 db r ab = 80 k ?64 db
ad5111/ad5113/ad5115 data sheet rev. | page 6 of 24 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 3 , 10 bandwidth bw code = half scale, ?3 db r ab = 5 k 4 mhz r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 5 k ?75 db r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 5 k 2.5 s r ab = 10 k 3 s r ab = 80 k 10 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 5 k 7 nv/hz r ab = 10 k 9 nv/hz r ab = 80 k 20 nv/hz flash/ee memory reliability 3 endurance 11 t a = 25c 1 mcycles 100 kcycles data retention 12 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 r-inl is the deviation from an ideal value measured between the maximum resistance and the min imum resistance wiper positions. r-dnl measures the relative step change from ideal between succes sive tap positions. the maximum wi per current is limited to 0.8 v dd /r ab . 3 guaranteed by design and characterization; not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor termin al w have no limitations on current direction with respect to eac h other. 6 c a is measured with v w = v a = 2.5 v, c b is measured with v w = v b = 2.5 v, and c w is measured with v a = v b = 2.5 v. 7 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 8 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 9 p diss is calculated from (i dd v dd ). 10 all dynamic characteristics use v dd = 5.5 v and v logic = 5 v. 11 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 12 retention lifetime equivalent at junction temperature (t j ) is 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory. a
data sheet ad5111/ad5113/ad5115 rev. a | page 7 of 24 electrical characteristics ad5115 10 k and 80 k versions: v dd = 2.3 v to 5.5 v, v a = v dd , v b = 0 v, ?40c < t a < +125c, unless otherwise noted. table 4. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution n 5 bits resistor integral nonlinearity 2 r-inl ?0.5 +0.5 lsb resistor differential nonlinearity 2 r-dnl ?0.25 +0.25 lsb nominal resistor tolerance r ab /r ab ?8 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 35 ppm/c wiper resistance r w code = zero scale 70 140 r bs code = bottom scale 45 80 r ts code = top scale 70 140 dc characteristicspotentiometer divider mode integral nonlinearity 4 inl ?0.25 +0.25 lsb differential nonlinearity 4 dnl ?0.25 +0.25 lsb full-scale error v wfse r ab = 10 k ?1 lsb r ab = 80 k ?0.5 lsb zero-scale error v wzse r ab = 10 k 1 lsb r ab = 80 k 0.25 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 10 ppm/c resistor terminals maximum continuous i a , i b , and i w current 3 r ab = 10 k ?6 +6 ma r ab = 80 k ?1.5 +1.5 ma terminal voltage range 5 gnd v dd v capacitance a, capacitance b 3 , 6 c a , c b f = 1 mhz, measured to gnd, code = half scale 20 pf capacitance w 3 , 6 c w f = 1 mhz, measured to gnd, code = half scale 35 pf common-mode leakage current 3 v a = v w = v b ?500 15 +500 na digital inputs input logic 3 high v inh 2 v low v inl 0.8 v input current 3 i n 1 a input capacitance 3 c in 5 pf power supplies single-supply power range 2.3 5.5 v positive supply current i dd v ih = v dd or v il = gnd, v dd = 5 v 0.75 3.5 ma v ih = v dd or v il = gnd, v dd = 2.7 v 2.5 ma v ih = v dd or v il = gnd, v dd = 2.3 v 2.4 ma eemem store current 3 , 7 i dd_nvm_store 2 ma eemem read current 3 , 8 i dd_nvm_read 320 a power dissipation 9 p diss v ih = v dd or v il = gnd 5 w power supply rejection 3 psr ?v dd /?v ss = 5 v 10% r ab = 10 k ?50 db r ab = 80 k ?64 db
ad5111/ad5113/ad5115 data sheet rev. | page 8 of 24 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 3 , 10 bandwidth bw code = half scale, ?3 db r ab = 10 k 2 mhz r ab = 80 k 200 khz total harmonic distortion thd v a = v dd /2 + 1 v rms, v b = v dd /2, f = 1 khz, code = half scale r ab = 10 k ?80 db r ab = 80 k ?85 db v w settling time t s v a = 5 v, v b = 0 v, 0.5 lsb error band r ab = 10 k 2.7 s r ab = 80 k 9.5 s resistor noise density e n_wb code = half scale, t a = 25c, f = 100 khz r ab = 10 k 9 nv/hz r ab = 80 k 20 v flash/ee memory reliability 3 endurance 11 t a = 25c 1 mcycles 100 kcycles data retention 12 50 years 1 typical values represent av erage readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 r-inl is the deviation from an ideal value measured between the maximum resistance and the min imum resistance wiper positions. r-dnl measures the relative step change from ideal between succes sive tap positions. the maximum wi per current is limited to 0.8 v dd /r ab . 3 guaranteed by design and characterization; not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operat ing conditions. 5 resistor terminal a, resistor terminal b, and resistor termin al w have no limitations on current direction with respect to eac h other. 6 c a is measured with v w = v a = 2.5 v, c b is measured with v w = v b = 2.5 v, and c w is measured with v a = v b = 2.5 v. 7 different from operating current; supply curr ent for nvm program lasts approximately 30 ms. 8 different from operating current; supply curr ent for nvm read lasts approximately 20 s. 9 p diss is calculated from (i dd v dd ). 10 all dynamic characteristics use v dd = 5.5 v and v logic = 5 v. 11 endurance is qualified at 100,000 cycles per jedec standard 22, me thod a117 and measured at 150c. 12 retention lifetime equivalent at junction temperature (t j ) is 125c per jedec standard 22, metho d a117. retention lifet ime based on an activa tion energy of 1 ev derates with junction temperature in the flash/ee memory. a
data sheet ad5111/ad5113/ad5115 rev. | page 9 of 24 interface timing spe cifications v dd = 2.3 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 5 . parameter test conditions /comments min typ max unit description f clk v dd 2 .7 v 50 mhz clock frequency v dd < 2.7 v 25 mhz t 1 25 ns cs setup time t 2 v dd 2.7 v 10 ns clk low time v dd < 2.7 v 20 ns t 3 v dd 2.7 v 10 n s clk high time v dd < 2.7 v 20 ns t 4 15 ns u/ d setup time t 5 6 ns u/ d hold time t 6 v dd 2.7 v 20 ns cs r ise to clk hold time v dd < 2.7 v 40 ns t 7 15 ns cs rising edge to next clk ignored t 8 v dd 2.7 v 12 ns u/ d minimum pulse time v dd < 2.7 v 24 ns t 9 12 ns u/ d rise to clk falling edge t 10 1 s minimum cs time t eeprom_program 1 15 50 ms memory program time t power_up 2 50 s power - on eeprom restore time 1 eeprom program time depends on the temperature and eeprom write cycles. higher timing is expected at a lower temperature and higher write cycles. 2 maximum time after v dd is equal to 2.3 v. timing diagram s t 1 r wb clk cs u/d t 2 t 4 t 5 t 6 t 3 t 10 t 7 09654-002 figure 2 . increment/decrement mode timing data eeprom new data t eeprom_program t 1 clk cs u/d t 8 t 6 09654-003 figure 3 . storage mode timing cs clk u/d t 1 t 9 t 6 09654-004 figure 4 . shutdown mode timing a
ad5111/ad5113/ad5115 data sheet rev. | page 10 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 6. parameter rating v dd to gnd C0.3 v to +7.0 v v logic to gnd C0.3 v to +7.0 v v a , v w , v b to gnd gnd ? 0.3 v to v dd + 0.3 v i a , i w , i b pulsed 1 frequency > 10 khz r aw = 5 k and 10 k 6 ma/d 2 r aw = 80 k 1.5 ma/d 2 frequency 10 khz r aw = 5 k and 10 k 6 ma/d 2 r aw = 80 k 1.5 ma/d 2 continuous r aw = 5 k and 10 k 6 ma r aw = 80 k 1.5 ma digital inputs u/ d , clk , and cs ?0.3 v to +7 v or v dd + 0.3 v (whichever is less) operating temperature range 3 ?40c to +125c maximum junction temperature (t j max) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 pulse duty factor. 3 includes programmin g of eeprom memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd-51, and the value is dependent on the test board and test environment. table 7. thermal resistance package type ja jc unit 8-lead lfcsp 90 1 25 c/w 1 jedec 2s2p test board, st ill air (0 m/sec air flow). esd caution a
data sheet ad5111/ad5113/ad5115 rev. | page 11 of 24 pin configuration and function descriptions ad5 11 1/ ad5 1 13/ ad5 1 15 3w 4b 1v dd 2a 6 clk 5 gnd top view (not to scale) 8 cs 7 u/d 09654-006 notes 1. the exposed p ad is internal ly flo a ting. figure 5 . pin configuration table 8 . pin function descriptions pin no. mnemonic description 1 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capaci tors. 2 a terminal a of rdac. gnd v a v dd . 3 w wiper terminal of rdac. gnd v w v dd . 4 b terminal b of rdac. gnd v b v dd . 5 gnd ground pin, logic ground reference. 6 clk clock input. each clock pulse executes the step - up or step- down of the resistance. the direction is determined by the state of the u/ d pin. clk is a negative edge trigger. data can be transferred at rates up to 50 mhz. 7 u/ d up/down selection counter control. 8 cs chip select. active low. epad exposed pad. the exposed pad is internally floating. a
ad5111/ad5113/ad5115 data sheet re v. | page 12 of 24 typical performance characteristics ?0.06 ?0.04 code (decimal) r-in l (lsb) ?0.02 0 0.02 0.04 0.06 0.08 0.10 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09654-007 figure 6. r - inl vs. code ( ad5111 ) ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-in l (lsb) 09654-008 figur e 7. r - inl vs. code ( ad5113 ) ?0.015 ?0.010 ?0.005 0 0. 005 0.010 0.015 0.020 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-inl (lsb) 09654-009 figure 8. r - inl vs. code ( ad5115 ) ?0.07 ?0.06 ?0. 05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) 09654-010 r-dnl (lsb) figure 9. r - dnl vs. code ( ad5111 ) 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 code (decimal) 09654-0 11 r-dn l (lsb) figure 10 . r - dnl vs. code ( ad5113 ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 ?0.018 ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) r-dnl (lsb) 09654-012 figure 11 . r - dnl vs. code ( ad5115 ) a
data sheet ad5111/ad5113/ad5115 rev. | page 13 of 24 code (decimal) inl (lsb) 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09654-013 figure 12 . inl vs. code ( ad5111 ) 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 code (decimal) in l (lsb) 09654-014 figure 13 . inl vs. code ( ad5113 ) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 code (decimal) inl (lsb) ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c 09654-015 figure 14 . inl vs. code ( ad5115 ) ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 7 14 21 28 35 42 49 56 63 70 77 84 91 98 105 1 12 1 19 127 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) dnl (lsb) 09654-016 figure 15 . dnl vs. code ( ad5111 ) ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 48 51 54 57 60 63 5k?, C40c 5k?, +25c 5k?, +125c 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c code (decimal) dn l (lsb) 09654-017 figure 16 . dnl vs. code ( ad5113 ) 09654-018 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 31 code (decimal) dnl (lsb) ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 10k?, C40c 10k?, +25c 10k?, +125c 80k?, C40c 80k?, +25c 80k?, +125c figure 17 . dnl vs. code ( ad5115 ) a
ad5111/ad5113/ad5115 data sheet re v. | page 14 of 24 ?100 0 100 200 300 supply current (na) 400 500 600 700 800 ?40 ?25 ?10 5 20 35 tempera ture (c) 50 65 80 95 1 10 125 09654-019 v dd = 2.3v v dd = 3.3v v dd = 5v figure 18 . supply current vs. temperature 0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 code (decimal) potentiometer mode tempco (ppm/c) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 ad5111 ad5113 ad5115 10k? 80k? 5k? 09654-020 v dd = 5v figure 19 . po tentiometer mode tempco ( (v w /v w )/ t 10 6 ) vs. code 0 ? 60 ? 50 ?4 0 ?3 0 ?2 0 ?1 0 1 00m 10 m 1m 100k 1 0k gain (db) frequency (hz) 0x20 0x10 0x08 0x04 0x02 0x01 0x00 09654-021 figure 20 . 5 k? gain vs. frequency vs. code 09654-022 0 0.2 0.4 0.6 0.8 1.0 1.2 0.05 0.65 1.25 1.85 2.45 3.05 3.65 4.25 4.85 digi tal input vo lt age (v) supply current (ma) v dd = 5v v dd = 3.3v v dd = 2.3v t a = 2 5 c figure 21 . supply current (i dd ) vs. digital input voltage 0 20 40 60 80 100 120 140 160 180 200 10k ? 80k ? 5k ? v dd = 5v rheostat mode tempco (ppm/c) 09654-023 0 20 40 60 code (decimal) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 ad5111 ad5113 ad5115 figure 22 . rheostat mode tempco ( (r wb /r wb )/ t 10 6 ) vs. code ?5 0 ?4 0 ?3 0 ?1 0 0 1m 10m 100k 10k gain (db) frequency (hz) 0x40 0x10 0x04 0x02 ?2 0 ? 70 ?6 0 0x08 0x01 0x20 09654-024 0x00 (0x20) (0x08) ( 0x02) (0x01) (0x04) (0x00) (0x10) [0x10] [0x04] [0x01] [0x00] [0x02] [ 0x08] ad5111 (ad5113) [ad5115] figure 23 . 10 k? gain vs. frequency vs. code a
data sheet ad5111/ad5113/ad5115 rev. | page 15 of 24 ?6 0 ?5 0 ?4 0 ?3 0 ?1 0 0 1 0k 1m 100 k gain (db) freque nc y (hz) ?2 0 ? 80 ?7 0 09654-025 0x40 0x10 0x04 0x02 0x08 0x01 0x20 0x00 (0x20) (0x08) (0x02) (0x01) (0x04) (0x00) (0x10) [0x10] [0x04] [0x01] [0x00] [0x02] [0x08] ad5111 (ad5113) [ad5115] figure 24 . 80 k? gain vs. frequency vs. code 09654-049 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 100k 1m 10m phase (degrees) frequenc y (hz) ful l scale half scale quarter scale r ab = 10k? figure 25 . normalized phase flatness vs. frequency 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 thd + n (db) frequenc y (hz) 20 200 2k 20k 200k 10k 5k 80k 09654-027 v dd = 5v v a = 2.5v + 1v rms v b = 2.5v code = half scale noise filter = 22khz figure 26 . total harmonic distortion + noise (thd + n) vs. frequency 0 10 20 30 40 50 60 70 bandwidth (mhz) 80 code (decimal) 09654-028 5k + 250pf 10k + 75pf 10k + 150pf 10k + 250pf 80k + 0pf 80k + 75pf 80k + 150pf 80k + 250pf 5k + 0pf 5k + 75pf 5k + 150pf 10k + 0pf 0 10 20 30 40 50 60 0 5 10 15 20 25 30 0 5 10 15 ad5111 ad5113 ad5115 figure 27 . maximum bandwidth vs. code vs. net capacitance 0 30 60 90 incremen tal wiper on resis t ance ( ?) 120 150 0 1 2 3 v dd (v) 4 5 6 5.5v 5v 3.3v 2.7v 2.3v 09654-029 t a = 25c figure 28 . incremental wiper on resistance vs. v dd thd + n (db) amplitude (v rms) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 09654-030 10k 5k 80k v dd = 5v v a = 2.5v + v in v b = 2.5v f in = 1khz code = half scale noise fi l ter = 22khz figure 29 . total harmonic distortion + noise (thd + n) vs. amplitude a
ad5111/ad5113/ad5115 data sheet re v. | page 16 of 24 ?0.10 ?0.05 0 0.05 0.10 0.15 rel a tive vo lt a ge (v) 0.20 0.25 0.30 0.35 ?1 1 3 5 time (s) 7 9 09654-048 5k ? 10k ? 80k ? v dd = 5v v a = v dd v b = gnd figure 30 . maximum transition glitch 0 0.2 0.4 0.6 0.8 1.0 1.2 0 0.0005 0.0010 0.0015 0.0020 0.0025 ?400 ?500 ?600 ?300 ?200 ?100 0 100 200 300 400 500 600 cumul a tive probabilit y probabilit y densit y resist or drift (ppm) 09654-050 figure 31 . resistor life t ime drift ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 f requenc y (hz) psrr (db) 09654-033 10 100 1k 10k 100k 1m 5k ? 10k ? 80k ? v dd = 5v 10% ac v a = 4v v b = gnd code = half scale t a = 25c figure 32 . power supply rejection ratio (psrr) vs. frequency ?120 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 volt age ( v) time ( s) 09654-034 v dd = 5v v a = v dd v b = gnd code = half scale figure 33 . digital feedthrough ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1k 10k 1m 10m gain (db) frequenc y (hz) 5k ? 10k ? 80k ? 09654-035 figure 34 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 theoretica l i max (ma) 10k ? 80k ? 5k ? 0 20 40 60 code (decimal) 80 100 120 0 10 20 30 40 50 60 0 5 10 15 20 25 30 ad5111 ad5113 ad5115 09654-036 figure 35 . theoretical maximum current vs. code a
data sheet ad5111/ad5113/ad5115 rev. | page 17 of 24 test circuits figure 36 to figure 41 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 09654-037 figure 36. resistor position nonlinearity error (rheostat operation: r-inl, r-dnl) a w b dut v ms v+ v += v dd 1lsb = v+/2 n 09654-038 figure 37. potentiometer divider nonlinearity error (inl, dnl) 09654-039 + ? dut 0.1v = 0.1v i wb i wb w b nc = no connect r w a nc gnd to v dd figure 38. wiper resistance a w b v ms ~ v a v dd v+ v+=v dd 10% ? v ms % ? v dd % pss (%/%) = psrr (db) = 20 log ? v ms ? v dd 09654-040 figure 39. power supply sensitivity (pss, psrr) offset gnd a b dut w +15 v v in v out ad8652 ?15v 2.5v 09654-041 figure 40. gain and phase vs. frequency 09654-042 dut i cm w b v dd gnd a v dd gnd gnd v dd gnd v dd figure 41. common-mode leakage current a
ad5111/ad5113/ad5115 data sheet re v. | page 18 of 24 theory of operation the ad5111 / ad5113 / ad5115 digital programmable resistors are designed to operate as true variable resistors for analog signals within the terminal voltage range of gnd < v term < v dd . the resistor wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register that allows unlimited changes of resistance settings. the rdac register can be programmed with any position setting using the up/down interface. once a desirable wiper position is found, this value can be stored in the eeprom. thereafter, the wiper position is always restored to that position for subsequent power - up. the storing of eeprom data takes approximately 30 ms; during this time, the device is locked and does not accept any new operation , thus preventing any changes from taking place. the ad5111 / ad5113 / ad5115 are designed to allow high speed digital control with clock rates up to 50 mhz. rdac register and ee prom the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is 0x40 ( ad5111 ), the wiper is connected to midscale of the variable resistor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. once a desirable wiper position is found, this value can be saved into the eeprom. thereafter, the wiper position is always set at that position for any future on - off - on power supply sequence or recall operation. basic operation when cs is pulled low , changing the res istance settings is achieved by clocking the clk pin. it is negative edge triggered , and the direction of stepping into the rdac register is determined by the state of the u/ d input. when a specific state of the u/ d remains, the device continues to change in the same direction under consecutive clocks until it comes to the end of the resistance setting . when the wiper reaches the maximum or minimum setting, additional clk pulses do not change the wiper setting. figure 2 shows a typical increment/decrement operation. the u/ d pin value can be changed only when the clk pin is low. low w iper r esistance feature the ad5111 / ad5113 / ad5115 include a new feature to reduce the resistance between terminals. these extra steps are called bottom scale and top s cale. at bottom scale, the typical wiper resistance decreases from 7 0 ? to 4 5 ?. at to p scale, the resistance between terminal a and terminal w is decreased by 1 lsb and the total resistance is reduced to 70 ?. the new extra steps are loaded automatically in the rdac register after zero - scale or full - scale position has bee n reached. the extra steps are not equal to 1 lsb and are not included in the inl, dnl, r - inl, and r - dnl specifications. shutdown mode this feature places terminal a in open circuit, disconnected from the internal resistor, and connects terminal w and term inal b. a finite wiper resistance of 45 is present between these two terminals. the command is sent by a low - to - high transition on the u/ d pin, when clk is high and cs is enabled . the command is execu ted on the clk negative edge , as shown in figure 4 . the ad5111 / ad5113 / ad5115 ret urn the wiper to prior shutdown position if any other operation is performed. eeprom write operati on the ad5111 / ad5113 / ad5115 contain an eeprom that allows the wiper position storage. once a desirable wiper position is found, this value can be saved into the eeprom. thereafter, the wiper position is always set at that position for any future power - up sequence or a memory recall operation. d uring the storage cycle, the device is locked and does not ac cept any new operation , thus preventing any changes from taking place. the write cycle is started by applying a pulse in the u/ d pin w hen cs is en abled and clk remains high, as shown in figure 3 . the write cycle takes approximately 20 ms. a
data sheet ad5111/ad5113/ad5115 rev. | page 19 of 24 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5111/ ad5113/ ad5115 employ a two-stage segmentation approach as shown in figure 42. the ad5111/ ad5113 / ad5115 wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v dd . r l r l r l r l r s w r s a b bs 5-bit/6-bit/7-bit address decoder ts 09654-043 figure 42. ad5111 / ad5113 / ad5115 simplified rdac circuit low wiper resistance feature in addition, the ad5111/ ad5113 / ad5115 include a new feature to reduce the resistance between terminals. these extra steps are called bottom scale and top scale. at bottom scale, the typical wiper resistance decreases from 70 to 45 . at top scale, the resistance between terminal a and terminal w is decreased by 1 lsb and the total resistance is reduced to 70 . the extra steps are not equal to 1 lsb and are not included in the inl, dnl, r-inl, and r-dnl specifications. programming the variable resistor rheostat operation ? 8% resistor tolerance the ad5111 / ad5113/ ad5115 operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating or tied to the w terminal as shown in figure 43. a w b a w b a w b 09654-044 figure 43. rheostat mode configuration the nominal resistance between terminal a and terminal b, r ab , is available in 5 k, 10 k, and 80 k and has 128/64/32 tap points accessed by the wiper terminal. the 5-/6-/7-bit data in the rdac latch is decoded to select one of the 128/64/32 possible wiper settings. the gene ral equations for determining the digitally programmed output resistance between the w terminal and b terminal are ad5111: bs wb rr ? bottom scale (1) w ab wb rr d dr ??? 128 )( from 0 to 128 (2) ad5113: bs wb rr ? bottom scale (3) w ab wb rr d dr ??? 64 )( from 0 to 64 (4) ad5115: bs wb rr ? bottom scale (5) w ab wb rr d dr ??? 32 )( from 0 to 32 (6) where: d is the decimal equivalent of the binary code in the 5-/6-/7-bit rdac register; 128, 64, and 32 refer to the top scale step. r ab is the end-to-end resistance. r w is the wiper resistance . r bs is the wiper resistance at bottom scale. a
ad5111/ad5113/ad5115 data sheet re v. | page 20 of 24 similar to the mechanical potentiometer, the resistance of the rdac between the w terminal and the a terminal also produces a digitally controlled complementary resistance, r wa . r wa s tarts at the maximum resistance value and decreases as the data loaded into the latch increases. the general equations for this operation are ad5111 : w ab aw rrr += bottom scale (7) w ab aw rr d dr + ? = 128 128 )( from 0 to 127 (8) ts aw rr = top scale (9) ad5113 : w ab aw rrr += bottom scale (10) w ab aw rr d dr + ? = 64 64 )( from 0 to 63 (11) ts aw rr = top scale (12) ad5115 : w ab aw rrr += bottom scale (13) w ab aw rr d dr + ? = 32 32 )( from 0 to 31 (14) ts aw rr = top scale (15) where: d is the decimal equivalent of the binary code in the 5- /6 - /7 - bit rdac register ; 128, 64 , and 32 refer to top scale step . r ab is the end - to - end resistance. r w is the wiper resistance . r ts is the wiper resistance at top scale. regardless of which setting the part is operating in, take care to limit the current between a to b, w to a, and w to b, to the maximum continuous c urrent of 6 ma (5 k? and 10 k?) or 1.5 ma (80 k?), or pulse current specified in table 6 . otherwise, degradation or possible destruction of the internal switch contact can occur. programming the pote ntiometer divider voltage ou tput operation the digital potentiometer easily generates a voltage divider at w- to - b and w - to - a that is proportional to the input voltage at a- to - b, as shown in figure 44 . unlike the polarity of v dd to gnd, which must be positive , current across a - to - b, w - to -a, and w - to - b can be in either direction. a v i w b v o 09654-045 figure 44 . potentiometer mode configuration if ignoring the effect of the wiper resistance for simplicity, connecting terminal a to 5 v and t erminal b to gro und produces an output voltage at w to b ranging from 0 v to 5 v. the general equation defining the output voltage at v w wi th respect to ground for any valid input voltage applied to terminal a and terminal b , is b ab aw a ab wb w v r dr v r dr dv += )( )( )( (16) where: r wb ( d ) can be obtained from equation 1 to equation 6. r aw ( d ) can be obtained from equation 7 to equation 14. operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheostat mode, the output vol tage is dependent mainly on the ratio of the internal resistors , r wa and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. terminal voltage operating range the ad5111 / ad5113 / ad5115 are designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltages. positive signals present on the a, b, or w terminals that exceed v dd a re clamped by the forward - biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than gnd. a
data sheet ad5111/ad5113/ad5115 rev. | page 21 of 24 power - up sequence because of the esd protection diodes that l imit the voltage compliance at the a, b, and w terminals (see figure 45), it is important to power on v dd before applying any voltage to the a, b, and w terminals. otherwise, the diodes are forward - biased such that v dd is powered on unintentionally and can affect other parts of the circuit. similarly, v dd should be powered down last. the ideal power - on sequence is in the following order: gnd, v dd , and v a /v b /v w . the order of powering v a , v b , v w a nd the digital inp uts is not importan t as long as they are powered on after v dd . gnd v dd a w b 09654-046 figure 45 . maximum terminal voltages set by v dd and gnd layout and power supply biasing it is always a good practice to use compact, minimum lead length layout design. the leads to th e input should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. apply low equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 46 illustrates the basic supply bypassing configuration for the ad5111 / ad5113 / ad5115 . v dd v dd + gnd c1 0.1f c2 10f agnd ad5111/ ad5113/ ad5115 09654-047 figure 46 . power supply bypassing a
ad5111/ad5113/ad5115 data sheet rev. a | page 22 of 24 outline dimensions 1.70 1.60 1.50 0.425 0.350 0.275 top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area 2.00 bsc sq seating plane 0.60 0.55 0.50 1.10 1.00 0.90 0.20 ref 0.175 ref 0.05 max 0.02 nom 0.50 bsc exposed pad p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 07-11-2011-b figure 47. 8-lead frame chip scale package [lfcsp_ud] 2 mm 2 mm body, very thin, dual lead (cp-8-10) dimensions shown in millimeters ordering guide model 1, 2 r ab (k) resolution temperature range package description package option branding code AD5111BCPZ10-RL7 10 128 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7s ad5111bcpz10-500r7 10 128 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7s ad5111bcpz80-rl7 80 128 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7t ad5111bcpz80-500r7 80 128 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7t ad5113bcpz5-rl7 5 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 85 ad5113bcpz5-500r7 5 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 85 ad5113bcpz10-rl7 10 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 84 ad5113bcpz10-500r7 10 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 84 ad5113bcpz80-rl7 80 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 86 ad5113bcpz80-500r7 80 64 ?40c to +125c 8-lead lfcsp_ud cp-8-10 86 ad5115bcpz10-rl7 10 32 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7y ad5115bcpz10-500r7 10 32 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7y ad5115bcpz80-rl7 80 32 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7z ad5115bcpz80-500r7 80 32 ?40c to +125c 8-lead lfcsp_ud cp-8-10 7z eval-ad5111sdz evaluation board 1 z = rohs compliant part. 2 the eval-ad5111sdz has an r ab of 10 k.
data sheet ad5111/ad5113/ad5115 rev. a | page 23 of 24 notes
ad5111/ad5113/ad5115 data sheet rev. a | page 24 of 24 notes ?2011C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09654-0-4/12(a)

▲Up To Search▲

Price & Availability of AD5111BCPZ10-RL7

	To Download AD5111BCPZ10-RL7 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .