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6 - 1 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper functional diagram integrated frequency sweeper - linear, coherent sweeps - 2-way, 1-way, & user defned sweep modes - automatic or triggered - programmable seed -spi & external triggering 5-gpios, can be used for external dsm cycle slip prevention support with pfd chip (hmc984lp4e) differential vco input & divider output programmable output current control: -5 ma to 17.5 ma open collector output driver 32 pin, 5 x 5 mm, lp5 package typical applications the HMC983LP5E is suitable for: ? test equipment ? portable instruments ? high performance fractional-n frequency synthe - sizers with ultra low spurious ? stand-alone divider and/or delta-sigma modulator general description HMC983LP5E is a fractional frequency divider targeted for fractional-n frequency synthesis, and stand-alone low noise frequency divider applications that require exceptional spurious performance. although the HMC983LP5E can work with any vco and/or compatible phase detector, best performance and features will be achieved when paired with the companion part, the hmc984lp4e. fabricated in sige bicmos process, the HMC983LP5E features a 48-bit delta sigma fractional modulator (dsm) with programmable phase accumulator size, enabling precise control of frequency step size and resolution. integrated dsm can generate frequencies with nearly 0 hz frequency error. the dsm also includes a built-in programmable frequency sweep capability, with various automatic and user defned sweep modes and triggering options, including hardware trigger pin, or spi trigger with optional delayed trigger. HMC983LP5E is a versatile part capable of various confgurations. it has 5 general purpose i/os (gpios). dsm outputs are made available from the gpio port, enabling the HMC983LP5E to import and/or export dsm sequences for various confguration options. HMC983LP5E divider outputs are differential, open collector with programmable current to accommodate different off-chip loads. features wideband: dc - 7 ghz input -20-bit frequency divider low noise: -160 dbc/hz low spurious: largest spurious - 95 dbc 48-bit 100 mhz delta-sigma modulator (dsm) - confgurable dsm size - programmable seed features (continued)
6 - 2 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 1. electrical specifcations ta = +25 c, avdd, vccps, vcchf, vddm, dvdd = 3 v 10%; vppbuf = 5 v 10%; gnd = 0 v parameter conditions min. typ. max. units rf input characteristics rf input frequency range dc 7 ghz rf input sensitivity -15 -10 0 dbm rf input capacitance external match recommended 3 pf divider range (20-bit) integer mode 32 1,048,575 fractional mode 36 1,048,571 divider output characteristics output buffer current programmable in 2.5 ma steps 5 12.5 17.5 ma output voltage swing single- ended, vpullup = 5 v 0.75 1 2 v output frequency range integer mode fractional mode mode a and mode b dc dc 150 125 mhz phase noise 50 mhz pfd, 6 ghz input, integer mode -160 dbc/hz fractional spurious largest observed at 10 khz fractional offset from integer boundary -95 -85 dbc logic inputs input high voltage (vih) dvdd-0.4 v input low voltage (vil) 0.4 v logic outputs output high voltage (voh) dvdd-0.4 v output low voltage (vol) 0.4 v dc load 1.5 ma serial port clock frequency main spi and auxspi 30 mhz power supplies avdd, vccps, vcchf analog supplies. avdd should be equal to dvdd. 2.7 3 3.3 v vppbuf output buffer supply. 4.5 5 5.5 v vddm, dvdd digital supplies 2.7 3 3.3 v current consumption idd - total current consumption integer mode / fractional mode (50 mhz divider output) 104 / 122 ma i - avdd (avdd current, 3 v) integer mode / fractional mode 5 / 5 ma i - vccps (vccps current, 3 v) integer mode / fractional mode 79 / 79 ma i - vcchf (vcchf current, 3 v) integer mode / fractional mode 8 / 8 ma i - vddm (vddm current, 3 v) integer mode / fractional mode 11 / 11 ma i - dvdd (total dvdd current, 3 v) integer mode / fractional mode 1 / 19 ma i - vppbuf (total vppbuf current, 5 v) 5 ua
6 - 3 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 1. rf input sensitivity [1] figure 3. output phase noise with 6 ghz input in integer mode [3] figure 2. output phase noise, 6 ghz input frequency [2] figure 5. time domain 18 mhz output, 6.5 ghz input [4] figure 4. time domain 10 mhz output, 6.5 ghz input [4] figure 6. time domain 35 mhz output, 6.5 ghz input [4] -200 -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 offset frequency (hz) phase noise (dbc/hz) rf input signal phase noise 100 mhz output frequency integer mode 100 mhz output frequency frac mode b 100 mhz output frequency frac mode a -80 -60 -40 -20 0 20 40 0 2000 4000 6000 8000 10000 +27 c -40 c +85 c rf input frequency (mhz) rf input power (dbm) recommended operating range maximum input power limit minimum input power limit -200 -180 -160 -140 -120 -100 -80 -60 10 2 10 3 10 4 10 5 10 6 10 7 10 8 offset frequency (hz) phase noise (dbc/hz) rf input signal phase noise calculated phase noise 50 mhz output frequency 100 mhz output frequency 142 mhz output frequency 4 4.5 5 5.5 0 50 100 150 200 250 300 350 time (ns) outout voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 50 100 150 200 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 20 40 60 80 100 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output [1] the maximum and minimum levels indicate operational limits of the HMC983LP5E . performance may degrade with input power greater than 0 dbm for frequencies higher than 6500 mhz. [2] due to delta sigma modulation in fractional mode, the output phase noise peaks at frequency offset of fout/2 from the output. agilent mxg n5182a used as a signal source. [3] rohde & schwarz smbv100a used as a signal source. [4] measured with 50 impedance per line, integer mode, 15 ma output buffer current ( reg 0fh [4:2]) selected
6 - 4 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper figure 7. time domain 124 mhz output, 6.5 ghz input [5] figure 8. time domain 66 mhz output, 6.5 ghz input [5] figure 9. time domain 61 mhz output, 6.5 ghz input [5] figure 10. time domain 66 mhz output, 6.5 ghz input [5] figure 11. 10 mhz output swing vs buffer current [6] figure 12. 50 mhz output swing vs buffer current [6] 4 4.5 5 5.5 0 5 10 15 20 25 30 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) 4 4.5 5 5.5 0 10 20 30 40 50 time (ns) output voltage (v) divckpfdp pin output divckpfdn pin output [5] measured with 50 impedance per line, integer mode, 15 ma output buffer current ( reg 0fh [4:2]) selected [6] measured with 50 impedance per line. buffer current is controled via reg 0fh [4:2].
6 - 5 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 13. 100 mhz output swing vs buffer current [7] figure 14. input return loss figure 15. two way frequency sweep, 50 mhz pfd [8] figure 16. one way frequency sweep, 10 mhz pfd and 10 hz external trigger [8] figure 17. pll cycle slip prevention, 100 mhz pfd [8] figure 18. pll cycle slip prevention, 50 mhz pfd [8] 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 12 13 14 15 16 17 18 -40 c +27 c +85 c output buffer current (ma) single-ended output swing (vpp) -20 -15 -10 -5 0 0 2000 4000 6000 8000 frequency (mhz) return loss (db) 6400 6500 6600 6700 6800 6900 7000 0 5 10 15 20 frequency (mhz) time (ms) 6400 6500 6600 6700 6800 6900 7000 0 200 400 600 800 1000 frequency (mhz) time (ms) 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (mhz) cycle slip disabled csp enabled reg0eh[18:15] = 8h csp enabled reg0eh[18:15] = 1h 6700 6750 6800 6850 6900 6950 7000 7050 0 50 100 150 200 250 300 time (us) pll output frequency (ghz) cycle slip disabled csp enabled reg0eh[18:15] = fh csp enabled reg0eh[18:15] = 5h [7] measured with 50 impedance per line. buffer current is controled via reg 0fh [4:2]. [8] measured with HMC983LP5E/hmc984lp4e chip set as fractional-n synthesizer. crystal input frequency = 100 mhz, cp current = 2.5 ma, cp offset current = 245 ua, loop flter bandwidth = 87 khz, dsm mode b selected. cycle slip prevention (csp) is disabled in hmc984lp4e by setting reg 01h [4] = 0. setting reg 01h [4] = 1 enables csp in the two chip pll.
6 - 6 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 2. pin descriptions pin number function description interface schematic 1, 2, 3 senb sdi sck main spi data input 4, 5 d1 d0 gpio bit 1 gpio bit 0 6, 7, 8 aux_sclk aux_senb aux_sdo auxiliary spi clock output auxiliary spi enable auxiliary spi data output 9 bias external decoupling for analog bias circuits 10 avdd 3 volt power supply pin for internal reference cur - rent sources 11 vccps 3 volt power supply pin for prescaler 12, 13 vcoin, vciop negative pin for prescaler differential input, ac-coupled positive pin for prescaler differential input, ac-coupled 14 vcchf 3 volt power supply pin for prescaler input buffer 15 vppbuf 5 volt power supply pin for divider output buffer 16 n/c no connect pin
6 - 7 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 2. pin descriptions pin number function description interface schematic 17, 18 divckpfdn, divckpfdp negative pin for open collector divider output driver positive pin for open collector divider output driver 19 vddm 3v supply pin for digital section of the frequency divider 20, 21, 22 d2, d3, d4 gpio bit 2, gpio bit 3, gpio bit 4 23 ref_eno gate control (output) to request tcxo clock export from hmc984lp4e 24, 25, 26 chip1, chip2, chip3 chip address pin 1, chip address pin 2, chip address pin 3 27, 30 dvdd 3v power supply for digital 28, dnsat, vco saturation input fag from hmc984lp4e chip (continued)
6 - 8 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 2. pin descriptions pin number function description interface schematic 29 upsat reference saturation input fag from hmc984lp4e chip 31 cen chip enable 32 sdo main spi data output (continued)
6 - 9 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com outline drawing part number package body material lead finish msl rating [2] package marking [1] HMC983LP5E rohs-compliant low stress injection molded plastic 100% matte sn msl1 h983 xxxx [1] 4-digit lot number xxxx [2] max peak refow temperature of 260 c package information table 3. absolute maximum ratings nominal 3v supplies to gnd -0.3 to 3.6 v nominal 3v digital supply to 3v analog supply -0.3 to +0.3 v nominal 5v supply to gnd (vppbuf) -0.3 to 5.5 v divckp, divckn common mode dc vccps + 0.5 v min vcoip, vcoin single ended ac 50 source + 7 dbm vcoip, vcoin differential ac 50 source + 13 dbm digital input voltage range -0.25 to dvdd + 0.5 v minimum digital load 1 k operating temperature range -40 c to +85 c maximum junction temperature 125 c storage temperature -65 to +125 c electrostatic sensitive device observe handling precautions thermal resistance (rth) (junction to ground paddle) 40 c/w refow soldering peak temperature time at peak temperature 260 c 40 s esd sensitivity (hbm) class 1b stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. notes: [1] package body material: low stress injection molded plastic silica and silicon impregnated. [2] lead and ground paddle material: copper alloy. [3] lead and ground paddle plating: 100% matte tin. [4] dimensions are in inches [millimeters]. [5] lead spacing tolerance is non-cumulative. [6] pad burr length shall be 0.15 mm max. pad burr height shall be 0.25 m max. [7] package warp shall not exceed 0.05 mm [8] all ground leads and ground paddle must be soldered to pcb rf ground. [9] refer to hittite application note for suggested pcb land pattern.
6 - 10 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper evaluation pcb item contents part number evaluation kit HMC983LP5E and hmc984lp4e pll chipset evaluation pcb usb interface board 6 usb a male to usb b female cable cd rom (contains user manual, evaluation pcb schematic, evaluation software) ekit01-HMC983LP5E table 4. evaluation order information the circuit board used in the application should use rf circuit design techniques. signal lines should have 50 ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown unless mentioned otherwise. a sufficient number of via holes should be used to connect the top and bottom ground planes. the evaluation circuit board shown is available from hittite upon request.
6 - 11 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com evaluation pcb block diagram
6 - 12 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper theory of operation the HMC983LP5E can be used in following confgurations: 1. fractional-n or integer mode rf frequency divider or prescaler 2. fractional-n frequency synthesizer with an appropriate phase detector and vco primary target application of the HMC983LP5E is to be used in conjunction with the hmc984lp4e as shown in figure 19 . together these two components form a high performance, low noise, ultra low spurious emissions fractional-n frequency synthesizer. figure 19. typical application of hmc984lp4e with HMC983LP5E to form a frequency synthesizer the HMC983LP5E consists of the following functional blocks 1. rf input buffer 2. 7 ghz frequency prescaler and multi modulus divider 3. 48-bit confgurable fractional delta sigma modulator 4. bias circuit 5. differential output driver 6. frequency sweeper 7. main serial port interface 8. auxiliary serial port interface (output only) 9. general purpose digital io 10. power on reset circuit rf input buffer the rf input stage provides the path from the external vco to the fractional rf divider. the rf input path is rated to operate nominally from dc to 7 ghz. the HMC983LP5E rf input stage is a differential common emitter stage with dc coupling, and is protected by esd diodes as shown in figure 20 . rf input is not matched to 50 ? due to wide input frequency range. at low frequencies, a simple shunt 50 ? resistor can be used external to the package to provide a 50 ? match. for better performance it is recommended to match the rf inputs externally and provide differential drive from the vco. in most applications the input is used single-ended into either the vcoip or vcoin pin with the other input connected to ground through a dc blocking capacitor. the preferred input level for best spectral performance is -10 dbm.
6 - 13 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 20. rf input stage rf path fractional-n divider the rf input buffer is followed by a high frequency prescaler and a multi modulus divider. the divider has been designed for the best output phase noise and spurious performance in both fractional and integer mode. the fractional-n divider can divide input frequencies from 32 to 2 20 -1 (1048575) in integer mode and from 36 to 2 20 -5 (1048571) in fractional-n mode. the divider output pulse width depends on the rf input period and is adjustable via spi setting (refer to duty cycle setting in register reg 0fh [14:12]). the output pulse width recommended setting is 40% to 60% where possible. at low output frequencies it may not be possible to set 50% duty cycle. in such cases the maximum pulse width setting is recommended. figure 21. divider path divider output buffer the divider output is differential and the output buffer stage is an open collector amplifer with off-chip pull-up resistors. due to sharp rise and fall times at the divider output, the external path should be designed differentially using rf techniques. when HMC983LP5E and hmc984lp4e are operating together as a frequency synthesizer, 50 ? pull-up resistors are provided in hmc984lp4e. vppbuf pin should be connected to 5 v power supply. this pin does not sink dc current and is only used to bias the internal esd diodes and to provide an appropriate voltage level for the phase detector chip (hmc984lp4e). the two possible interface confgurations are shown in figure 22 and figure 23 below.
6 - 14 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper figure 22. generic divider output interface figure 23. divider interface with hmc984lp4e chip address pins the HMC983LP5E has three spi chip address pins (spi address [2:0] = chip3, chip2, chip1), which enable multiple HMC983LP5E devices to use the same spi bus. spi chip address bits are read at power up, or every time HMC983LP5E is reset. by default, all three pins are internally pulled to dvdd, thus there is no need to connect the pins to dvdd to set them to logic high. to assign a 0 to any chip address bit, the corresponding pin should be connected to ground. when used on the same spi bus together with the companion part (the hmc984lp4e), to form a frequency synthesizer, some spi commands, such as changing the reference division ratio to the hmc984lp4e may also require an action by the HMC983LP5E. in order to avoid the necessity to write two separate spi transfers to implement one command (one to confgure hmc984lp4e, and the other one to confgure the HMC983LP5E), it is possible to write the spi address of the companion part (hmc984lp4e) into reg 09h of the HMC983LP5E. in such cases, the HMC983LP5E is able to recognize an spi command to the companion part (the hmc984lp4e) that requires its own action, and act accordingly to update its own corresponding registers. writing HMC983LP5Es own chip address to the companion chip address register reg 09h will disable this feature.
6 - 15 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com saturation detection input pins dnsat, upsat when the HMC983LP5E is operating with its companion chip the hmc984lp4e as a frequency synthesizer, it automatically detects large phase errors and tries to tune the vco faster by using its algorithm for cycle-slip prevention (csp). the upsat and dnsat provide indication which frequency is higher (vco or reference) from the counterpart phase detector/charge pump (the hmc984lp4e). the csp algorithm manipulates the rf divider and the phase detector at appropriate intervals to lock faster. see hmc984lp4e data sheet for more details. these pins should be connected to ground if not used. ref_eno pin ref_eno pin is a digital output pin that is used by the HMC983LP5E to request crystal oscillator clock from the phase detector / charge pump chip (the hmc984lp4e). the crystal oscillator clock is multiplexed on the HMC983LP5Es dnsat pin. the internal frequency divider, programmed in reg 02h, is used to generate the actual reference frequency present at the phase detector. the imported clock is only used to communicate through the auxspi. at all other times, the clock and the local reference dividers are turned off. in stand-alone applications, if the HMC983LP5E is required to communicate through the auxiliary spi, the HMC983LP5E will expect to receive the auxiliary spi clock on dnsat pin. setting reg 04h [15] = 1 keeps the auxiliary spi clock enabled on the dnsat pin. multi purpose digital io pins d0, d1, d2, d3, d4 (gpio pins) the fve general purpose digital input/outputs can be used for various modes of operation as well as test/debugging purposes. gpio pins are enabled by writing reg 01h [4] = 1 (gpio master enable). setting reg 01h [4] = 0 places the gpio pins in tri-state high impedance mode. gpio pins are confgured in reg 08h [13:0]. all of the pins can confgured to be either inputs or outputs by writing to reg 08h [13:9]. in frequency sweep mode, pin d4 can be used as an external trigger pin, by writing reg 08h [13] = 0. writing to reg 08h [3:0] selects HMC983LP5Es internal signals to be multiplexed out on the gpio pins, as shown in table 5 . signals include: 1. the output of the delta-sigma modulator reg 08h [3:0] = 0010b. 2. gpio test signals reg 08h [3:0] = 0000b, which outputs data written to reg 08h [8:4] to test the gpio pins. 3. sweep status fags, when the HMC983LP5E is confgured to be in sweep mode reg 08h [3:0] = 1000b. table 5. gpio pin assignment and output signals reg 08h [3:0] HMC983LP5E gpio pins d4 d3 d2 d1 d0 0000 gpo_test_out[4] gpo_test_out[3] gpo_test_out[2] gpo_test_out[1] gpo_test_out[0] 0001 reserved reserved reserved reserved reserved 0010 dsm_out[4] dsm_out[3] dsm_out[2] dsm_out[1] dsm_out[0] 0011 reserved reserved reserved reserved reserved 0100 reserved reserved reserved reserved reserved 0101 reserved reserved reserved reserved reserved 0110 reserved reserved reserved 0 0 0111 reserved reserved reserved reserved reserved 1000 ramp_ready_fag ramp_start_fag ramp_stop_fag ramp_busy_falg reserved 1001-1111 0 0 0 0 0
6 - 16 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper fractional mode of operation in addition to providing simple integer division ratios, the HMC983LP5E has a sophisticated, confgurable 48-bit delta sigma modulator (dsm), that allows fractional division of the input frequency in ultra fne steps. the dsms size can be confgured to 16/24/32/48 bits ( reg 16h [5:0]). HMC983LP5Es auto-seed mode allows coherent frequency sweeps. the HMC983LP5E with its counterpart (the hmc984lp4e), together with an external vco comprise a fully functional fractional-n synthesizer. in that case, the output frequency of the external vco is given by: int int 2 xtal xtal vco frac frac l f f f n n f f r r = ? + ? = + ? (eq 1) when the HMC983LP5E is being used as frequency divider, the output frequency is given by; int 2 vco out frac l f f n n = + (eq 2) where f vco is the vco frequency in hz; f xtal is the crystal oscillator frequency in hz; n int is the integer part of frequency division ratio (set in reg 05h [19:0]); n frac is the fractional part of frequency division ratio (n frac [47:18] = reg 06h [29:0], n frac [17:0] = reg 07h [17:0]) r is the reference frequency division ratio; l is the size of the dsm accumulators (set in reg 16h [5:0]) example 1: calculate the vco frequency with the following parameters; f xtal = 50 mhz; f pfd = 25 mhz n int = 25; n frac = 1; l = 24 where f pfd is the frequency at the phase detector, thus r = 2. according to (eq 1) , the vco frequency with the above parameters will be; 24 50 50 25 1 2500 1.49 2 2 2 vco mhz mhz f mhz hz = ? + ? = + ? if accumulator width (l) is changed to 48-bit, then the frequency resolution will improve and the fractional resolution of the vco frequency will be 88.8178 nano-hz. example 2: set the vco frequency to 4600.025 mhz using 100 mhz crystal, r = 2 and l = 16. compare if l = 32. for this example the f pfd = 100 mhz/2 = 50 mhz, the overall division ratio is 4600.025 mhz/50 mhz = 92.0005 the nearest integer would be 92, thus n int = reg 05h [19:0] = 92d = 5ch. for l = 16, n frac = 32.768 or 33d rounded up. thus n frac = 33d or 21h ( reg 06h [29:0] = 0, reg 07h [17:0] = 21h). for l = 32, n frac = 2147483.648 or 2147484d rounded up. thus n frac = 20c49ch ( reg 06h [29:0] = 8h, reg 07h [17:0] = 001100010010011100d). since n frac must be an integer, the actual frequencies in the two cases will have an error of + 177.02 hz for l = 16 and only +0.004098 hz for l = 32.
6 - 17 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com phase noise in integer and fractional modes in a normal integer frequency divider the in-band phase noise is scaled from the input phase noise by 20log10(n), where n is the divider value. in HMC983LP5E fractional mode, the frequency divider is modulated by the delta sigma modulator to generate output frequencies that are fractional multiple of the input frequency. delta sigma modulator shapes the quantization noise such that quantization noise density has a high pass shape which peaks at fs/2, where fs is the sampling frequency (the divider output frequency in case of HMC983LP5E). in fractional mode this quantization noise peak appears at an offset frequency of fout/2. in the pll, this peak is attenuated by the loop flter. however, when the HMC983LP5E is used stand-alone in fractional mode its output will exhibit the quantization noise as shown in figure 2 and figure 3 . as a result, it is not possible to achieve the same noise foor in fractional mode as in integer mode without further fltering. cw frequency sweeper the HMC983LP5E features a built-in frequency sweeper function that supports automatic or externally triggered sweeps. external triggering can be executed via an external trigger pin d4 or the spi interface. HMC983LP5E sweep function can be confgured to operate in the following modes: ? 2-way sweep mode ? repeating alternating positive and negative frequency sweep ramps ? frequency increments swept with automatic sequencer ? automatic or triggered ? symmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp) ? 1-way sweep mode ? repeating one directional frequency sweeps followed by a reset to the starting frequency ? frequency increments swept with automatic sequencer ? triggered user defned sweep mode ? manually programmed user defned sweep patterns ? triggered ? symmetric or asymmetric (the positive ramp can have a different slope from that of the negative ramp) in all sweep modes, the starting sweep direction can be set to positive (increasing) or negative (decreasing). the trigger can be applied instantaneously or delayed by a programmable time delay. HMC983LP5Es sweep function is illustrated in figure 24 . the HMC983LP5E generates a frequency sweep by implementing automatic, or triggered in user defned mode, discrete miniature frequency increments in time. a smooth and continuous sweep is then generated, at the output of the vco, after the stepped signal is fltered by the loop flter, as shown in figure 24 . the stepped sweep approach enables the frequency synthesizer (comprising of HMC983LP5E together with its counterpart, the hmc984lp4e) to be in lock for the entire duration of the sweep. this approach results in a number of advantages over conventional methods including: ? the ability to generate a linear sweep. ? the ability to have phase coherence between different sweep ramps, so that the phase profle of each sweep is identical. ? the ability to generate user defned sweeps in user defned sweep mode.
6 - 18 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper figure 24. HMC983LP5E sweep function it is important to note that the synthesized ramp is subject to normal phase locked loop dynamics. if the loop bandwidth in use is much wider than the rate of frequency increments then the locking will be fast and the ramp will have a staircase shape. if the update rate is higher than the loop bandwidth, as is normally the case, the loop will not fully settle before a new frequency step is received. hence the swept output will have a lag and will sweep in a near continuous fashion. in all sweep modes, ramp_busy fag indicates an active sweep and will stay high between the 1st and nth ramp increment. ramp_busy may be monitored on pin d1 by setting reg 08h [3:0] = 8h. triggering in sweep mode, the HMC983LP5E can be triggered via one of two methods ? spi trigger by setting reg 0eh [12]=1. this triggering method is asynchronous to the reference clock. to enable spi trigger write reg 0eh [13] = 0. ? or applying an external trigger on pin d4. setting reg 0eh [13] = 1 and reg 08h [13] = 0h confgures HMC983LP5Es pin d4 as external trigger input. external trigger on pin d4 is triggered on the rising edge of the trigger. gpio master enable ( reg 01h [4] = 1) is also required. ? external triggering method can be synchronized with the reference clock, by enabling trigger delay ( reg 0eh [7] = 1), and programming a trigger delay in reg 05h [20:0] = number of delayed reference periods. writing reg 05h [20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge. to disable trigger delay write reg 0eh [7] = 0. 2-way sweep mode HMC983LP5Es 2-way sweep mode is shown in figure 25 . the 2-way sweep mode can be automatic or triggered. in automatic 2-way sweep, the trigger is generated internally based on user defned 2-way sweep mode confguration. in a triggered 2-way sweep, frequency ramps are triggered either by external pin d4, or spi trigger.
6 - 19 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com figure 25. HMC983LP5E 2-way triggered sweep triggered 1-way sweeps HMC983LP5Es 1-way sweeps is shown in figure 26 . unlike 2-way sweeps, 1-way sweeps require that the vco hop back to the start frequency after the dwell period. triggered 1-way sweeps also require a 3rd trigger to start the new sweep. the 3rd trigger must be timed appropriately to allow the vco to settle after the large frequency hop back to the start frequency. subsequent odd numbered triggers will start each sweep and repeat the process. figure 26. HMC983LP5E 1-way triggered sweep 1-way sweeps are not recommended in auto-sweep mode since in auto-sweep the new sweep will start immediately after the 2nd trigger, as it does in 2-way mode. user defned sweep mode in user defned sweep mode, the HMC983LP5E is able to generate various user-defned sweep patterns by adjusting the time interval between adjacent frequency increments, which are executed by trigger events. HMC983LP5Es user defned sweep mode is shown in figure 27 . in this mode, an external trigger is required for each frequency increment of the sweep.
6 - 20 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper figure 27. HMC983LP5E user defned sweep user defned sweep can function in both 1-way or 2-way sweep mode. in 1-way sweep mode, the n+1 trigger will cause the ramp to jump to the start frequency, and the n+2 trigger will restart the 1-way sweep. detailed sweeper confguration recommended procedure for confguring HMC983LP5E sweeper in all three modes is shown in table 6 .
6 - 21 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 6. HMC983LP5E sweeper confguration sequence steps description sweeper modes 2-way sweep mode user defned sweep mode 1-way sweep mode 1 lock to start frequency (f o ) ? set the integer ( reg 05h ) and fractional ( reg 06h and reg 07h ) divider values. ? optionally, if required the seed ( reg 0ah and reg 0bh ) can also be programmed 2 place the dsm in sweep mode ? write reg 0eh [11] = 1 3 confgure sweep mode ? disable single step ramp mode ( reg 0eh [24] = 0), so that each frequency increment will be incremented automatically ? enable 2-way sweep mode (disable 1-way sweep mode ( reg 0eh [25] = 0)) ? to place the HMC983LP5E in automatic sweep mode write reg 0eh [2:3] = 11. to place the HMC983LP5E in triggered mode write reg 0eh [2:3] = 00. ? enable the single step ramp mode ( reg 0eh [24] = 1), so that each frequency increment will require a trigger ? enable 1-way sweep mode ( reg 0eh [25] = 1), or enable 2-way sweep mode ( reg 0eh [25] = 1) ? to place the HMC983LP5E in triggered mode write reg 0eh [2:3] = 00. automatic user defned sweep mode is not supported. ? disable single step ramp mode ( reg 0eh [24] = 0), so that each frequency increment will be incremented automatically ? enable 1-way sweep mode ( reg 0eh [25] = 1) ? to place the HMC983LP5E in triggered mode write reg 0eh [2:3] = 00. automatic 1-way sweep mode is not supported. 4 program sweep direction ? reg 0eh [26] = 1 begin sweep in positive direction, reg 0eh [26] = 0 begin sweep in negative direction 5 confgure symmetrical/ asymmetrical sweep ? program ramp mode (symmetrical - reg 0eh [22] = 1, asymmetrical - reg 0eh [22] = 0). if symmetrical ramp mode is selected ( reg 0eh [22] = 1), only up sweep parameters will be used for both positive and negative sweeps, and hence down sweep parameters dont need to be programmed. in symmetrical ramp mode the positive and negative ramps are identical and opposite in direction. ? program reg 0eh [22] = 1. asymmetrical sweep is not defned in 1-way sweep mode 6 program up sweep parameters ? set dwell time(dwell time[47:0] = reg 10h [29:0], dwell time[17:0] = reg 11h [17:0]) ? set step size (step size[47:18] = reg 12h [29:0], step size[17:0] = reg 13h [17:0]) ? set the number of steps in a sweep (number of steps[47:18] = reg 14h [29:0], number of steps[17:0] = reg 15h [17:0]) 7 program down sweep parameters (only if using asymmetrical sweep (if reg 0eh [22] = 0) in step 5) ? set dwell time (dwell time[47:0] = reg 06h [47:18], dwell time[17:0] = reg 07h [17:0]) ? set step size (step size[47:18] = reg 19h [29:0], step size[17:0] = reg 1ah [17:0]) ? set the number of steps in a sweep (number of steps[47:18] = reg 0ch [29:0], number of steps[17:0] = reg 0dh [17:0]) ? asymmetrical sweep is not defned in 1-way sweep mode 8 confgure and apply trigger ? to use spi trigger write reg 0eh [13] = 0 to select spi trigger. spi trigger is executed by writing to reg 0eh [12] = 1. ? to use external trigger on pin d4 write reg 0eh [13] = 1 to confgure pin d4 as an external trigger. write reg 08h [13] = 0h to confgure pin d4 to be an input. applying master enable to gpio pins ( reg 01h [4] = 1 ) is required. ? enable trigger delay ( reg 0eh [7] = 1), or disable trigger delay ( reg 0eh [7] = 0). ? if using trigger delay, write delay value to reg 05h [20:0], where reg 05h [20:0] = number of delayed reference periods. writing reg 05h [20:0] = 1 for example ensures that the trigger is applied at the instant of the rising edge of the next reference rising edge. HMC983LP5E sweep parameters are defned in the following way: f o initial frequency of the synthesizer
6 - 22 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper f f frequency of the synthesizer at the end of the sweep r reference divider value( reg 02h [13:0]) stepsize frequency increment step size. in case of symmetric and up sweeps, stepsize[47:18] = reg 12h [29:0], stepsize[17:0] = reg 13h [17:0]). in case of asymmetric sweeps, (downsweep stepsize[47:18] = reg 12h [29:0], down sweep stepsize[17:0] = reg 13h [17:0]) ?f step frequency step size = 2 xtal l f stepsize r ? ? , l size of the dsm (set in reg 16h [5:0]) t ref period of the divided reference (f pfd ) at the phase detector. t ref = r f xtal n total number of frequency step increments in a single sweep. n [47:18] = reg 14h [29:0], n[17:0] = reg 15h [17:0] t ramp total time of one frequency sweep from f o to f f . t ramp = t ref x n then fnal frequency f f is given by: f f = f o + (?f step x n) setting autoseed ( reg 0eh [8] = 1) ensures that different sweeps have identical phase profle. this is achieved by loading the seed (seed[47:18] = reg 0ah [29:0], seed[17:0] = reg 0bh [17:0]) into the phase accumulator at the beginning of each ramp. example: calculate sweep parameters for an asymmetric 2-way sweep from f 0 = 3000 mhz to f f = 3105 mhz with positive t ramp 2 ms, and negative t ramp 4 ms, and positive dwell time = negative dwell time = 2 s, with f pd = 50 mhz, and a 48-bit delta-sigma modulator size. assuming r = 1. 1. calculate the integer and fractional divider values for initial start frequency f 0 ? start nint = reg 05h = 60d ? start nfrac = reg 06h = reg 07h = 0d 2. calculate the number of divided (r = 1) reference periods in the sweep = number of frequency increments n ? nup = 2 ms/(1/50 mhz) = 100000 ? ndown = 4 ms/(1/50 mhz) = 200000 3. calculate stepsize (size of frequency increments) ? stepssize up = abs(f f - f 0 )/nup = abs(3000 mhz - 3105 mhz)/100000 = 1050 hz. then as per table 6 , reg 12h [29:0] = 0h, reg 13h [17:0] = 1050d = 41ah ? stepsize down = abs(ff - f0)/ndown = abs(3000 mhz - 3105 mhz)/200000 = 525 hz then as per table 6 , reg 19h [29:0] = 0h, reg 1ah [17:0] = 1050d = 41ah note that it is possible to have a case where the frequency f f cannot be generated exactly. in that case it is required to approximate the fnal frequency to f f = f o + (?f step x n) desired fnal frequency. 4. calculate number of divided (r = 1) reference periods in required dwell time ? up dwell time ( reg 10h [29:0], reg 11h [17:0]) = down dwell time ( reg 06h [29:0], reg 07h [17:0]) = dwell time/ (1/ 50 mhz) = 2 s/(1/50 mhz) = 100. then as per table 6 , reg 10h [29:0] = reg 06h [29:0] = 0h, and reg 11h [17:0] = reg 07h [17:0] = 100d = 64h. then proceed to confgure the sweep according to the steps outlined in table 6 . serial port interface the HMC983LP5E features a four wire serial port for simple communication with the host controller. typical serial port operation can be run with sck at speeds up to 30 mhz.
6 - 23 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com the details of spi access for the HMC983LP5E is provided in the following sections. note that the read operation below is always preceded by a write operation to register 0 to defne the register to be queried. also note that every read cycle is also a write cycle in that data sent to the spi while reading the data will also be stored by the HMC983LP5E when senb goes high. if this is not desired then it is suggested to write to register 0 during the read operation so that the status of the device will be unaffected. power on reset and soft reset the HMC983LP5E has a built in power on reset (por) and a serial port accessible soft reset (sr). por is accomplished when power is cycled for the HMC983LP5E while sr is accomplished via the spi by writing reg 00h = 80h, followed by writing reg 00h =00h. all chip registers will be reset to default states approximately 250 us after power up. serial port write operation the host changes the data on the falling edge of sck and the HMC983LP5E reads the data on the rising edge. a typical write cycle is shown in figure 28 . it is 32 clock cycles long. 1. the host both asserts senb (active low serial port enable) and places the msb of the data on sdi followed by a rising edge on sck. 2. HMC983LP5E reads sdi (the msb) on the 1st rising edge of sck after senb. 3. HMC983LP5E registers the data bits, d23:d0, in the next 23 rising edges of sck (total of 24 data bits). 4. host places the 5 register address bits, a4:a0, on the next 5 falling edges of sck (msb to lsb) while the HMC983LP5E reads the address bits on the corresponding rising edge of sck. 5. host places the 3 chip address bits, ca2:ca0=[110], on the next 3 falling edges of sck (msb to lsb). note the HMC983LP5E chip address is fxed as 6d or 110b. 6. senb goes from low to high after the 32nd rising edge of sck. this completes the write cycle. 7. HMC983LP5E also exports data back on the sdo line. for details see the section on read operation. serial port read operation the spi can read from the internal registers in the chip. the data is available on sdo pin. this pin itself is tri-stated when the device is not being addressed. however when the device is active and has been addressed by the spi master, the HMC983LP5E controls the sdo pin and exports data on this pin during the next spi cycle. HMC983LP5E changes the data to the host on the rising edge of sck and the host reads the data from HMC983LP5E on the falling edge. a typical read cycle is shown in figure 28 . read cycle is 32 clock cycles long. to specifcally read a register, the address of that register must be written to dedicated reg 0h . this requires two full cycles, one to write the required address, and a 2nd to retrieve the data. a read cycle can then be initiated as follows; 1. the host asserts senb (active low serial port enable) followed by a rising edge sck. 2. HMC983LP5E reads sdi (the msb) on the 1 st rising edge of sck after senb. 3. HMC983LP5E registers the data bits in the next 23 rising edges of sck (total of 24 data bits). the lsbs of the data bits represent the address of the register that is intended to be read. 4. host places the 5 register address bits on the next 5 falling edges of sck (msb to lsb) while the HMC983LP5E reads the address bits on the corresponding rising edge of sck. for a read operation this is 00000. 5. host places the 3 chip address bits [110] on the next 3 falling edges of sck (msb to lsb). 6. senb goes from low to high after the 32 nd rising edge of sck. this completes the frst portion of the read cycle.
6 - 24 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper 7. the host asserts senb (active low serial port enable) followed by a rising edge sck. 8. HMC983LP5E places the 24 data bits, 5 address bits, and 3 chip id bits, on the sdo, on each rising edge of the sck, commencing with the frst rising edge beginning with msb. 9. the host de-asserts senb (i.e. sets senb high) after reading the 32 bits from the sdo output. the 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. this completes the read cycle. note that the data sent to the HMC983LP5E spi during this portion of the read operation is stored in the spi when senb is de-asserted. it is recommended that during the second phase of the read operation that reg 00h is addressed with either the same address or the address of another register to be read during the next cycle. figure 28. spi timing diagram dvdd = 5 v 10%, gnd = 0 v table 7. main spi timing characteristics parameter conditions min typ max units t 1 sdi to sck setup time 8 nsec t 2 sdi to sck hold time 8 nsec t 3 sck high duration [1] 10 nsec t 4 sck low duration 10 nsec t 5 senb low duration 20 nsec t 6 senb high duration 20 nsec t 7 sck to senb [2] 8 nsec t 8 sck to sdo out [3] 8 nsec [1] the spi is relatively insensitive to the duty cycle of sck. [2] senb must rise after the 32 nd falling edge of sck but before the next rising sck edge. if sck is shared amongst several devices this timing must be respected. [3] typical load to sdo is 10 pf, maximum 20 pf
6 - 25 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com register map table 8. reg 00h chip id, soft reset, read register bit type name w deflt description [6:0] r/w read register address 7 0 address of the register to be read in the next cycle. [7] r/w soft reset 1 0 soft reset. writing 1 generates soft reset. resets all the digital and registers to default states. writing 0 resumes normal chip operation. [31:8] r/w chip id 24 97330h part number, description. read reg00h returns chip id. table 9. reg 01h - settings register bit type name w deflt description [0] r/w vco buffer enable 1 1 enables vco input rf buffer. [1] r/w reserved 1 1 write 0 to this bit. [2] r/w auxspi enable 1 1 enables auxiliary spi. [3] r/w sigma delta enable 1 1 enables sigma delta function. [4] r/w gpio enable 1 1 enables output from all gpio pins. [5] r/w rf divider enable 1 1 enables rf divider. [6] r/w output buffer enable 1 1 enables divider output driver. [7] r/w bias enable 1 1 enables bias generator for all blocks. [8] r/w psclk to digital enable 1 1 enable prescaler clock going to digital counters. [9] r/w unused 1 1 table 10. reg 02h r-divider register bit type name w deflt description [13:0] r/w r divider ratio 14 1h local value for reference division ratio. auxiliary spi registers the following two registers defne the communication through the auxspi. if the auxspi is enabled ( reg 04h [4] = 0), writes to auxspi are executed via reg 03h . the auxiliary device address is expected in reg 04h [2:0]. if HMC983LP5E is working as a standalone frequency divider the auxspi clock is expected on the dnsat pin, and reg 04h [15] must be set to 1. it is recommended to disable auxspi when not used. table 11. reg 03h aux. vco data register bit type name w deflt description [3:0] r/w auxspi register address 4 0h 4-bit register address for the auxiliary device spi. [12:4] r/w auxspi data 9 000h 9-bit long register data for the auxiliary device spi.
6 - 26 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 12. reg 04h - aux. vco settings register bit type name w deflt description [2:0] r/w auxiliary device address 3 000h chip address used by auxspi. [3] r/w divide clock by 4 for auxspi 1 0 0 = use xtal for auxspi clock. 1 = use xtal divided by 4 for auxspi clock. [4] r/w start auxspi 1 0 0 = start auxspi when data is written to reg03h. 1 = reserved. [7:5] r/w reserved 3 4h [9:8] r/w reserved 2 2h [13:10] r/w reserved 4 8h [14] r/w reserved 1 0 [15] r/w keep xtal gate open 1 0 when 1, keeps the xtal gate open to get xtal from the companion pfd/cp chip hmc984lp4e. [18:16] r/w reserved 3 0h table 13. reg 05h integer set-point, trigger delay register bit type name w deflt description [19:0] r/w integer division ratio 20 200d sigma-delta modulator integer set point. specifes the integer part of the division ratio for the rf divider in fractional mode or the integer division ration in integer mode. ramp trigger delay also used as delay counter for hardware ramp trigger (pin d4) in ramp mode. this value is valid when reg 0eh [11] = 1. table 14. reg 06h fractional set-point, down dwell register (msb) bit type name w deflt description [29:0] r/w fractional division ratio (msb) 30 0 most signifcant 30 bits to specify fractional set point for sigma- delta modulator. total fractional bits are 48. down dwell for asymmetric frequency. ramp (msb) defnes the msb portion of the dwell down time in the asymmetric frequency sweep mode, valid when reg 0eh [11]=1. table 15. reg 07h fractional set-point, down dwell register (lsb) bit type name w deflt description [17:0] r/w fractional division ratio (lsb) 18 0 least signifcant 18 bits to specify fractional set point for sigma- delta modulator. total fractional bit are 48. down dwell for asymmetric frequency. ramp (lsb) defnes the lsb portion of the dwell down time in the asymmetric frequency sweep mode, valid when reg0e[11]=1.
6 - 27 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 16. reg 08h gpio confguration register bit type name w deflt description [3:0] r/w gpo output select 4 0h selects exported output signals to gpio pins. see table 5 for details. master enable for gpio reg 01h [4] = 1 is required. . [8:4] r/w gpo static test value 5 00000b static gpio test signals for output (d4,d3,d2,d1,d0). writing these value and reading them back test the gpio functionality. master enable for gpio reg 01h [4] = 1 is required. . [13:9] r/w gpo pin enable 5 11111b independent gpio pin enables. reg08[13] = 0 - d4 input reg08[13] = 1 - d4 output reg08[12] = 0, d3 input reg08[12] =1, d3 output reg08[11] = 0, d2 input reg08[11] = 1, d2 output reg08[10] = 0, d1 input reg08[10] = 1, d1 output reg08[9] = 0, d0 input reg08[9] = 1, d0 output master enable for gpio reg 01h [4] = 1 is required. table 17. reg 09h companion chip address local register bit type name w deflt description [2:0] r/w counterpart hmc984lp4e chip address 3 2h chip address of the companion chip hmc984lp4e. table 18. reg 0ah sigma delta modulator seed msb register bit type name w deflt description [29:0] r/w seed msb 30 4241h most signifcant bits of the seed for the 1st accumulator in sigma-delta modulator. table 19. reg 0bh sigma delta modulator seed lsb register bit type name w deflt description [17:0] r/w seed lsb 18 10081h least signifcant bits of the seed for the 1st accumulator in sigma-delta modulator. table 20. reg 0ch ramp nstep down msb register bit type name w deflt description [29:0] r/w down ramp number of steps (msb) 30 0h most signifcant bits of the number of steps for the frequency ramp in down direction in sweep mode. table 21. reg 0dh ramp nstep down lsb register bit type name w deflt description [17:0] r/w down ramp number of steps (lsb) 18 0h least signifcant bits of the number of steps for the frequency ramp in down direction in sweep mode.
6 - 28 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 22. reg 0eh sigma delta modulator confguration register bit type name w deflt description [1:0] r/w sd modulator type 2 11b dsm type. 00 = mash1 - reserved 01 = mash11 - reserved 10 = mash111 - delta sigma modulator mode b 11 - delta sigma modulator mode a [2] r/w ramp auto repeat control from spi 1 0 recommended to write 1 to this bit in ramp mode. when this bit is 1, the ramp will repeat itself if ramp_auto_repeat_on/off_from_ spi is 1 at the end of the each sweep. [3] r/w ramp auto repeat control from spi on/off 1 0 ramp will automatically repeat itself if this bit is 1 and bit 2 is also set to 1. [6:4] r/w integer path delay 3 111 delay through the integer signal path to compensate for the fractional path. 000 = no delay. 110 = 6 clock cycles delay. 111 = automatic. [7] r/w ramp start delay enable 1 0 delay the start of sweep as defned in reg 05h [8] r/w autoseed mode enable 1 1 reseed when changing the frac setpoint. [9] r/w reserved 1 0 [10] r/w maintain dsm state enable 1 0 maintain dsm state within the same integer boundary. [11] r/w ramp mode enable 1 0 puts dsm in frequency sweeper (ramp) mode. [12] r/w ramp start from spi 1 0 start ramp signal from spi. [13] r/w start ramp from ext. trigger 1 0 allow external trigger to manipulate ramp. [14] r/w bypass all 1 0 bypass delta sigma modulator. place synthesizer in integer mode without disabling the dsm. [18:15] r/w csp step size 4 1111b cycle slip prevention (csp) step size. in a pll confguration with the hmc984lp4e one step is equivalent to one divided vco cycle, and step size is the number of vco cycles. [19] r/w external dsm sequence enable 1 0 use external dsm sequence imported through gpio port. [20] r/w use falling edge of dsm clock for external sequence 1 0 use falling edge of sd clock to get the external sequence. [21] r/w lock using external trigger pin 1 0 allow external trigger to start locking process. writing to the integer or fractional division ratio registers does not have any effect when this bit is set to 1. pll will lock only when external trigger goes high. [22] r/w symmetrical ramp mode 1 1 use symmetric frequency sweeping for up and down directions otherwise dn parameters are taken from registers reg 0ch , reg 0dh , reg 19h and reg 1ah for asymmetric mode. [23] r/w integer mode lock strobe 1 0 re-lock when integer set-point reg 06h is updated. [24] r/w singlestep ramp mode enable 1 0 single-step the ramp. each step of the ramp must be popped by strobe (either spi or hardware pin). [25] r/w single direction ramp mode enable 1 0 single direction mode for ramp (ramp one way, pop to base the other way). [26] r/w ramp start direction 1 1 starting direction of ramp. it is only loaded while rampmode = 0. 1 = positive 0 = negative [27] r/w use external clock for dsm 1 0 1 = use external clock from gpio pin to clock dsm. [28] r/w reserved 1 0 [29] r/w use x16 csp step 1 0 1 = increase the csp step size given in bits [18:15] by a factor of 16.
6 - 29 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 23. reg 0fh vco divider confguration register bit type name w deflt description [0] r/w increase divider pulse width to dsm 1 0 increase the width of the clock pulse going to dsm (available only when division ratio > 64). [1] r/w increase divider pulsewidth to pfd 1 1 increase pulse width (low duration) of the clock going to pfd. [4:2] r/w output buffer current select 2 011b sets current for divider output buffer. helps to control voltage swing for various impedance options. 000 = 5ma 001 = 7.5ma 010 = 10ma 011 = 12.5ma 100 = 10ma 101 = 12.5ma 110 = 15ma 111 = 17.5ma [5] r/w reset rf divider 1 0 resets the rf divider. [8:6] r/w divider resynch bias select 3 011b bias current setting for divider resync. default value recommended. [11:9] r/w rf buffer bias select 3 001b bias current setting for input rf buffer. default value recommended. [14:12] r/w divider pulsewidth select 3 011b divider output pulse width control. 000 = 5 vco cycles. 001 = 13 vco cycles. 010 = 21 vco cycles. 011 = 29 vco cycles. 100 = 37 vco cycles. 101 = 45 vco cycles. 110 = 53 vco cycles. 111 = 61 vco cycles. table 24. reg 10h ramp dwell symmetrical or up msb register bit type name w deflt description [29:0] r/w symmetric ramp dwell (msb) 30 0 represents msbs for ramp dwell time in up and down directions for symmetric frequency sweep mode. in asymmetric mode it represents the up dwell time only. table 25. reg 11h ramp dwell symmetrical or up lsb register bit type name w deflt description [17:0] r/w symmetric ramp dwell (lsb) 18 0 represents lsbs for ramp dwell time in up and down directions for symmetric frequency sweep mode. in asymmetric mode it represents the up dwell time only. table 26. reg 12h ramp step size symmetrical or up msb register bit type name w deflt description [29:0] r/w symmetric ramp step size (msb) 30 0 represents the msb for ramp step size in up and down directions for symmetric frequency sweep mode. in asymmetric mode it represents the up step size only.
6 - 30 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper table 27. reg 13h ramp step size symmetrical or up lsb register bit type name w deflt description [17:0] r/w symmetric ramp step size (lsb) 18 0 represents the lsb for ramp step size in up and down directions for symmetric frequency sweep mode. in asymmetric mode it represents the up step size only. table 28. reg 14h ramp nstep symmetrical or up msb register bit type name w deflt description [29:0] r/w symmetric ramp number of steps (msb) 30 0 represents the msb of the number of steps for the frequency ramp in up and down directions in symmetric frequency sweep mode. in asymmetric mode it represents the number of steps in up direction only. table 29. reg 15h ramp nstep symmetrical or up lsb register bit type name w deflt description [17:0] r/w symmetric ramp number of steps (lsb) 18 0 represents the lsb of the number of steps for the frequency ramp in up and down directions in symmetric frequency sweep mode. in asymmetric mode it represents the number of steps in up direction only. table 30. reg 16h dsm confguration register bit type name w deflt description [1:0] r/w dsm 1st accumulator size 2 00b dsm 1st accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [3:2] r/w dsm 2nd accumulator size 2 00b dsm 2nd accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [5:4] r/w dsm 3rd accumulator size 2 00b dsm 3rd accumulator width. 00 = 48 bits 01 = 32 bits 10 = 24 bits 11 = 16 bits [8:6] r/w disable frac. register clock 3 000b clock gates for the 3 accumulators (fractional part), 1 disables the clock. [11:9] r/w disable integer register clock 3 000b clock gates for the 3 accumulators (integer part), 1 disables the clock. [12] r/w disable dsm mode a clock 1 0 1 = disable delta sigma modulator mode a clock [13] r/w disable dsm mode b clock 1 0 1 = disable delta sigma modulator mode b clock [14] r/w reserved 1 0 [15] r/w disable integer path clock 1 0 1 = disables integer path clock [16] r/w disable input buffer clock 1 0 1 = disables input buffer clock [17] r/w disable output buffer clock 1 0 1 = disables output buffer clock [18] r/w reserved 1 0 [19] r/w reserved 1 0
6 - 31 frequency dividers & detectors - smt 6 HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com table 31. reg 17h this register does not exist bit type name w deflt description this register does not exist table 32. reg 19h ramp down step size msb register bit type name w deflt description [29:0] r/w ramp step down msb. 30 0 represents msbs to defne the step size for the ramp in down direction in ramp mode. table 33. reg 1ah ramp down step size lsb register bit type name w deflt description [17:0] r/w ramp step down lsb. 18 0 represents lsbs to defne the step size for the ramp in down direction in ramp mode.
6 - 32 frequency dividers & detectors - smt 6 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com HMC983LP5E v00.0911 dc - 7 ghz fractional-n divider and frequency sweeper notes:

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