1/26//2001 1 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cmpwr120 california micro devices ?2001 california micro devices corp. all rights reserved. smartor? is a trademark of california micro devices corp. 250ma / 3.3v smartor? power regulator features automatic detection of v cc input supply drive output logic to control external switch glitch-free output during supply transitions 250ma output maximum load current built-in hysteresis during supply selection controller operates from either v cc or v out 8-pin soic narrow package product description california micro devices? smartor tm cmpwr120 is a low dropout regulator that delivers up to 250ma of load current at a fixed 3.3v output. an internal threshold level (typically 4.1v) is used to prevent the regulator from being operated below dropout voltage. the device continuously monitors the input supply and will automati- cally disable the regulator when v cc falls below the threshold level. when the regulator is disabled, the control signal ?drive? (active low) is enabled, which allows an external pmos switch to power the load from an auxiliary 3.3v supply. applications pci adapter cards network interface cards (nic?s) dual power systems systems with standby capabilities see application note ap211 c0610999 when v cc is restored to a level above the select thresh- old, the control signal for the external pmos switch is disabled and the regulator is once again enabled. all the necessary control circuitry needed to provide a smooth and automatic transition between the supplies has been incorporated. this allows v cc to be dynamically switched without loss of output voltage. pin diagram, application circuit, and electrical schemati c 1 2 3 4 v cc nc nc gnd 8 7 6 5 drive v out v out nc top view cmpwr120 8-pin soic narrow v cc v cc 5v v aux 3.3v gnd gnd gnd drive mgsf1p02elt1 v out v out 3.3v 200ma cmpwr120 4? + ? + ? c in 1? c out + + v out 3.3v 200ma v ref 3.3v + ? v cc + ? deselect 4.1v gnd drive enable pin diagram simplified electrical schematic typical application circuit
?2001 california micro devices corp. all rights reserved. smartor? is a trademark of california micro devices corp. 1/26/2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 2 cmpwr120 california micro devices ab so l u te maxim u m ratin gs p a r a m e t e r ratin g u ni t esd protection ( hbm ) 2 000 v v cc input voltage 6, gnd ? 0.5 v drive logic voltage v cc 0.5, gnd ? 0.5 v storage temperature range ? 40 to 150 ? c operating ambient 0 to 70 ? c operating junction 0 to 125 ? c power dissipation: soic (note 1) 0.5 w o peratin g co nditi o n s p a r a m e t e r ran g e u ni t v cc 5 0 . 5 v temperature (ambient) 0 to 70 ? c load current 0 to 250 ma c ext 4.7 10% f ele c tri c al o peratin g c hara c teri s ti cs (over operatin g conditions unless specified otherwise ) s y m b o l p a r a m e t e r c onditions min typ max u ni t v out re g ulator output volta g e 2 50 ma < i load < 0 ma 3 .1 35 3 . 30 3 .4 65 v i out regulator output current 250 ma v ccsel select voltage regulator enabled 3.90 4.35 4.45 v v ccdes deselect voltage regulator disabled 3.90 4.10 4.45 v v cchyst hysteresis voltage hysteresis (note 2) 3.90 0.25 4.45 v i s/c short circuit output current v cc = 5v, v out = 0v 1200 ma i rcc v cc pin reverse leakage v out = 3.3v, v cc = 0v 5 50 a v r load load regulation v cc = 5v, i load = 20 to 250ma 35 mv v r line line regulation v cc = 4.5v to 5.5v, i load = 5ma 2 mv i cc quiescent supply current v cc > v ccsel , i load = 0ma 1.0 3.0 ma v ccdes > v cc > v out 0.15 0.25 ma v out > v cc 0.01 0.02 ma i gnd ground pin current (note 3) v ccsel (regulator disabled) 0.15 0.30 ma v cc = 5v, i load = 5ma 1.0 2.5 ma v cc = 5v, i load = 250ma 1.2 3.0 ma r oh drive pull-up resistance r pullup to v cc , v cc > v ccsel 100 400 ? r ol drive pull-down resistance r pulldown to gnd, v ccdes > v cc 200 400 ? t dh drive high delay c drive = 1nf, v cc t rise < 100ns 1.0 s t dl drive low delay c drive = 1nf, v cc t fall < 100ns 0.2 s note 1: the power rating is based on a printed circuit board heat spreading capability equivalent to 2 square inches of copper connecte d to the gnd pins. typical multi-layer boards using power plane construction will provide this heat spreading ability without the ne ed for additional dedicated copper area. (please consult with factory for thermal evaluation assistance.) note 2: the hysteresis defines the maximum level of acceptable disturbance on v cc during switching. it is recommended that the v cc source impedance be kept below 0.25 ? to ensure the switching disturbance remains below the hysteresis during select/deselect transitions. an input capacitor may be required to help minimize the switching transient. note 3: ground pin current consists of controller current (0.15ma) and regulator current if enabled. the controller always draws 0.15ma from either v cc or v out , whichever is greater. all regulator current is supplied exclusively from v cc . at high load currents a small increase occurs due to current limit protection circuitry.
1/26//2001 3 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cmpwr120 california micro devices ?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. interface signals v cc is the power source for the internal regulator and is monitored continuously by an internal controller circuit. whenever v cc exceeds v ccsel (4.35v typ), the internal regulator (250ma max) will be enabled and deliver a fixed 3.3v at v out . when v cc falls below v ccdes (4.10v typ) the regulator will be disabled. internal loading on this pin is typically 1.0ma when the regulator is enabled, which reduces to 0.15ma whenever the regulator is disabled. if v cc falls below the voltage on the v out pin the v cc loading will further reduce to only a few microamperes. during a v cc power up sequence, there will be an effective step increase in v cc line current when the regulator is enabled. the amplitude of this step increase will depend on the dc load current and any necessary current required for charging/discharging the load capacitance. this line current transient will cause a voltage disturbance at the v cc pin. the magnitude of the disturbance will be directly proportional to the effective power supply source impedance being delivered to the v cc input. to prevent chatter during select and deselect transi- tions, a built-in hysteresis voltage of 250mv has been incorporated. it is recommended that the power supply connected to the v cc input should have a source resis- tance of less than 0.25 ? to minimize the event of chatter during the enabling/disabling of the regulator. an input filter capacitor in close proximity to the v cc pin will reduce the effective source impedance and help minimize any disturbances. if the v cc pin is within a few inches of the main input filter, a capacitor may not be necessary. otherwise an input filter capacitor in the range of 1f to 10f will ensure adequate filtering. gnd is the negative reference for all voltages. the current that flows in the ground connection is very low (typ 1.0ma) and has minimal variation over all load conditions. v out is the regulator output voltage connection used to power the load. an output capacitor of ten microfarads is used to provide the necessary phase compensation, thereby preventing oscillation. the capacitor also helps to minimize the peak output disturbance during power supply changeover. when v cc falls below v out , then v out will be used to provide the necessary quiescent current for the internal reference circuits. this ensures excellent start-up characteristics for the regulator. drive is an active low logic output intended to be used as the control signal for driving an external pfet whenever the regulator is disabled. this will allow the voltage at v out to be powered from an auxiliary supply voltage (3.3v). the drive pin is pulled high to v cc whenever the regulator is enabled. this ensures that the auxiliary remains isolated during normal regulator operation. output current sinking and sourcing ability of this logic signal is equivalent to 400 ? . nc pins are electrically isolated from the internal circuitry. these pins can be connected to any external voltage level without impacting the device functionality. pin f u n c ti o n s s y mbol descri p tio n v cc positive supply input for re g ulator. when v cc falls below 4.1v the re g ulator is disabled . gnd negative reference for all voltages v out regulator voltage ouput (3.3v) regulator when v cc is present. when v cc is not present, the voltage on v out is used to bias the internal references. drive cmos logic output intended to control external pmos switch for selecting an auxiliary voltage supply when v cc is not present. nc unconnected pins which are electrically isolated from internal circuitry
?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. 1/26/2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 4 cmpwr120 california micro devices typical dc characteristics unless stated otherwise, all dc characteristics were measured at room temperature with a nominal v cc supply voltage of 5.0v and an output capacitance of 4.7f. the external pmos switch was present and resistive load conditions were used. with normal production devices, the v deselect voltage prevents the regulator from operating in dropout mode. for the purposes of obtaining full dropout characteristics, the evaluation test device had access to the v deselect voltage. by forcing this voltage artificially low, full dropout characteristics were obtained. dropout characteristics of the regulator are shown in figure 1. output regulation under full load conditions is maintained down the line at voltages of 3.6v. in normal operation, the regulator is deselected at 4.1v, which ensures a regulation output droop of less than 20mv is maintained. figure 1. dropout characteristics load regulation performance is shown from zero to maximum rated load in figure 2. a change in load from 10% to 100% of rated, results in an output voltage change of less than 35mv. this translates into an effective output impedance of approximately 0.15 ? . figure 2. load regulation ground current is shown across the entire range of load conditions. the ground current has minimal varia- tion across the range of load conditions and shows only a slight increase at maximum load. this slight increase at rated load is due to the current limit protection circuitry becoming active. see figure 3. figure 3. ground current v cc supply current of the device is shown across the entire v cc range for both v aux present (3.3v) and absent (0v). see figure 4. in the absence of v aux , the supply current remains fixed at approximately 0.15ma until v cc reaches the select voltage threshold of 4.35v. at this point the regulator is enabled and a supply current of 1.0ma is conducted. when v aux is present, the v cc supply current is less than 10a until v cc exceeds v aux , at which point v cc then powers the controller (0.15ma). when v cc reaches v select , the regulator is enabled. figure 4. v cc supply current (no load). 3.15 3.20 3.25 3.30 3.35 3.5 4.0 v cc (v) v out (v) 4.5 50ma load 250ma load 5.0 load current (ma) current (ma) 0.0 0 100 500 400 300 200 0.5 1.0 1.5 2.0 v cc (v) v aux = 3.3v v aux = 0v supply current ( a ) 1234 5 10,000 1000 100 10 3.40 3.35 3.30 3.25 3.20 0100 load current (ma) v out (v) 200 300
1/26//2001 5 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cmpwr120 california micro devices ?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. v cc v cc 5v tr = 20ms tf= 20ms v aux 3.3v mgsf1p02elt1 drive v out v out gnd gnd cmpwr120 r s 0.2 ? c1 c2 4.7? 0.1? + c3 c4 0.1? 4.7? (250ma) 13.2 ? + transient characteristics test setup typical transient characteristics the transient characterization test setup shown below includes the effective source impedance of the v cc supply (r s ). this was measured to be approximately 0.2 ? . it is recommended that this effective source impedance be no greater than 0.25 ? to ensure that precise switching is maintained during v cc selection and deselection. both the rise and fall times during v cc power-up/down sequencing were controlled at a 20ms duration. this is considered to represent worst case conditions for most application circuits. a maximum rated load current of 250ma was used during characterization, unless specified otherwise. during a selection or deselection transition, the dc load current is switching from v aux to v cc and vice versa. in addition to the normal load current, there may also be an in-rush current for charging/discharging the load capaci- tor. the total current pulse being applied to either v aux or v cc is equal to the sum of the ds load and the corre- sponding in-rush current. transient currents in excess of 0.5a can readily occur for brief intervals when either supply commences to power the load. the oscilloscope traces of v cc power-up/down show the full bandwidth response at the v cc and v out pins under full load (250ma) conditions. see application note ap211 for more information. v cc power-up cold start. figure 5 shows the output response during an initial v cc power-up with v aux not present. when v cc reaches the select threshold, the regulator turns on. the uncharged output capacitor causes maximum in-rush current to flow, resulting in a large voltage disturbance at the v cc pin of about 200mv. the built-in hysteresis of 250mv ensures the regulator remains enabled throughout the transient. prior to v cc reaching an acceptable logic supply level (2v), a disturbance on the drive pin can be observed. figure 5. v cc power-up cold start 3.5v drive 250ma load v cc v out m 1ms 1v ch1 ch2 5v 3 2 ch3 1v 50ks/s tek 1 acqs ch1
?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. 1/26/2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 6 cmpwr120 california micro devices typical transient characteristics (continued) v cc power-up (v aux = 3.3v). figure 6 shows the output response as v cc approaches the select threshold during a power-up when v aux is present (3.3v). the output capacitor is already fully charged. when v cc reaches the select threshold, the in-rush current is minimal and the v cc disturbance is only 130mv. the built-in hysteresis of 250mv ensures the regulator remains enabled through- out the transient. v out offset = 3.3v, v cc offset = 4.3v figure 6. v cc power-up (v aux = 3.3v) v cc power-up (v aux = 3.0v). figure 7 shows the output response as v cc approaches the select threshold during power-up. the auxiliary voltage input is set to the low figure 7. v cc power-up (v aux = 3.0v). level of 3.0v. when v cc reaches the select threshold, a modest level of in-rush current is required to further charge the output capacitor resulting in v cc disturbance of 150mv. the built-in hysteresis of 250mv ensures the regulator remains enabled throughout the transient. the output shows a smooth transition as it ramps from the v aux voltage up to the regulator output. v out offset = 3.3v, v cc offset = 4.3v v cc power-down (v aux = 3.3v). figure 8 shows the output response as v cc approaches the deselect voltage during a power-down transition with v aux set to 3.3v. when v cc reaches v ccdes (4.1v), a disturbance of 70mv is observed due to the step change reduction in v cc line current. the built-in hysteresis of 250mv ensures the regulator remains disabled throughout the transient. v out offset = 3.3v, v cc offset = 4.3v figure 8. v cc power-down (v aux = 3.3v). the output voltage experiences a disturbance of approxi- mately 100mv during the transient. some of this disturbance is attributed to the response at v aux input pin. v cc power-down (v aux = 0v). figure 9 shows the output response of the regulator during a complete power- down situation under full load conditions. regulation on the output is fully maintained until v cc falls below the deselect voltage. when v cc eventually collapses below an acceptable logic supply level (2v), a disturbance on the drive pin can be observed. v cc offset = 5.0v 3.2v drive 250ma load v cc v out m 20? 100mv 5v 3 1 ch3 ch1 100mv 2.50ms/s tek 1 acqs ch3 3.2v drive 250ma load v cc v out m 20? 100mv 5v 3 2 ch3 ch2 100mv 2.50ms/s tek 1 acqs ch3 3.2v drive 250ma load v cc v out m 20? 100mv 5v 3 1 ch3 ch1 100mv 2.50ms/s tek 1 acqs ch3
1/26//2001 7 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com cmpwr120 california micro devices ?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. typical transient characteristics (continued) figure 9. v cc power-down (v aux = 0v). load step response. figure 10 shows the output response of the regulator during a step load change from 5ma to 250ma. during the application and removal of the step load minimal overshoot is observed and transient has settled within 10s. the dc voltage change on the output is approximately 40mv, which demonstrates the regulator output imped- ance of 0.15 ? . v out offset = 3.3v figure 10. load step response. line step response. figure 11 shows the regulator output response to a step transient (1vpp) on the v cc input. the load condition applied is 5ma. a disturbance of less than 30mv is observed on the output during the transient. v out offset = 3.3v figure 11. line step response. thermal dissipation of junction heat consists primarily of two paths in series. the first path is the junction to the case ( jc ) thermal resistance, which is defined by the package style, and the second path is the case to ambient ( ca ) thermal resistance, which is dependent on board layout and construction. for a given package style and board layout, the operat- ing junction temperature is a function of junction power dissipation p junc and the ambient temperature, resulting in the following thermal equation: t junc = t amb + p junc ( jc ) + p junc ( ca ) the 8-pin soic narrow style package has jc of 60 c/w. when mounted on a printed circuit board with a heat- spreading ability equivalent to 2 square inches of copper, the resulting ca is approximately 40 c/w. based on maximum power dissipation of 0.5w (2v x 250ma) with an ambient of 70 c, the resulting junction temperature will be: t junc = t amb + p junc ( jc ) + p junc ( ca ) = 70 c + 0.5w (60 c/w) + 0.5w (40 c/w) = 70 c + 30 c + 20 c = 120 c 3.2v drive 250ma load v cc v out m 1ms 1v 5v 2 1 ch3 ch1 ch2 1v 2.50ks/s tek 1 acqs ch3 1.72v 5ma to 250ma load step v out m 10? 100mv 2 ch1 ch2 2v 5ms/s tek 2 acqs ch2 1 4.92v 4.5v to 5.5v 5ma load v out v cc m 100? 20mv 2 ch1 ch2 1v 500ks/s tek 2 acqs ch2 1
?2001 california micro devices corp. all rights reserved. smartor is a trademark of california micro devices corp. 1/26/2001 215 topaz street, milpitas, california 95035 tel: (408) 263-3214 fax: (408) 263-7846 www.calmicro.com 8 cmpwr120 california micro devices s tandard part o rderin g inf o rmati on packa g e orderin g part numbe r pin s st y le t ubes ta p e & reel part markin g 8 soic narrow cmpwr120s/t cmpwr120s/r cmpwr120s typical transient characteristics (continued) the cmpwr120 can therefore be operated at full rated load conditions when provided with a case to ambient thermal resistance of 40 c/w. most multilayer boards using power plane construction will readily provide this acceptable thermal environment. measurements showing performance up to maximum junction temperature of 125 c were performed under light load conditions (5ma). this allows the ambient temperature to be representative of the internal junction temperature. output voltage vs. temperature. figure 12 shows the regulator v out performance up to the maximum rated junction temperature. the overall 100 c variation in junction temperature causes an output voltage change of about 30mv, reflecting a voltage temperature coefficient of 90ppm/ c. figure 12. output voltage vs. temperature. 3.20 3.25 3.30 3.35 25 50 junction temperature ( ? c) v out (v) 75 5ma load 100 125 thresholds vs. temperature. figure 13 shows the regulator select/deselect threshold variation up to the maximum rated junction temperature. the overall 100 c change in junction temperature causes a 30mv variation in the select threshold voltage (regulator enable). the deselect threshold level varies about 50mv over the 100 c change in junction temperature. this results in the built-in hysteresis having minimal variation over the entire operating junction temperature range. figure 13. threshold vs. temperature. 4 4.1 4.2 4.4 4.3 25 50 junction temperature ( ? c) threshold (v) 75 v select v deselect 100 125
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