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1. general description the saf7115 is a video capture device that, due to its improved comb ?lter performance and 10-bit video output capabilities, is suitable for various applications such as in-car video reception, in-car entertainment or in-car navigation. the saf7115 is a combination of a two channel analog preprocessing circuit and a high performance scaler. the two channel analog preprocessing circuit includes source-selection, an anti-aliasing ?lter and analog-to-digital converter (adc) per channel, an automatic clamp and gain control, two clock generation circuits (cgc1 and cgc2) and a digital multi standard decoder that contains two-dimensional chrominance/luminance separation utilizing an improved adaptive comb ?lter. the high performance scaler has variable horizontal and vertical up and down scaling and a brightness/contrast/saturation control circuit. the decoder is based on the principle of line-locked clock decoding and is able to decode the color of pal, secam and ntsc signals into itu-601 compatible color component values. the saf7115 accepts cvbs or s-video (y/c) from tv or vcr sources as analog inputs, including weak and distorted signals. the expansion port (x-port) for digital video (bi-directional half duplex, d1 compatible) can be used to either output unscaled video using 10-bit or 8-bit dithered resolution or to connect to other external digital video sources for reuse of the saf7115 scaler features. the enhanced image port (i-port) of the saf7115 supports 8-bit and 16-bit wide output data with auxiliary reference data for interfacing, e.g. with vga controller applications. it is also possible to output video in square pixel formats accompanied by a square pixel clock of the appropriate frequency. the saf7115 also incorporates provisions for capturing the serially coded data in the vertical blanking interval (vbi-data) of several standards in parallel. three basic options are available to transfer the vbi data to other devices: ? capturing raw video samples, after interpolation to the required output data rate, using the scaler and transferring the data to a device connected to the i-port ? slicing the vbi data using the built-in vbi data slicer (data recovery unit) and transferring the data to a device connected to the i-port ? slicing the vbi data using the built-in vbi data slicer and reading out the sliced data through the i 2 c-bus (for several slow vbi data type standards only) saf7115 multistandard video decoder with super-adaptive comb ?lter, scaler and vbi data read-back via i 2 c-bus rev. 01 15 october 2008 product data sheet
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 2 of 35 nxp semiconductors saf7115 multistandard video decoder the saf7115 incorporates a frame locked audio clock generation. this function ensures that there is always the same number of audio samples associated with a frame, or a set of ?elds. this prevents the loss of synchronization between video and audio, during capture or playback. furthermore, there is an option to use a second analog onboard pll to enhance this audio clock to a low jitter frame locked audio clock. the saf7115 is controlled through the i 2 c-bus with full write/read capability for all programming registers and a bit-rate of up to 400 kbit/s. see ref . 1 for a detailed register description, pin strapping and applications. 2. features 2.1 video acquisition n six analog inputs, internal analog source selectors, e.g. (6 cvbs) or (2 y/c and 2 cvbs) or (1 y/c and 4 cvbs) n two differential (bi-phase) video inputs as an alternative n two built-in analog anti-alias ?lters n two improved 9-bit cmos adcs in differential cmos style at two-fold itu-656 oversampling (27 mhz) n fully programmable static gain or automatic gain control (agc) for the selected cvbs or y/c channel n automatic clamp control (acc) for cvbs, y and c n switchable white peak control. two 9-bit video cmos adcs, digitized cvbs or y/c n signals are available on the expansion port (x-port) n requires only one crystal (32.11 mhz or 24.576 mhz) for all standards n independent gain and offset adjustments for raw data path 2.2 comb ?lter video decoder n digital pll for synchronization and clock generation from all standard and non-standard video sources e.g. consumer grade video tape recorders (vtr) n automatic detection of 50 hz and 60 hz ?eld frequencies n automatic recognition of all common broadcast standards n enhanced horizontal and vertical sync detection n luminance and chrominance signal processing for: u pal bgdhin u combination-pal n u pal m u ntsc m u ntsc-japan u ntsc 4.43 u secam (50 hz/60 hz) n pal delay line for correcting pal phase errors n improved 2/4-line comb ?lter for two dimensional chrominance/luminance-separation operating with adaptive comb ?lter parameters. u increased luminance and chrominance bandwidth for all pal and ntsc-standards u reduced cross color and cross luminance artefacts
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 3 of 35 nxp semiconductors saf7115 multistandard video decoder n independent brightness contrast saturation (bcs) - adjustment for decoder part n user programmable sharpness control n detection of copy protected input signals: u according to macrovision standard u indicating the level of protection n automatic tv/vcr detection n 10-bit wide video output at comb ?lter video decoder n x-port video output either as: u noise shaped 8-bit itu-656 video or u full 10-bit itu-656 interface (dc-performance 9-bit) 2.3 video scaler n horizontal and vertical down-scaling and up-scaling to randomly sized windows n horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: h and v zoom are restricted by the transfer data rates) n vertical scaling with linear phase interpolation and accumulating ?lter for anti-aliasing (6-bit phase accuracy) n conversion to square pixel format n generation of a video output stream with improved synchronization grid at the i-port n two independent programming sets for scaler part, to de?ne two regions (e.g. for different scaling for vbi and active picture) per ?eld or sequences over frames n fieldwise switching between decoder part and expansion port (x-port) input n brightness, contrast and saturation controls for scaled outputs 2.4 vbi data slicer n versatile vbi-data decoder, slicer, clock regeneration and byte synchronization, e.g.: u wst525/wst625 (ccst) u vps u us/european close caption (cc) u wss525 (cgms), wss625 u us nabts u vitc 525/vitc 625 u gemstar 1x u gemstar 2x u moji n i 2 c-bus read-back of the following decoded data types: u us close caption (cc) u european close caption (cc) u wss525 (cgms) u wss625 (cgms) u gemstar 1x u gemstar 2x
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 4 of 35 nxp semiconductors saf7115 multistandard video decoder 2.5 clock generation n on-chip line locked clock generation according itu-601 n generation of a frame locked audio master clock to support a constant number of audio clocks per video ?eld n second onboard analog phase-locked loop (pll) to be used for: u on-chip line locked square pixel clock generation for pal and ntsc square pixel video output or u the generation of a low jitter frame locked audio clock from the audio master clock through reuse of the analog square pixel pll. the audio clock frequencies supported are 256 f s , 384 f s and 512 f s (f s = 32 khz, 44.1 khz or 48 khz) 2.6 general features n cmos 3.3 v device with 5 v tolerant digital inputs and i/o ports n programming through serial i 2 c-bus, full read-back ability by an external controller, bit-rate up to 400 kbit/s n software controlled power saving stand-by modes n boundary scan test circuit complies to the ieee std. 1149.b1-1994 3. applications n general industrial video applications n in-car tv reception n in-car entertainment n in-car navigation platforms 4. ordering information table 1. ordering information type number package name description version SAF7115HW htqfp100 plastic thermal enhanced thin quad ?at package; 100 leads; body 14 14 1 mm; exposed die pad sot638-1 saf7115et tfbga160 plastic thin ?ne-pitch ball grid array package; 160 balls sot1016-1
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 5 of 35 nxp semiconductors saf7115 multistandard video decoder 5. block diagram fig 1. block diagram 001aag268 saf7115 analog dual adc frame locked audio clock pll programming register array boundary scan test a/b register mux pll2 audio clock generation cgc2 line fifo buffer video fifo video/text arbiter 32 to 8(16) mux text fifo x port i/o formatting rt out i/o control i 2 c-bus expansion port pin mapping clock generation and power-on control digital decoder with adaptive comb filter fir prefilter prescaler and scaler bcs vertical scaling horizontal fine (phase) scaling general purpose vbi data slicer event controller image port mapping ipd[7:0] idq igph igpv igp0 igp1 itrdy itri iclk test[9:0] xtri xrdy xrv ai11 agnd ai12 ai21 ai22 ai23 ai24 aout ai1d ai2d reso_n ce xtout xtali xtalo rts1 rts0 rtc0 llc2 llc xpd[7:0] xrh xdq xclk sda hpd[7:0] scl tdo alrclk amclk asclk axmclk v ssa(xtal) v dda(xtal) v ssa v ssd(io) v ssd(core) v dda2 v dda1 v dda0 v ddd(io) v ddd(core) tdi tms tck trst_n pulse generator
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 6 of 35 nxp semiconductors saf7115 multistandard video decoder 6. pinning information 6.1 pinning a. htqfp100 b. tfbga160 fig 2. pin con?guration SAF7115HW 75 26 50 100 76 51 1 25 001aag269 001aah235 saf7115et transparent top view n p m l k j h f d g e c b a ball a1 index area 24681012 13579111314 table 2. pin allocation table (htqfp100) pin symbol pin symbol pin symbol pin symbol 1v ddd(io) 2 tdo [1] 3 tdi [1] 4 xtout 5v ssa(xtal) 6 xtalo 7 xtali 8 v dda(xtal) 9v ssa 10 ai24 11 v dda2 12 ai23 13 ai2d 14 ai22 15 v ssa 16 ai21 17 v dda1 18 ai12 19 ai1d 20 ai11 21 agnd 22 aout 23 v dda0 24 v ssa 25 v ddd(io) 26 v ssd(io) 27 ce 28 llc 29 llc2 30 reso_n 31 scl 32 sda 33 v ddd(core) 34 rts0 35 rts1 36 rtco [1] 37 amclk 38 v ssd(core) 39 asclk 40 alrclk 41 amxclk 42 itrdy 43 v ddd(core) 44 test0 45 iclk 46 idq 47 itri 48 igp0 49 igp1 50 v ssd(io) 51 v ddd(io) 52 igpv 53 igph 54 ipd7 55 ipd6 56 ipd5 57 ipd4 58 v ddd(core) 59 ipd3 60 ipd2 61 ipd1 62 ipd0 63 v ssd(core) 64 hpd7 65 hpd6 66 hpd5 67 hpd4 68 v ddd(core) 69 hpd3 70 hpd2 71 hpd1 72 hpd0 73 test1 74 test2 75 v ddd(io) 76 v ssd(io)
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 7 of 35 nxp semiconductors saf7115 multistandard video decoder [1] see t ab le 4 . 77 test3 78 test4 79 test5 80 xtri 81 xpd7 82 xpd6 83 v ddd(core) 84 xpd5 85 xpd4 86 xpd3 87 xpd2 88 v ssd(core) 89 xpd1 90 xpd0 91 xrv 92 xrh 93 v ddd(core) 94 xclk 95 xdq 96 xrdy 97 trst_n [1] 98 tck [1] 99 tms [1] 100 v ssd(io) table 3. pin allocation table (tfbga160) [1] pin symbol pin symbol pin symbol pin symbol row a a1 v ddd(io) a2 tms [2] a3 trst_n [2] a4 xrdy a5 xclk a6 xrh a7 xpd0 a8 v ssd(core) a9 xpd3 a10 xpd5 a11 xpd6 a12 xtri a13 test4 a14 v ddd(io) -- -- row b b1 xtout b2 tdo [2] b3 tck [2] b4 xdq b5 v ddd(core) b6 xrv b7 xpd1 b8 xpd2 b9 xpd4 b10 v ddd(core) b11 xpd7 b12 test5 b13 test2 b14 test3 - - - - row c c1 xtalo c2 tdi [2] c13 hpd0 c14 test1 row d d1 xtali d2 v ssa(xtal) d4 v ssd(io) d5 v ssd(io) d6 v ssd(io) d7 v ssd(io) d8 v ssd(io) d9 v ssd(io) d10 v ssd(io) d11 v ssd(io) d13 hpd2 d14 hpd1 row e e1 v dda(xtal) e2 v ssa e4 v ssd(io) e5 v ssd(io) e6 v ssd(io) e7 v ssd(io) e8 v ssd(io) e9 v ssd(io) e10 v ssd(io) e11 v ssd(io) e13 v ddd(core) e14 hpd3 row f f1 v dda2 f2 ai24 f4 v ssd(io) f5 v ssd(io) f6 v ssd(io) f7 v ssd(io) f8 v ssd(io) f9 v ssd(io) f10 v ssd(io) f11 v ssd(io) f13 hpd5 f14 hpd4 row g g1 ai23 g2 ai2d g4 v ssd(io) g5 v ssd(io) g6 v ssd(io) g7 v ssd(io) g8 v ssd(io) g9 v ssd(io) g10 v ssd(io) g11 v ssd(io) g13 hpd7 g14 hpd6 row h h1 ai22 h2 v ssa h4 v ssd(io) h5 v ssd(io) h6 v ssd(io) h7 v ssd(io) h8 v ssd(io) h9 v ssd(io) table 2. pin allocation table (htqfp100) continued pin symbol pin symbol pin symbol pin symbol
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 8 of 35 nxp semiconductors saf7115 multistandard video decoder [1] i.c.: internally connected; do not connect [2] see t ab le 4 . 6.2 pin description h10 v ssd(io) h11 v ssd(io) h13 ipd0 h14 v ssd(core) row j j1 ai21 j2 v dda1 j4 v ssd(io) j5 v ssd(io) j6 v ssd(io) j7 v ssd(io) j8 v ssd(io) j9 v ssd(io) j10 v ssd(io) j11 v ssd(io) j13 ipd2 j14 ipd1 row k k1 ai12 k2 ai1d k4 v ssd(io) k5 v ssd(io) k6 v ssd(io) k7 v ssd(io) k8 v ssd(io) k9 v ssd(io) k10 v ssd(io) k11 v ssd(io) k13 v ddd(core) k14 ipd3 row l l1 ai11 l2 agnd l4 test6 l5 test7 l6 v ssd(io) l7 v ssd(io) l8 v ssd(io) l9 v ssd(io) l10 test8 l11 test9 l13 ipd5 l14 ipd4 row m m1 aout m2 v dda0 m13 ipd7 m14 ipd6 row n n1 v ssa n2 ce n3 llc2 n4 scl n5 v ddd(core) n6 rts1 n7 amclk n8 asclk n9 amxclk n10 v ddd(core) n11 iclk n12 itri n13 igp1 n14 igph - - - - row p p1 v ddd(io) p2 llc p3 reso_n p4 sda p5 rts0 p6 rtco [2] p7 v ssd(core) p8 alrclk p9 itrdy p10 test0 p11 idq p12 igp0 p13 igpv p14 v ddd(io) -- -- table 3. pin allocation table (tfbga160) [1] continued pin symbol pin symbol pin symbol pin symbol table 4. pin description symbol pin type [1] description htqfp100 tfbga160 supplies (analog) v dda0 23 m2 p analog supply voltage 0 [2] v dda1 17 j2 p analog supply voltage 1 [3] v dda2 11 f1 p analog supply voltage 2 [4] v dda(xtal) 8 e1 p crystal analog supply voltage v ssa 9, 15 and 24 e2, h2 and n1 p analog ground supply voltage v ssa(xtal) 5 d2 p crystal analog ground supply voltage
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 9 of 35 nxp semiconductors saf7115 multistandard video decoder supplies (digital) v ddd(io) 1, 25, 51 and 75 a1, a14, p1 and p14 p i/o digital supply voltage v ddd(core) 33, 43, 58, 68, 83 and 93 b5, b10, e13, k13, n5 and n10 p core digital supply voltage v ssd(core) 38, 63 and 88 a8, h14 and p7 p core digital ground supply voltage v ssd(io) 26, 50, 76 and 100 d4 to d11, e4 to e11, f4 to f11, g4 to g11, h4 to h11, j4 to j11, k4 to k11 and l6 to l9 p i/o digital ground supply voltage analog inputs agnd 21 l2 p analog signal ground reference for all aix inputs ai21 16 j1 ai analog input 21 ai22 14 h1 ai analog input 22 ai23 12 g1 ai analog input 23 ai24 10 f2 ai analog input 24 ai2d 13 g2 ai differential input for adc channel 2 (pins ai24, ai23, ai22 and ai21) [5] ai11 20 l1 ai analog input 11 ai12 18 k1 ai analog input 12 ai1d 19 k2 ai differential input for adc channel 1 (pins ai12 and ai11) [5] analog output aout 22 m1 ao analog test output (do not connect) i 2 c-bus scl 31 n4 i (/o)/od serial clock input (/output) with inactive output path sda 32 p4 i (/o)/od serial data input (/output) general control ce 27 n2 i/pu chip enable or reset input (with internal pull-up) reso_n 30 p3 o reset output (active low) audio clock alrclk 40 p8 (i/) o/st/pd audio left/right clock output: can be strapped to supply through a 3.3 k w resistor indicating that the default 24.576 mhz crystal (internal pull-down) has been replaced by a 32.11 mhz crystal amclk 37 n7 o audio master clock output amxclk 41 n9 i audio master external clock input asclk 39 n8 o audio serial clock output table 4. pin description continued symbol pin type [1] description htqfp100 tfbga160
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 10 of 35 nxp semiconductors saf7115 multistandard video decoder real time signals rtco 36 p6 (i/) o/st/pd real time control output [6] rts1 35 n6 o real time status or sync information, controlled by subaddresses 11h and 12h rts0 34 p5 o real time status or sync information, controlled by subaddresses 11h and 12h clocks llc 28 p2 o line-locked system clock output (27 mhz nominal), for backward compatibility; use pin xclk for new applications llc2 29 n3 o line locked 1/2 clock output (13.5 mhz nominal) for backward compatibility; do not use for new applications xtali 7 d1 i input terminal for 24.576 mhz (32.11 mhz) crystal oscillator or connection of external oscillator with ttl compatible square wave clock signal xtalo 6 c1 o 24.576 mhz (32.11 mhz) crystal oscillator output; not connected if pin xtali is driven by an external single-ended oscillator xtout 4 b1 o crystal oscillator output signal, auxiliary signal boundary scan test tck 98 b3 i/pu test clock for boundary scan test (with internal pull-up) [7] tdi 3 c2 i/pu test data input for boundary scan test (with internal pull-up) [7] tdo 2 b2 o test data output for boundary scan test [7] tms 99 a2 i/pu test mode select for boundary scan test or scan test (with internal pull-up) [8] trst_n 97 a3 i/pu test reset for boundary scan test (active low with internal pull-up); for board design without boundary scan connect trst_n to ground, e.g. through v ssd(core) or v ssd(io) [8] test interface test9 - l11 i/pd do not connect, reserved for future extensions and for testing test8 - l10 ai do not connect, reserved for future extensions and for testing test7 - l5 ai do not connect, reserved for future extensions and for testing test6 - l4 i/pu do not connect, reserved for future extensions and for testing test5 79 b12 i/pu do not connect, reserved for future extensions and for testing test4 78 a13 o do not connect, reserved for future extensions and for testing test3 77 b14 i/pu do not connect, reserved for future extensions and for testing test2 74 b13 i/pu do not connect, reserved for future extensions and for testing test1 73 c14 i/pu do not connect, reserved for future extensions and for testing test0 44 p10 o do not connect, reserved for future extensions and for testing image port (i-port) iclk 45 n11 i/o clock output signal for image port or optional asynchronous back end clock input idq 46 p11 o output data quali?er for image port (optional: gated clock output) igp1 49 n13 o general purpose output signal 1; image port (controlled by subaddresses 84h and 85h); same functions as pin igp0 table 4. pin description continued symbol pin type [1] description htqfp100 tfbga160
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 11 of 35 nxp semiconductors saf7115 multistandard video decoder igp0 48 p12 o general purpose output signal 0; image port (controlled by subaddresses 84h and 85h) igph 53 n14 o multipurpose horizontal reference output signal; image port (controlled by subaddresses 84h and 85h) igpv 52 p13 o multipurpose vertical reference output signal; image port (controlled by subaddresses 84h and 85h) ipd7 54 m13 o msb of image port data output ipd6 55 m14 o msb - 1 of image port data output ipd5 56 l13 o msb - 2 of image port data output ipd4 57 l14 o msb - 3 of image port data output ipd3 59 k14 o msb - 4 of image port data output ipd2 60 j13 o msb - 5 of image port data output ipd1 61 j14 o msb - 6 of image port data output ipd0 62 h13 o lsb of image port data output itrdy 42 p9 i/pu target ready input, image port (with internal pull-up) itri 47 n12 i (/o)/pd image port output control signal, affects all i-port pins including iclk, enable and active polarity is under software control (bits ipe in subaddress 87h) output path used for testing: scan output expansion port (x-port) xclk 94 a5 i/o clock i/o expansion port xdq 95 b4 i/o data quali?er i/o expansion port xpd7 81 b11 i/o msb of expansion-port data: in 8-bit video output mode: this signal represents the video bit 7; in 10-bit video output mode: this signal represents the video bit 9 xpd6 82 a11 i/o msb - 1 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 6; in 10-bit video output mode: this signal represents the video bit 8 xpd5 84 a10 i/o msb - 2 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 5; in 10-bit video output mode: this signal represents the video bit 7 xpd4 85 b9 i/o msb - 3 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 4; in 10-bit video output mode: this signal represents the video bit 6 xpd3 86 a9 i/o msb - 4 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 3; in 10-bit video output mode: this signal represents the video bit 5 xpd2 87 b8 i/o msb - 5 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 2; in 10-bit video output mode: this signal represents the video bit 4 xpd1 89 b7 i/o msb - 6 of expansion-port data: in 8-bit video output mode: this signal represents the video bit 1; in 10-bit video output mode: this signal represents the video bit 3 xpd0 90 a7 i/o expansion-port data: in 8-bit video output mode: this signal represents the video bit 0 (lsb); in 10-bit video output mode: this signal represents the video bit 2 table 4. pin description continued symbol pin type [1] description htqfp100 tfbga160
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 12 of 35 nxp semiconductors saf7115 multistandard video decoder [1] a = analog, i = input, o = output, p = power, st = strapping, pu = pull-up, pd = pull-down, od = open-drain. [2] for cgc1 and cgc2. [3] for analog inputs ai1x. [4] for analog inputs ai2x. [5] for normal operation connect pins ai1d and ai2d to ground through a capacitor. in principle both analog input stages can ope rate in differential mode, too, depending on the application. this may be interesting for differential video (cvbs). please contact nxp for more information. [6] this contains information about actual system clock frequency, ?eld rate, odd/even sequence, decoder status, subcarrier phas e and frequency and pal sequence (according to rtc level 3.1, refer to external document rtc functional speci?cation for details), can be strapped to supply through a 3.3 k w resistor to change the default i 2 c-bus read and write addresses from 42h and 43h (internal pull-down) to 40h and 41h. [7] according to the ieee1149.b1-1994 standard pins tdi and tms are input pins with an internal pull-up transistor and tdo is a 3-state output pin. pins tck and trst_n are also built with internal pull-up. [8] this pin provides easy initialization of bst circuitry. pin trst_n can be used to force the test access port (tap) controlle r to the test-logic-reset state (normal operation) at once. xrdy 96 a4 o task ?ag or read signal from scaler, controlled by bit xrqt (subaddress 83h) xrh 92 a6 i/o horizontal reference i/o expansion-port: in 10-bit video output mode: this signal represents the video bit 1 xrv 91 b6 i/o vertical reference i/o expansion-port: in 10-bit video output mode: this signal represents the video bit 0 (lsb) xtri 80 a12 i/pd x-port output control signal, affects all x-port pins (xpd[7:0], xrh, xrv, xdq and xclk) enable and active polarity is under software control (bits xpe in subaddress 83h) host port (h-port) hpd7 64 g13 i/o msb of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd6 65 g14 i/o msb - 1 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd5 66 f13 i/o msb - 2 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd4 67 f14 i/o msb - 3 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd3 69 e14 i/o msb - 4 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd2 70 d13 i/o msb - 5 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd1 71 d14 i/o msb - 6 of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes hpd0 72 c13 i/o lsb of host port data i/o, carries cbcr chrominance information in 16-bit video i/o modes table 4. pin description continued symbol pin type [1] description htqfp100 tfbga160
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 13 of 35 nxp semiconductors saf7115 multistandard video decoder 7. limiting values [1] condition for maximum voltage at digital inputs or i/o pins: 3.0 v < v ddd < 3.6 v. [2] class 2 according to eia/jesd22-114 . [3] class c3b according to aec-q100-011 . 8. thermal characteristics [1] the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly and use maximum areas for power and ground planes in the application pcb. in order to meet the speci?ed r th(j-a) value the exposed die pad of the package has to be soldered directly to the ground layer of the application pcb. [2] the overall r th(j-a) value can vary depending on the board layout. to minimize the effective r th(j-a) all power and ground pins must be connected to the power and ground layers directly and use maximum areas for power and ground planes in the application pcb. the r th(j-a) value is calculated for a 4 layer pcb (100 100 mm 2 ) with at least 50 plated through-hole-vias at the center of the package (large ground area). this calculation assumes 80 % coverage for power and ground metal layers and a natural convection ?ow at top and bottom sides of the pcb. maximum ball temperature then is 110 c, assuming ambient temperature t amb(max) = 85 c. table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). all ground pins connected together and grounded (0 v); all supply pins connected together. symbol parameter conditions min max unit v dda0 analog supply voltage 0 for cgc1 and cgc2 - 0.5 +4.6 v v dda1 analog supply voltage 1 for analog inputs ai1x - 0.5 +4.6 v v dda2 analog supply voltage 2 for analog inputs ai2x - 0.5 +4.6 v v dda(xtal) crystal analog supply voltage - 0.5 +4.6 v v ddd(core) core digital supply voltage - 0.5 +4.6 v v ddd(io) i/o digital supply voltage - 0.5 +4.6 v v i(a) analog input voltage - 0.5 +4.6 v v i input voltage at pins xtali, sda and scl - 0.5 v ddx + 0.5 v v i(d) digital input voltage outputs in 3-state - 0.5 +4.6 v [1] - 0.5 +5.5 v d v ss ground supply voltage difference - 100 mv t stg storage temperature - 65 +150 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage human body model, all pins [2] - 2000 v charged device model, corner pins [3] - 750 v charged device model, all other pins [3] - 500 v table 6. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air saf7115et [1] 23 k/w SAF7115HW [2] 35 k/w
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 14 of 35 nxp semiconductors saf7115 multistandard video decoder 9. characteristics table 7. characteristics v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in figure 3 and figure 4 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit supplies v dda0 analog supply voltage 0 for cgc1 and cgc2 3.1 3.3 3.5 v v dda1 analog supply voltage 1 for analog inputs ai1x 3.1 3.3 3.5 v v dda2 analog supply voltage 2 for analog inputs ai2x 3.1 3.3 3.5 v v dda(xtal) crystal analog supply voltage 3.1 3.3 3.5 v v ddd(core) core digital supply voltage 3.0 3.3 3.6 v v ddd(io) i/o digital supply voltage 3.0 3.3 3.6 v i dda analog supply current v ddax = 3.3 v; bits aosl1 and aosl0 = 0b [1] cvbs mode - 81 - ma y/c mode - 142 - ma i ddd digital supply current x-port 3-state; 8-bit i-port out - 108 - ma p power dissipation digital part; open pin aout - 356 - mw analog part; v ddax = 3.3 v cvbs mode - 267 - mw y/c mode - 468 - mw analog and digital parts cvbs mode - 623 - mw y/c mode - 825 - mw power-down mode [2] -7- mw power-save mode [3] - 115 - mw analog part v i(p-p) peak-to-peak input voltage for normal video levels 1 v (p-p), - 3db termination 18 w to 56 w and ac coupling required; coupling capacitor is 47 nf - 0.7 - v i cl clamping current v i =1vdc - 8- m a | z i | input impedance clamping current off 200 - - k w c i input capacitance - - 10 pf a cs channel separation f i < 5 mhz - - - 50 db 9-bit analog-to-digital converters b bandwidth at - 3 db - 7 - mhz j dif differential phase ampli?er plus anti-alias ?lter bypassed - 2 - deg
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 15 of 35 nxp semiconductors saf7115 multistandard video decoder g dif differential gain ampli?er plus anti-alias ?lter bypassed -2- % f clk(adc) adc clock frequency 25.4 - 28.6 mhz dle dc dc differential linearity error - 0.7 - lsb ile dc dc integral linearity error - 1 - lsb d g adc adc gain difference [4] -3- % digital inputs v il low-level input voltage pins scl and sda [5] - 0.5 - +0.3 v cc(i2c-bus) v any other pin, including pin xtali [5] - 0.3 - +0.8 v v ih high-level input voltage pins scl and sda [5] 0.7 v cc(i2c-bus) -v cc(i2c-bus) + 0.5 v pin xtali 2.0 - v dda(xtal) + 0.3 v any other pin 2.0 - 5.5 v i li input leakage current - - 1 m a i l(i/o) leakage current (i/o) - - 10 m a c i input capacitance i/o at high-impedance - - 8 pf digital outputs [6] v ol low-level output voltage pin sda at 3 ma sink current - - 0.4 v all digital clocks 0 - 0.6 v for all other digital outputs 0 - 0.4 v v oh high-level output voltage all digital output pins 2.4 - v ddd(io) + 0.5 v clock output timing (llc and llc2) [7] c o(l) output load capacitance 15 - 50 pf t cy cycle time pin llc 35 - 39 ns pin llc2 70 - 78 ns d duty cycle for t clkh /t cy ; c l = 40 pf 40 - 60 % t r rise time 0.2 v to v ddd(io) - 0.2 v - - 5 ns t f fall time v ddd(io) - 0.2 v to 0.2 v - - 5 ns t d delay time between llc and llc2: measured at 1.5 v; c l =25pf - 4+1+8 ns horizontal pll f hl(nom) nominal horizontal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f hl /f hl(nom) horizontal line frequency deviation - - 5.7 % table 7. characteristics continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in figure 3 and figure 4 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 16 of 35 nxp semiconductors saf7115 multistandard video decoder subcarrier pll f subc(nom) nominal subcarrier frequency pal bghi - 4433619 - hz ntsc m - 3579545 - hz pal m - 3575612 - hz pal n - 3582056 - hz d f subc(lock-in) subcarrier lock-in frequency 400 - - hz expansion port (x-port) output timing with xclk clock output c o(l) output load capacitance 15 - 50 pf t cy cycle time xclk output 35 - 39 ns d duty cycle for t xclkh /t cy 35 - 65 % t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns data and control signal output timing x-port including rt-port, related to xclk output (for xpck[1:0] 83h[5:4] = 01b) [7] c o(l) output load capacitance 15 - 50 pf t h(q) data output hold time [8] 2-- ns t pd propagation delay from positive edge of xclk output [8] - - 23 ns expansion port (x-port) input timing with xclk clock input t cy cycle time xclk input 31 - 45 ns d duty cycle for t xclkh /t cy 40 50 60 % t r rise time - - 5 ns t f fall time - - 5 ns data and control signal input timing x-port, related to xclk input (for xpck[1:0] 83h[5:4] = 11b); t su(d) data input set-up time [9] 6-- ns t h(d) data input hold time [9] --6 ns t h(q) data output hold time [10] -3- ns t pd propagation delay from positive edge of xclk input [10] -23- ns image port (i-port) output timing with iclk clock output c o(l) output load capacitance 15 - 50 pf t cy cycle time 31 - 90 ns d duty cycle for t iclkh /t cy ; c l =40pf 35 - 65 % t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns image port (i-port) output timing with iclk clock input t cy cycle time 31 - 100 ns d duty cycle for t iclkh /t cy 40 50 60 % table 7. characteristics continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in figure 3 and figure 4 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 17 of 35 nxp semiconductors saf7115 multistandard video decoder [1] this setting connects pin aout to ground. [2] controlled through chip enable input (ce) from normal operation mode at typical supply voltage of v ddd =v dda = 3.3 v. [3] i 2 c-bus controlled through subaddress 88h set to xx00 1011b. [4] the adc gain difference is . [5] v cc(i2c-bus) is the external supply voltage of the i 2 c-bus (3.3 v or 5 v). [6] the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l =50pf. [7] the effects of rise and fall times are included in the calculation of t h(q) and t pd . timings and levels refer to drawings and conditions illustrated in figure 3 and figure 4 . [8] valid for outputs: xpd [7:0], xrh, xrv, xdq, rts0, rts1, rtco [9] valid for inputs: xpd [7:0], hpd [7:0], xrh, xrv, xdq [10] valid for output: xrdy [11] valid for outputs: ipd [7:0], hpd [7:0], igph, igpv, idq, igp1, igp0 [12] valid for input: itrdy t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns data and control signal output timing i-port, related to iclk output (for ipck[1:0] 87h[5:4] = 11b) c o(l) output load capacitance at all outputs 15 - 50 pf t h(q) data output hold time [11] 3-- ns t pd propagation delay [11] - - 23 ns data and control signal input timing i-port, related to iclk output (for ipck[1:0] 87h[5:4] = 11b) t su(d) data input set-up time [12] 18 - - ns t h(d) data input hold time [12] -- - 2ns data and control signal output timing i-port, related to iclk input (for ipck[1:0] 87h[5:4] = 11b) c o(l) output load capacitance at all outputs 15 - 50 pf t h(q) data output hold time [11] 3-- ns t pd propagation delay from positive edge of llc output [11] - - 23 ns data and control signal input timing i-port, related to iclk input (for ipck[1:0] 87h[5:4] = 01b) t su(d) data input set-up time [12] 12 - - ns t h(d) data input hold time [12] --2 ns amclk clock output c o(l) output load capacitance 15 - 50 pf t r rise time 0.6 v to 2.6 v - - 5 ns t f fall time 2.6 v to 0.6 v - - 5 ns table 7. characteristics continued v ddd = 3.0 v to 3.6 v; v dda = 3.1 v to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in figure 3 and figure 4 ; unless otherwise speci?ed. symbol parameter conditions min typ max unit d g adc maximum deviation minimum deviation ----------------------------------------------- - 1 C ? ?? 100 =
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 18 of 35 nxp semiconductors saf7115 multistandard video decoder (1) see t ab le 7 . (2) see t ab le 7 . fig 3. x-port input and output timing (1) see t ab le 7 . fig 4. i-port output timing, also valid for ix-port and h-port 001aae770 t xclkh t r t f t h(d) t su(d) t cy clock output xclk data and control inputs (x port) (1) data and control outputs x port (2) 2.6 v 0.6 v 1.5 v 2.0 v 0.8 v t h(q) t pd 2.4 v 0.6 v not valid 001aae771 t iclkh t r t f t cy clock input or output iclk data and control outputs i port (1) 2.6 v 0.6 v 1.5 v t h(q) t pd 2.4 v 0.6 v
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 19 of 35 nxp semiconductors saf7115 multistandard video decoder [1] the crystal oscillator drive level is typical 0.28 mw. [2] effect from c 0 excluded. table 8. typical external fundamental crystal characteristics (see section 10.1 ) symbol parameter conditions min typ max unit crystal oscillator for 32.11 mhz [1] f xtal(nom) nominal crystal frequency 3rd harmonics - 32.11 - mhz d f/f xtal(nom) nominal crystal frequency deviation -- 100 ppm crystal speci?cation (x1) c l load capacitance 3rd harmonics [2] --8 pf fundamental [2] --8 pf r s series resistance 3rd harmonics - 50 w fundamental - - 60 w c 0 shunt capacitance 3rd harmonics - - 4.3 pf fundamental - - 3.3 pf crystal oscillator for 24.576 mhz [1] f xtal(nom) nominal crystal frequency 3rd harmonics - 24.576 - mhz d f/f xtal(nom) nominal crystal frequency deviation -- 70 ppm crystal speci?cation (x1) c l load capacitance 3rd harmonics [2] - - 10 pf fundamental [2] - - 20 pf r s series resistance 3rd harmonics - 40 80 w fundamental - - 60 w c 0 shunt capacitance 3rd harmonics - - 3.5 pf fundamental - - 7 pf
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 20 of 35 nxp semiconductors saf7115 multistandard video decoder 10. application information 10.1 oscillator applications 10.1.1 generic oscillator applications figure 5 shows the generic oscillator circuit with quartz crystals and with direct clock input. t ab le 9 shows con?guration examples for different quartz crystals. [1] see t ab le 8 . [2] see section 10.1.2 . 10.1.2 fundamental quartz crystals with restricted drive level leave out l and c 1 when using fundamental quartz crystal and restricted drive level (see section 10.1.1 ). use a series resistance r s at pin xtalo, when the internal oscillator of the saf7115 provides too much power p drive to the selected quartz crystal. note that the decreased crystal amplitude results in a lower drive level, but on the other hand the jitter performance will decrease. 10.2 pcb layout guidelines for oscillator applications place the quartz crystal on the pcb as close to pins xtali and xtalo as possible to minimize susceptibility to noise from current loops. minimize parasitic capacitances. a. generic oscillator circuit b. with direct clock. fig 5. oscillator applications (see t ab le 9 ) c 2 c 3 r s c 1 l d1 (7) xtali xtalo c1 (6) f xtal(nom) saf7115 001aah884 001aah706 d1 (7) xtali xtalo n.c. clock 32.11 mhz or 24.576 mhz c1 (6) saf7115 table 9. con?guration examples quartz crystal (see figure 5 ) example quartz crystal [1] oscillator circuit type f xtal(nom) (mhz) c l (pf) l ( m h) c 1 (nf) c 2 (pf) c 3 (pf) r s ( w ) [2] 1 3rd harmonic 32.11 8 4.7 1 15 15 0 2 3rd harmonic 24.576 8 4.7 1 18 18 0 3 fundamental 32.11 20 none none 33 33 0 4 fundamental 32.11 8 none none 10 10 0 5 fundamental 24.576 8 none none 15 15 0
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 21 of 35 nxp semiconductors saf7115 multistandard video decoder 11. test information 11.1 quality information this product has been quali?ed in accordance with the automotive electronics council (aec) standard q100 - stress test quali?cation for integrated circuits , and is suitable for use in automotive applications. 11.2 boundary scan test the saf7115 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the saf7115 follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag). the 5 dedicated pins are test mode select (tms), test clock (tck), test reset (trst_n), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, sample, clamp and idcode are all supported (see t ab le 10 ). details about the jtag bst-test can be found in speci?cation ieee std. 1149.1 . 11.2.1 initialization of boundary scan circuit the test access port (tap) controller of an ic should be in the reset state (test_logic_reset) when the ic is in the functional mode. the reset state also forces the instruction register into a functional instruction such as idcode or bypass. to compensate for the power-up reset, the standard speci?es that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trst_n pin low. table 10. bst instructions supported by the saf7115 instruction description bypass this mandatory instruction provides a minimum length serial path (1-bit) between tdi and tdo when no test operation of the component is required extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component; it can also be used to preload data values into the latched outputs of the boundary scan register clamp this optional instruction is useful for testing when not all ics have bst; this instruction addresses the bypass register while the boundary scan register is in external test mode idcode this optional instruction will provide information on the components manufacturer, part number and version number
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 22 of 35 nxp semiconductors saf7115 multistandard video decoder 11.2.2 device identi?cation codes a device identi?cation register is speci?ed in ieee std. 1149.1b-1994 . it is a 32-bit register which contains ?elds for the speci?cation of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and the determination of the version number of ics during ?eld service. when the idcode instruction is loaded into the bst instruction register, the identi?cation register will be connected between tdi and tdo of the ic. the identi?cation register will load a component speci?c code during the capture_data_register state of the tap controller and this code can be subsequently shifted out. this code can be used at board level to verify component manufacturer, type and version number. the device identi?cation register contains 32 bits, numbered 31 to 0, where bit 31 is the most signi?cant bit (nearest to tdi) and bit 0 is the least signi?cant bit (nearest to tdo); see figure 6 . fig 6. 32 bits of identi?cation code 001aag284 nnnn 0111 0001 0001 0101 00000010101 4-bit version code 16-bit part number 11-bit manufacturer identification 1 31 msb tdo 27 11 1 lsb tdi 12 28 0
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 23 of 35 nxp semiconductors saf7115 multistandard video decoder 12. package outline fig 7. package outline htqfp100 (sot638-1) unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 ms-026 03-04-07 05-02-02 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e q e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 24 of 35 nxp semiconductors saf7115 multistandard video decoder fig 8. package outline tfbga160 (sot1016-1) references outline version european projection issue date iec jedec jeita sot1016-1 - - - sot1016-1 07-06-20 07-07-27 unit a max mm 1.2 0.4 0.3 0.80 0.65 12.1 11.9 12.1 11.9 0.8 10.4 0.15 0.05 0.1 a 1 dimensions (mm are the original dimensions) tfbga160: plastic thin fine-pitch ball grid array package; 160 balls b a e 2 0 5 10 mm scale a 2 b 0.5 0.4 d e e e 1 e 2 10.4 v w y 0.08 y 1 a a 1 d e a b c d e f h k g j l m n p 24681012 1357911 14 13 ball a1 index area e e e 1 a c b ? v m c ? w m c y c y 1 x detail x b ball a1 index area 1/2 e 1/2 e a 2
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 25 of 35 nxp semiconductors saf7115 multistandard video decoder 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 26 of 35 nxp semiconductors saf7115 multistandard video decoder 13.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 9 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 11 and 12 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 9 . table 11. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 12. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 27 of 35 nxp semiconductors saf7115 multistandard video decoder for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 14. abbreviations msl: moisture sensitivity level fig 9. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 13. abbreviations acronym description acc automatic clamp control adc analog-to-digital converter aec automotive electronic council agc automatic gain control bcs brightness contrast saturation cc close caption ccst chinese character system teletext cgc clock generation circuit cgms copy generation management system cmos complementary mos cvbs composite video blanking sync [1] dc directed current eia electronic industries alliance esd electrostatic discharge fifo first in first out ic integrated circuit i 2 c-bus inter-ic-bus ieee institute of electrical and electronics engineers i/o input/output
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 28 of 35 nxp semiconductors saf7115 multistandard video decoder [1] cvbs is also known as composite video signal. 15. glossary arbiter electronic means to allocate access to shared resources. h-port digital host port for cbcr video input or output. i-port digital image port for scaled video data output. macrovision copy protection the saf7115 includes macrovision detection only. moji japanese teletext. moji means character. x-port digital video expansion port (x-port), for unscaled digital video input and output. y/c luminance and separated modulated chrominance video signal. ycbcr digital color coding format. itu international telecommunication union jtag joint test action group llc line-locked clock lsb least signi?cant bit mos metal-oxide-semiconductors msb most signi?cant bit mux multiplexer nabts north-american broadcast text system ntsc national television systems committee pal phase alternating line pcb printed circuit board pll phase-locked loop rt real time rtc real time control secam systeme electronique coleur avec mmoire (french color tv standard) smd surface mount device tap test access port ttl transistor-transistor logic tv television us united states of america vbi vertical blanking interval vcr video cassette recorder vga video graphics array vitc vertical interval time code vps video program system vtr video tape recorder wss wide screen signalling wst world system teletext table 13. abbreviations continued acronym description
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 29 of 35 nxp semiconductors saf7115 multistandard video decoder 16. references [1] saf7115 user manual ; please contact your local sales of?ce (see section 19 ). 17. revision history table 14. revision history document id release date data sheet status change notice supersedes saf7115_1 20081015 product data sheet - -
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 30 of 35 nxp semiconductors saf7115 multistandard video decoder 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 18.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 18.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 licenses 18.5 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 19. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation. purchase of nxp ics with macrovision copyright protection technology this product incorporates copyright protection technology that is protected by claims of u.s. patent nos. 5583936, 6516132, 6836549, 7050698 (encoder devices) or u.s. patent no. 6600873 (detection devices) and other intellectual property rights owned by macrovision corporation and other rights owners. the encoder devices may only be purchased by buyers who, according to information supplied by macrovision corporation to nxp semiconductors, have a valid license obtained from macrovision corporation, 2830 de la cruz boulevard, santa clara ca 95050, usa. tel: +1 (408) 562-8400, fax: +1 (408) 567-1800. use of this copyright protection technology is intended for home and other limited viewing uses only, unless otherwise authorized by macrovision corporation. reverse engineering or disassembly is prohibited.
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 31 of 35 continued >> nxp semiconductors saf7115 multistandard video decoder 20. index a abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 adaptive comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9 analog part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 analog supply voltages . . . . . . . . . . . . . . . . . . . . . . . . .8, 14 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . .14 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 audio clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2, 5, 9 automatic detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 automatic field detection . . . . . . . . . . . . . . . . . . . . . . . . . .2 automatic recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 b block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . .5, 10, 21 brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 broadcast standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 c chrominance/luminance separation . . . . . . . . . . . . . . . . . .1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 10 comb filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2 configuration examples quartz crystal . . . . . . . . . . . . . . .20 contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 conversion to square pixel format . . . . . . . . . . . . . . . . . . .3 crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 d data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 digital input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 15 digital output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 15 digital supply voltages . . . . . . . . . . . . . . . . . . . . . . . . .9, 14 direct clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 e expansion port . . . . . . . . . . . . . . . . . . .1, 2, 3, 5, 11, 16, 18 external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 f field detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23, 24 fundamental crystal . . . . . . . . . . . . . . . . . . . . . . . . . .19, 20 g gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 general control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 9 general industrial video applications . . . . . . . . . . . . . . . . . 4 h horizontal pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 host port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 12, 18 h-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 12, 18 i i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 5, 15 identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 image port . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 5, 10, 16, 18 in-car entertainment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 4 in-car navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 4 in-car tv reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 in-car video reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 9, 14 i-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 3, 5, 10, 16, 18 l line-locked clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5, 10 luminance and chrominance processing . . . . . . . . . . . . . 2 m multistandard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1, 2, 3 n navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 20 o ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 oscillator applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 p package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4, 6, 23, 24 pcb footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23, 24 pcb layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . 13, 20 performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 pin allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 pin types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 4, 5, 15, 16 programmable gain control . . . . . . . . . . . . . . . . . . . . . . . . 2 programmable sharpness control . . . . . . . . . . . . . . . . . . . 3 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 programming registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 programming set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 q quartz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19, 20 r read-back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3, 4
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 32 of 35 nxp semiconductors saf7115 multistandard video decoder real time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 4 recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 s saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3, 5 sharpness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 square pixel clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 square pixel format . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 3 subcarrier pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8, 14 t teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3, 5 test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5, 10 tv applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 tv standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 u user manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 v variable zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 vbi capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 vbi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 vbi data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 video acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 video applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 video capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 video processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 5 video reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 videotext . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 w wide screen signalling . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 world standard teletext . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 x x-port . . . . . . . . . . . . . . . . . . . . . . . . . . . .1, 2, 3, 11, 16, 18 z zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 33 of 35 nxp semiconductors saf7115 multistandard video decoder 21. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .4 table 2. pin allocation table (htqfp100) . . . . . . . . . . . .6 table 3. pin allocation table (tfbga160) [1] . . . . . . . . . .7 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 5. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .13 table 6. thermal characteristics . . . . . . . . . . . . . . . . . .13 table 7. characteristics . . . . . . . . . . . . . . . . . . . . . . . . .14 table 8. typical external fundamental crystal characteristics (see section 10.1 ) . . . . . . . . . .19 table 9. con?guration examples quartz crystal (see figure 5 ) . . . . . . . . . . . . . . . . . . . . . . . . .20 table 10. bst instructions supported by the saf7115 . .21 table 11. snpb eutectic process (from j-std-020c) . . .26 table 12. lead-free process (from j-std-020c) . . . . . .26 table 13. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 14. revision history . . . . . . . . . . . . . . . . . . . . . . . .29
saf7115_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 15 october 2008 34 of 35 nxp semiconductors saf7115 multistandard video decoder 22. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 fig 2. pin con?guration . . . . . . . . . . . . . . . . . . . . . . . . . .6 fig 3. x-port input and output timing . . . . . . . . . . . . . . .18 fig 4. i-port output timing, also valid for ix-port and h-port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 fig 5. oscillator applications (see t ab le 9 ) . . . . . . . . . .20 fig 6. 32 bits of identi?cation code. . . . . . . . . . . . . . . . .22 fig 7. package outline htqfp100 (sot638-1). . . . . . .23 fig 8. package outline tfbga160 (sot1016-1). . . . . .24 fig 9. temperature pro?les for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
nxp semiconductors saf7115 multistandard video decoder ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 october 2008 document identifier: saf7115_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 video acquisition. . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 comb ?lter video decoder. . . . . . . . . . . . . . . . . 2 2.3 video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 vbi data slicer. . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 clock generation. . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 general features . . . . . . . . . . . . . . . . . . . . . . . . 4 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 8 thermal characteristics. . . . . . . . . . . . . . . . . . 13 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 10 application information. . . . . . . . . . . . . . . . . . 20 10.1 oscillator applications. . . . . . . . . . . . . . . . . . . 20 10.1.1 generic oscillator applications . . . . . . . . . . . . 20 10.1.2 fundamental quartz crystals with restricted drive level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.2 pcb layout guidelines for oscillator applications. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 21 11.1 quality information . . . . . . . . . . . . . . . . . . . . . 21 11.2 boundary scan test. . . . . . . . . . . . . . . . . . . . . 21 11.2.1 initialization of boundary scan circuit . . . . . . . 21 11.2.2 device identi?cation codes . . . . . . . . . . . . . . . 22 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 13 soldering of smd packages . . . . . . . . . . . . . . 25 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 25 13.2 wave and re?ow soldering . . . . . . . . . . . . . . . 25 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 13.4 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 15 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 29 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 30 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 18.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.4 licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.5 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30 19 contact information . . . . . . . . . . . . . . . . . . . . 30 20 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 21 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 22 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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