MK1491-14 opti acpi firestar clock source mds 1491-14 b 1 revision 061801 integrated circuit systems, inc. ?525 race street ?san jose ?a ?5126 ?(408)295-9800tel ?www.icst.com block diagram description features the MK1491-14 is a low cost, low jitter, high performance clock synthesizer for opti? firestar and firestar+ chipsets for pentium processor-based mobile computer applications. using analog phase-locked loop (pll) techniques, the device uses a 14.318 mhz crystal input to produce multiple output clocks up to 75 mhz. it provides selectable host and pci local bus clocks as well as selectable clocks for super i/o or universal serial bus (usb). the device has up to seven host output clocks. the chip has three different power down modes that reduce power on various clocks. ?packaged in 28 pin, 150 mil wide ssop ?provides all critical timing for opti acpi firestar and firestar+ ?early host clock of 3.5ns ?separate vdd and skew adjust for host 5,6, and 7 supports field upgrade to firestar+ and new 2.5v processors ?48mhz usb, 24mhz sio, and audio clock support ?single pin cpu(host) slowdown to 33.3mhz ?multiple power down modes ?low emi enable pin reduces emi radiation (patent pending) crystal oscillator vdd gnd host/pci clocks stop# sel0 14.31818 mhz crystal output buffers output buffer fixed clock output buffers xi xo ps vdd host1-4 sel1 host/2 f2 host 5, 7 pci 1:5 slow# low emi enable output buffer 14.318 mhz f1 output buffer fs1:0 synch./asynch. pci host1:4 output buffers 4 2 5 vdd host5-7 ehost6 33m mux hs 3 4
MK1491-14 opti acpi firestar clock source mds 1491-14 b 2 revision 061801 integrated circuit systems, inc. ?525 race street ?san jose ?a ?5126 ?(408)295-9800tel ?www.icst.com pin descriptions table #2. host/pci frequency select (mhz) pin assignment 1 8 9 2 3 4 5 6 7 10 11 12 13 14 16 15 20 17 18 19 25 24 23 22 21 26 27 28 host3 host2 host1 x14o vdd 14.3(hs) host4 vdd host1-4 x14i gnd vdd host5-7 gnd ehost6 host5 table #1. f1, f2 frequency select (mhz) table #4. power down control (idd measured at 3.3v) sel1 sel0 f1 f2 0 0 14.318 14.318 0 1 14.318 48.000 1 0 24.000 14.318 1 1 16.934 24.576 low emi for host & pci le low emi 0 off 1 on key: i = input, o = output, p = power supply connection, i/o = input on power up, becomes an output after 10ms. internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28. hs 2.5v 0 3.3v 1 table #3. host 5-7 skew control vdd pcif(le) gnd vdd stop# pci(s/a) pci(sel1) f1(sel0) f2(ps) host7 pci(fs0) slow# gnd pci(fs1) *pci function select (ps) set at power up. ps=0, pci=low; ps=1, pci=on when clock is switched to ?lk off?mode. fs1 fs0 host pci (s/a=0) pci (s/a=1) 0 0 66.66 33.33* host/2 0 1 60 33.33* host/2 1 0 75 33.33* host/2 1 1 50 33.33* host/2 vdd host5-7 *2 mhz accuracy pin # name type description 1, 20, 26 vdd p connect to +3.3v. must be same voltage on all pins. 2 x14i i crystal connection. connect to a 14.31818 mhz crystal or input clock. 3 x14o o crystal connection. connect to a 14.31818 mhz crystal, or leave unconnected for clock. 4, 11, 17, 23 gnd p connect to ground. 5 14.3(hs) i/o 14.318 mhz output. amplitude matches vdd. skew input control for host 5-7. 6, 7, 9, 10 host 1, 2, 3, 4 o host output clocks 1, 2, 3 and 4. amplitude matches vdd 8 vdd p connect to vdd supply. 12 host 5 o host output clock 5. amplitude matches vdd . 13 ehost 6 o early host output clock 6. amplitude matches vdd . 14 vdd p connect to 2.5 v or 3.3 v. host 5-7 skew adjusted with hs input. see table #3 above. 15 host7 o host output clock 7. amplitude matches vdd . 16 slow# i controls clock frequency and power downs, as defined in table #4 above. 18 pci(fs0) i/o pci output clock, cpu frequency select input, as per table #2 above. amplitude = vdd. 19 pci(s/a) i/o pci output clock, and asynchronous pci select input, as per table #2 above. 21 pci(sel1) i/o pci output clock, and frequency select 1 input, as per table #1 above. 22 pcif(le) i/o pci output clock that stays enabled when other pci clocks are low. low emi enable input. 24 pci(fs1) i/o pci output and frequency select input. see table #2 above. 25 f2(ps) i/o fixed frequency output and pci function select for "clk off" mode. 27 f1(sel0) i/o fixed frequency output and frequency sel0 input per table #1 above. 28 stop# i controls clock frequency and power downs, as defined in table #4 above. host1-4 host1-4 host5-7 host5-7 host5-7 stop# slow# state host pci description idd typ. 1 1 on on on all clocks on. 50 ma 1 0 slow 33 mhz on host clock smooth frequency transition to and from 33.33 mhz. 32 ma 0 0 clk off low asynchronously clamp host5, 7 to gnd. host1-4,6, pcif, f1, f2, 14.3m, continue to run. 44 ma 0 1 pll/osc off low low all outputs asynchronously clamped low. plls and 14.3 mhz oscillators are off. 1 ? * host5-7
MK1491-14 opti acpi firestar clock source mds 1491-14 b 3 revision 061801 integrated circuit systems, inc. ?525 race street ?san jose ?a ?5126 ?(408)295-9800tel ?www.icst.com electrical specifications parameter conditions minimum typical maximum units absolute maximum ratings (note 1) absolute maximum ratings (note 1) supply voltage, vdd referenced to gnd 7 v inputs and clock outputs referenced to gnd -0.5 vdd+0.5 v ambient operating temperature 0 70 ? soldering temperature max of 10 seconds 260 ? storage temperature -65 150 ? dc characteristics (vdd = 3.3v or 2.5v unless noted) dc characteristics (vdd = 3.3v or 2.5v unless noted) operating voltage vdd 3.3 3.6 v operating voltage 2.5/3.3 vdd v input high voltage, vih 2 v input low voltage, vil 0.8 v output high voltage, voh ioh=-8ma 2.4 v output low voltage, vol iol=8ma 0.4 v output high voltage, voh ioh=-8ma vdd-0.4 v operating supply current, idd no load, 66.6mhz 48 ma power down mode supply current 3 ma short circuit current each output ?0 ma short circuit current ?5 ma input capacitance 7 pf ac characteristics (vdd = 3.3v or 2.5v unless noted) ac characteristics (vdd = 3.3v or 2.5v unless noted) input frequency 14.31818 mhz output clock rise time 0.8 to 2.0v 1.5 ns host output clock rise time 2.5 ns output clock fall time 2.0 to 0.8v 1.5 ns host output clock fall time 2.5 ns output clock duty cycle, all mhz clocks at 1.5v 45 49 to 51 55 % host1-4 output to output skew rising edges at 1.5v 250 ps skew of host 5,7 with respect to host 1-4 with proper hskew setting 750 ps pci output to output skew rising edges at 1.5v 500 ps lead of ehost6 outputs with respect to pci rising edges at 1.5v 1.9 ns lead of ehost6 with respect to host1-5, 7 rising edges at 1.5v 3.9 ns cycle to cycle jitter, cpu clocks 1000 ps absolute clock period jitter, other mhz clocks, except 14.318 mhz -500 500 ps emi reduction, peaks of 5th - 19th odd harmonics 66.6 mhz clocks, le=1 6 11 db power up time, stop# going high to all clocks stable 8 20 ms power on time, applied vdd to all clocks stable 12 25 ms note 1. stresses beyond those listed under absolute maximum ratings could cause permanent damage to the device. prolonged exposure to levels above the operating limits but below the absolute maximums may affect device reliability. vdd host1-4, host5-7 vdd host = 2.5v vdd host = 2.5v vdd host = 2.5v
MK1491-14 opti acpi firestar clock source mds 1491-14 b 4 revision 061801 integrated circuit systems, inc. ?525 race street ?san jose ?a ?5126 ?(408)295-9800tel ?www.icst.com while the information presented herein has been checked for both accuracy and reliability, microclock incorporated assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by microclock. microclock reserves the right to change any circuitry or specifications without notice. microclock does not authorize or warrant any microclock product for use in life support devices or critical medical instruments. b d e h e q c a h x 45 package outline and package dimensions ordering information 28 pin ssop inches inches millimeters millimeters symbol min max min max a 0.061 0.068 1.55 1.73 b 0.008 0.012 0.203 0.305 c 0.007 0.010 0.190 0.254 d 0.385 0.400 9.780 10.160 e 0.150 0.160 3.810 4.064 h 0.230 0.245 5.840 6.223 e .025 bsc .025 bsc 0.635 bsc 0.635 bsc h 0.016 0.410 q 0.004 0.01 0.127 0.254 part/order number marking low emi feature package temperature mk1491e-14r mk1491e-14r yes 28 pin ssop 0-70? mk1491e-14rtr mk1491e-14r yes add tape & reel - i/o structure the mk1491 provides more functionality in a 28 pin package by using a unique i/o technique. the device checks the status of all i/o pins during power-up. this status (pulled high or low) then determines the frequency selections and power down modes (see the tables on page 2). within 10ms after power up, the inputs change to outputs and the clocks start up. in the diagrams to the right, the 33 w resistors are the normal output termination resistors. the 10k w resistor pulls low to generate a logic zero. internal pull-up resistors are present on all inputs to generate a logic one when an external pull-down resistor is not connected. pentium is a trademark of intel corporation to load i/o to load i/o for select = 0 (low) for select = 1 (high) 10k w 33 w 33 w external components the mk1491 requires some inexpensive external components for proper operation. decoupling capacitors of 0.1? should be connected on each vdd pin to ground, as close to the mk1491 as possible. a series termination resistor of 33 w may be used for each clock output. see the discussion on page 4 for other external resistors required for proper i/o operation. the 14.318 mhz oscillator has internal caps that provide the proper load for a parallel resonant crystal with c l =18pf. for tuning with other values of c l , the formula 2?c l -18) gives the value of each capacitor that should be connected between x1 and ground and x2 and ground.
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