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ics557-05a mds 557-05a e 1 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com quad differential pci-express clock source description the ics557-05a is a spread-spectrum clock generator that supports pci-express requirements. it is used in pc or embedded systems to substantially reduce electro-magnetic interference (emi). the device provides four differential hcsl or lvds high-frequency outputs with spread spectr um capability. the output frequency and spread type are selectable using external pins. features ? packaged in 20-pin tssop ? available in pb (lead) free package ? supports pci-express applications ? four differential spread spectrum clock outputs ? spread spectrum for emi reduction ? uses external 25 mhz clock or crystal input ? power down pin turns off chip ? oe control tri-states outputs ? spread and frequency selection via external pins ? spread bypass option available ? industrial temperature range available block diagram spread spectrum/ output clock selection clkouta clkouta rr(iref) pll clock synthesis 3 gnd vdd clock oscillator x1 sel[2:0] spread spectrum circuitry 2 2 clkoutb clkoutd x2 25 mhz crystal or clock oe pd optional tuning crystal capacitors clkoutd clkoutc clkoutc clkoutb
quad differential pci-express clock source mds 557-05a e 2 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a pin assignment spread spectrum selection table 13 4 12 5 11 x1 8 9 10 gndoda oe clkc clkd gndxd clkd 17 16 iref 3 s1 s2 clkb 18 clkb 1 vddxd s0 clka 20 clka 19 14 2 7 x2 pd vddoda clkc 15 6 20-pin (173 mil) tssop s2 s1 s0 spread% spread type output frequency (mhz) 0 0 0 -0.5 down 100 0 0 1 -1.0 down 100 0 1 0 -1.5 down 100 0 1 1 no spread not applicable 100 1 0 0 -0.5 down 200 1 0 1 -1.0 down 200 1 1 0 -1.5 down 200 1 1 1 no spread not applicable 200
quad differential pci-express clock source mds 557-05a e 3 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a pin descriptions pin pin name pin type pin description 1 vddxd power connect to +3.3 v digital supply. 2 s0 input spread spectrum select pin #0. see table above. internal pull-up resistor. 3 s1 input spread spectrum select pin #1. see table above internal pull-up resistor. 4 s2 input spread spectrum select pin #2. see table above. internal pull-up resistor. 5 x1 input crystal connection. connect to a fundamental mode crystal or clock input. 6 x2 output crystal connection. connect to a fundamental mode crystal or leave open. 7pd input powers down all pll?s and tri-states outputs when low. internal pull-up resistor. 8 oe input provides output on, tri-st ates output (high = enable ou tputs; low = disable outputs). internal pull-up resistor. 9 gnd power connect to digital ground. 10 iref output precision resistor attached to this pi n is connected to the internal current reference. 11 clkd output selectable 100/200 mhz spread spectrum differential compliment output clock d. 12 clkd output selectable 100/200 mhz spread s pectrum differential true output clock d. 13 clkc output selectable 100/200 mhz spread spectrum differential compliment output clock c. 14 clkc output selectable 100/200 mhz spread s pectrum differential true output clock c. 15 vddoda power connect to +3.3 v analog supply. 16 gnd power connect to analog ground. 17 clkb output selectable 100/200 mhz spread spectrum differential compliment output clock b. 18 clkb output selectable 100/200 mhz spread s pectrum differential true output clock b. 19 clka output selectable 100/200 mhz spread spectrum differential compliment output clock a. 20 clka output selectable 100/200 mhz spread s pectrum differential true output clock a.
quad differential pci-express clock source mds 557-05a e 4 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a application information decoupling capacitors as with any high-performance mixed-signal ic, the ics557-05a must be isolated from system power supply noise to perform optimally. decoupling capacitors of 0.01f must be connected between each vdd and the pcb ground plane. pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 2) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor can be mounted on the back). other signal traces should be routed away from the ics557-05a. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. external components a minimum number of external components are required for proper operation. decoupling capacitors of 0.01 f should be connected between vdd and gnd pairs (1,9 and 15,16) as close to the device as possible. on chip capacitors - crystal capacitors should be connected from pins x1 to ground and x2 to ground to optimize the initial accuracy. the value (in pf) of these crystal caps equal (c l -12)*2 in this equation, c l =crystal load capacitance in pf. for example, for a crystal with a 16 pf load cap, each external crystal cap would be 8 pf. [(16-12)x2]=8. current reference source r r (iref) if board target trace impedance (z) is 50 ? , then rr = 475 ? (1%), providing iref of 2.32 ma, output current (i oh ) is equal to 6*iref. load resistors r l since the clock outputs are open source outputs, 50 ohm external resistors to ground are to be connected at each clock output. output termination the pci-express differential clock outputs of the ics557-05a are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are shown in detail in the pci-express layout guidelines section. the ics557-05a can also be configured for lvds compatible voltage levels. see the lvds compatible layout guidelines section.
quad differential pci-express clock source mds 557-05a e 5 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a output structures general pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. each 0.01f decoupling capacitor should be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias should be used between decoupling capacitor and vdd pin. 3. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces should be routed away from the ics557-05a.this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. r r 475 6*iref =2.3 ma iref see output termination sections - pages 3 ~ 5 ?
quad differential pci-express clock source mds 557-05a e 6 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a pci-express layout guidelines pci-express device routing typical pci-express (hcsl) waveform common recommendations for differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch l3 length, route as non-coupled 50 ohm trace. 0.2 max inch r s 33 ohm r t 49.9 ohm differential routing on a single pcb dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch differential routing to a pci express connector dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch r s r s r t r t pci-express load or connector l1 l2 l3? l4 l1? l2? l3 l4? ics557-05a output clock 0.175 v 0.52 v 0.175 v 0.52 v t or t of 500 ps 500 ps 700 mv 0
quad differential pci-express clock source mds 557-05a e 7 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a lvds compatible layout guidelines lvds device routing typical lvds waveform lvds recommendations for differentia l routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch r p 100 ohm r q 100 ohm r t 150 ohm l3 length, route as coupled 50 ohm differential trace. l3 length, route as coupled 50 ohm differential trace. l1 l2? l3 l1? l2 l3? r q r p lvds device load ics557-05a clock output r t r t 1150 mv 1250 mv t or t of 500 ps 500 ps 1325 mv 1000 mv 1150 mv 1250 mv
quad differential pci-express clock source mds 557-05a e 8 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics557-05a. these ratings are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specificat ions is not implied. expo sure to absolute maximum rating conditions for ext ended periods can affect product reliabilit y. electrical parameters are guaranteed only over the recommended operating temperature range. dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c 1 single edge is monotonic when transitioning through region. 2 inputs with pull-ups/-downs are not included. item rating supply voltage, vdd, vdda 5.5 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c esd protection (input) 2000 v min. (hbm) parameter symbol conditions min. typ. max. units supply voltage v 3.135 3.465 input high voltage 1 v ih 2.0 vdd +0.3 v input low voltage 1 v il vss-0.3 0.8 v input leakage current 2 i il 0 < vin < vdd -5 5 a operating supply current i dd 50 ?, 2pf load@ 100mhz 105 ma i ddoe oe =low 40 ma i ddpd no load, pd =low 500 a input capacitance c in input pin capacitance 7 pf output capacitance c out output pin capacitance 6 pf pin inductance l pin 5nh output resistance rout clk outputs 3.0 k ? pull-up resistance r pup oe, sel, pd pins 110 k ?
quad differential pci-express clock source mds 557-05a e 9 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a ac electrical characteristics - clkouta/clkoutb unless stated otherwise, vdd=3.3 v 5% , ambient temperature -40 to +85 c 1 test setup is r l =50 ohms with 2 pf, rr = 475 ? (1%). 2 measurement taken from a single-ended waveform. 3 measurement taken from a differential waveform. 4 measured at the crossing point where instantaneous voltages of both clkout and clkout are equal. 5 clkout pins are tri-stated when oe is low. asserted. clkout is driven diff erential when oe is high unless its pd = low. thermal characteristics parameter symbol conditions min. typ. max. units input frequency 25 mhz output frequency hcsl termination 200 mhz lvds termination 100 mhz output high voltage 1,2 v oh 660 700 850 mv output low voltage 1,2 v ol -150 0 mv crossing point voltage 1,2 absolute 250 350 550 mv crossing point voltage 1,2,4 variation over all edges 140 mv jitter, cycle-to-cycle 1,3 60 ps modulation frequency spread spectrum 30 31.5 33 khz rise time 1,2 t or from 0.175 v to 0.525 v 175 332 700 ps fall time 1,2 t of from 0.525 v to 0.175 v 175 344 700 ps skew between outputs at crossing point voltage 50 ps duty cycle 1,3 45 55 % output enable time 5 all outputs 10 us output disable time 5 all outputs 10 us power-up time t stable from power-up vdd=3.3 v 3.0 ms spread change time t spread settling period after spread change 3.0 ms parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 93 c/w ja 1 m/s air flow 78 c/w ja 3 m/s air flow 65 c/w thermal resistance junction to case jc 20 c/w
quad differential pci-express clock source mds 557-05a e 10 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a pci-express layout guidelines pci-express de vice routing typical pci-express (hcsl) waveform common recommendations for differential routing dimension or value unit l1 length, route as non-coupled 50 ohm trace. 0.5 max inch l2 length, route as non-coupled 50 ohm trace. 0.2 max inch l3 length, route as non-coupled 50 ohm trace. 0.2 max inch r s 33 ohm r t 49.9 ohm differential routing on a single pcb dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch differential routing to a pci express connector dimension or value unit l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch r s r s r t r t pci-express load or connector l1 l2 l3? l4 l1? l2? l3 l4? ics557-03 output clock 0.175 v 0.52 v 0.175 v 0.52 v t or t of 500 ps 500 ps 700 mv 0
quad differential pci-express clock source mds 557-05a e 11 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a package outline and package dimensions (20-pin tssop, 173 mil body) package dimensions are kept current with jedec publication no. 95, mo-153 index area 1 2 20 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a1.200.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 6.40 6.60 0.252 0.260 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
quad differential pci-express clock source mds 557-05a e 12 revision 011606 integrated circuit systems, inc. 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics557-05a ordering information parts that are ordered with a ?lf? suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics557g-05a ics557g-05a tubes 20-pin tssop 0 to +70 c ics557g-05atr ics557g-05a tape and reel 20-pin tssop 0 to +70 c ics557g-05alf 557g-05alf tubes 20-pin tssop 0 to +70 c ics557g-05alftr 557g-05alf tape and reel 20-pin tssop 0 to +70 c ics557gi-05a 557gi-05a tubes 20-pin tssop -40 to +85 c ics557gi-05atr 557gi-05a tape and reel 20-pin tssop -40 to +85 c ics557gi-05alf 557GI05ALF tubes 20-pin tssop -40 to +85 c ics557gi-05alftr 557GI05ALF tape and reel 20-pin tssop -40 to +85 c

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