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" % 1* " channel a exploded view databus control interrupt iei ieo intack int control cpu & dma bus interface control interrupt logic control interrupt logic channel b register channel a register rxda channel a channel b receive logic receive mux crc checker data decode & sync character detection rec. status fifo 3 byte rec. status fifo 3 byte sdlc frame status fifo 10 x 19 ctsa dcda synca rtsa dtra /reqa modem/control logic digital phase-locked loop baud rate generator crystal oscillator amplifier receive and transmit clock multiplexer transmit buffer transmit logic transmit mux data encoding & crc generation txda trxca rtxca < & /)!!0)#)!) ' ! %' 4 5 1 ' &4..' * ) ' *) )+,5 ' & : & 5. ,5 $ 5 ' &4+ 2 3 1 d& : e+94' & & 5 .. 4 =1 ' & 1 ' & : # . +94& 5 .. =1 ' 3.31 5 #& & &+?'& '.# 55 144 .. #. &+%' & ' & &' />1' 5 : # + 2 31 d& : e+%' &4 : 1 4' 3 & 5 .. 4 =1 +' # ' & 5 #& & &&+?'& '.# 55 144 .. #. 5# +%' & ' & &' />1' 5 : + 4 4(52 3 4 4(51 d& : e+%' # &4 ' & 5 .. ' <%1+%' 3 1 5 #& & & 4 <7 + /)!!0)#)!) < & 6(6 d& : 5'e+9=9 '9=4 . & 3#' ' ' . ' & : : + '5'9=9 '' '5' & 3 : ' & : 5 &+ 6( d& : 5'e+9=5' 349=9 5' ' /> :5' & ' 5 &d & 6 5 3 3e+9= ' - & 3 : j9=9& ' '1 &4 . & 3 : + 67 d& & # : e+%'5 : ' ' &+ 67 28 d& : e+%'5 : 9 & 6 5 3 +< 5'3 ' & 3' +' < < 1 . : ' & &: ' 1d49=95'e+ 9;% k ' 13' 5 5 4/ k+ 8 d&e+%'' . 6 3' b 5 +/ k%% : 5 +/ k ': 3&' '& '' . 3 . 6+ < & /)!!0)#)!) 9 4:234:1 d& : 5'e+%' 5 : %% : + 4 ;2 34 ;1 d& : e+%' &1 & 5 .. : 44 & 5. +9 ''# %- .3&& 3' : 6 ' . 6 ' 64 ' ? ' 64 ' <5 /' #6 &+%' & 1 & 5 .. 4 '' & : @; & 3 +%' : 6.31 ! !" "$. ' 3' . + 4 2 34 1 d& : e+' ' % d%e1 5 d,5 e ' 9%5 5 +' ' %1 ' 3' . =1 ' 5 5 5'4 ' . .&3+93' . 34 ' 4' % 1+?'&1 5 #& & &+ <72 3 <71 ! " d& & : e+%' &4# & & & 4' 3 +9' 3' : . d 3 & e ' & &. % < < +9' . ' 44 ' 4' 3' # c1 5 )d,5 *e1': ' 4+ /)!!0)#)!) < & % 9=- 3' b. '' 3 ' &+9'. @; . 1 : 4 : 63 4 ' 1' 3' ' : + ' .1 31 5 ' 5 5 4' : 6.. 3& 5' # :4@; + 9' 9 3' b. d73 ?3e ' ' 3 ' && : 3 5' & 4' : 63 ''3# ' ' 5b %'3' ' +%' & : '. 3' b & 5b d 5 4' 1 e+9 < . ' && : &4 4 5+ :23 :1 d& : 5'e+%' &5 . %% : + 4;2 3 4;1 d& & : e+%' & 1 & 5 .. : 44 & 5. +%- .3&& 3' : 6 ' . 6' & . && 3' &4' <5 /' # 6 & ' 3 ' ? ' . 6 ' &. + = 4(52 3= 4(51 # d& & # ' & 5 .. 4 4 : 5' ' & 5 .. 4 4# e+%' #& & &.31 & 5 .. < & /)!!0)#)!) %% 4 <7 3' b ' />' +%' + c? ! ! $ d&e+%'5 ' ' ''' & + = ! d& : e+%'5 ' 4 & + <0m<) $ d1 # e+%' 3 .# . 4 .' + < d&e+%'5 4 ' 3& 44 .# 4 4 .' + 5' # 4 f .. + < d& : e+%'5 & ' ' 1 ' j1 : + < 5' 9 & 6 5 3 '5 5 ' # &: ' 14' ' '5' & 3 : 5 &+ /)!!0)#)!) < & %, # d& : e+' ' '5 & +%' 49 < & + <0m <) $ d1 : 5' % # e+%' . # & - 3 5 ' 4 .+ d& : e+ <0m <) ' 13' 5 5 4'5 + ) ! % d& : e+%'5 ' # 3 '' <0m <) .1 : 4 ' 1 + ! ! & d& : 5'e+%' 5 . 1 : 1 4 ' 1 + ! . .: ' 5'' + < & /)!!0)#)!) % < d& : e+%'5 & : .54 ' 4 4 4' +94 < ' 4 & + c c d&e+%'5 & 4 ' ' ' & 1 & 4 . + ! " , 6 2 " d1 d3 d5 d7 int ieo iei intack +5v w /reqa synca rtxca rxda trxca txda dtr /reqa rtsa ctsa dcda pclk d0 d2 d4 d6 rd wr a/b ce d/c gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 z85c30 ad1 ad3 ad5 ad7 int ieo iei intack +5v w /reqa synca rtxca rxda trxca txda dtr /reqa rtsa ctsa dcda pclk ad0 ad2 ad4 ad6 ds as r/w cs0 cs1 gnd w /reqb syncb rtxcb rxdb trxcb txdb dtr /reqb rtsb ctsb dcdb 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 z80c30 /)!!0)#)!) < & %/ ! " 2 " ieo z85c30 iei intack +5v w /reqa synca rtxca rxda trxca txda nc a/b ce d/c nc gnd w /reqb syncb rtxcb rxdb trxcb txdb int d7 d5 d3 d1 d0 d2 d4 d6 rd wr nc dtr /reqa rtsa ctsa dcda pcld dcdb ctsb rtsb dtr /reqb nc 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 39 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 ieo z80c30 iei intack +5v w /reqa synca rtxca rxda trxca txda nc r/w cs0 cs1 nc gnd w /reqb syncb rtxcb rxdb trxcb txdb int ad7 ad5 ad3 ad1 ad0 ad2 ad4 ad6 ds as nc dtr /reqa rtsa ctsa dcda pclk dcdb ctsb rtsb dtr /reqb nc 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 39 6543214443424140 18 19 20 21 22 23 24 25 26 27 28 < & /)!!0)#)!) % ! " / ! z85c30 serial data channel clocks ch-a channel controls for modem, dma and other ch-b serial data channel clocks channel controls for modem, dma and other data bus d7 d6 d5 d4 d3 d2 d1 d0 rd wr a/b ce d/c int intack iei ieo txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb rxdb trxcb and reset control interrupt bus timing /)!!0)#)!) < & %0 ! " ! z80c30 serial data channel clocks ch-a channel controls for modem, dma and other ch-b serial data channel clocks channel controls for modem, dma and other data bus ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 as ds r/w cs1 cs0 int intack iei ieo txda rxda trxca rtxca synca w /reqa dtr /reqa rtsa ctsa dcda txdb rtxcb syncb w /reqb dtr /reqb rtsb ctsb dcdb rxdb trxcb and reset control interrupt bus timing /)!!0)#)!) , < & %' " # %' ' 4' 1 4 . &4: ( + .. : '' . : : 34& f + . & & &' ''' 44 : 1 4 ': & <7 && + %' j& &' .. 1 ' 4 5 +,5 !&5 " ' 1 6 5 .+,5 " 0' ' 4' .. 1 ' : . 5' 3 .1+%' 4 # &'4 '4' j ?' + /)!!0)#)!) , < & % ! " 0 ) from receiver crc-gen zero insert (5 bits) 20-bit tx shift register sync register sync register internal data bus to other channel internal txd txd nrz encode transmit mux & 2-bit delay transmit clock tx buffer 1 byte final tx mux wrb wr6 sync sync sdlc wr7 , < & /)!!0)#)!) %9 ! " ' 4 # ) 6 6 3 ... 4 .' & 4 . ' 5' ' j 5 +%' - 5 5' 5 +%1 ! 5 & : 1 4 &4' 4+ to transmit section mux nrzi decode mux internal txd dpll sync register & zero delete out sdlc-crc crc checker crc result sync crc crc delay register (8 bits) receive shift register 3-bit rxd dpll in dpll 1-bit hunt mode (bisync) 14-bit counter rec. error logic brg output rec. error fifo 3 byte deep rec. error fifo 3 byte deep status fifo 10 x 19 frame i/o data buffer internal data bus cpu/i/o brg input 16-bit down counter div 2 upper byte (wr13) time constant lower byte (wr12) time constant /)!!0)#)!) , < & , %' 5'' . +' 5 4 # '' 4 5hi4 5 hi 4 5 +, -.& ( $ 5 $4 ' 5 4 ' c1'' % 4 4 " ! 4 " ! ) % .c : 144 =- ! & : 7 4 &: d ' ? 3e>. 4 &: d ' 3e 9 &/ 51d ' 3e * : ?44 !) 7 ! 13 4? . ! >&& 13 4? . ! =- c &4 . , = 4 " ! 4 " ! ) b b.. 4 ' : . 5 & ! % .c : & 4 . 4 , < & /)!!0)#)!) ,% %' ' . ' .: 4' ( + / 5 + 9 &d: #: e + ? 6% 4 +%' ? 6% 4 . 1 .& . # /> <7 + 9 &: d ' 5' ' ' e : & . $ % .c : . & . . % .& . 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' + 9' ' 9 &/ 5d9/e15 4 # & :5+' 9/1! ' 9=9&5' ' 9;% && 5 &+9' 4' 9= 1 13 1 5 & ' ' 9/4 ' : +%' 9/1 1 + +5 v +5 v d7?d0 int ntack iei d7?d0 int intack ieo iei d7?d0 int intack ieo iei d7?d0 int intack peripheral peripheral peripheral /)!!0)#)!) , < & ,/ %' 9>15 ' & 1 5 : +94 9> & 4 & 3' - ' & : 4 . 5 &+%' & '1 13' 4' 3' ' & 3 : '1 13' 9= &4' 1 5& & &5 1 & &' + 9>1 59 & 6 5 3 4' '5' & 3 : 5 &+ %' ' 3& 4 &(% . : =- # c+=' &3& 1 & 5 . ' ' ':5'5' & 3' ' ? ' : % . =- c && b ' ' '' + ' 1 ' : &' /> 4' 3+ + 9 &, : ' & : + 9 & : ' & : + 9 && : 3 9 &, ' & 9 & & 3 3& 3 '' ? 6% 4 . + & : 4' 4 5+ : : 4 .5 3' . #4#4 . < . & 3 & 3 +%' & : & 44 4 . 3 : ' : 1 & 313' & ' : 5' 9 & 6 5 3 +99 &, : ' # & 4 .& : 3. 4 ' 4 : ' &+ %' .44' =- c &. ' 5 4' % < < @; & ' : =- c & 13% .> , < & /)!!0)#)!) , fb ' ? f13' # 4? 6d 3' . e 1 d< . e =/ d< &. e ' .+%' & 13' 1 =/'& 4 5' & ' ' 1 =/ . +%'4 4 ' & & .4' . 5 b4' -. 5 ' .54' 1 - 5< . +9< &. '4 3 5b ' & . 3 55 4' & 5 & + $ 6 2*$ " ' 7: 4' ' &6 5 3 1 ' 5'4 +94 5 d e 1< 5 de &6 # 5 3 1 - 3+6 ' 9;% k 3 4 6 5 ' 9;% & 5' ' 9=&5 ' 9> '4 ' '5' & 3 && 5+ . 5' ' 9;% k5 4 6 # 5 3 ' 5' 9>.. 1 ' & : +' : &6 # 5 3 ' 4 '5' 9>.# . +94 4 .' ' . 4 : +94 4 .' ? ' ' : . 4 ' 4' &+%' a 9 da9e ;a d;ae1 5 ' 1 ) !+ ' ' 9;% k 9=9& 1 5 ' 3' 1 & &a && ' 5' d!)k'.3& e+ /)!!0)#)!) , < & ,0 @21* %' & : ? 6% 4 . .. /> 1 6 4 4 7 +%' ? 6% 4 . ' 9% c =>=% &2 '' c 1!+%' 9 % c =>=% &1 4 4 9% ' />? 6 % 4 . =l>=% ' <7 ? 6% 4 . + %<7 ' =l>=%& '' 3 4 4 .. . 3%' /> ' 9% '' = 3 4 ' 13 5'' /> - ' 9c3 +%' <% c =l>=% 4 # & -& <7 + %' & : & 4 # & -& 5 ..1 ' 4 3..3' 3' ..& d,5 e+='4' ..# ' ' 4 &1 + , < & /)!!0)#)!) ,' ! " 9 2.) : .& ' & 3 '' '4: 5'1& ' & & : & 3 %' . && 3 # ##' 4 &1 & ' & : 1 6&3. +%' : 1 6# 5 &' />1'' ' 4 : 1 6+ && 4 . &6 13 &6 # 2 . '.'' 6' 5 #' 41. 4 : ' : &d-< -3& + flag address information crc1 crc2 information flag data sync crc1 signal crc1 crc2 marking line data crc2 sync data data crc1 crc2 sync data data start sdlc/hdlc/x.25 parity stop data data data marking line external sync bisync monosync asynchronous /)!!0)#)!) , < & , , .5 : 144 5 ' '' & ' ''' 3 +a & 4 :5 5 + 1 #' 65& : ' & 4 4 .5 1+ 4 .5 ' # 4 #' 41. ' & ''' '4 ' - 11 5+ %' 3.. . : 6 5 #4 5 4' : 34 6 + %' . : ' && ' : . 6&+9 3' . ' @; &.31 & 5 .. & 4 4' . 5 5 + .) %' && 1'13 1# 3' ..# +3' 13 # & ' :# . +%' 3 ' 3' b '"#1 *# 13' d73e !#1 !"#13' b# & d?3e ' - 35 + 53 ' .: ' &5' />+ # 0#13' ' '*# !"#1 & ' 13: &&5' 5 & . # & .53' ' ,5 !)+ ! " % "a'a1 .)) data data data data sync sync 7 bits 8 16 sync , < & /)!!0)#)!) ,9 ' 654 3' 13 # . 3 13 ' . '' />.3 1 ' 65 & 4' %'4 & .' .& . 4& # '9?7?3+ ?' #!"dn!"on!ono!e 9%%dn!"on!ono !e #' 65& 3. && +=' & 3. .31 3' . +> .3& ' 5 ' 6 !j )j+%' & # : 4 '. 3 . ' ' : 1 4 .+%'4 4 '5' & . <7 ' 4 /> : ' 4. 5 +' ' 3' . ' . "# *# !"#13' 5 4' & 5 .. ' 5'+ %' && 3' 1# & ' < < 13& 4 .5.4 5 5 b 5 + & .. 1 4 . .+ ' 4. 5 ' . 3 .' 54 5 ' ' # . +%' . .3 1 & 5 .. 544 5' 3 . 65 + 94 . ' . 4. 5 - # c & ' />4''5 5 1 +%' .3 1 & 5 .. 1 4 4 :5' />4'6+ 5' 1& ' 1 5 &4. 5 '& 4 .1' ' ' 4 # .4 44 . + /)!!0)#)!) , < & %' : . 3 3' b' 5 4 544 . < < & : 3' b 5 ' @; &d & 1 & 5 .. e+ %' : 1 & 5 .. '4 4 . 135 13 d 4 1 '13 e4 # 5 1 1 +9'. 4 . .'5 ' ' # 1 5 + %' .1 4 13 - 4 , :5 &' 4 : ' & : 3' & 3d # 4#4 . e1 %' : . 3 )j 13' . 5' .1 3 . 3' 6 : 4 . .# + ' 4 . ' 4 : 4 . : 1 ' 5 +9< . ' .1 & 5 .. ' < & 3. 1' 5 ' 6 .31 & !j )j+%' : 1 4 . ' : ' 65' 1& )))!!!)!)))) !!!!+ ; ;9 ,7 5.31 3!-. %' & 3 &: 1 9 3' . : 1 3# ' . + %' && < &. . < + 9< & & . 3 .5 ' . # 5 444 ' & 3.1 4 3+ 9< &. ' & 4 .' 44 # 3 ' & 5 5 < . d,5 !!e+< &. 1 13 5 !)1 , < & /)!!0)#)!) % ! " %% 2 3< & 3 5' . 5 ' & 4 & ' . # 5 ' 4' &13 .5' . ' #1# . 3+%' 3& . 5 ' & 3& 4. +%' 5 ' 3 .. 5 13 5& ' =/d= 4/ e ' &+%' =/' ' 1& !!!!!!!)+? 4b 5. # 5 '1& 3 5b + ' 3. 5 . # 5b =/' '5 ' 1 3!4' =/ )1 4 .+%''5 '' 44 4 5 ' =/4 5 +%' 3 & . 5 ' & . ' . 5 '=/+ 3 34 ' ' & '. 5 .&& ' . 5 ' . 5 4' 4 # 313' . & + 3 3 '# . 5 '' .5. 5 secondary #2 secondary #3 secondary #4 controller secondary #1 /)!!0)#)!) , < & , & '1 4 .& 5. 5 ' &d - & ' 5# b5=/e+9< &. ; ;9 ,7 5 .3 1 + %' j1 3 : '5'& 16##16< 4 . .-.b 13!)# &13! #1 ,9,+' 1 d' 5'! 1<e & : ' <7 ' 1 3 4 . . 3'' /> -.# ' . 5 +, '< 4 . !$#113 c 1 +%' 13 1 ' 5' 5 " 0+ 5 " 0 3 1 ' ' < ,9, 1 +%' !) -! ,9, & 4 .' #13 : ,9,+ 14 & ='' ' & 5 ..1 ? +='5 4 *#1. 5# '4 .!"#1. !"#1 4 &' && 5 : + #& ' &4 & 5' ' : ' . 5 ' ' 5 +%' &4' ? 55 ' '# 5) ' : ' . 5 ' ' & & +%' . .31 '5 3. 1' : 6 44 ' - 4' + %' &4' ? .31 ' ' . 6 ' : 6 1'+9 : ' <5# /' # 6 &d - e+ 94' : 6 . 6& 5 .. . 4 .' %- & ' &4' ? .31 ' ' 5'' %- &+%' 4 54 . ' . ' 1 ' / k %- ' ? , < & /)!!0)#)!) &4 3 b+%' 6. ! !" "$ 5 $ 1<" <0+3' # & . ! 3' . !" "$+ " ) a * %' <5 /' #6 &d64 .4 . . ';9 ,7 5+ %' 6'. 3d;9e !" d,7e. ' +%' 6 5 '' . 64 ' +%' 6 ' : 6 ' . 6 1'+' ' ' . 6 & : 2 #4 6&'' 5 ' + , ;9 5 ' 6 .# 1. + ' - 6 ' e & 5 . ' 4' 1 + , ,7 5 ' & 5 1. +' ' 6 ' 6 5 ' . 1 ! !" 1 ! )+%' 64 5 3 # 5. ' !!"5 + time constant = pclk or rtxc frequency 2(baud rate)(clock rate) -2 /)!!0)#)!) , < & / %' - 64 ' 4 44 . ' d,5 !e+9; 5 ! & 135' : ) & 13 : + 9;9 5 ! & 13'5 : ) & 13'5 : + 9,7!d. & & 3 1#&' . 6e ' 1 554 : 31 + ! & 13 # ' 4' 1 ) & 13 # ' 4' 1 + 9,7)d1#&' & e ' 1 554 : 31 + ) & 13 ' 4' 1 ! & 13 # ' 4' 1 + 9 ' 4 . ' ' 1 7' d1#&' : e 135' 3& ' 4' 1 +94 ' )! ' 1)+94' !) ' 1 !+ , < & /)!!0)#)!) ! " %, ( " ) 2() * %' &1 4. 3 '5 : 3'5 : +%'4 4 . 3 3' . 1 63' < . + ='. d%-)-)e ';9 ,7 5 ' 31 ' . 1 4 .# +9 ='. ' % &5 . 1 d '5' '& &4 & 5 .. e+9'. ' . 3 13& ' & 5 .. &1 4 1 5 # . & 9%c=l>=% .+ %' &1 4 &16+9'. %-< -<. ='. + : &16 . ' . ' : -<5 d - &1 ' ' 5'%- + : ' & # data nrz nrzi fm1 fm0 manchester 1 10 0 0 1 /)!!0)#)!) , < & 0 &+ &16 6 3' 3' < . '; ;9 ,7 54' .+ !6! ! !6! () %' j1 3 : '5'& 16##16< 4 . .-.b 13!)# &13! #1 ,9,+' 1 d' 5'! 1<e & : ' <7 ' 1 3 4 . . 3'' /> -.# ' . 5 +, '< 4 . !$#113 c 1 +%' 13 1 ' 5' 5 " 0+ 5 " 0 3 1 ' ' < ,9, 1 +%' !)-! ,9, & 4 .' #13 : ,9,+ ' ' ' . 1 ' 5 ! d!e 13 4 ' < 4 . ' !)-! 1,9,+%' 5 . ' <7 4 ' -4 . . . 3 ' ' />: 4 '' . 5 & & 3 : + .. b5' & f : .1 ' 5'13 ,9,1 4 1 5 4 . . 3 13' <7 +' 4 5 : ' 4 < 4 . ' 4 . 13 4 .' !$#1 4: 1 ' ,9,4 : 413' />+%' ' 6 . 3 & & 4 ' -4 . ''1 5.. 3+ ' 13 : 4 '4 . ' . 5 5 3: 4 . +4 .4 &!)4 . 1 4 ,9,: + 944 . . ' ?% ' 13 ' ,9, ' 4 ' -4 . + , < & /)!!0)#)!) ' !6! , 1 54' ,9,& 4 ' 1 6 5 .,5 !+ ( %',9,.& . 1 ' ! 1< ' ' < c< . +' ' 5 13&' ,9, 5 3' 1 # 4 d' ,9,& 5 ' ' 1 ' 5'' & # e+' ' ,9,. # 1 ' .&1 '' ;7*)+ %' ,9,. 1 & #&d!< ) e+%' 44 416 .&1 3' 5 '$.5 4) .5 4! " .5 4 0.5 4+, ' 4' 5 4 ,5 !"+%' 4' ,9,=1 5 1 13 5! 1<+94' ,9, 1 ' 1 !f' + 4 ' !1< ' ,9, .&3 ' - 5 ! 5 0 " 4 .' ,9,+ 5 5 ! 4' ,9, 1 . .&3+ 4 5' 13 ' # ' +? 4 ' ,9, 4 # 1 +9' ' . & - ' 5 34 .' 5 + 4 .0 " 1' 4 +?<"40d,9,< : # 1 e . 4 .54 .' ,9, 3 4 .' 5 '' ! ' ' ,9, .&3+; 1 ' ,9,+%' / # /)!!0)#)!) , < & 3 =,113&' ,9,+1 ' 5'' ,9, ?de : = + ! " % ! !6! over equal reset on flag detect increment on byte detection enable count in sdlc end of frame signal status read comp tail pointer 4-bit counter head pointer 4-bit counter 4-bit comparator 14 bits byte counter frame status fifo circuitry 5 bits fifo array 10 deep by 19 bits wide scc status reg residue bits (3) overrun, crc error rr1 5 bits en 6 bits 8 bits 6-bit mux 2 bits eof = 1 6 bits rr1 bit 7 bit 6 bits 5-0 rr6 fifo enable rr7 d5-d0 + rr6 d7-d0 byte counter contains 14 bits for a 16 kbyte maximum count rr7 d6 fifo data available status bit status bit set to 1 when reading from fifo rr7 d7 fifo overflow status bit msb pf rr(7) is set on status fifo overflow wr(15) bit 2 set enables status fifo in sdlc mode the following definitions apply ? all sent bypasses mux and equals contents of scc status register ? parity bits bypasses mux and does the same ? eof is set to 1 whenever reading from the fifo interface to scc , < & /)!!0)#)!) 9 %' 4 & 4' 13 ,9, 5 ' 5 ' 4 5 +! " !d # 5"& e+ 5& : ' ,9,4 .1 5 .& 13. & 4 .!+%' 4 .! ' ' ,9, .&3c4 1d)"e ' . & - 4 .' . 5 4' ,9,d ' ,9, .&3e+%' 4 .! 31 4 .' ,9,d4' ,9, .&3 5 & # : ,9, 4 e+ = ' ' 4< 4 . d=,e : ' ,9, 1 ' 4' 13 # 5 ' ,9,+%' =,5 . ' ,9,+94' ,9,: 4 0 1<0d,9,: 4 e ' : 4 +%'1 ' ,9, 5 13 1 5 # 1 5' ,9, 1d! 1)e+, 4,9, .5 5< 4 . 4 ,5# !$+ ! " %/ 1. " don ? t load counter on 1st flag reset byte counter here reset byte counter load counter into fifo and increment ptr internal byte strobe increments counter reset byte counter internal byte strobe increments counter reset byte counter load counter into fifo and increment ptr f ad d dd c c f 07 0 f add dd c c f 07 0 /)!!0)#)!) , < & / " " %' 5 '' ' & # 5 .. 13' 3 . & 345 ' 4 & # 34' ' + 9' ' 5 3 13 5 5'' 5 +%' ' 4 ' 5 4' & ' 5 4' 5# 5' 5 .31 '4'+ %' & 1 . 3 4 ' & ')d )e 5+ 5 3 1 + .. )? ' ' ' & ' c 1' 1 554 3 +9' '45'. ' ' c?6 4 . <) ' 4 <5 +9' '4 4. ' ' c?6 4 . < ' 4 <)5 + <0 <" 35 1 ' 5 & <$# , < & /)!!0)#)!) /% 6 b %' 3 .& 5 .4 4.. b ' 1. 4& +%'4 13' .. 43 '' . +, -.& ' 3' . ' 5' 6 .1 4& 1 : & 3.1 4 +%' &. 4 3 ' : . 1 + = 4 " %' ! 5 4 ' *) ) ' ' !"4 ' * )d . 5 45' .144 e '' +%' 5 & # 5 .. & 345 ' 4 h& 3i4' ' +%' 5 d e' 13' ' ' ' 5' ' 4' .+# ' &: 4 1'' ' ' & 1 .. +,5 !' 5'!* &' 4 .4 ' 5 + /)!!0)#)!) , < & /, ! " % = 4 " 1 ! register 0 * 0 0 01 1 0 1 1 0 0 0 1 1 0 1 1 null code null code null code null code null code * b channel only reset rx crc checker reset tx crc checker reset tx underrun/eom latch reset ext/status interrupts send abort enable int on next rx character reset tx int pending error reset reset highest ius select shift left mode select shift right mode 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 write register 0 (multiplexed bus mode) d7 d6 d5 d4 d3 d2 d1 d0 write register 0 (non-multiplexed bus mode) null code 0 0 0 1 1 0 1 1 * with point high command reset rx crc checker reset tx crc generator reset tx underrun/eom latch register 1 register 2 register 3 register 4 register 5 register 6 register 7 register 8 register 9 register 10 register 11 register 12 register 13 register 14 register 15 * 0 00 00 00 0 00 0 0 000 0 0 0 0 0 0 0 0 0 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000 00 00 0 00 0 0 1 11 1 1 1 1 1 1 1 1 1 null code point high reset ext/status interrupts send abort (sdlc) enable int on next rx character reset tx int pending error reset reset highest ius d7 d6 d5 d4 d3 d2 d1 d0 write register 1 0 0 0 0 1 1 1 1 ext int enable tx int enable parity is special condition rx int on special condition only int on all rx characters or special condition rx int on first character or special condition wait/dma request on receive /transmit rx int disable wait /dma request function wait/dma request d7 d6 d5 d4 d3 d2 d1 d0 write register 2 v0 v1 v2 v3 v4 v5 v6 v7 interrupt vector d7 d6 d5 d4 d3 d2 d1 d0 write register 3 rx enable sync character load inhibit address search mode (sdlc) rx crc enable enter hunt mode auto enables 0 0 0 0 1 1 1 1 rx 5 bits/character rx 7 bits/character rx 6 bits/character rx 8 bits/character , < & /)!!0)#)!) / ! " %0 = 4 " 1 ! d7 d6 d5 d4 d3 d2 d1 d0 write register 4 parity enable parity even/odd 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 sync modes enable 1 stop bit/character 1 1/2 stop bits/character 2 stop bits/character 8-bit sync character 16-bit sync character sdlc mode (01111110 flag) external sync mode x1 clock mode x16 clock mode x32 clock mode x64 clock mode d7 d6 d5 d4 d3 d2 d1 d0 write register 5 0 0 0 0 1 1 1 1 tx crc enable rts sdlc /crc-16 tx enable send break dtr tx 5 bits (or less)/character tx 7 bits/character tx 6 bits/character tx 8 bits/character /)!!0)#)!) , < & // ! " %' = 4 " 1 ! d7 d6 d5 d4 d3 d2 d1 d0 write register 6 sync7 sync1 sync7 sync3 adr7 adr7 sync6 sync0 sync6 sync2 adr6 adr6 sync5 sync5 sync5 sync1 adr5 adr5 sync4 sync4 sync4 sync0 adr4 adr4 sync3 sync3 sync3 1 x adr3 sync2 sync2 sync2 1 x adr2 sync1 sync1 sync1 1 x adr1 sync0 sync0 sync0 1 x adr0 monosync, 8 bits monosync, 6 bits bisync, 16 bits bisync, 12 bits sdlc sdlc (address range) d7 d6 d5 d4 d3 d2 d1 d0 write register 7 sync7 sync5 sync15 sync11 monosync, 8 bits monosync, 6 bits bisync, 16 bits bisync, 12 bits sdlc 0 sync6 sync4 sync14 sync10 1 sync5 sync3 sync13 sync9 1 sync4 sync2 sync12 sync8 1 sync3 sync1 sync11 sync7 1 sync2 sync0 sync10 sync6 1 sync1 x sync9 sync5 1 sync0 x sync8 sync4 0 d7 d6 d5 d4 d3 d2 d1 d0 wr 7 ? prime (85c30 only) auto tx flag auto eom reset auto rts deactivation force txd high dtr /req fast mode complete crc reception extended read enable reserved (program as 0) , < & /)!!0)#)!) / ! " % = 4 " 1 ! 0 0 0 0 1 1 1 1 d7 d6 d5 d4 d3 d2 d1 d0 write register 9 no reset channel reset b channel reset a force hardware reset vis nv dlc mie status high/status low software intack enable d7 d6 d5 d4 d3 d2 d1 d0 write register 9 0 0 0 0 1 1 1 1 nrz nrzi fm1 (transition = 1) fm1 (transition = 0) crc preset i/o go active on poll mark/flag idle abort/flag on underrun loop mode 6-bit/8-bit sync d7 d6 d5 d4 d3 d2 d1 d0 write register 11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 trxc out = xtal output trxc out = transmit clock trxc out = br generator output trxc out = dpll output trxc o/i transmit clock = rtxc pin transmit clock = trxc pin transmit clock = br generator output transmit clock = dpll output receive clock = rtxc pin receive clock = trxc pin receive clock = br generator output receive clock = dpll output rtxc xtal/no xtal d7 d6 d5 d4 d3 d2 d1 d0 write register 9 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 lower byte of time constant upper byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 write register 13 tc8 tc9 tc10 tc11 tc12 tc13 tc14 tc15 d7 d6 d5 d4 d3 d2 d1 d0 write register 14 br generator enable br generator source dtr /request function auto echo local loopback 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 null command enter search mode reset missing clock disable dpll set source = br generator set source = rtxc set fm mode set nrzi mode d7 d6 d5 d4 d3 d2 d1 d0 write register 15 0 zero count ie sdlc fifo enable dcd ie sync/hunt ie cts ie tx underrun/eom ie break/abort ie /)!!0)#)!) , < & /0 4 4 " %' 5 d : 5' : 144 d*e '' e+, 4' .31 1 4 .d) ! !) !e+% 5 d! !e ' ? . + ' ' . 4 &: d ' e ' : . 4 134 .d ' ?e+' 9 &/ 5d9/e1d ' 3m ,5 ! e+" 0' 4 .' < , . ,9, 1 3 ' !< d,5 ! )e+ , < & /)!!0)#)!) /' ! " %9 4 4 " 1 ! d7 d6 d5 d4 d3 d2 d1 d0 read register 0 rx character available zero count tx buffer empty dcd sync/hunt cts tx underrun/eom break/abort d7 d6 d5 d4 d3 d2 d1 d0 read register 1 all sent residue code 2 residue code 1 residue code 0 parity error rx overrun error crc/framing error end of frame (sdlc) d7 d6 d5 d4 d3 d2 d1 d0 read register 2 v0 v1 v2 v3 v4 v5 v6 v7 interrupt vector * * modified in b channel d7 d6 d5 d4 d3 d2 d1 d0 read register 12 tc0 tc1 tc2 tc3 tc4 tc5 tc6 tc7 lower byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 read register 10 0 on loop 0 0 loop sending 0 two clocks missing one clocks missing d7 d6 d5 d4 d3 d2 d1 d0 read register 3 channel b ext/status ip channel b tx ip channel b rx ip channel a ext/status ip channel a tx ip channel a rx ip 0 0 * * always 0 in b channel /)!!0)#)!) , < & / ! " , 4 4 " 1 ! " %' 5 5 4 .' < ' / k+/ k'&' '& ' < ' 35 5' 5 & # : . 4 . #1 && +%'5: : 3. / k+%' : 3. && 3 1 1 : :5' +%' : 3. 4 & & & & 4 4 .' 4 5 5 4 < ' 4 : :5' ' 4 5 5 4 < ' : :5' + %'. .1 / k 5 4 '' 5 ' 1 5 + 4 . " ,5 ! 3 .5+ c? +94 = 4 4 < 4 4 = 1 4 < ' 44 : < ' + d7 d6 d5 d4 d3 d2 d1 d0 read register 13 tc8 tc9 tc10 tc11 tc12 tc13 tc14 tc15 upper byte of time constant d7 d6 d5 d4 d3 d2 d1 d0 read register 15 0 zero count ie 0 dcd ie sync/hunt ie cts ie tx underrun/eom ie break/abort ie , < & /)!!0)#)!) /9 ! " ,% 4 . " = . " ,5 3 .5+ c? +94 = 4 4 4 4 = 1 4 ' 44 : ' + d7 ? d0 data valid rd ce intack a/b , d/c address valid /)!!0)#)!) , < & ! " ,, = . " 6 2*$ " . " ,5 9 & 6 5 3 .5+? ' . 9;% k 5 ' 4 5 5 4< ' - 9=9c9= 3' +94' & & 5' 9=95' ' < 4 ' 6 # 5 3 4 ' +9' ' .31 & 5 .. & < 13& 5 &: <0#<)+9' ' && & 9 &#> # : ' 3+94' - 3' & . # p* ' && 3 3' ' +94' - 3' ' ' 4 # ' ' c %.5%1 $g $gg $ a <a <0#<) = 9;% k c? < & /)!!0)#)!) % ; 5/5 "4 5' 3#' . + ! " , 6 2*$ " . " " %' 5 5 4 . < ' / k+? / k'&' '& ' < ' 35 5' 5# .& : . 4 . 1 && +%' 5: : 3. / k+%' : 3. && 31 1 : :5' %' : 3. 4 & & & & 4 4 .' 4 5 5 4< ' 4 : :5' ' 4 5 5 4< ' : :5' + 4 . " ,5 $ 3 .5+%' <0m <) ' 4 ) 9;% k ' 13' 5 5 4 +c.1 5' 3 + !. 1 5'4 ' 3 +%' 1 : ' ' 1 ' < + d7 ? d0 rd intack vector /)!!0)#)!) , < & , ! " ,/ 4 . " = . " ,5 3 .5+%' <0m <) ' 4 ) 9;% k ' 13' 5 5 4 +c .1 3 + !.1 5' 4 ' 3 < 1 ' ' + intack ds as cs0 r/w cs1 ad7 ? ad0 address data valid , < & /)!!0)#)!) ! " , = . " 6 2*$ " . " ,5 " 9 & 6 5 3 .5+%' <0m <) ' 4 ) 9;% k ' 13' 5 5 4 +949;% k ' ) 5 +%' 4' c ! 5 4 ' 4' 9 & 6 5 3 + ? ' 5 5 4 ' 4 5 5 4< ' # - 9=9c9= 3' +94' & & 5' 9=95' ' < 4 ' 6 # 5 3 4 ' +9' ' & # intack ds as cs0 r/w cs1 ad7 ? ad0 address data /)!!0)#)!) , < & / 5 .. & < 13& 5 &: <0#<) 3 5' && & 9 &#> # # : '+ ! " ,0 6 2*$ " . " ad7 ? ad0 ds (ignored) (ignored) vector as cs0 intack /)!!0)#)!) 1 7-..5 $ % 2 : 4 " 5 '' 1 7-..# 5.3 & . .5 ' : %' 5 3+& 4' : 3 1: ' ' & 4' & 4 .& +=-& 1 .-.. 5 4 - & .344 : 1 3+ %' < ' & 1 && 34 ' 4 5 ' + : 5 4 ;<+/: 4 ' 4# &+ 4 ,5 0 *+ + o$+)a a ff o+)a + ;<q)a + % $ & 4 594 . a&& 3a 5 5 #)+ao0+)a a 5 & ' & ;< #aa o)+a % $ & 5 .1 % .& 594 . 5 % .& #"r o!)r /)!!0)#)!) = ' 0 ! " ,' ! " , a 100 pf 250 m a 2.1 k w from output under test from output 50 pf 2.2 k w = ' /)!!0)#)!) ' %1 ' & & 1 & + "*)) ) %1 $ ' ' 4 ' *) )c* ) : + . : @ ,1 9& & !) &, d + &,q!7b : & 4 .& 5 + >. / e 1+ >. & + 287 & & ! &, ,2 ? & ) &, /)!!0)#)!) = ' / ) . . : @ a ,+ 9&5' a 5 + a && o)+ d + a && qa!)s ' & 4 : & 4 .& 5 + a a ,/ 9& a 5 #)+ )+* a a 2+ &5' a 5 +$ a 9 2+ q#!+". a 2+ &5' a 5 a && #)+* a 9 2+ q#) a 2/ & a 5 )+$ a 9 2/ qo+). 9 ,/ 9& 65 !)+) )+$a ,1 o+$a 9 2/ & 65 !)+) )+$a 287 o+$a 9 && a && && 3 e 1+ %3& 9 && . ' 44+ 0 !d!)7be . a && qaa ,+ q$+*a ,/ q) !d!"+*$7be . 3 44 9 &&26& 3 f + ;9 && d e.-& 4 & 3 - 4 34 + $ . 4 ' 9 && = ' /)!!0)#)!) 9 2) 4 = " " ,5 ' 5' ' * ) c .5 # 5 .+%1 ' * ).5& . + /)!!0)#)!) = ' 0 ! " ,9 4 = " " pclk a/b , d/c intack ce rd d7 ? d0 read wr d7 ? d0 write w /req wait w /req request dtr /req request int 6 1 2 5 11 13 10 16 19 22 active valid 23 25 27 28 31 29 32 33 34 37 35 36 24 26 17 20 30 3 4 7 10 15 18 12 14 9 21 = ' /)!!0)#)!) 0% ! " 6 2*$ " " " ! " % . " " d7 ? d0 int pclk intack rd iei ieo 41 38 10 23 active valid 10 14 24 26 42 40 38 15 45 44 43 ce 49b 49b 49a pclk rd or wr /)!!0)#)!) = ' 0, ! " , 4 " " 4 = " 7 . cb %cb %0cb : : : ! % / 9 / k ' $ ))) $) ))) " ))) % / ' / k5' ' $ ))) $) ))) " ))) %4/ / k, %. !) !) $ % / / k %. !) !) %/ / k 3 %. !!* $))) !)) $))) "! $))) " % de , &%. "" ) 0 %' de %. ))) * % d = ' /)!!0)#)!) 0 !! % de d 9;% k , &%. !$) !) 0) ! %'9 de 9;% k %. ))) ! % d %. * ) ! !" % =9de = , &%. ))) !0 %' =de = %. ))) !* % ='de = 5' , &%. * ) ) ! % =9d 3 ))) 4 = "> ? 7 . cb %cb %0cb : : : /)!!0)#)!) = ' 0/ $ % < d<e < < ;a < 3 ))) % <9d<e < , <a < 3 ! !) 0) " % 3 * ) 0 % d<e < a < 3 !) !") !)) * % 9 ' !$ ! 0 % d<e , <a < 3 ) ) %'<de < %. ))) ! % de e , a < 3 !"* !)) ) % < 3 !"* !)) ) % 4d=le , c=l ;a < 3 !"* !) 0) $ % <4d=le f < , c=l ;a < 3 !"* !) 0) % d=le , <% c =l ;a $%/ $%/ $%/ 1 % d=le , <% c =l ;a !"* !)) 0) 4 = "> ? 7 . cb %cb %0cb : : : = ' /)!!0)#)!) 0 " % < =le < <% c =l ;a < 3 ; ; ; 0 % / d9;%e / k, 9;% a < 3 )) ) !0 * % 9 d 3 !$ ) ) % < < d 6 5 e ' !$ ! 0 $) % < d<e < , d 6e <a < 3 ! !) 0) $! %=9d< e 9=9< , d 6e &%. *) ) $ %'9=9d< e 9=9< d 6e %. ) ) ) $ % 9= 9=e 9=99=< 3 %. *) $ $$ % / d9=e / k 9= < 3 ! !0 *) $ % < d9;%e < , 9;% 9: < 3 $*) ) )) $" % < le < , < 34 ; ! ! !) 4 = "> ? 7 . cb %cb %0cb : : : /)!!0)#)!) = ' 00 ,5 ' * )5 .5 5 .+%1 " ' * )5 .5' +* )3 ..5 ' ,5 $ 1 %1 0+%1 *& : * ) c .5' + ,5 ' 5'0 *) ) c .5 & 6 5 .5 .5 & : 3+%1 & # : *) ) c .5' + $0 % ld 34 ; ! ! !) $* % = < 4 !$ !)) 0 $ % h a : 3%. +%/ +%/ +%/ $ 1 % i < , / , & %. ) ) ) + / . && 39 & 6 5 + 1+ & # & . '& # + + / . && ' . 3d0j<$q!e+ + / . 3 . & +, 3 ' 3' % 9 d 31 : :5' * )!$*) 4c< 4 5 5 3' b / k4 5 5 ' % q%/+ 4+ %'& 4 3&& 1 ' a : 3%. '/ k+ 4 = "> ? 7 . cb %cb %0cb : : : = ' /)!!0)#)!) 0' ! " & " " sync input cts /trxc dcd cts /trxc rtxc cts /trxc output 22 22 22 22 20 18 19 16 17 14 15 1 2 6 7 4 5 8 9 3 12 11 13 txd rtxc transmit cts /trxc , sync external 10 rxd rtxc receive cts /trxc , w /req wait w /req request pclk /)!!0)#)!) = ' 0 0 & " 7 . cb %cb %0cb : : : ! % / d=le / k c=la ) !) *) % / de / k 9: ) ) !*) %n d/ e - / k & %. de ;c ;c ;c $ %n %. %/ %/ %/ !) %%n d/ e %- / k & %. gh ;c ;c ;c !! % %n 4d%n %. k $** $)) $$ = ' /)!!0)#)!) 09 !"1 %%nd=e %- 3 %. ! !)) !+ !0 %%nn 3 +/ l ! !))) !)) !))) " !))) !* % %n' %- 5' ' !) !) !*) ! % %n9 %- ' !) !) *) ) %%n %- 3 %. $** $)) $$ ! % =n% < < % / ' )) !) 0) % @ @; / ' )) !) 0) + - %- %- '' : && 35' : 6+ 1+ 3' b4- / k . : 134 & + + / . && 3,7 5c 5+ + %- %- c%- '' : && 35' . 6+ + =- / k%- %- 3' b . . 4 / k : #13#4 & +%- %- 4 . / k+ 4 .5& %4/ % / +%- -& 6 ' 1 6 &.-..4) + & . & k 5 ' 1 4 ' & ''' 1 5 '' : + 4+ / . && 34 . : f / k . + 5+ =; ; =<,= %>=t%- & 3+ '+ %' .-.. : . !c$/ k+ + ?'%- @; ': )&,& 5 + *) )5 .5' ,5 * '& . & # : %1 !)+*) )3 ..5' ,5 ' & . & : %1 !!+ 0 & " > ? 7 . cb %cb %0cb : : : /)!!0)#)!) = ' ' ! " / . " " 10 int sync input int cts , dcd dtr /req request wai t w /req request w /req trxc , rtxc transmit int sync output wait w /req request w /req rtxc , trxc receive 9 8 7 6 6 4 3 1 2 = ' /)!!0)#)!) '% ' . " 7 . cb %cb %0cb : : : ! % n d=le - 5' c=l a de + - %- %- '' : && 35' : 6+ 1+ > %/+ * ! * ! * ! % n de - 5' 9: f + & # & . '& # + * !$ * !$ * !$ % n d@e - 5'@; a $0$0$0) $ %n d9;%e - 5'9;%a !) !" !) !" !) !" % %n d=le %- c=l a g + %- %- %- '' : && 35' . 6+ * * * " % %n de %- 9: !!!!!! 0 % %n d<le %- <% c=l a $ 0 $ 0 $ 0 * % %n d9;%e %- 9;% a " !) " !) " !) % @d9;%e @; 9;%a " " " 1 % @d9;%e @; 9;%a h + > + !) % =n%d9;%e < < % 9;% a " " " /)!!0)#)!) = ' ', 4 = " 7 . cb %cb %0cb : : : ! % / 9 / k ' $ ))) $) ))) " ))) % / ' / k5' ' $ ))) $) ))) " ))) %4/ / k, %. !) !) $ % / / k %. !) !) %/ / k 3 %. !!* $))) !)) $))) "! $))) " % de , & %. "" ) 0 %' de %. ) ) ) * % d = ' /)!!0)#)!) ' ! " 4 = " " wait w /req request pclk 42 40 41 43 44 44 27 int dtr /req request w /req 25 26 24 22 15 15 16 17 16 12 13 19 21 ad7 ? ad0 read ad7 ? ad0 write ds 12 write r /w write r /w read intack 7 8 9 cs1 cs0 7 4 4 14 6 10 10 18 20 23 2 as /)!!0)#)!) = ' '/ ! " 0 6 2*$ " " " ! " ' 4 " " int ieo iei 36 35 34 32 31 22 33 20 30 19 29 8 7 ad7 ? ad0 ds intack as ds as 37 38 35 = ' /)!!0)#)!) ' 9 4 = " d 7 . cb %cb : : ! % ' ) % <d e < , < 3 e ! !) % d e ) &%. ) ) $ %' d e ) %. ) ) % !d<e !< , &%. " ) " %' !d<e !< %. ) ) 0 % d e 9;% k &%. !) !) * %'9 d e 9;% k %. !) ! %d<ec d e< , & %. " ) !) %'d<e c < %. ) ) !! %d<e c d e< , & %. ) ) ! % d<e < , < 3 ) ) ! % <9 < ' !) ! !$ % a : 3%. f $%/ $%/ ! % d e & %. !) !) !" %' d e %. ) !0 %<d<e << , & %. ! !) !* %'<d<e << %. ) ) /)!!0)#)!) = ' '0 ! % <d< e < , < : < 3 ) ) ) % < d<e < <;a < 3 ) ) ! % <4d<e < , <a < 3 !$) !) % d<e <a < 3 ) ! ) % <d<be < <, < 3 g $) $ % d<e a <a < 3 ") !) % <de < , a < 3 h !0) !") " % <4d=le < , c=l ;a < 3 !0) !") 0 % < d=le < , <% c=l ;a < 3 $%/ $%/ * % d9;%e 9;% a < 3 )) )) % d< e < , d 6 5 e< 3 i ) ) % < < d 6 5 e ' !) ! ! % < d<e < , d 6 5 e <a < 3 !$) !) %=9d< e 9=9< , d 6 5 e &%. *) *) 9 4 = " d > ? 7 . cb %cb : : = ' /)!!0)#)!) '' %'9=9d< e 9=9< d 6 5 e %. ) ) $ % 9=9d9=e 9=99=< 3 ) ) % d9=e 9=< 3 j )) !0 " % < d9;%e < , d 6 5 e9;% 9: < 3 $) $) 0 % <d le < , < 34 ; ! ! * % ld<e < , < 34 ; ) ! % = < 4 k !) !)) $) % / 9 / k ' ) !))) $) !))) $! % / ' / k5' ' ) !))) $) !))) $ %/ / k 3 %. ! ))) !)) ))) $ % / / k %. !) !) $$ %4/ / k, %. !) !) + > de ' + 1+ / . && 39 & 6 5 + + / . && 31 : :5' + + , 3 4 ' . 4 )+a'5 ' & '.-.. < ... + + & # & . '& # + 4+ / . 3 . & +, 3# ' 3'+% d< e.1 5 '' .4% d9=e4 ' '5' & 3 : ' 3'%=9d< e 4 ' # % 9= 4d9=e4 ' : & 5' .' 3'+ 9 4 = " d > ? 7 . cb %cb : : /)!!0)#)!) = ' ' 5+ / . && 3# & 59;% ' 1 554' 9 & 6 5 + '+ 9 3 4 ' & : 13' ?1 5b 13' # + .5 4 . )a4 5h!i )*a4 5h)i+ ,5 * & 3*) )5 .5 %1 !) ' 5 .5' +,5 & 3' *) )3 ..5 '' & . % 1 !! + = ' /)!!0)#)!) '9 ! " & " " sync input 22 22 22 22 cts , dcd trxc rtxc trxc output trxc , rtxc transmit sync external rxd rtxc , trxc receive w /req wait w /req request pclk 20 19 18 16 17 14 15 13 8 11 10 9 4 5 6 3 7 1 2 12 txd /)!!0)#)!) = ' % & " d 7 . cb %cb : : ! % / d=le / k c=la ) )) %/ de / k 9: ) )) %n d/ e - 5' / k 5' & %. ef ; ; ; ; $ %n %. %/ %/ !) %%n d/ e %- / k 5' & %. h ; ; !! % %n 4d%n %. j $0 $)) !"1 %--d %. 7 k ) !0 %%nn 3 +/ l !!* !))) !)) !))) !* % %n' %- 5' ' !) !) = ' /)!!0)#)!) % ! % %n9 %- ' !) !) ) %%n %- 3 %. $0 $)) ! % =n% < < %/ ' )) !) % @ @; / ' )) !) + > de' + 1+ - %- d%- '' : && 35' : 6+ + 3' b4- / k . : 134 & + + / . && 3,7 5c 5+ + %- %- %- '' : && 35' . 6+ 4+ / . && 34 . : f / k . + 5+ %' .-.. : . !c$/ k+ '+ && 6 37-.. 4!c$/ k && 6 ' ': )s 33 + + ?'%- @; ': )&4& 5 ' .+ % & " d > ? 7 . cb %cb : : /)!!0)#)!) = ' , ! " 9 . " " sync input cts , dcd trxc rtxc trxc output txd trxc , rtxc transmit sync external 22 22 21 21 20 18 19 17 18 14 15 11 10 12 rxd 10 rtxc , trxc receive w /req wait 9 8 4 5 3 w /req request pclk 6 7 2 1 = ' /)!!0)#)!) %% . " 7 . cb %cb : : ! % n d=le - 5' c=l a de + - %- %- '' : && 35' : 6+ 1+ > %/+ *!*! % n de - 5'9: f + & # & . '& # + * !$ * !$ % n d@e - 5'@; a $ 0 $ 0 $ % n d9;%e - 5'9;%a * ! * ! ; g + > + % %n d=le %- c=l a h + %- %- %- '' : && 35' . 6+ ** " % %n de %- 9: !! !! 0 % %n d<le %- <% c=l a $ 0 $ 0 * % %n d9;%e %- 9;% a $ " $ " ; % @d9;%e @; 9;%a " " 1 % @d9;%e @; 9;%a !) % =n%d9;%e ; /)!!0)#)!) = ' / /)!!0)#)!) /655 5 &' ( ( *" 6 ,5 $) $! ' $)#&<9/&65 $$#& / &65 5 .+ ! " / /a 6*" " /)!!0)#)!) /655 5 / ! " /% //a *" " "6 %1 !& : 54 .4 ' *) ) ' * ) : + /655 5 /)!!0)#)!) *" /q/ <9/ aq/ '& <q .<9/ =q#$)r o!))r q)ro0)r *q*7b !)q!)7b !"q!"7b (# q/ %, "6 cb %cb %0cb *) ))*/ *) )!)/ * )!"/ *) ))*a *) )!)a * )!"a * ))*/ c/= * )!)/ c/= * ))*a ;= * )!)a ;= /)!!0)#)!) /655 5 0 (: d example environmental flow temperature package speed product number zilog prefix is a z80c30, 16 mhz, plcc, 0 ? c to +70 ? c, plastic standard flow z 80c30 16 p s c |
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