ics650-36 mds 650-36 d 1 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com networking & pci clock source description the ics650-36 is a low cost frequency generator designed to support networking and pci applications. using analog/digital phase locked-loop (pll) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 mhz to produce four output clocks supporting lan, pci, and 100m sdram functions. the device also has a power down feature that tri-states the clock outputs and turns off the pll when the pdts pin is taken low. features ? packaged in 16-pin tssop ? available in pb (lead) free package ? replaces multiple cr ystals and oscillators ? input crystal or clock frequency of 25 mhz ? fixed reference output frequency of 25 mhz ? selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 mhz ? duty cycle of 40/60 ? operating voltage of 3.3 v ? advanced, low-power cmos process ? industrial and commercial temperature ranges block diagram x1/iclk x2 pll1 pll2 crystal oscillator/ clock buffer 25 mhz crystal input external capacitors may be required. vdd gnd pdts (all outputs and plls) clk1 3 3 pll3 clk3 clk2 ref select/ control circuit 3 s2:0
networking & pci clock source mds 650-36 d 2 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 pin assignment clk output selection table note: all frequencies are in mhz. pin descriptions 12 1 11 2 10 3 9 x2 4 x1 5 gnd 6 gnd 7 clk3 8 pdts ref s0 vdd s2 clk1 s1 clk2 gnd 16 15 14 13 vdd vdd 16-pin (173 mil) tssop s2 s1 s0 ref clk1 clk2 clk3 0 0 0 off 33.30 50 125 0 0 1 on 33.333 33.333 125 0 1 0 on 33.333 66.666 125 0 1 1 on 66.666 66.666 125 1 0 0 on 33.333 50 125 1 0 1 on 33.333 50 100 1 1 0 on 33.333 66.666 100 1 1 1 on 33.30 50 125 pin number pin name pin type pin description 1 x2 output crystal connection. connect to 25 mhz crystal input or float for clock. 2 x1 input crystal connection. connect to 25 mhz crystal or clock input. 3 gnd power connect to ground. 4 clk3 output selectable clock output. see table above for frequency. weak internal pull-down when tri-state. 5 pdts input powers down entire chip and tri-states outputs when low. internal pull-up resistor. 6 s2 input select pin. selects clock output frequency from table above. internal pull-up resistor. 7 clk2 output selectable clock output. see table above for frequency. weak internal pull-down when tri-state. 8 vdd power connect to +3.3 v. 9 s1 input select pin. selects clock output frequency from table above. internal pull-up resistor. 10 gnd power connect to ground. 11 clk1 output selectable clock output. see table above for frequency. weak internal pull-down when tri-state. 12 vdd power connect to +3.3 v. 13 s0 input select pin. selects clock output frequency from table above. internal pull-up resistor.
networking & pci clock source mds 650-36 d 3 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 external components decoupling capacitor as with any high performance mixed-signal ic, the ics650-36 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between each vdd and the pcb ground plane. series termination resistor clock output traces over one inch should use series termination. to series terminate a 50 ? trace (a commonly used trace impedance), place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very shor t pcb traces (and no vias) between the crystal and device. crystal capacitors must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -6 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each cryst al capacitor would be 20 pf [(16-6) x 2 = 20]. pcb layout recommendations observed the following guidelines for optimum device performance and lowest output phase noise: 1) the 0.01f decoupling capacitors should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between the decoupling capacitors and vdd pins. the pcb trace to vdd pins should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. the x1 and x2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. 3) place the 33 ? series termination resistor (if needed) close to the clock output to minimize emi. 4) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the ics650-36. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 14 ref output reference 25 mhz clock output. weak internal pull-down when tri-state. 15 gnd power connect to ground. 16 vdd power connect to +3.3 v. pin number pin name pin type pin description
networking & pci clock source mds 650-36 d 4 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the ics650-36. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd -0.5 v to 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (commercial) 0 to +70 c ambient operating temperature (industrial) -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 +70 c ambient operating temperature (industrial) -40 +85 c power supply voltage (measured in respect to gnd) +3.135 +3.3 +3.465 v
networking & pci clock source mds 650-36 d 5 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c ac electrical characteristics unless stated otherwise, vdd = 3.3 v 5% , ambient temperature -40 to +85 c note 1: measured with a 15 pf load. parameter symbol conditions min. typ. max. units operating voltage vdd 3.135 3.3 3.465 v supply current idd no load, pdts =1 25 ma power down current iddpd no load, pdts =0 100 a input high voltage v ih pdts , s2:0 2 v input low voltage v il pdts , s2:0 0.8 v output high voltage v oh i oh = -4 ma vdd-0.3 v output high voltage v oh i oh = -12 ma 2.4 v output low voltage v ol i ol = 12 ma 0.4 v short circuit current i os clock outputs 65 ma input capacitance, inputs c in 5pf nominal output impedance z out 20 ? internal pull-up resistor r pu pdts , s2:0 500 k ? internal pull-down resistor r pd outputs 250 k ? parameter symbol conditions min. typ. max. units input frequency f in 25 mhz output rise time t or 20% to 80%, note 1 0.8 ns output fall time t of 80% to 20%, note 1 0.7 ns output clock duty cycle at vdd/2, note 1 40 60 % absolute clock period jitter note 1 125 ps clock jitter, cycle-to-cycle 33.333m, 66.666m, note 1 150 ps clock jitter, long term 25m, n=1000, note1 900 ps frequency synthesis error 0 ppm output enable time t oe pdts high to output locked to 1% 350 s output disable time t od pdts low to tri-state 25 ns
networking & pci clock source mds 650-36 d 6 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 thermal characteristics marking diagrams (ics650g-36) (ICS650GI-36) (ics650g-36lf) (ICS650GI-36lf) notes: 1. ###### is the lot code. 2. yyww is the last two digits of the year, and the week number that the part was assembled. 3. ?lf? or ?l? designates pb free packaging. 4. ?i? designates industrial temperature range. 5. bottom marking: (origin). origin = country of origin if not usa. parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 78 c/w ja 1 m/s air flow 70 c/w ja 3 m/s air flow 68 c/w thermal resistance junction to case jc 37 c/w 1 8 9 16 650g-36 ###### yyww$$ 1 8 9 16 650gi-36 ###### yyww$$ 1 8 9 16 650g36lf ###### yyww 1 8 9 16 650gi36l ###### yyww
networking & pci clock source mds 650-36 d 7 revision 030206 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 297-1201 www.icst.com ics650-36 package outline and package dimensions (16-pin tssop, 173 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a "lf" suffix to the part nu mber are the pb-free configur ation and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems (ics) assumes no responsibility for either its use or for the infringemen t of any patents or other rights of third parties, which wou ld result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring ex tended temperature range, high re liability, or other extraordina ry environmental requirements are not recomm ended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices o r critical medical instruments. part / order number marking shipping packaging package temperature ics650g-36 (see page 6) tubes 16-pin tssop 0 to +70 c ics650g-36t tape and reel 16-pin tssop 0 to +70 c ics650g-36lf tubes 16-pin tssop 0 to +70 c ics650g-36lft tape and reel 16-pin tssop 0 to +70 c ICS650GI-36 (see page 6) tubes 16-pin tssop -40 to +85 c ICS650GI-36t tape and reel 16-pin tssop -40 to +85 c ICS650GI-36lf tubes 16-pin tssop -40 to +85 c ICS650GI-36lft tape and reel 16-pin tssop -40 to +85 c index area 1 2 16 d e1 e seating plane a 1 a a 2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.1 0.193 0.201 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
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