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general description the MAX3346E bidirectional transceiver converts logic- level signals to usb signals, and usb signals to logic- level signals. the MAX3346E includes the 1.5k ? usb pullup resistor internally, and supports both full-speed (12mbps) and low-speed (1.5mbps) usb operation. the device has built-in ?5kv esd protection circuitry to guard the usb i/o pins, d+ and d-. the MAX3346E operates with v l voltages as low as 1.65v, ensuring compatibility with low-voltage asics. the device features a logic-selectable suspend mode that lowers current draw to less than 40?. the MAX3346E has an enumerate function that allows devices to logically disconnect while plugged in. the MAX3346E is fully compliant with usb specification 1.1, and the full-speed and low-speed operation under usb specification 2.0. the MAX3346E is available in the miniature 4 x 4 chip- scale package (ucsp tm ), as well as the small 14-pin tssop, and is rated for the -40? to +85? extended temperature range. applications cell phones pc peripherals data cradles pdas mp3 players features ? 15kv esd protection on d+ and d- ? internal linear regulator allows direct powering from the usb cable ? internal 1.5k ? pullup resistor for low/full-speed operation ? supports low-speed and full-speed usb communications ? complies with usb specification revision 1.1 and 2.0 (low speed and full speed) ? three-state outputs ? enumerate input?allows usb connection through software ? no power-supply sequencing required ? operates with v l of 1.65v to 3.6v, ensuring compatibility with low-voltage asics ? available in miniature chip-scale package MAX3346E 15kv esd-protected usb transceiver in ucsp ________________________________________________________________ maxim integrated products 1 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v l vtrm d+ d- vm mode vp rcv top view MAX3346E gnd v cc speed susp enum oe tssop bottom view ucsp v cc v l gnd vtrm d+ d- speed mode rcv susp vm vp enum oe MAX3346E a b c d 1234 pin configurations ordering information 19-3172; rev 0; 2/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX3346Eeud -40? to +85? 14 tssop MAX3346Eebe-t -40? to +85? 4 x 4 ucsp ucsp is trademark of maxim integrated products, inc.
MAX3346E 15kv esd-protected usb transceiver in ucsp 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage (v cc ) ...............................................-0.3v to +6v output of internal regulator (vtrm) ..........-0.3v to (v cc + 0.3v) input voltage (d+, d-) ..............................................-0.3v to +6v system supply voltage (v l ) .....................................-0.3v to +6v rcv, susp, vm, vp, mode, oe , speed, enum ....................................-0.3v to (v l + 0.3v) short-circuit current (d+, d-) to v cc or gnd (note 1) ..........................................continuous maximum continuous current (all other pins) ..................?5ma continuous power dissipation (t a = +70?) 4 x 4 ucsp (derate 7.4mw/? above +70?) .....589mw [b16-2] 1 4-pin tssop (derate 9.1mw/? above +70?) .. 727mw [u14-1] operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? bump temperature (soldering) reflow............................+235? parameter symbol conditions min typ max units supply inputs (v cc , vtrm, v l ) regulated supply voltage v vtrm internal regulator 3.0 3.3 3.6 v v l input range 1.65 3.60 v v cc input range 4.0 5.5 v operating v cc supply current i vcc full-speed transmitting/receiving at 12mbps, c l = 50pf on d+ and d- 8ma operating v l supply current i vl full-speed transmitting/receiving at 12mbps 6ma full-speed idle: v d+ > 2.7v, v d- < 0.3v 340 450 full-speed idle and se0 supply current i vcc ( idle ) se0: v d+ < 0.3v, v d- < 0.3v 390 500 ? static v l supply current i vl ( static ) full-speed idle, se0, or suspend mode 5 a suspend supply current i vcc ( susp ) susp = oe = high 40 ? disable-mode supply current i vcc ( dis ) v l = gnd or open 20 ? d+/d- disable-mode load current i d_(dis) v l = gnd or open, v d _ = 0 or +5.5v 5 a sharing-mode v l supply current i vl ( sharing ) v cc = gnd or open, oe = low, susp = high 20 ? d+/d- sharing-mode load current i d_ ( sharing ) v cc = gnd or open, v d _ = 0 or +5.5v 20 ? linear regulator external capacitor c out compensation of linear regulator 1 f (all voltages referenced to gnd, unless otherwise noted.) note 1: external 23.7 ? resistors connected to d+ and d-. electrical characteristics (v cc = +4v to +5.5v, gnd = 0, vtrm = +3.0v to +3.6v, v l = +1.65v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v, v l = +2.5v, t a = +25?.) (note 2)
parameter symbol conditions min typ max units esd protection (d+, d-) human body model 15 kv iec 1000-4-2 air-gap discharge 10 kv iec 1000-4-2 contact discharge 8kv logic-side i/o input high voltage v ih vp, vm, susp, speed, oe , mode, enum (2/3) x v l v input low voltage v il vp, vm, susp, speed, oe , mode, enum 0.4 v output high voltage v oh i source = +2ma, rcv, vp, vm v l - 0.4 v output low voltage v ol i sink = -2ma, rcv, vp, vm 0.4 v input leakage current vp, vm, susp, enum, oe , mode = 0 or v l 1a usb-side i/o output-voltage low v old r l = 1.5k ? from d+ or d- to 3.6v 0.3 v output-voltage high v ohd r l = 15k ? from d+ and d- to gnd 2.8 3.6 v input impedance z in v d _ = 0 or +3.6v, enum = 0, three-state driver 1m ? ? internal resistor r pullup 1.410 1.5 1.540 k ? input common-mode voltage 0.8 2.5 v differential input sensitivity 200 mv MAX3346E 15kv esd-protected usb transceiver in ucsp _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +4v to +5.5v, gnd = 0, vtrm = +3.0v to +3.6v, v l = +1.65v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v, v l = +2.5v, t a = +25?.) (note 2) timing characteristics (v cc = +4v to +5.5v, gnd = 0, vtrm = +3.0v to +3.6v, v l = +1.65v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v, v l = +2.5v, t a = +25?.) (note 2) parameter symbol conditions min typ max units speed independent timing characteristics oe to vp/vm three-state delay disable time t pvz figures 1a and 4a 20 ns oe to vp/vm delay enable time t pzv figures 1a and 4a 25 ns d+/d- to rcv propagation delay t plh c l = 25pf, figures 4b and 5 18 ns d+/d- to rcv propagation delay t phl c l = 25pf, figures 4b and 5 18 ns
MAX3346E 15kv esd-protected usb transceiver in ucsp 4 _______________________________________________________________________________________ timing characteristics (continued) (v cc = +4v to +5.5v, gnd = 0, vtrm = +3.0v to 3.6v, v l = +1.65v to +3.6v, t a = t min to t max , unless otherwise noted. typical values are at v cc = +5v, v l = +2.5v, t a = +25?.) (note 2) parameter symbol conditions min typ max units t plh c l = 25pf, figures 4b and 5 18 d+/d- to vp/vm propagation delay t phl c l = 25pf, figures 4b and 5 18 ns full-speed timing characteristics oe to transmit delay enable time t pzd (figures 1b, 4d) 20 ns oe to driver three-state delay disable time t pdz (figures1b, 4d) 20 ns t plh (figures 3, 4c) 18 vp/vm to d+/d- propagation delay (mode = 1) t phl (figures 3, 4c) 18 ns t phl0 c l = 50pf (figures 2, 4c) 20 vp to d+/d- propagation delay (mode = 0) t plh0 c l = 50pf (figures 2, 4c) 20 ns d+, d- rise time t r c l = 50pf, 10% to 90% of |v oh - v ol |4 20 ns d+, d- fall time t f c l = 50pf, 90% to 10% of |v oh - v ol |4 20 ns rise- and fall-time matching (note 3) t r /t f c l = 50pf 90 110 % output-signal crossover voltage (note 3) v crs c l = 50pf 1.3 2.0 v low-speed timing characteristics t plh figures 3 and 4c, c l = 50pf to 600pf 30 250 vp/vm to d+/d- propagation delay (mode = 1) t phl figures 3 and 4c, c l = 50pf to 600pf 30 250 ns t phl0 figures 2 and 4c, c l = 50pf to 600pf 30 250 vp to d+/d- propagation delay (mode = 0) t plh0 figures 2 and 4c, c l = 50pf to 600pf 30 250 ns d+/d- rise time t r c l = 50pf to 600pf 75 300 ns d+/d- fall time t f c l = 50pf to 600pf 75 300 ns rise- and fall-time matching t r /t f c l = 50pf to 600pf 80 125 % output-signal crossover voltage v crs c l = 50pf to 600pf 1.3 2.0 v note 2: parameters are 100% production tested at +25?, limits over temperature are guaranteed by design. note 3: guaranteed by design, not production tested.
MAX3346E 15kv esd-protected usb transceiver in ucsp _______________________________________________________________________________________ 5 single-ended receiver propagation delay vs. v l MAX3346E toc01 v l (v) propagation delay (ns) 3.3 3.0 1.8 2.1 2.4 2.7 8 9 10 11 12 13 14 15 7 1.5 3.6 t a = +85 c t a = +25 c t a = -40 c single-ended receiver propagation delay vs. v cc MAX3346E toc02 v cc (v) propagation delay (ns) 5.00 5.25 4.75 4.25 4.50 8 9 10 11 12 13 14 15 7 4.00 5.50 t a = +85 c t a = +25 c t a = -40 c skew vs. v cc (mode 0, full speed) MAX3346E toc03 v cc (v) skew (ns) 5.00 5.25 4.75 4.25 4.50 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.4 4.00 5.50 t a = +85 c t a = +25 c t a = -40 c 0 0.1 0.2 0.6 0.4 0.8 0.3 0.7 0.5 0.9 1.0 4.00 4.50 4.25 4.75 5.00 5.25 5.50 skew vs. v cc (mode 0, low speed) MAX3346E toc04 v cc (v) skew (ns) t a = -40 c t a = +25 c t a = +85 c MAX3346E toc05 a 0 0 200ns/div b 0 c oe, vp, vm timing a: vp, 2v/div b: vm, 2v/div c: oe, 5v/div (figure 4a) MAX3346E toc06 a 0 0 200ns/div b 0 c oe, vp, vm timing a: vp, 2v/div b: vm, 2v/div c: oe, 5v/div (figure 4a) vtrm vs. v cc MAX3346E toc07 v cc (v) vtrm (v) 5.25 5.00 4.75 4.50 4.25 3.1 3.2 3.3 3.4 3.5 3.0 4.00 5.50 i vtrm = 15ma t ypical operating characteristics (v cc = +5v, v l =+3.3v, t a = +25?, unless otherwise noted.)
MAX3346E 15kv esd-protected usb transceiver in ucsp 6 _______________________________________________________________________________________ rise- and fall-time matching (low speed) MAX3346E toc09 d+ 100ns/div 0 d- f = 750khz rise- and fall-time matching (full speed) MAX3346E toc10 d+ 20ns/div 0 d- f = 6mhz t ypical operating characteristics (continued) (v cc = +5v, v l = +3.3v, t a = +25?, unless otherwise noted.) pin description pin tssop ucsp name input/ output function 1d 2 rcv output receiver output. single-ended cmos output. rcv responds to the differential input on d+ and d- (see table 3). 2d1vp input/ output system-side data input/output. drive oe high to make vp a receiver output. drive oe low to make vp a driver input (see table 3). 3c 2 mode input mode control input. selects single-ended (mode zero) or differential (mode one) input for the system side when converting logic-level signals to usb-level signals. if mode is forced high, mode one is selected. if mode is forced low, mode zero is selected (see table 3). 4c1vm input/ output system-side data input/output. drive oe high to make vm a receiver output. drive oe low to make vm a driver input (see table 3). 5b1 oe input output enable. drive oe high to enable the receiver. drive oe low to enable the driver input. 6a 1 enum input enumerate input. drive enum low to disconnect the internal 1.5k ? resistor, and enumerate the usb. with enum high, the internal 1.5k ? resistor is connected to either d+ or d-, depending on the state of speed. suspend response MAX3346E toc08 a 0 100ns/div 0 b a: susp, 2v/div b: rcv, 2v/div
MAX3346E 15kv esd-protected usb transceiver in ucsp _______________________________________________________________________________________ 7 detailed description the MAX3346E is a bidirectional transceiver that con- verts single-ended or differential logic-level signals to differential usb signals, and converts differential usb signals to single-ended or differential logic-level sig- nals. the MAX3346E includes an internal 1.5k ? pullup resistor that can be connected to either d+ or d- for full-speed or low-speed operation (see the functional diagram ). the MAX3346E can be energized without concern about power-supply sequencing. additionally, the usb i/o, d+ and d-, are esd protected to ?5kv. the MAX3346E can get its usb-side power, v cc , directly from the usb connection, and can operate with system-side power, v l , down to 1.65v and still meet the usb physical layer specifications. the MAX3346E sup- ports both full-speed (12mbps) and low-speed (1.5mbps), usb specification 1.1 operation. the MAX3346E has an enumerate feature that works when power is on. driving enum low disconnects the internal 1.5k ? pullup resistor from both d+ and d-, reenumerating the usb. this is useful if changes in com- munication protocol are required while power is applied, and while the usb cable is connected. pin tssop ucsp name input/ output function 7b 2 susp input suspend input. drive susp low for normal operation. force susp high for low- power state. in low-power state rcv is low, d+/d- are high impedance if oe is floating, and vp/vm are active outputs. 8a2 speed input usb transmission speed select input. if speed is forced high, full speed (12mbps) is selected and the internal 1.5k ? pullup resistor is connected to d+. if speed is forced low, low speed (1.5mbps) is selected and the internal 1.5k ? pullup resistor is connected to d-. 9a3v cc power usb-side power-supply input. connect v cc to the incoming usb power supply. bypass v cc to gnd with a 1? ceramic capacitor. 10 a4 gnd power ground 11 b4 d- input/ output usb differential data input/output. connect to the usb? d- signal through a 24.3 ? 1% resistor. 12 c4 d+ input/ output usb differential data input/output. connect to the usb? d+ signal through a 24.3 ? 1% resistor. 13 d4 vtrm power regulated output voltage. 3.3v output derived from the v cc input. bypass vtrm to gnd with a 1? (or more) low-esr capacitor, such as ceramic or plastic film types. 14 d3 v l power system-side power-supply input. connect to the system? logic-level power supply, 1.65v to 3.6v. bypass to gnd with a 0.1? capacitor. b3, c3 not populated. the solder sphere is omitted from these locations (see the package information ). pin description (continued)
MAX3346E 15kv esd-protected usb transceiver in ucsp 8 _______________________________________________________________________________________ applications information power-supply configurations normal operating mode connect v l and v cc to system power supplies (table 1). connect v l to a +1.65v to +3.6v supply. connect v cc to a +4.0v to +5.5v supply. alternatively, the MAX3346E can derive power from a single li+ battery. connect the battery to v cc . vtrm remains above +3.0v for v cc as low as +3.1v. additionally, the MAX3346E can derive power from a 3.3v ?0% voltage regulator. connect v cc and vtrm to an external +3.3v voltage regulator. disable mode connect v cc to a system power supply and leave v l unconnected or connect to gnd. d+ and d- enter a tri- state mode and v cc consumes less than 20? of sup- ply current. d+ and d- withstand external signals up to +5.5v in disable mode (table 2). sharing mode connect v l to a system power supply and leave v cc (or v cc and v vtrm ) unconnected or connect to gnd. d+ and d- enter a tri-state mode, allowing other circuit- ry to share the usb d+ and d- lines, and v l consumes less than 20? of supply current. d+ and d- withstand external signals up to +5.5v in sharing mode (table 2). device control oe oe controls the direction of communication through the device. with oe low, the MAX3346E transfers data from the system side to the usb side. with oe high, the MAX3346E transfers data from the usb side to the system side. enum the MAX3346E allows software control of usb enumera- tion. usb specification 1.1 requires a 1.5k ? pullup resistor to d+ or d- to set the transmission speed (see the speed section). enumerating the usb requires removing the 1.5k ? resistor from the circuit, and is accomplished with the MAX3346E by driving enum low. with enum high, the volt- age at speed determines how the internal resistor is con- nected (see the functional diagram ). mode mode is a control input that selects whether differential or single-ended logic signals are recognized by the system side of the MAX3346E (table 3). if mode is forced high, differential input is selected. with differential input selected, outputs d+ and d- follow the differential inputs at vp and vm. if vp and vm are both forced low, an se0 condition is forced on the usb. drive mode and vm low for single-ended input mode. with single-ended input selected, the differential sig- nal on d+ and d- is controlled by vp. if vm is high when mode is low, d- and d+ are both low, forcing an se0 condition. v cc (v) vtrm (v) v l (v) configuration notes +4.0 to +5.5 +3.3 output +1.65 to +3.6 normal mode +3.1 to +4.5 +3.3 output +1.65 to +3.6 battery supply +3.0 to +3.6 +3.0 to +3.6 input +1.65 to +3.6 voltage regulator supply gnd or floating output +1.65 to +3.6 sharing mode table 2 +3.0 to +5.5 output gnd or floating disable mode table 2 table 1. power-supply configurations inputs/outputs disable mode sharing mode v cc /vtrm ?+5v input/+3.3v output ?+3.3v input/+3.3v output ?+3.7v input/+3.3v output floating or connected to gnd v l floating or connected to gnd +1.65v to +3.6v input d+ and d- high impedance high impedance speed, susp, oe , enum high impedance high impedance table 2. disable-mode and sharing-mode configurations
MAX3346E 15kv esd-protected usb transceiver in ucsp _______________________________________________________________________________________ 9 susp susp, or suspend, is a control input. when susp is forced high the MAX3346E enters a low-power state. in this state, the quiescent supply current into v cc is less than 40?. in this mode, rcv is forced low, and d+ and d- are high-impedance inputs (table 3d). in suspend mode, data can only be transmitted with full-speed slope control. speed speed is a control input that selects between low-speed (1.5mbps) and full-speed (12mbps) usb transmission. internally, it selects whether the 1.5k ? pullup resistor is connected to d+ (full-speed) or d- (low-speed) ( functional diagram ). force speed high to select full speed, or force speed low to select low speed. vtrm vtrm is the 3.3v output of the internal linear voltage regulator. the regulator is used to power the internal portions of the usb side of the MAX3346E. the vtrm regulator? supply input is v cc . connect a 1.0? (or greater) ceramic or plastic capacitor from vtrm to gnd, as close to vtrm as possible. do not use vtrm to provide power to external circuitry. d+ and d- d+ and d- are the transceiver i/o connections, and are esd protected to ?5kv using the human body model, making the MAX3346E ideal for applications where a robust transmitter is required. v cc bypass v cc to gnd with a 1? capacitor. place the 1? capacitor as close as possible to the MAX3346E. figure 1b. enable and disable timing, transmitter figure 1a. enable and disable timing, receiver d+/d- t pdz t pzd v ohd - 0.3v v old + 0.3v v l 0v v l /2 oe vpo t phlo v l 0v d+ d- 0v vtrm v l /2 t plho figure 2. mode 0 timing t plh1 v l 0v 0v vtrm v l /2 d+ vp vm d- v l 0v t phl1 v l /2 t plh1 t phl1 v l /2 figure 3. mode 1 timing vp/vm v oh - 0.3v t pzv t pvz v ol + 0.3v v l 0v v l /2 oe timing diagrams
MAX3346E 15kv esd-protected usb transceiver in ucsp 10 ______________________________________________________________________________________ (a) load for enable and disable time, vp/vm. (b) load for vp, vm and rcv. (c) load for d+/d-. (d) load for enable and disable time, d+/d-. vp or vm gnd or v cc test point 200 ? 25pf + - MAX3346E vm or vp or rcv 25pf MAX3346E test point d+ or d- 23.7 ? c l 15k ? 1.5k ? 3.3v MAX3346E test point d+ or d- 200 ? 23.7 ? MAX3346E 50pf gnd or v cc + - test point figure 4. test circuits t phl t plh t phl t plh t plh t phl d+ d- rcv vp vm d+/d- rise/fall times 8ns, v l = 1.65v, 2.5v, 3.3v 3v 0v v l v l /2 v l /2 v l /2 0v v l 0v v l 0v figure 5. d+/d- to rcv, vp, vm propagation delays
MAX3346E 15kv esd-protected usb transceiver in ucsp ______________________________________________________________________________________ 11 oe = 0 (transmit) input output vp vm d+ d- rcv result 00 00 rcv* se0 01 01 0 logic 0 10 10 1 logic 1 11 11x undefined table 3b. truth table, transmit (mode = 1) oe = 1 (receive) input output d+ d- vp vm rcv result 00 00 rcv* se0 01 01 0 logic 0 10 10 1 logic 1 11 11x undefined table 3c. truth table, receive susp enumerate oe d+/d- rcv vp/vm function 00 0 driving active high-z normal driving 00 1 high-z active active normal receiving, r pullup disconnected 01 0 driving active high-z normal driving 01 1 high-z active active normal receiving, r pullup connected 10 0 or 1 high-z 0 active suspend mode, r pullup disconnected 11 0 or 1 high-z 0 active suspend mode, r pullup connected table 3d. function select oe = 0 (transmit) input output vp vm d+ d- rcv result 00 01 0 logic 0 01 00 rcv* se0 10 10 1 logic 1 1100xse0 table 3a. truth table, transmit (mode = 0) * rcv denotes the signal level on output rcv just before se0 state occurs. this level is stable during the se0 period. * rcv denotes the signal level on output rcv just before se0 state occurs. this level is stable during the se0 period. * rcv denotes the signal level on output rcv just before se0 state occurs. this level is stable during the se0 period.
MAX3346E 15kv esd-protected usb transceiver in ucsp 12 ______________________________________________________________________________________ external components external resistors two external resistors are required for usb connection, each of them from 23.7 ? ?% to 27.4 ? ?%, 1/2w (or greater). place one resistor in series between d+ of the MAX3346E and d+ of the usb connector. place the other resistor in series between d- of the MAX3346E and d- of the usb connector. the typical operating circuit shows these connections. external capacitors four external capacitors are recommended for proper operation. use a 0.1? ceramic for decoupling v l , a 1? ceramic capacitor for decoupling v cc , and a 1.0? (or greater) ceramic or plastic filter capacitor on vtrm. return all capacitors to gnd. receiving data from the usb data received from the usb are output to vp/vm and rcv in either of two ways, differentially or single ended. to receive data from the usb, force oe high, and force susp low. differential data arriving at d+/d- appears as differential logic signals at vp/vm, and as a single- ended logic signal at rcv. if both d+ and d- are low, then vp and vm are low, signaling an se0 condition on the bus; rcv retains the last state before se0 (see table 3). transmitting data to the usb the MAX3346E outputs data to the usb differentially on d+ and d-. the logic driving the signals may be either differential or single ended. for sending differential logic, force mode high, force oe and susp low, and apply data to vp and vm. if sending single-ended logic, force mode, susp, oe, and vm low, and apply data to vp. with vp low, d+ is low and d- high, result- ing in a logic 0 state. with vp high, d+ is high and d- low, resulting in a logic 1 state (see table 3). esd protection to protect the MAX3346E against esd, d+ and d- have extra protection against static electricity to protect the device up to ?5kv. the esd structures withstand high esd in all states; normal operation, suspend, and pow- ered down. for the 15kv esd structures to work cor- rectly, a 1f or greater capacitor must be connected from vtrm to gnd. esd protection can be tested in various ways; the d+ and d- input/output pins are characterized for protection to the following limits: 1) ?5kv using the human body model. 2) ?kv using the contact discharge method specified in iec 1000-4-2. 3) ?0kv using the iec 1000-4-2 air-gap method. esd test conditions esd performance depends on a variety of conditions. contact maxim for a reliability report that documents test setup, test methodology, and test results. human body model figure 6a shows the human body model, and figure 6b shows the current waveform it generates when dis- charged into a low impedance. this model consists of a 100pf capacitor charged to the esd voltage of interest, which is then discharged into the test device through a 1.5k ? resistor. charge-current limit resistor discharge resistance storage capacitor c s 100pf r c 1m ? r d 1500 ? high- voltage dc source device under test figure 6a. human body esd test models i p 100% 90% 36.8% t rl time t dl current waveform peak-to-peak ringing (not drawn to scale) i r 10% 0 0 amperes figure 6b. human body model current waveform
MAX3346E 15kv esd-protected usb transceiver in ucsp ______________________________________________________________________________________ 13 13 ___________________________________________________________________________________________________ iec 1000-4-2 the iec 1000-4-2 standard covers esd testing and performance of finished equipment; it does not specifi- cally refer to integrated circuits. the MAX3346E helps to design equipment that meets level 2 of iec 1000-4- 2, without the need for additional esd-protection com- ponents. the major difference between tests done using the human body model and iec 1000-4-2 is a higher peak current in iec 1000-4-2, because series resistance is lower in the iec 1000-4-2 model. hence, the esd with- stand voltage measured to iec 1000-4-2 is generally lower than that measured using the human body model. figure 7a shows the iec 1000-4-2 model. the air-gap discharge test involves approaching the device with a charged probe. the contact discharge method connects the probe to the device before the probe is energized. machine model the machine model for esd tests all pins using a 200pf storage capacitor and zero discharge resistance. its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufactur- ing. of course, all pins require this protection during manufacturing, not just usb inputs and outputs. therefore, after pc board assembly, the machine model is less relevant to i/o ports. ucsp applications information for the latest application details on ucsp construction, dimensions, tape carrier information, printed circuit board techniques, bump-pad layout, and recommended reflow temperature profile as well as the latest information on reliability testing results, go to the maxim website at www.maxim-ic.com/ucsp for the application note, ?csp? wafer-level chip-scale package. charge-current limit resistor discharge resistance storage capacitor c s 150pf r c 50m ? to 100m ? r d 330 ? high- voltage dc source device under test figure 7a. iec 1000-4-2 esd test model
MAX3346E 15kv esd-protected usb transceiver in ucsp 14 ______________________________________________________________________________________ 23.7 ? 1% 23.7 ? 1% 1.0 f ceramic usb cable 15k ? 15k ? gnd d- d+ usb power pc MAX3346E gnd d- d+ v cc speed susp enum rcv vm vp v l mode 1.0 f ceramic asic 0.1 f ceramic system power vtrm oe t ypical operating circuit
MAX3346E 15kv esd-protected usb transceiver in ucsp ______________________________________________________________________________________ 15 linear regulator internal power 1.5k ? level shifter and control logic gnd vm vp rcv susp mode enum v l speed v cc vtrm d+ d- MAX3346E oe functional diagram chip information transistor count: 2162 process: bicmos
MAX3346E 15kv esd-protected usb transceiver in ucsp 16 ______________________________________________________________________________________ tssop4.40mm.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX3346E 15kv esd-protected usb transceiver in ucsp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 17 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. 16l,ucsp.eps h 1 1 21-0101 package outline, 4x4 ucsp pa ck ag e information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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