View MAX7428EKA-T_6052729.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max7428/max7430/max7432 filters are low-cost, high-performance replacements for standard discrete fil- ter and buffer solutions. the max7428/max7430/ max7432 are ideal for anti-aliasing and dac smoothing video applications, when analog video is reconstructed from a digital data stream. these devices require a sin- gle +5v supply and the filters have a cutoff frequency optimized for ntsc, pal, and standard definition digital tv (sdtv) video signals. the max7428/max7430/ max7432 feature maxim? single pin bus (mspb) interface to digitally control channel selection (in_a or in_b), adjust high-frequency boost, bypass the filter, configure luma vs. chroma operation, and control the output disable. the max7428 single-channel filter is ideal for composite (cvbs) video signals. the max7430 dual filter is optimized for s-video (y/c) applications. the max7432 triple filter is optimized for component (yp b p r or embedded synchronous rgb) video signals. the max7428 is available in a tiny 8-pin sot23 package, the max7430 is available in a miniature 10-pin ?ax pack- age, and the max7432 is available in a 14-pin tssop package. the max7428/max7430/max7432 are fully specified over the -40? to +85? extended temperature range. applications set-top boxes dvd players hard-disk recorders camcorders features ideal for cvbs, y/c (s-video), and rgb (y p b p r ) outputs for ntsc, pal, and sdtv 6th-order lowpass filter drives two 150 ? video loads four levels of passband high-frequency boost control input 2 to 1 multiplexer output disable filter bypassing +5v single-supply voltage tiny 8-pin sot23 package (max7428), 10-pin max package (max7430), and 14-pin tssop package (max7432) max7428/max7430/max7432 standard definition video reconstruction filters and buffers ________________________________________________________________ maxim integrated products 1 +6db level shift 6th-order filter out serial interface and control data d/a ina inb * *optional sync aux input bias generator gnd rext encoder max7428 syncio v cc 75 ? 75 ? c in c in * functional diagrams ordering information 19-2119; rev 2; 9/02 pin configurations appear at end of data sheet. functional diagrams continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package top mark max7428 eka-t -40 c to +85 c 8 sot23-8 aaiu max7430 eub -40 c to +85 c 10 max max7432 eud -40 c to +85 c 14 tssop mspb is a trademark of maxim integrated products, inc.
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = +5v 10%, r rext = 300k ? 1%, c in = 0.1f, c rext = (1nf to 1f) 1%, c load = 0 to 20pf; boost0_, boost1_ = 0, 0; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ...........................................................................+6v all other pins to gnd .................................-0.3v to (v cc + 0.3v) maximum current into any pin ......................................... 50ma continuous power dissipation (t a = +70 c) 8-pin sot23 (derate 9.71mw/ c above +70 c)..........777mw 10-pin max (derate 6.94mw/ c above +70 c) ......555.5mw 14-pin tssop (derate 9.1mw/ c above +70 c) .........727mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units f = 100khz to 4.2mhz relative to 100khz -0.5 +0.5 passband response f = 100khz to 5mhz relative to 100khz -1.0 +1.0 db stopband attenuation a sb f > 27mhz 48 db hf boost relative step size, 4 levels f = 4.2mhz to 5mhz 0.2 0.4 0.6 db differential gain dg 5-step modulated staircase 0.2 % differential phase d 5-step modulated staircase 0.2 degrees harmonic distortion thd f = 100khz to 5mhz 0.1 0.5 % signal-to-noise ratio snr peak signal (2vp-p) to rms noise, f = 100hz to 50mhz 72 db group delay deviation ? t g deviation from 100khz to 3.58 (4.43)mhz 20 ns line-time distortion h dist 18s, 100 ire bar 0.3 % field-time distortion v dist 130 lines, 18s, 100 ire bar 0.5 % clamp settling time t clamp to 1% (note 1) 100 lines clevel = 0 0.8 1.3 output dc clamp level clevel = 1 1.35 1.85 v low-frequency gain a v gain at 100khz 1.9 1.975 2.05 v/v group delay matching t g(match) low frequency channel-to-channel matching f = 100khz 2ns low-frequency gain matching a v ( match ) c hannel - to- channel g ai n m atchi ng , f = 100kh z5% channel-to-channel crosstalk x talk channel-to-channel crosstalk, f = 100khz to 5.5mhz -60 db output short-circuit current i sc out_ shorted to ground or v cc 50 ma input leakage current i in 10 a y inp-p clevel = 0 1.4 input dynamic swing c inp-p clevel = 1 0.9 vp-p v cc supply range v cc 4.5 5.5 v
max7428/max7430/max7432 standard definition video reconstruction filters and buffers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v cc = +5v 10%, r rext = 300k ? 1%, c in = 0.1f, c rext = (1nf to 1f) 1%, c load = 0 to 20pf; boost0_, boost1_ = 0, 0; t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (note 2) mspb interface timing specifications (v cc = +5v 10%, r rext = 300k ? 1%, c rext = (1nf to 1f) 1%, c load = 0 to 20pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) (figures 4 through 9) note 1: one horizontal line = 63.5s. note 2: max7428 devices are 100% production tested at t a = +25 c and are guaranteed by design from t a = t min to t max . parameter symbol conditions min typ max units mspb timing logic-zero/prompt pulse width t 0 , t p 158s logic-one pulse width t 1 24 30 36 s transaction pulse width t t 80 100 120 s separation between pulses t wait 0.5 s bus release time by host after prompt pulse t release 1s bus reclaim time by host after prompt pulse t reclaim 13 s read back data valid window after the prompt pulse t read 2.3 4.7 s parameter symbol conditions min typ max units max7428 24 32 max7430 45 62 supply current i cc no load max7432 68 86 ma power-supply rejection ratio psrr v in = 100mvp-p, f = 0 to 5.5mhz 40 db in_a/in_b crosstalk v in = 100mvp-p, f = 100khz to 5.5mhz -60 db logic characteristics logic input high voltage v ih 2v logic input low voltage v il 0.8 v logic input current i ih /i il v il = 0 (source), v ih = v cc (sink) 10 a logic output high voltage v oh i (source) = 500a v cc - 0.5 v logic output low voltage v ol i (sink) = 500a 0.4 v
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 4 _______________________________________________________________________________________ typical operating characteristics (v cc = +5v, r rext = 300k ? ; boost0_, boost1_ = 0, 0; v in_ = 1vp-p, t a = +25 c, unless otherwise noted.) 0.1 1 10 100 amplitude vs. frequency max7428/30/32 toc01 frequency (mhz) amplitude (db) 0 -60 -50 -40 -30 -20 -10 0.1 1 10 passband amplitude vs. frequency max7428/30/32 toc02 frequency (mhz) amplitude (db) 2 -10 -8 -6 -4 -2 0 a c d b a: boost1, boost0 = 1, 1 b: boost1, boost0 = 1, 0 c: boost1, boost0 = 0, 1 d: boost1, boost0 = 0, 0 0.1 1 10 phase response vs. frequency max7428/30/32 toc03 frequency (mhz) phase (degrees) 180 -180 -120 -60 0 60 120 0.1 1 10 group delay vs. frequency max7428/30/32 toc04 frequency (mhz) group delay (ns) 120 0 20 40 60 80 100 200ns/div 2t response (1ire = 7.14mv) ina_ 200mv/div out_ 200mv/div max7428/30/32 toc05 400ns/div modulated 12.5t response (1ire = 7.14mv) ina_ 200mv/div out_ 200mv/div max7428/30/32 toc06 22 24 23 26 25 27 28 -40 10 -15 35 60 85 supply current vs. temperature max7428/30/32 toc07 temperature ( c) supply current (ma) no load 0.2 0.1 0 -0.1 -0.2 -0.3 differential gain (%) 0 -0.01 -0.04 -0.08 -0.10 -0.06 1st. 2nd. 3rd. 4th. 5th. 6th. differential gain max7428/30/32 toc08 max7428/30/32 toc09 0.20 0.15 0.10 0.05 0 -0.05 1st. 2nd. 3rd. 4th. 5th. 6th. 0 0.04 0.06 0.06 0.04 0.02 differential phase (degrees) differential phase
max7428/max7430/max7432 standard definition video reconstruction filters and buffers _______________________________________________________________________________________ 5 0.1 1 10 output impedance vs. frequency max7428/30/32 toc10 frequency (mhz) impedance (? ) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 200ns/div output transient due to input mux switching out_ 500mv/div max7428/30/32 toc11 -70 -95 0.1 1 10 passband channel-to-channel crosstalk vs. frequency -90 max7428/30/32 toc12 frequency (mhz) crosstalk (db) -85 -80 -75 boost = code 00 typical operating characteristics (continued) (v cc = +5v, r rext = 300k ? ; boost0_, boost1_ = 0, 0; v in = 1vp-p, t a = +25 c, unless otherwise noted.) pin description pin max7432 max7430 max7428 name function 1 1 in1a video input 1a. master channel, sync signal required. use a 0.1? series input capacitor for proper operation. 2 2 in2a video input 2a. slave channel, clamping controlled by master channel sync. use a 0.1? series input capacitor for proper operation. 3 in3a video input 3a. slave channel, clamping controlled by master channel sync. use a 0.1? series input capacitor for proper operation. 4, 10 8 4 gnd ground 5 4 in1b video input 1b. master channel, sync signal required. use a 0.1? series input capacitor for proper operation. 6 5 in2b video input 2b. slave channel, clamping controlled by master channel sync. use a 0.1? series input capacitor for proper operation. 7 in3b video input 3b. slave channel, clamping controlled by master channel sync. use a 0.1? series input capacitor for proper operation. 8 6 6 data serial data interface 9 out3 buffer output 3 11 7 out2 buffer output 2 12 3 7 rext external resistor. connect a 300k ? resistor from rext to gnd for internal biasing. connect a 1nf to 1? capacitor from rext to gnd for chip-address programming (see table 3).
d/a d/a 0.1 f 0.1 f ina inb gnd encoder 75 ? 75 ? 75 ? **220 f 75 ? c1 300k ? serial i/o sync pulse in or out out v cc 5v rext data syncio **220 f *1m ? *1m ? max7428 z 0 = 75 ? z 0 = 75 ? 5v 10k ? *** c1 = 1nf to 1 f (see table 3) *needed only in filter bypass mode **optional capacitor ***only one pullup resistor needed per bus figure 1. max7428 typical application circuit max7428/max7430/max7432 detailed description the max7428/max7430/max7432 filter and buffer the outputs of dac encoder chipsets that process digital video information in applications such as set-top boxes, hard-disk recorders, dvd players, recorders, and digi- tal vcrs. these devices also filter and clean-up ana- log video signals. each channel in the max7428/ max7430/max7432 includes an input mux to select the input channel, a 6th-order sallen-key filter with four adjustable high-frequency boost levels, an output buffer with a 6db gain, a sync detector and clamp, and an external resistor to set internal bias levels. output disable adds additional multiplexing in a wired-or con- figuration. filter bypass, in conjunction with the two inputs, can be used to provide filtered and unfiltered video signal processing. maxim s single pin bus (mspb) interface controls all of the above features. an external capacitor is used to assign each device a unique address that allows control of up to 16 devices on the same bus. typical application circuits for the max7428/max7430/max7432 are shown in figures 1, 2, and 3. input considerations use a 0.1f ceramic capacitor to ac-couple the input to the max7428/max7430/max7432. this input capaci- tor stores a dc level to level-shift the input signal to an optimal point between v cc and gnd. the absel bit on the control register sets which channel (in_a or in_b) is selected ( control register section). the in_a and in_b inputs have a typical input resistance of 50k ? . standard definition video reconstruction filters and buffers 6 _______________________________________________________________________________________ pin description (continued) pin max7432 max7430 max7428 name function 13 9 out1 buffer output 1 14 10 2 v cc +5v supply voltage 1 ina video input a. use a 0.1f series input capacitor for proper operation. 3 inb video input b. use a 0.1f series input capacitor for proper operation. 5 syncio sync pulse input or output 8 out buffer output
max7428/max7430/max7432 standard definition video reconstruction filters and buffers _______________________________________________________________________________________ 7 0.1 f *1m ? d/a 0.1 f *1m ? 0.1 f *1m ? d/a 0.1 f *1m ? 75 ? z 0 = 75 ? z 0 = 75 ? 75 ? z 0 = 75 ? z 0 = 75 ? 200 f** 200 f** 75 ? 75 ? 75 ? 75 ? 200 f** 200 f** 75 ? 75 ? serial i/o 300k ? c1 +5v max7430 in1a in1b in2a in2b out1 out2 data rext gnd v cc encoder encoder +5v 10k ? *** c1 = 1nf to 1 f (see table 3) *needed only in filter bypass mode **optional output capacitor ***only one pullup resistor needed per bus aux in aux in figure 2. max7430 typical application circuit
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 8 _______________________________________________________________________________________ 0.1 f *1m ? d/a 0.1 f *1m ? 0.1 f *1m ? d/a 0.1 f *1m ? 75 ? 75 ? 220 f** 220 f** 75 ? 75 ? 75 ? 75 ? 220 f** 220 f** 75 ? 75 ? serial i/o 300k ? c1 +5v max7432 in1a in1b in2a in2b 0.1 f *1m ? d/a 0.1 f *1m ? in3a in3b out1 out2 75 ? 75 ? z 0 = 75 ? z 0 = 75 ? z 0 = 75 ? z 0 = 75 ? z 0 = 75 ? z 0 = 75 ? 220 f** 220 f** 75 ? 75 ? out3 data rext gnd v cc encoder encoder encoder c1 = 1nf to 1 f (see table 3) *needed only in filter bypass mode **optional output capacitor ***only one pullup resistor needed per bus aux in aux in aux in +5v *** figure 3. max7432 typical application circuit
max7428/max7430/max7432 standard definition video reconstruction filters and buffers _______________________________________________________________________________________ 9 filter filter response the reconstruction filter consists of a 6th-order butterworth filter in three second-order stages. the butterworth filter features a maximally flat passband for ntsc and pal bandwidths. the stopband offers typical- ly 50db of attenuation at sampling frequencies of 25mhz and above (see typical operating characteristics ). the corner frequency is not critical since the response of the filter meets both the stopband and passband specifications. the max7428/max7430/max7432 incorporate an autotrimming feature that reduces the corner frequency variation digitally. it is possible, although not likely, that a discrete shift in the corner fre- quency may occur due to an external environmental change. the autotrimming operates continuously so that the corner frequency remains centered over the full operating temperature range. high-frequency boost the high-frequency boost compensates for signal degra- dation and roll-off in the signal path prior to the max7428/ max7430/max7432. high-frequency boost is program- mable in four steps to increase image sharpness. output buffer the output buffer is able to drive two 150 ? video loads with a 2vp-p signal. the +6db gain of the output buffer is independent of the filter bypass or input selection. the output buffer drives the 75 ? backmatch resistors and series capacitor (typically 220f). the max7428/ max7430/max7432 are able to drive the video load directly without using the 220f capacitor. this feature is common in scart applications. the outdisable bit of the control register disables the output (mute) (see control register section). filter bypass the max7428/max7430/max7432 offer selectable filter bypassing that allows either of the video inputs to be fil- tered or unfiltered. the 1m ? optional input resistors are needed only in filter bypass mode to provide a dis- charge path for the input coupling capacitors. serial interface maxim s single pin bus (mspb) interface uses data to transfer data to and from the microprocessor (p) and the max7428/max7430/max7432. this negative logic protocol uses three different pulse widths to represent a logic 1 , logic 0 , and control commands. mspb allows up to 16 devices to be connected on the same bus by assigning a unique 4-bit identification address to each device. the p can communicate to each device individually or by sending a broadcast mes- sage to all the devices. the unique address for each device is set by means of the time constant set by the external capacitor connected in parallel with the exter- nal 300k ? resistor (see initializing the max7428/ max7430/max7432 section). max7428 control register table 1 defines the structure of the max7428 8-bit con- trol register programmed by mspb. this register con- trols the selection of ina or inb, syncio functionality, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. see maxim s single pin bus interface (mspb) section for detailed program- ming instructions. syncio: syncio select bit. a logic 0 sets the syncio pin to function as an output while a logic 1 sets syncio to function as an input. absel: channel select bit. a logic 0 selects the input at inb to be processed while a logic 1 selects the input at ina to be processed. bypass: filter bypass select bit. a logic 1 selects the filter while a logic 0 bypasses the filter. table 1. max7428 control register (msb) first bit (lsb) name syncio absel bypass clevel boost1 boost0 outdisable default 0 1 1 0 0 0 0 0 boost1 boost0 relative high-frequency boost 00 0 0 1 0.45db 1 0 0.90db 1 1 1.35db table 2. boost level programming
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 10 ______________________________________________________________________________________ clevel: clamp level bit. a logic 0 selects a clamp level of 1v while a logic 0 selects a clamp level of 1.5v at the output. [boost1, boost0]: high-frequency boost control bits. the adjust bits select the amount of high-frequency boost for the filter. table 2 defines four levels of adjustment. outdisable: output disable bit. a logic 0 selects normal operation while a logic 1 places the output in a high-impedance state. max7430 control register table 3 defines the structure of the max7430 16-bit con- trol register programmed by mspb. this register controls the selection of in_a or in_b, selection of filter 1 or 2, filter bypassing, clamp-level selection, high-frequency boost control, and output disable. see maxim s single pin bus interface (mspb) section for detailed programming instructions. absel_: channel select bit. a logic zero selects the input at in_b to be processed while a logic 1 selects the input at in_a to be processed. bypass_: filter bypass select bit. a logic 1 selects the channel filter while a logic 0 bypasses the channel filter. clevel_: clamp level bit. a logic 0 selects a channel clamp level of 1v while a logic 0 selects a channel clamp level of 1.5v at the output. [boost1_, boost0_]: high-frequency boost control bits. the adjust bits select the amount of high-frequency boost for the channel filter. table 4 defines four levels of adjustment. outdisable_: output disable bit. a logic 0 selects normal channel output operation while a logic 1 puts the channel output in a high-impedance state. max7432 control register table 5 defines the structure of the max7432 24-bit control register programmed by mspb. this register controls the selection of in_a or in_b, selection of filter 1, 2, or 3, filter bypassing, clamp-level selection, high- frequency boost control, and output disable. see maxim s single pin bus interface (mspb) section for detailed programming instructions. absel_: channel select bit. a logic zero selects the input at in_b to be processed while a logic 1 selects the input at in_a to be processed. bypass_: filter bypass select bit. a logic 1 selects the channel filter while a logic 0 bypasses the channel filter. clevel_: clamp level bit. a logic 0 selects a channel clamp level of 1v while a logic 0 selects a channel clamp level of 1.5v at the output. [boost1_, boost0_]: high-frequency boost control bits. the adjust bits select the amount of high-frequency boost for the channel filter. table 6 defines four levels of adjustment. outdisable_: output disable bit. a logic 0 selects normal channel output operation while a logic 1 puts the channel output in high-impedance state. (msb) name absel2 bypass2 clevel2 boost1(2) boost0(2) out disable2 default 0 1 1 0 0 0 0 0 name absel1 bypass1 clevel1 boost1(1) boost0(1) out disable1 default 0 1 1 0 0 0 0 0 first bit (lsb) table 3. max7430 control register boost1_ boost0_ relative high- frequency boost 00 0 0 1 0.45db 1 0 0.90db 1 1 1.35db table 4. boost level programming
max7428/max7430/max7432 standard definition video reconstruction filters and buffers ______________________________________________________________________________________ 11 applications information maxim? single pin bus (mspb) serial interface the mspb interface uses three pulses of different widths to represent commands and data bits. figure 4 shows the set of pulses that the single pin interface uses to communicate with the device. a combination of the one pulse (t 1 ), zero pulse (t 0 ), transaction pulse (t t ), and prompt pulse (t p ), writes to, reads back from, and sends broadcast data to the devices on the bus. note: the zero pulse and prompt pulse are the same. initialization pulses are significantly longer and are used only on power-up or software reset. initializing the max7428/max7430/max7432 initialization is performed only after power-up or software reset. it assigns a unique address to each device on the bus. the time constant of the capacitor connected to r ext in parallel with the 300k ? resistor determines the order in which the devices are initialized (address assigned). the device with the largest time constant is initialized first and so on, in descending order. table 7 shows the initialize wait and initialize time pulse widths needed for a specific capacitor value and toler- ance. program each device on the bus with this com- mand sequence starting with the device with the biggest capacitor. to reinitialize a device, cycle the power or use a software reset. the following is the command sequence and timing diagram (figure 5) for initialization as shown below. chip id is entered lsb first. note: if there is only one device on the bus, no initial- ization is needed. communicate to the device using the broadcast command described on page 13. (msb) name absel3 bypass3 clevel3 boost1(3) boost0(3) out disable3 default 0 1 1 0 0 0 0 0 name absel2 bypass2 clevel2 boost1(2) boost0(2) out disable2 default 0 1 1 0 0 0 0 0 name absel1 bypass1 clevel1 boost1(1) boost0(1) out disable1 default 0 1 1 0 0 0 0 0 first bit (lsb) table 5. max7432 control register boost1_ boost0_ relative high- frequency boost 00 0 0 1 0.45db 1 0 0.90db 1 1 1.35db table 6. boost level programming zero/prompt pulse t p = t 0 = 5 s t 1 = 30 s t 0 one pulse transaction pulse t 1 t t = 100 s t t figure 4. mspb interface pulses
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 12 ______________________________________________________________________________________ programming the max7428/max7430/max7432 an address sequence precedes a write or read opera- tion to determine with which device to communicate. if the address transmitted in this mode matches with a device s address, the device and p can initiate data transfer. when entering the four address bits, ensure that the lsb is entered first. the following is the com- mand sequence and timing diagram (figure 6) for an address sequence. use a write sequence to load data into the data register of the device. it must follow an address sequence. transmit a minimum of eight data bits for the max7428, 16 data bits for the max7430, or 24 data bits for the max7432 to make this transaction valid starting with the lsb first. the last 8/16/24 data bits are used if more than 8/16/24 bits are loaded into the register. the fol- lowing is the command sequence and timing diagram (figure 7) for a write sequence. during the read sequence, the p sends a prompt pulse causing the device to output the data word lsb first. similar to the write transaction, the read transac- tion must be preceded by an address sequence. if more than 8 prompts (max7428), 16 prompts (max7430), or 24 prompts (max7432) are available, the device outputs the same data starting with the lsb again. the following is the command sequence and timing diagram (figure 8) for a read sequence. write command sequence: t001 data 8-bits (max7428, see table 1) data 16-bits (max7430, see table 3) data 24-bits (max7432, see table 5) t111 address command sequence: t010 address = 4-bits t111 initialization command sequence: initialize wait t011 initialize time address id = 4-bits t111 initializing time period (ms) with r rext = 300k ? (t int ) capacitor value (nf) initializing wait period (ms) (t intwait ) min typ max 1000 20.000 162 (136.8) 171 (144) 179 (151.2) 680 13.600 112 118 123 470 9.400 52.6 (44.1) 55.4 (46.4) 58.2 (48.72) 220 4.400 35.90 37.80 39.70 150 3.000 23.90 (13.7) 25.20 (14.4) 26.50 (15.1) 100 2.000 16.25 17.10 17.95 68 1.360 11.21 (4.4) 11.80 (4.64) 12.39 (4.9) 47 0.940 5.26 5.54 5.82 22 0.440 3.59 3.78 3.97 15 0.300 2.39 2.52 2.65 10 0.200 1.625 (1.37) 1.710 (1.44) 1.795 (1.51) 6.8 0.136 1.121 1.180 1.239 4.7 0.094 0.526 (0.441) 0.554 (0.464) 0.582 (0.487) 2.2 0.044 0.359 0.378 0.397 1.5 0.030 0.239 0.252 0.265 1 0.020 0.162 (0.137) 0.171 (0.144) 0.179 (0.151) table 7. initialization capacitor values and pulse widths (c rext = 10% tolerance, r rext = 1% tolerance) note: ( ) indicates the time periods associated with 20% capacitors. this limits the maximum number of devices on the bus to seven.
max7428/max7430/max7432 standard definition video reconstruction filters and buffers ______________________________________________________________________________________ 13 the broadcast sequence writes data to the control regis- ters of all the devices on the bus at the same time. write data with the lsb first. the following is the command sequence and timing diagram (figure 9) for the broad- cast transaction. no address sequence is required. use the broadcast command when there is only one device on the bus. executing a software reset serves the same function as a power-on reset and is achieved by transmitting all data bits (eight or more) for the max7428, sixteen or more ones for the max7430, or 24 or more ones for the max7432 to that device register. composite video filtering the max7428 is ideally suited for filtering composite video signals. program the syncio as an output when processing composite video signals. in the rare occa- sion that an external sync pulse is needed to process the composite video, program the syncio as an input. broadcast command sequence: t000 data 8-bits (max7428) data 16-bits (max7430) data 24-bits (max7432) t111 read command sequence: t101 prompts 8 (max7428) prompts 16 (max7430) prompts 24 (max7432) t111 address: 0001 t wait t intwait t int t t t 1 t 1 t 1 t t t 1 t 1 t 1 t 0 t 0 t 0 t 0 lsb msb figure 5. initialization timing diagram address: 0001 t wait t t t t t 1 t 1 t 0 t 1 t 1 t 1 t 0 t 0 t 0 t 0 lsb msb figure 6. address timing diagram data: 1***000 t wait t t t 1 t 0 t 1 t t t 1 t 1 t 1 t 0 t 0 t 0 t 0 lsb msb figure 7. write timing diagram software reset command sequence: t000 8 or more 1s (max7428) 16 or more 1s (max7430) 24 or more 1s (max7432) t111 or t010 address = 4-bits t111 t001 8 or more 1s (max7428) 16 or more 1s (max7430) 24 or more 1s (max7432) t111
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 14 ______________________________________________________________________________________ when processing composite video set the clamp level to +1v (clevel = 0). use the max7430 to process two synchronous composite signals simultaneously. use the max7432 to process three synchronous composite sig- nals simultaneously. y/c video filtering the max7430 is ideally suited for processing s-video (y/c) signals (figure 10). ensure that in1_ filters the signal that contains the sync information (y) since the clamping on in2_ is internally controlled by the master channel (in1_) sync. set the clamp level for in1_ to +1v (clevel1 = 0) and set the clamp level for in2_ to +1.5v (clevel2 = 1). use two max7428s for y/c video filtering. since only the y signal contains the sync, a typical y/c video-filtering application requires a master-slave configuration of the syncio. the max7428 processing the y signal should have syncio configured as an output, which in turn dri- ves the syncio of the second max7428, processing the c signal that has its syncio configured as an input (figure 11). clamping level for the y signal should be set for +1v (clevel = 0), and clamping level for the c sig- nal should be set for +1.5v (clevel = 1). use the max7432 to filter one y/c and one composite video sig- nal that are synchronous. component video (rgb or y p b p r ) filtering component video consists of three separate signals. typically the three signals are separate red, green, and blue (rgb) signals or y (luma) and two color difference signals: b-y (p b ) which is blue minus luma and r-y (p r ), which is red minus luma. sync information is included with the y signal of y p b p r component video, or in the case of rgb, sync is usually carried on the g or on a separate h sync line. the max7432 is ideally suited for filtering component video signals. ensure that the sync signal (y for y p b p r signals and usually g for rgb sig- nals) is filtered by in1_ since in2_ and in3_ are inter- nally synced to in1_. set the clamp level for in1_ to +1v (clevel1 = 0) and set the clamp levels for in2_ and in3_ to +1.5v (clevel2, 3 = 1) for y p b p r filtering (figure 12) and set all clamp levels to 1v (clevel_ = 0) for rgb filtering (figure 13). a y p b p r component video-filter application requires three max7428s with syncio master-slave configuration. the max7428 pro- cessing the y signal has its syncio configured as an output, which in turn drives the syncio inputs of the other max7428s (figure 14). for rgb video signal fil- tering with a separate horizontal sync signal, configure all max7428s for syncio as an input (figure 15). t wait t t t t t 1 t 1 t p t 1 t 1 t 1 t 0 ab cd high-z t p t p reads 1st bit (lsb) a: p will release bus by time a b: p can start reading bit at time b c: p has until time c to finish reading bit d: device will release bus by time d note: time a, b, c, d are referenced to t 0 . reads 2nd bit repeat to read 6 more bits 0 or 1 0 or 1 t 0 ab cd 0 or 1 t o figure 8. read timing diagram data: 1***000 t wait t t t 1 t t t 1 t 1 t 1 t 0 t 0 t 0 t 0 t 0 t 0 lsb msb figure 9. broadcast timing diagram
max7428/max7430/max7432 standard definition video reconstruction filters and buffers ______________________________________________________________________________________ 15 set the clamping levels for component video so the max7428 processing y clamps at +1v (clevel = 0). the remaining two max7428s should have clamp levels set to +1.5v (clevel = 1). for rgb video with external sync (h), all three max7428s should have clamp levels set to +1v (clevel = 0). power-supply bypassing and layout the max7428/max7430/max7432 operate from a sin- gle +5v supply. bypass v cc to gnd with a 0.1f capacitor. place all external components as close to the devices as possible. refer to the max7428evkit for a proven pc board layout example. ina (clevel = 0) out y (luma) syncio max7248 ina (clevel = 1) out c (chroma) syncio max7248 figure 11. y/c video filter application max7430 in1a out2 out1 in2a [clevel = 0] [clevel = 1] y (luma) c (chroma) figure 10. max7430 y/c video filter application b r g (must contain sync signal) max7432 in1a out2 out1 in2a [clevel = 0] [clevel = 0] out3 in3a [clevel = 0] figure 13. max7432 rgb video filter with embedded sync application p r p b y (luma) (includes sync signal) max7432 in1a out2 out1 in2a [clevel = 0] [clevel = 1] out2 in3a [clevel = 1] figure 12. max7432 y p b p r video filter application
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 16 ______________________________________________________________________________________ chip information transistor count: max7428 = 4955 max7430 = 7413 max7432 = 9873 process: bicmos inb ina (clevel = 0) out y (luma) (includes sync signal) syncio max7248 inb ina (clevel = 1) out p r syncio max7248 (clevel = 1) max7248 inb ina out p b syncio figure 14. y p b p r video filter application inb ina (clevel = 0) out r syncio max7248 inb ina (clevel = 0) out g syncio max7248 (clevel = 0) max7248 inb ina out b external h sync syncio figure 15. rgb video filter with external sync application
max7428/max7430/max7432 standard definition video reconstruction filters and buffers ______________________________________________________________________________________ 17 data syncio gnd 1 2 8 7 out rext v cc inb ina sot23 top view 3 4 6 5 max7428 1 2 3 4 5 10 9 8 7 6 v cc out1 gnd out2 in1b rext in2a in1a max7430 max data in2b 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc out1 rext out2 gnd in3a in2a in1a max7432 gnd out3 data in3b in2b in1b tssop pin configurations serial interface and control bias generator gnd rext max7430 v cc +6db level shift 6th-order filter d/a in1a in1b aux input * * out1 sync +6db level shift 6th-order filter d/a in2a encoder * * out2 in2b aux input data *optional output capacitor functional diagrams (continued)
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 18 ______________________________________________________________________________________ functional diagrams (continued) serial interface and control bias generator gnd rext max7432 v cc +6db level shift 6th-order filter d/a in1a in1b aux input * * out1 sync +6db level shift 6th-order filter d/a in2a * * out2 in2b aux input data +6db level shift 6th-order filter d/a in3a encoder * * out3 in3b aux input *optional output capacitor
max7428/max7430/max7432 standard definition video reconstruction filters and buffers ______________________________________________________________________________________ 19 sot23, 8l.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max7428/max7430/max7432 standard definition video reconstruction filters and buffers 20 ______________________________________________________________________________________ 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 i rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max7428/max7430/max7432 standard definition video reconstruction filters and buffers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 21 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. tssop4.40mm.eps package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)

▲Up To Search▲

Price & Availability of MAX7428EKA-T

	To Download MAX7428EKA-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .