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? 2003 fairchild semiconductor corporation ds500729 www.fairchildsemi.com may 2002 revised august 2003 74lvxz161284 ? 74lvxz161284b low voltage ieee 161284 translating transceiver with power-up protection 74lvxz161284 74lvxz161284b low voltage ieee 161284 translating transceiver with power-up protection general description these transceivers contain eight bidirectional data buffers and eleven control/status buffers to implement a full ieee 1284 compliant interface. the devices support the ieee 1284 standard and are intended to be used in an extended capabilities port mode (ecp). the pinout allows for easy connection from the peripheral (a-side) to the host (cable side). outputs on the cable side can be configured to be either open drain or high drive ( 14 ma) and are connected to a separate power supply pin (v cc-cable ) that allows these outputs to be driven by a higher supply voltage than the a-side. the pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. in addition, the c inputs and the b and y outputs on the cable side contain internal pull-up resistors connected to the v cc-cable supply to provide proper input termination and pull-ups for open drain output mode. outputs on the peripheral side are standard low-drive cmos outputs designed to interface with 3v logic. the dir input controls data flow on the a 1 ?a 8 /b 1 ?b 8 transceiver pins. the devices also have an added power-up protection fea- ture which forces the y outputs (y 9 - y 13 ) to a high state after power-on until one of the associated inputs (a 9 - a 13 ) goes high. when an associated input (a 9 - a 13 ) goes high, all y outputs (y 9 - y 13 ) are activated. the 74lvxz161284b device provides increased noise tol- erance for stable power-on circuit logic states. features supports ieee 1284 level 1 and level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals translation capability allows outputs on the cable side to interface with 5v signals all inputs have hysteresis to provide noise margin b and y output resistance optimized to drive external cable b and y outputs in high impedance mode during power down c inputs and b, y outputs on cable side have internal 1.4 k ? pull-up resistors flow-through pin configuration allows easy interface between the ?peripheral and host? replaces the function of two (2) 74act1284 devices power-up protection prevents errors when the printer is powered on but no valid signal is at the input pins (a 9 - a 13 ). ordering code order number package number package description 74LVXZ161284MEA ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [rail] 74lvxz161284mex ms48a 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide [tape and reel] 74lvxz161284mtd mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [rail] 74lvxz161284mtx mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tape and reel] 74lvxz161284bmt mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [rail] 74lvxz161284btx mtd48 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide [tape and reel]
www.fairchildsemi.com 2 74lvxz161284 74lvxz161284b logic symbol connection diagram pin descriptions truth table note 1: y 9 ? y 13 open drain outputs with 1.4 k ? pull-ups note 2: b 1 ? b 8 open drain outputs with 1.4 k ? pull-ups pin names description hd high drive enable input (active high) dir direction control input a 1 ? a 8 inputs or outputs b 1 ? b 8 inputs or outputs a 9 ? a 13 inputs y 9 ? y 13 outputs a 14 ? a 17 outputs c 14 ? c 17 inputs plh in peripheral logic high input plh peripheral logic high output hlh in host logic high input hlh host logic high output inputs outputs dir hd llb 1 ? b 8 data to a 1 ? a 8 , and a 9 ? a 13 data to y 9 ? y 13 (note 1) c 14 ? c 17 data to a 14 ? a 17 plh open drain mode lhb 1 ? b 8 data to a 1 ? a 8 , and a 9 ? a 13 data to y 9 ? y 13 c 14 ? c 17 data to a 14 ? a 17 hla 1 ? a 8 data to b 1 ? b 8 (note 2) a 9 ? a 13 data to y 9 ? y 13 (note 1) c 14 ? c 17 data to a 14 ? a 17 plh open drain mode hha 1 ? a 8 data to b 1 ? b 8 a 9 ? a 13 data to y 9 ? y 13 c 14 ? c 17 data to a 14 ? a 17
3 www.fairchildsemi.com 74lvxz161284 74lvxz161284b logic diagrams input detection circuit figure 1. input detection circuit timing
www.fairchildsemi.com 4 74lvxz161284 74lvxz161284b with 74lvxz161284b any of the a 9 - a 13 inputs may transition high prior to v cc and v cc-cable becoming stable. in this case it is critical that v cc-cable does not ramp earlier than v cc . v cc and v cc-cable ramping concurrently will result in valid operation of this device. concurrent ramping is defined as v cc and v cc-cable having less than a 500 s delta between them. figure 2. 74lvxz161284b adds tolerance to power-on noise
5 www.fairchildsemi.com 74lvxz161284 74lvxz161284b absolute maximum ratings (note 3) recommended operating conditions note 3: absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. fairchild does not recom- mend operation outside the databook specifications. note 4: either voltage limit or current limit is sufficient to protect inputs. dc electrical characteristics supply voltage v cc ? 0.5v to + 4.6v v cc ? cable ? 0.5v to + 7.0v v cc ? cable must be v cc input voltage (v i ) ? (note 4) a 1 ? a 13 , plh in , dir, hd ? 0.5v to v cc + 0.5v b 1 ? b 8 , c 14 ? c 17 , hlh in ? 0.5v to + 5.5v (dc) b 1 ? b 8 , c 14 ? c 17 , hlh in ? 2.0v to + 7.0v* *40 ns transient output voltage (v o ) a 1 ? a 8 , a 14 ? a 17 , hlh ? 0.5v to v cc + 0.5v b 1 ? b 8 , y 9 ? y 13 , plh ? 0.5v to + 5.5v (dc) b 1 ? b 8 , y 9 ? y 13 , plh ? 2.0v to + 7.0v* *40 ns transient dc output current (i o ) a 1 ? a 8 , hlh 25 ma b 1 ? b 8 , y 9 ? y 13 50 ma plh (output low) 84 ma plh (output high) ? 50 ma input diode current (i ik ) ? (note 4) dir, hd, a 9 ? a 13 , plh, hlh, c 14 ? c 17 ? 20 ma output diode current (i ok ) a 1 ? a 8 , a 14 ? a 17 , hlh 50 ma b 1 ? b 8 , y 9 ? y 13 , plh ? 50 ma dc continuous v cc or ground current 200 ma storage temperature ? 65 c to + 150 c esd human body model 4000v machine model 200v charged device model 2000v supply voltage v cc 3.0v to 3.6v v cc ? cable 3.0v to 5.5v dc input voltage (v i )0v to v cc open drain voltage (v o ) 0v to 5.5v operating temperature (t a ) ? 40 c to + 85 c symbol parameter v cc (v) v cc ? cable (v) t a = 0 ct a = ? 40 c units conditions to + 70 cto + 85 c guaranteed limits v ik input clamp 3.0 3.0 ? 1.2 ? 1.2 v i i = ? 18 ma diode voltage v ih minimum a n , b n , plh in , dir, hd 3.0 to 3.6 3.0 to 5.5 2.0 2.0 v high level c n 3.0 to 3.6 3.0 to 5.5 2.3 2.3 input voltage hlh in 3.0 to 3.6 3.0 to 5.5 2.6 2.6 v il maximum a n , b n , plh in , dir, hd 3.0 to 3.6 3.0 to 5.5 0.8 0.8 v low level c n 3.0 to 3.6 3.0 to 5.5 0.8 0.8 input voltage hlh in 3.0 to 3.6 3.0 to 5.5 1.6 1.6 ? v t minimum input a n , b n , plh in , dir, hd 3.3 5.0 0.4 0.4 v v t + ? v t ? hysteresis c n 3.3 5.0 0.8 0.8 v t + ? v t ? hlh in 3.3 5.0 0.2 0.2 v t + ? v t ? v oh minimum high a n , hlh 3.0 3.0 2.8 2.8 v i oh = ? 50 a level output 3.0 3.0 2.4 2.4 i oh = ? 4 ma voltage b n , y n 3.0 3.0 2.0 2.0 i oh = ? 14 ma b n , y n 3.0 4.5 2.23 2.23 i oh = ? 14 ma plh 3.15 3.15 3.1 3.1 i oh = ? 500 a
www.fairchildsemi.com 6 74lvxz161284 74lvxz161284b dc electrical characteristics (continued) note 5: output impedance is measured with the output active low and active high (hd = high). note 6: power-down leakage to v cc or v cc ? cable is tested by simultaneously forcing all pins on the cable-side (b 1 ? b 8 , y 9 ? y 13 , plh, c 14 ? c 17 and hlh in ) to 5.5v and measuring the resulting i cc or i cc ? cable . note 7: this parameter is guaranteed but not tested, characterized only. note 8: connect all v cc pins and v cc-cable pins when forcing voltage applied, dir = hd = 0v. symbol parameter v cc (v) v cc ? cable (v) t a = 0 ct a = ? 40 c units conditions to + 70 cto + 85 c guaranteed limits v ol maximum low a n , hlh 3.0 3.0 0.2 0.2 v i ol = 50 a level output 3.0 3.0 0.4 0.4 i ol = 4 ma voltage b n , y n 3.0 3.0 0.8 0.8 i ol = 14 ma b n , y n 3.0 4.5 0.77 0.77 i ol = 14 ma plh 3.0 3.0 0.85 0.95 i ol = 84 ma plh 3.0 4.5 0.8 0.9 i ol = 84 ma r d maximum output b 1 - b 8 , y 9 -y 13 3.3 3.3 60 60 ? (note 5)(note 7) impedance 3.3 5.0 55 55 minimum output b 1 - b 8 , y 9 - y 13 3.3 3.3 30 30 (note 5)(note 7) impedance 3.3 5.0 35 35 r p maximum pull-up b 1 - b 8 , y 9 - y 13, 3.3 3.3 1650 1650 ? resistance c 14 - c 17 3.3 5.0 1650 1650 minimum pull-up b 1 -b 8 , y 9 - y 13 3.3 3.3 1150 1150 ? resistance c 14 - c 17 3.3 5.0 1150 1150 i ih maximum input a 9 - a 13 , plh in , 3.6 3.6 1.0 1.0 a v i = 3.6v current in hd, dir, hlh in high state c 14 - c 17 3.6 3.6 50.0 50.0 v i = 3.6v c 14 -c 17 3.6 5.5 100 100 v i = 5.5v i il maximum input a 9 - a 13 , plh in , 3.6 3.6 ? 1.0 ? 1.0 av i = 0.0v current in hd, dir, hlh in low state c 14 - c 17 3.6 3.6 ? 3.5 ? 3.5 ma v i = 0.0v c 14 - c 17 3.6 5.5 ? 5.0 ? 5.0 i ozh maximum output a 1 - a 8 3.6 3.6 20 20 a v o = 3.6v disable current b 1 - b 8 3.6 3.6 50 50 v o = 3.6v (high) b 1 - b 8 3.6 5.5 100 100 v o = 5.5v i ozl maximum a 1 - a 8 3.6 3.6 ? 20 ? 20 a v o = 0.0v output disable b 1 - b 8 3.6 3.6 ? 3.5 ? 3.5 ma current (low) b 1 - b 8 3.6 5.5 ? 5.0 ? 5.0 i ozpu maximum power-up y 9 - y 13 0 to 1.5 0 to 1.5 350 350 av o = 5.5v disable current b 1 - b 8 (note 8) (note 8) ? 5 ? 5mav o = 0.0v i ozpd maximum power-down y 9 - y 13 0 to 1.5 0 to 1.5 350 350 av o = 5.5v disable current b 1 - b 8 (note 8) (note 8) ? 5 ? 5mav o = 0.0v i off power down b 1 - b 8 , y 9 - y 13 , 0.0 0.0 100 100 av o = 5.5v output leakage plh i off power down c 14 ? c 17 , hlh in 0.0 0.0 100 100 av i = 5.5v input leakage i off ? icc power down 0.0 0.0 250 250 a (note 6) leakage to v cc i off ? icc2 power down leakage 0.0 0.0 250 250 a (note 6) to v cc ? cable i cc maximum supply 3.6 3.6 45 45 ma v i = v cc or gnd current 3.6 5.5 70 70 ma v i = v cc or gnd
7 www.fairchildsemi.com 74lvxz161284 74lvxz161284b ac electrical characteristics note 9: open drain note 10: t skew is measured for common edge output transitions and compares the measured propagation delay for a given path type: (i) a 1 ? a 8 to b 1 ? b 8 , a 9 ? a 13 to y 9 ? y 13 (ii) b 1 ? b 8 to a 1 ? a 8 (iii) c 14 ? c 17 to a 14 ? a 17 note 11: this parameter is guaranteed but not tested, characterized only. capacitance note 12: c i/o is measured at frequency = 1 mhz, per mil-std-883b, method 3012 symbol parameter t a = 0 c to + 70 ct a = ? 40 c to + 85 c units figure number v cc = 3.0v ? 3.6v v cc = 3.0v ? 3.6v v cc ? cable = 3.0v ? 5.5v v cc ? cable = 3.0v ? 5.5v min max min max t phl a 1 ? a 8 to b 1 ? b 8 2.0 40.0 2.0 44.0 ns figure 3 t plh a 1 ? a 8 to b 1 ? b 8 2.0 40.0 2.0 44.0 ns figure 4 t phl b 1 ? b 8 to a 1 ? a 8 2.0 40.0 2.0 44.0 ns figure 5 t plh b 1 ? b 8 to a 1 ? a 8 2.0 40.0 2.0 44.0 ns figure 5 t phl a 9 ? a 13 to y 9 ? y 13 2.0 40.0 2.0 44.0 ns figure 3 t plh a 9 ? a 13 to y 9 ? y 13 2.0 40.0 2.0 44.0 ns figure 4 t phl c 14 ? c 17 to a 14 ? a 17 2.0 40.0 2.0 44.0 ns figure 5 t plh c 14 ? c 17 to a 14 ? a 17 2.0 40.0 2.0 44.0 ns figure 5 t skew lh-lh or hl-hl 10.0 12.0 ns (note 10) t phl plh in to plh 2.0 40.0 2.0 44.0 ns figure 3 t plh plh in to plh 2.0 40.0 2.0 44.0 ns figure 4 t phl hlh in to hlh 2.0 40.0 2.0 44.0 ns figure 5 t plh hlh in to hlh 2.0 40.0 2.0 44.0 ns figure 5 t phz output disable time 2.0 15.0 2.0 18.0 ns figure 9 t plz dir to a 1 ? a 8 2.0 15.0 2.0 18.0 t pzh output enable time 2.0 50.0 2.0 50.0 ns figure 10 t pzl dir to a 1 ? a 8 2.0 50.0 2.0 50.0 t phz output disable time 2.0 50.0 2.0 50.0 ns figure 11 t plz dir to b 1 ? b 8 2.0 50.0 2.0 50.0 t pen output enable time 2.0 25.0 2.0 28.0 ns figure 4 hd to b 1 ? b 8 , y 9 ? y 13 2.0 25.0 2.0 28.0 t pdis output disable time 2.0 25.0 2.0 28.0 ns figure 4 hd to b 1 ? b 8 , y 9 ? y 13 2.0 25.0 2.0 28.0 t pen ? t pdis output enable- 10.0 12.0 ns output disable t slew output slew rate t plh b 1 ? b 8 , y 9 ? y 13 0.05 0.40 0.05 0.40 v/ns figure 7 t phl 0.05 0.40 0.05 0.40 figure 6 t r , t f t rise and t fall 120 120 ns figure 8 b 1 ? b 8 (note 9), 120 120 (note 11) y 9 ? y 13 (note 9) symbol parameter typ units conditions c in input capacitance 3 pf v cc = 0.0v (hd, dir, a 9 ? a 13 , c 14 ? c 17 , plh in and hlh in ) c i/o (note 12) i/o pin capacitance 5 pf v cc = 3.3v
www.fairchildsemi.com 8 74lvxz161284 74lvxz161284b ac loading and waveforms pulse generator for all pulses: rate 1.0 mhz; z o 50 ? ; t f 2.5 ns, t r 2.5 ns. figure 3. port a to b and a to y propagation delay waveforms figure 4. port a to b and a to y output waveforms figure 5. port b to a, c to a and hlhin to hlh propagation delay waveforms
9 www.fairchildsemi.com 74lvxz161284 74lvxz161284b ac loading and waveforms (continued) figure 6. port a to b and a to y hl slew test load and waveforms figure 7. port a to b and a to y lh slew test load and waveforms
www.fairchildsemi.com 10 74lvxz161284 74lvxz161284b ac loading and waveforms (continued) t r = output rise time, open drain t f = output fall time, open drain figure 8. ports a to b and a to y rise and fall test load and waveforms for open drain outputs figure 9. t phz and t plz test load and waveforms, dir to a 1 ? a 8
11 www.fairchildsemi.com 74lvxz161284 74lvxz161284b ac loading and waveforms (continued) figure 10. t pzh and t pzl test load and waveforms, dir to a 1 ? a 8 figure 11. t phz and t plz test load and waveforms dir to b 1 ? b 8
www.fairchildsemi.com 12 74lvxz161284 74lvxz161284b physical dimensions inches (millimeters) unless otherwise noted 48-lead small shrink outline package (ssop), jedec mo-118, 0.300" wide package number ms48a
13 www.fairchildsemi.com 74lvxz161284 74lvxz161284b low voltage ieee 161284 translating transceiver with power-up protection physical dimensions inches (millimeters) unless otherwise noted (continued) 48-lead thin shrink small outline package (tssop), jedec mo-153, 6.1mm wide package number mtd48 fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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