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| publication number s29cd-j_cl-j_00 revision b amendment 1 issue date september 27, 2006 s29cd-j & s29cl-j flash family s29cd032j, s29cd016j, s29cl032j, s29cl016j 32/16 megabit cmos 2.6 volt or 3.3 volt-only simultaneous read/write, dual boot, burst mode flash memory with versatilei/o? data sheet preliminary notice to readers: this document indicates states the current technical specifications regarding the spansi on product(s) described herein. the preliminary status of this document in dicates that a product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.
ii s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary notice on data sheet designations spansion issues data sheets with advance info rmation or preliminary de signations to advise readers of product information or intended specif ications throughout the product life cycle, in - cluding development, qualification, initial production, and full production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their de - sign. the following descriptions of spansion data sheet designations are presented here to high - light their presence and definitions. advance information the advance information designation indicates that spansion is developing one or more specific products, but has not committed any design to pr oduction. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion therefore places the following conditions upon advance information con - tent: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without con- tacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. this designation covers several aspects of the prod - uct life cycle, including product qualification, in itial production, and the su bsequent phases in the manufacturing process that occur before full production is achi eved. changes to the technical specifications presented in a preliminary docume nt should be expected while keeping these as - pects of production under consid eration. spansion places the fo llowing conditions upon prelimi - nary content: ?this document states the current technical specific ations regarding the spansion product(s) described herein. the preliminary status of this document indi cates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifica- tions due to changes in technical specifications.? combination some data sheets will contain a combination of pr oducts with different designations (advance in - formation, preliminary, or full pr oduction). this type of document will distinguish these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with dc charac teristics table and ac erase an d program table (in the table notes). the disclaimer on the first page refe rs the reader to the notice on this page. full production (no desi gnation on document) when a product has been in produc tion for a period of time such th at no changes or only nominal changes are expected, the preliminary designatio n is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a descript ion or to correct a typographical error or incor - rect specification. spansion applies the followi ng conditions to documents in this category: ?this document states the current technical specific ations regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that sub- sequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these docume nt designations may be directed to your local sales office. publication number s29cd-j_cl-j_00 revision b amendment 1 issue date september 27, 2006 general description the spansion s29cd-j and s29cl-j devices are floating gate products fabricated in 110-nm process technology. these burst-mode flash devices are capable of performing simultaneo us read and write operations with zero latency on two separate banks, using separate data and address pins. th ese products can operate up to 75 mhz (32 mb) or 66 mhz (16 mb), and use a single v cc of 2.5v to 2.75v (s29cd-j) or 3.0v to 3.6v (s29cl-j) that make them ideal for today's demanding automotive applications. distinctive characteristics ? single 2.6 v (s29cd-j) or 3.3 v (s29cl-j) for read/program/erase ? 110 nm floating gate technology ? simultaneous read/write operation with zero latency ? x32 data bus ? dual boot sector config uration (top and bottom) ? flexible sector architecture ? cd016j & cl016j: eight 2k double word, thirty-two 16k double word, and eight 2k double word sectors ? cd032j & cl032j: eight 2k double word, sixty-two 16k double word, and eight 2k double word sectors ? versatilei/o? control (1.65v to 3.6v) ? programmable burst interface ? linear for 2, 4, and 8 double word burst with or without wrap around ? secured silicon sector that can be either factory or customer locked ? 20 year data retention (typical) ? cycling endurance: 1 million write cycles per sector (typical) ? command set compatible with jedec (jc42.4) standard ? supports common flash interface (cfi) ? extended temperature range ? persistent and password methods of advanced sector protection ? unlock bypass program command to reduce programming time ? acc input pin to reduce factory programming time ? data polling bits indicate program and erase operation completion ? hardware (wp#) protection of two outermost sectors in the large bank ? ready/busy (ry/by#) output indicates data available to system ? suspend and resume commands for program and erase operation ? offered packages ?80-pin pqfp ? 80-ball fortified bga ? pb-free package option available ? known good die performance characteristics s29cd-j & s29cl-j flash family s29cd032j, s29cd016j, s29cl032j, s29cl016j 32/16 megabit cmos 2.6 volt or 3.3 volt-only simultaneous read/write , dual boot, burst mode flash memory with versatilei/o? data sheet preliminary read access times speed option (mhz) 75 (32mb only) 66 56 40 max asynch. access time, ns (t acc ) 48 54 54 54 max synch. burst access, ns (t bacc ) 7.5 (fbga) 8 8 8 min initial clock delay (clock cycles) 5443 max ce# access time, ns (t ce ) 52 54 54 54 max oe# access time, ns (t oe ) 20 20 20 20 current consumption (max values) continuous burst read @ 75mhz 90 ma program 50 ma erase 50 ma standby mode 60 a typical program and erase times double word programming 18 s sector erase 1.0 s 2 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary table of contents 1 ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 input/output descriptions and logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4 block diagram of simultaneous read/write circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 physical dimensions/connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 80-pin pqfp connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.2 prq080?80-lead plastic quad flat package physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.3 80-ball fortified bga connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.1 special package handling instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 laa080?80-ball fortified ball grid array (13 x 11 mm) physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 specification bulletins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 hardware and software support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 contacting spansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7 product overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 device operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.2 asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4 synchronous (burst) read mode & configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.4.1 2-, 4-, 8- double word linear burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4.2 initial burst access delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 autoselect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.6 versatilei/o? (v io ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7 program/erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7.1 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7.2 sector erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.3 chip erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.4 erase suspend / erase resume commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.7.5 program suspend/program resume commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.7.6 accelerated program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.7.7 unlock bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.7.8 simultaneous read/write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.8 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 8.8.1 dq7: data# polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.8.2 dq6: toggle bit i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.8.3 dq2: toggle bit ii. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.8.4 reading toggle bits dq6/dq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.8.5 dq5: exceeded timing limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.8.6 dq3: sector erase timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.8.7 ry/by#: ready/busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.9 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 advanced sector protection/unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 advanced sector protection overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2 persistent protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9.2.1 programming ppb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.2.2 erasing ppb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.3 persistent protection bit lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.4 dynamic protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.5 password protection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 3 preliminary 9.6 hardware data protection methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6.1 wp# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6.2 low v cc write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6.3 write pulse ?glitch protection? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6.4 power-up write inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6.5 v cc and v io power-up and power-down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.6.6 logical inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 secured silicon sector flash memory region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 secured silicon sector protection bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.2 secured silicon sector entry and exit commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11 electronic marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12 power conservation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 automatic sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.3 hardware reset# input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12.4 output disable (oe#). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 13 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 15 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.1 cmos compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 15.2 zero power flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 16 test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 17.1 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 18 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 18.1 v cc and v io power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 18.2 asynchronous operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 18.3 synchronous operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 18.4 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 18.5 write protect (wp#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 18.6 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 18.7 alternate ce# controlled erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.8 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.9 latchup characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 18.10pqfp and fortified bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19 appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 19.1 common flash memory interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 20 appendix 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 20.1 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 21 revision summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 4 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary figures figure 8.1 asynchronous read operation .......................................................................................... .................21 figure 8.2 synchronous/asynchronous state diagram ................ ............................................................... ..........23 figure 8.3 end of burst indicator (ind/wai t#) timing for linear 8-word burst operation ........................................25 figure 8.4 initial burst delay control .......................................................................................... .......................26 figure 8.5 program operation .................................................................................................... ......................29 figure 8.6 erase operation...................................................................................................... .........................31 figure 8.7 data# polling algorithm.............................................................................................. ......................35 figure 8.8 toggle bit algorithm ................................................................................................. .......................38 figure 9.1 advanced sector protection/unp rotection.............................................................................. ..............41 figure 9.2 pbb program operation ................................................................................................ ....................43 figure 9.3 ppb erase operation .................................................................................................. ......................44 figure 13.1 maximum negative overshoot wave form ................................................................................. ...........50 figure 13.2 maximum positive overshoot waveform .................. ............................................................... ............50 figure 15.1 i cc1 current vs. time (showing active and automatic sleep currents) ....................................................53 figure 15.2 typical i cc1 vs. frequency ................................................................................................................5 3 figure 16.1 test setup .......................................................................................................... ............................54 figure 17.1 input waveforms and measuremen t levels .............................................................................. ...........54 figure 18.1 v cc and v io power-up diagram .........................................................................................................55 figure 18.2 conventional read operations timings ................ ................................................................ ...............56 figure 18.3 asynchronous command write timing................................................................................... .............57 figure 18.4 burst mode read (x32 mode) .......................................................................................... ..................59 figure 18.5 synchronous command write/read timing ................ ............................................................... ..........59 figure 18.6 reset# timings...................................................................................................... ........................60 figure 18.7 wp# timing.......................................................................................................... ..........................61 figure 18.8 program operation timings.............................. ............................................................. ....................62 figure 18.9 chip/sector erase operation timings................................................................................. .................63 figure 18.10 back-to-back cycle timings ......................................................................................... .....................63 figure 18.11 data# polling timings (during embedded algorithms) . ................................................................ .........64 figure 18.12 toggle bit timings (during embedded algorithms) .... ................................................................ ...........64 figure 18.13 dq2 vs. dq6 for erase/erase suspend operations..................................................................... ...........64 figure 18.14 synchronous data polling timing/ toggle bit timings ................................................................. ...........65 figure 18.15 sector protect/unprotect timing diagram ............................................................................ ...............65 figure 18.16 alternate ce# cont rolled write operat ion timings................................................................... .............66 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 5 preliminary ta b l e s table 7.1 s29cd016j/cl016j (top boot)sector and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7.2 s29cd016j/cl016j (bottom boot) sect or and memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 7.3 s29cd032j/cl032j (top boot) sector & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 7.4 s29cd032j/cl032j (bottom boot) sect or & memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 table 8.1 device bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8.2 32- bit linear and burst data order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8.3 valid configuration register bit definition for ind/wa it# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8.4 burst initial access delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 8.5 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8.6 configuration register after device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8.7 s29cd-j & s29cl-j flash family au toselect codes (high voltage method) . . . . . . . . . . . . . . . . . . . . . . . 2 8 table 8.8 dq6 and dq2 indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 8.9 write operation status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8.10 reset command timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9.1 sector protection schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10.1 secured silicon sector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 17.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18.1 v cc and v io power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 18.2 asynchronous read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 18.3 burst mode read for 32 mb and 16 mb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 18.4 hardware reset (reset#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18.5 erase/program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 18.6 erase and programming performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 18.7 latchup characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 18.8 pqfp and fortified bga pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 19.1 cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 19.2 cfi system interface string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 19.3 device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 19.4 cfi primary vend or-specific extended query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 20.1 memory array command definitions (x32 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 20.2 sector protection command definitions (x32 mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 1 ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations lists configurations planned to be supported in volume for this device. consul t your local sales office to c onfirm availability of specific valid combinations and to check on newly released combinations. note on bga package markings: the ordering part number that appears on bga packages omits the leading ?s29?. s29cd032j 0 j f a i 0 0 0 packing type 0 = tray, fbga: 180 per tray, min. 10 trays per box tray, pqfp: 66 per tray, min. 10 trays per box 2 = 7? tape and reel, fbga: 400 per reel 3 = 13? tape and reel, fbga: 1600 per reel 13? tape and reel, pqfp: 500 per reel boot sector option (16th character) 0 = top boot with simultaneous operation 1 = bottom boot with simultaneous operation 3 = top boot without simultaneous operation 4 = bottom boot without simultaneous operation autoselect id option (15th character) 0 = 7e, 08, 01/00 autoselect id 1 = 7e, 36, 01/00 autoselect id s29cd016j only 0 = 7e, 46, 01/00 autoselect id s29cl016j only 0 = 7e, 09, 01/00 autoselect id s29cd032j only 0 = 7e, 49, 01/00 autoselect id s29cl032j only temperature range i = industrial (?40c to +85c) m = extended (?40c to +125c) material set a=standard f=pb-free option package type q = plastic quad flat package (pqfp) f = fortified ball grid array, 1.0 mm pitch package clock frequency (10th character) j = 40 mhz m = 56 mhz p = 66 mhz r = 75 mhz (contact factory) initial burst access delay (9th character) 0 = 5-1-1-1, 6-1-1-1, and above 1 = 4-1-1-1 device number/description s29cd032j/s29cd016j (2.5 volt-only) s29cl032j/s29cl016j (3.3 volt-only) 32 or 16 megabit (1 m or 512 k x 32-bit) cmos burst mode, dual boot, simultaneous read/write flash memory manufactured on 110 nm floating gate technology s29cd-j/s29cl-j valid combinations s29cd016j s29cl016j 0j, 0m, 0p, 1j qai, qfi, qam, qfm fai, ffi, fam, ffm 00, 01, 02, 03, 10, 11, 12, 13 1m 02, 03, 12, 13 s29cd032j s29cl032j 0j, 0m, 0p, 0r, 1j qai, qfi, qan, qfn fai, ffi, fan, ffn 00, 01, 02, 03, 10, 11, 12, 13 1m 02, 03, 12, 13 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 7 preliminary 2 input/output descri ptions and logic symbols table identifies the input and output package connections provided on the device. symbol type description a19-a0 input address lines for s29cd-j and s29cl-j (a18-a0 for 16mb and a19-a0 for 32mb). a9 supports 12v autoselect input. dq31-dq0 i/o data input/output ce# input chip enable. this signal is asynchronous relative to clk for the burst mode. oe# input output enable. this signal is asynchronous relative to clk for the burst mode. we# input write enable vcc supply device power supply. this signal is asynchronous relative to clk for the burst mode. vio input versatilei/o tm input. vss i/o ground nc no connect not connected internally ry/by# output ready/busy output and open drain which require a external pull up resistor. when ry/by# = v oh , the device is ready to accept read operations and commands. when ry/by# = v ol , the device is either executing an embedded algorithm or the device is executing a hardware reset operation. clk input clock input that can be tied to the system or microprocessor clock and provides the fundamental timing and internal operating frequency. avd # input load burst address input. indicates that the valid address is present on the address inputs. ind# output end of burst indicator for finite bursts only. ind is low when the last word in the burst sequence is at the data outputs. wait# output provides data valid feedback only when the burst length is set to continuous. wp# input write protect input. at v il , disables program and erase functions in two outermost sectors of the large bank. acc input acceleration input. at v hh , accelerates erasing and programming. when not used for acceleration, acc = v ss to v cc . reset# input hardware reset. 8 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 3 block diagram note: address bus is a19?a0 for 32 mb device, a 18?a0 for 16 mb device. data bus is d31?dq0. input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# acc wp# word# ce# oe# dq max ? dq0 a max ?a0 data latch y-gating cell matrix address latch dq max ?dq0 a max ?a0 burst state control burst address counter adv# clk a max ?a0 v io ind/ wait# september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 9 preliminary 4 block diagram of simultaneous read/write circuit v cc v ss upper bank address reset# we# ce# adv# state control & command register upper bank x-decoder y-decoder latches and control logic oe# dq max ?dq0 dq max ?dq0 lower bank y-decoder x-decoder latches and control logic lower bank address status control a max ?a0 a max ?a0 a max ?a0 a max ?a0 a max ?a0 dq max ?dq0 dq max ?dq0 10 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 5 physical dimensions/connection diagrams 5.1 80-pin pqfp connection diagram notes: 1. on 16 mb device, pin 44 (a19) is nc. 2. pin 69 (ry/by#) is open drain and requires an external pull-up resistor. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 dq16 dq17 dq18 dq19 v ccq v ss dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 v ccq v ss dq28 dq29 dq30 dq31 nc a0 a1 a2 dq15 dq14 dq13 dq12 v ss v ccq dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 v ss v ccq dq3 dq2 dq1 dq0 a19 a18 a17 a16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 nc ind/wait# nc wp# we# oe# ce# v cc nc v ss adv# ry/by# nc clk reset# v ccq a3 a4 a5 a6 a7 a8 v ss acc v cc a9 a10 a11 a12 a13 a14 a15 25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80-pin pqfp september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 11 preliminary 5.2 prq080?80-lead plastic quad fl at package physical dimensions 3213\38.4 c package pqr 080 jedec mo-108(b)cb-1 notes symbol min nom max a -- -- 3.35 a1 0.25 -- -- a2 2.70 2.80 2.90 b 0.30 -- 0.45 see note 4 c 0.15 -- 0.23 d 17.00 17.20 17.40 d1 13.90 14.00 14.10 see note 3 d3 -- 12.0 -- reference e -- 0.80 -- basic, see note 7 e 23.00 23.20 23.40 e1 19.90 20.00 20.10 see note 3 e3 -- 18.40 -- reference aaa --- 0.20 --- ccc 0.10 l 0.73 0.88 1.03 p24 q40 r64 s80 notes: 1. all dimensions and tolerances conform to ansi y14.5m-1982. 2. datum plane -a- is located at the mold parting line and is coincident with the bottom of the lead where the lead exits the plastic body. 3. dimensions "d1" and "e1" do not includ mold protrusion. allowable protrusion is 0.25 mm per side. dimensions "d1" and "e1" include mold mismatch and are determined at datum plane -a- 4. dimension "b" does not include dambar protrusion. 5. controlling dimensions: millimeter. 6. dimensions "d" and "e" are measured from both innermost and outermost points. 7. deviation from lead-tip true position shall be within ?.0076 mm for pitch > 0.5 mm and within ?.04 for pitch < 0.5 mm. 8. lead coplanarity shall be within: (refer to 06-500) 1 - 0.10 mm for devices with lead pitch of 0.65 - 0.80 mm 2 - 0.076 mm for devices with lead pitch of 0.50 mm. coplanarity is measured per specification 06-500. 9. half span (center of package to lead tip) shall be within ?.0085". b c section s-s 6 3 3 6 -b- pin r pin s -a- pin one i.d. d1 d d3 pin q -d- pin p e e1 e3 see note 3 a a1 a2 -c- -a- seating plane 2 e basic see detail x s s detail x 0.25 a c ccc sd s 4 c ab m a a b 0?-7? a 0?min. l gage plane 7? typ. 0.30 ?0.05 r 7? typ. 0.20 min. flat shoulder 12 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 5.3 80-ball fortified bg a connection diagrams notes: 1. on 16 mb device, ball d3 (a19) is nc. 2. ball f5 (ry/by#) is open drain and re quires an external pull-up resistor. 5.3.1 special package handling instructions special handling is required for flash memory pr oducts in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b8 c8 d8 e8 f8 g8 h8 dq20 v ccq v ss v ccq dq29 a0 a1 dq18 dq23 dq24 dq26 dq30 nc a4 dq19 dq21 dq25 dq28 dq31 a7 a5 dq17 dq22 ry/by# dq27 nc nc a8 wp# dq9 dq5 dq1 nc a10 a9 dq11 dq10 dq6 dq2 a19 a11 a12 a3 a4 a5 a6 a7 a8 a2 a3 a6 v ss acc v cc b2 c2 d2 e2 f2 g2 h2 dq12 dq8 dq7 dq4 dq0 a18 a13 a2 a14 b1 c1 d1 e1 f1 g1 h1 dq13 j3 j4 j5 j6 j7 j8 dq16 ind/wait# oe# ce# nc adv# j2 dq14 j1 dq15 k3 k4 k5 k6 k7 k8 nc nc we# v cc v ss clk k2 reset# k1 v ccq v ccq v ss v ccq dq3 a17 a16 a1 a15 80-ball fortified bga september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 13 preliminary 5.4 laa080?80-ball fortified ball gr id array (13 x 11 mm) physical dimensions 3214\38.12c package laa 080 jedec n/a 13.00 x 11.00 mm note package symbol min nom max a -- -- 1.40 profile height a1 0.40 -- -- standoff a2 0.60 -- -- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 9.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 10 matrix size d direction me 8 matrix size e direction n 80 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd/se 0.50 bsc solder ball placement notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row , sd or se = e/2 8. n/a 9. "+" indicates the theoretical center of depopulated balls. bottom view side view top view 2x 2x c 0.20 c 0.20 6 7 7 a c c 0.10 0.25 m m b c 0.25 0.15 c a b c seating plane j k ed (ink or laser) corner a1 a2 d e 0.50 a1 corner id. 1.00?.5 1.00?.5 a a1 corner a1 nx b sd se ee e1 d1 1 2 3 4 5 6 7 8 a cb d fe g h 14 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 6 additional resources visit www.spansion.com to obtain the following related documents: 6.1 application notes the following is a list of application notes related to this product. all spansion application notes are available at http://www.spansion.com/support/technical_documents/ application_notes.html ? using the operation status bits in amd devices ? understanding page mode flash memory devices ? mirrorbit? flash memory write buffer programming and page buffer read ? common flash interface version 1.4 vendor specific extensions 6.2 specification bulletins contact your local sales office for details. 6.3 hardware and software support downloads and related information on flash device support is available at www.spansion.com/support/index.html ? spansion low-level drivers ? enhanced flash drivers ? flash file system downloads and related information on simulati on modeling and cad modeling support is avail - able at http://www.spansion.com/support/simulation_models.html ? vhdl and verilog ? ibis ? orcad an faq (frequently asked questions) list is available at www.spansion.com/support/ses/index.html 6.4 contacting spansion obtain the latest list of company locations and contact information on our web site at www.spansion.com/about/location.html september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 15 preliminary 7 product overview the s29cd-j and s29cl-j families consist of 32 mb and 16 mb, 2.6 volts-only (cd-j) or 3.3 volts- only (cl-j), simultaneous read/write, dual boot burst mode flash device s optimized for today's automotive designs. these devices are organized in 1,048,576 double words (32mb) or 524,288 double words (16mb) and are capable of linear burst read (2, 4, or 8 double words) with or without wraparound. (note that 1 double word = 32 bits.) these products also offer single word programming with program/ erase suspend and resume functionality. additional features include: ? advanced sector protection methods for protecting sectors as re - quired. ? 256 bytes of secured silicon area for storing customer or factory secured information. the secured silicon sector is one-time pro - grammable. ? electronic marking. 16 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 7.1 memory map the s29cd-j and s29cl-j devices consist of two banks organized as shown in table 7.1 , ta b l e 7.2 , table 7.3 and table 7.4 . notes: 1. secured silicon sector overla ys this sector when enabled. 2. the bank address is determined by a18 and a17. ba = 00 for bank 1 and ba = 01, 10, or 11 for bank 2. 3. this sector has the additional wp# pin sector protection feature. ta b l e 7 . 1 s29cd016j/cl016j (top boot)s ector and memory address map sector sector group x32 address range (a18:a0) sector size (kdwords) sector sector group x32 address range (a18:a0) sector size (kdwords) bank 0 (note 2) sa0 (note 1) sg0 00000h?007ffh 2 bank 1 (note 2) sa15 sg10 20000h?23fffh 16 sa1 sg1 00800h?00fffh 2 sa16 24000h?27fffh 16 sa2 sg2 01000h?017ffh 2 sa17 28000h?2bfffh 16 sa3 sg3 01800h?01fffh 2 sa18 2c000h?2ffffh 16 sa4 sg4 02000h?027ffh 2 sa19 sg11 30000h?33fffh 16 sa5 sg5 02800h?02fffh 2 sa20 34000h?37fffh 16 sa6 sg6 03000h?037ffh 2 sa21 38000h?3bfffh 16 sa7 sg7 03800h?03fffh 2 sa22 3c000h?3ffffh 16 sa8 sg8 04000h?07fffh 16 sa23 sg12 40000h?43fffh 16 sa9 08000h?0bfffh 16 sa24 44000h?47fffh 16 sa10 0c000h?0ffffh 16 sa25 48000h?4bfffh 16 sa11 sg9 10000h?13fffh 16 sa26 4c000h?4ffffh 16 sa12 14000h?17fffh 16 sa27 sg13 50000h?53fffh 16 sa13 18000h?1bfffh 16 sa28 54000h?57fffh 16 sa14 1c000h?1ffffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 sa31 sg14 60000h?63fffh 16 sa32 64000h?67fffh 16 sa33 68000h?6bfffh 16 sa34 6c000h?6ffffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 sg16 7c000h?7c7ffh 2 sa39 sg17 7c800h?7cfffh 2 sa40 sg18 7d000h?7d7ffh 2 sa41 sg19 7d800h?7dfffh 2 sa42 sg20 7e000h?7e7ffh 2 sa43 sg21 7e800h?7efffh 2 sa44 (note 3) sg22 7f000h?7f7ffh 2 sa45 (note 3) sg23 7f800h?7ffffh 2 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 17 preliminary notes: 1. this sector has the additional wp# pin sector protection feature. 2. the bank address is determined by a18 and a17. ba = 00, 01, or 10 for bank 0 and ba = 11 for bank 1. 3. secured silicon sector overla ys this sector when enabled. ta b l e 7 . 2 s29cd016j/cl016j (bottom boot) sector and memory address map sector sector group x32 address range (a18:a0) sector size (kdwords) sector sector group x32 address range (a18:a0) sector size (kdwords) bank 0 (note 2) sa0 (note 1) sg0 00000h?007ffh 2 bank 1 (note 2) sa31 sg14 60000h?63fffh 16 sa1 (note 1) sg1 00800h?00fffh 2 sa32 64000h?67fffh 16 sa2 sg2 01000h?017ffh 2 sa33 68000h?6bfffh 16 sa3 sg3 01800h?01fffh 2 sa34 6c000h?6ffffh 16 sa4 sg4 02000h?027ffh 2 sa35 sg15 70000h?73fffh 16 sa5 sg5 02800h?02fffh 2 sa36 74000h?77fffh 16 sa6 sg6 03000h?037ffh 2 sa37 78000h?7bfffh 16 sa7 sg7 03800h?03fffh 2 sa38 sg16 7c000h?7c7ffh 2 sa8 sg8 04000h?07fffh 16 sa39 sg17 7c800h?7cfffh 2 sa9 08000h?0bfffh 16 sa40 sg18 7d000h?7d7ffh 2 sa10 0c000h?0ffffh 16 sa41 sg19 7d800h?7dfffh 2 sa11 sg9 10000h?13fffh 16 sa42 sg20 7e000h?7e7ffh 2 sa12 14000h?17fffh 16 sa43 sg21 7e800h?7efffh 2 sa13 18000h?1bfffh 16 sa44 sg22 7f000h?7f7ffh 2 sa14 1c000h?1ffffh 16 sa45 (note 3) sg23 7f800h?7ffffh 2 sa15 sg10 20000h?23fffh 16 sa16 24000h?27fffh 16 sa17 28000h?2bfffh 16 sa18 2c000h?2ffffh 16 sa19 sg11 30000h?33fffh 16 sa20 34000h?37fffh 16 sa21 38000h?3bfffh 16 sa22 3c000h?3ffffh 16 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa27 sg13 50000h?53fffh 16 sa28 54000h?57fffh 16 sa29 58000h?5bfffh 16 sa30 5c000h?5ffffh 16 18 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary note: 1. secured silicon sector overla ys this sector when enabled. 2. the bank address is determined by a19 and a18. ba = 00 for bank 0 and ba = 01, 10, or 11 for bank 1. 3. this sector has the additional wp# pin sector protection feature. ta b l e 7 . 3 s29cd032j/cl032j (top boot) sector & memory address map sector sector group x32 address range (a19:a0) sector size (kdwords) sector sector group x32 address range (a19:a0) sector size (kdwords) bank 0 (note 2) bank 1 (note 2) sa0 (note 1) sg0 00000h?007ffh 2 sa23 sg12 40000h?43fffh 16 sa1 sg1 00800h?00fffh 2 sa24 44000h?47fffh 16 sa2 sg2 01000h?017ffh 2 sa25 48000h?4bfffh 16 sa3 sg3 01800h?01fffh 2 sa26 4c000h?4ffffh 16 sa4 sg4 02000h?027ffh 2 sa27 sg13 50000h?53fffh 16 sa5 sg5 02800h?02fffh 2 sa28 54000h?57fffh 16 sa6 sg6 03000h?037ffh 2 sa29 58000h?5bfffh 16 sa7 sg7 03800h?03fffh 2 sa30 5c000h?5ffffh 16 sa8 sg8 04000h?07fffh 16 sa31 sg14 60000h?63fffh 16 sa9 08000h?0bfffh 16 sa32 64000h?67fffh 16 sa10 0c000h?0ffffh 16 sa33 68000h?6bfffh 16 sa11 sg9 10000h?13fffh 16 sa34 6c000h?6ffffh 16 sa12 14000h?17fffh 16 sa35 sg15 70000h?73fffh 16 sa13 18000h?1bfffh 16 sa36 74000h?77fffh 16 sa14 1c000h?1ffffh 16 sa37 78000h?7bfffh 16 sa15 sg10 20000h?23fffh 16 sa38 7c000h?7ffffh 16 sa16 24000h?27fffh 16 sa39 sg16 80000h?83fffh 16 sa17 28000h?2bfffh 16 sa40 84000h?87fffh 16 sa18 2c000h?2ffffh 16 sa41 88000h?8bfffh 16 sa19 sg11 30000h?33fffh 16 sa42 8c000h?8ffffh 16 sa20 34000h?37fffh 16 sa43 sg17 90000h?93fffh 16 sa21 38000h?3bfffh 16 sa44 94000h?97fffh 16 sa22 3c000h?3ffffh 16 sa45 98000h?9bfffh 16 sa46 9c000h?9ffffh 16 sa47 sg18 a0000h?a3fffh 16 sa48 a4000h?a7fffh 16 sa49 a8000h?abfffh 16 sa50 ac000h?affffh 16 sa51 sg19 b0000h?b3fffh 16 sa52 b4000h?b7fffh 16 sa53 b8000h?bbfffh 16 sa54 bc000h?bffffh 16 sa55 sg20 c0000h?c3fffh 16 sa56 c4000h?c7fffh 16 sa57 c8000h?cbfffh 16 sa58 cc000h?cffffh 16 sa59 sg21 d0000h?d3fffh 16 sa60 d4000h?d7fffh 16 sa61 d8000h?dbfffh 16 sa62 dc000h?dffffh 16 sa63 sg22 e0000h?e3fffh 16 sa64 e4000h?e7fffh 16 sa65 e8000h?ebfffh 16 sa66 ec000h?effffh 16 sa67 sg23 f0000h?f3fffh 16 sa68 f4000h?f7fffh 16 sa69 f8000h?fbfffh 16 sa70 sg24 fc000h?fc7ffh 2 sa71 sg25 fc800h?fcfffh 2 sa72 sg26 fd000h?fd7ffh 2 sa73 sg27 fd800h?fdfffh 2 sa74 sg28 fe000h?fe7ffh 2 sa75 sg29 fe800h?fefffh 2 sa76 (note 3) sg30 ff000h?ff7ffh 2 sa77 (note 3) sg31 ff800h?fffffh 2 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 19 preliminary notes: 1. this sector has the additional wp# pin sector protection feature. 2. the bank address is determined by a19 and a18. ba = 00, 01, or 10 for bank 0 and ba = 11 for bank 1. 3. the secured silicon sector overlays this sector when enabled. ta b l e 7 . 4 s29cd032j/cl032j (bottom boot) sector & memory address map sector sector group x32 address range (a19:a0) sector size (kdwor ds) sector sector group x32 address range (a19:a0) sector size (kdwor ds) bank 0 (note 2) bank 0 (continued) sa0 (note 3) sg0 00000h?007ffh 2 sa51 sg19 b0000h?b3fffh 16 sa1 (note 3) sg1 00800h?00fffh 2 sa52 b4000h?b7fffh 16 sa2 sg2 01000h?017ffh 2 sa53 b8000h?bbfffh 16 sa3 sg3 01800h?01fffh 2 sa54 bc000h?bffffh 16 sa4 sg4 02000h?027ffh 2 bank 1 (note 2) sa5 sg5 02800h?02fffh 2 sa55 sg20 c0000h?c3fffh 16 sa6 sg6 03000h?037ffh 2 sa56 c4000h?c7fffh 16 sa7 sg7 03800h?03fffh 2 sa57 c8000h?cbfffh 16 sa8 sg8 04000h?07fffh 16 sa58 cc000h?cffffh 16 sa9 08000h?0bfffh 16 sa59 sg21 d0000h?d3fffh 16 sa10 0c000h?0ffffh 16 sa60 d4000h?d7fffh 16 sa11 sg9 10000h?13fffh 16 sa61 d8000h?dbfffh 16 sa12 14000h?17fffh 16 sa62 dc000h?dffffh 16 sa13 18000h?1bfffh 16 sa63 sg22 e0000h?e3fffh 16 sa14 1c000h?1ffffh 16 sa64 e4000h?e7fffh 16 sa15 sg10 20000h?23fffh 16 sa65 e8000h?ebfffh 16 sa16 24000h?27fffh 16 sa66 ec000h?effffh 16 sa17 28000h?2bfffh 16 sa67 sg23 f0000h?f3fffh 16 sa18 2c000h?2ffffh 16 sa68 f4000h?f7fffh 16 sa27 sg13 50000h?53fffh 16 sa69 f8000h?fbfffh 16 sa28 54000h?57fffh 16 sa70 sg24 fc000h?fc7ffh 2 sa29 58000h?5bfffh 16 sa71 sg25 fc800h?fcfffh 2 sa30 5c000h?5ffffh 16 sa72 sg26 fd000h?fd7ffh 2 sa31 sg14 60000h?63fffh 16 sa73 sg27 fd800h?fdfffh 2 sa32 64000h?67fffh 16 sa74 sg28 fe000h?fe7ffh 2 sa33 68000h?6bfffh 16 sa75 sg29 fe800h?fefffh 2 sa34 6c000h?6ffffh 16 sa76 sg30 ff000h?ff7ffh 2 sa19 sg11 30000h?33fffh 16 sa77 (note 1) sg31 ff800h?fffffh 2 sa20 34000h?37fffh 16 sa21 38000h?3bfffh 16 sa22 3c000h?3ffffh 16 sa23 sg12 40000h?43fffh 16 sa24 44000h?47fffh 16 sa25 48000h?4bfffh 16 sa26 4c000h?4ffffh 16 sa35 sg15 70000h?73fffh 16 sa36 74000h?77fffh 16 sa37 78000h?7bfffh 16 sa38 7c000h?7ffffh 16 sa39 sg16 80000h?83fffh 16 sa40 84000h?87fffh 16 sa41 88000h?8bfffh 16 sa42 8c000h?8ffffh 16 sa43 sg17 90000h?93fffh 16 sa44 94000h?97fffh 16 sa45 98000h?9bfffh 16 sa46 9c000h?9ffffh 16 sa47 sg18 a0000h?a3fffh 16 sa48 a4000h?a7fffh 16 sa49 a8000h?abfffh 16 sa50 ac000h?affffh 16 20 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 8 device operations this section describes the read, program, erase, simultaneous read/write operations, and reset features of the flash devices. operations are initiated by writing specific co mmands or a sequence with specific address and data patterns into the command register (see table 8.1 ). the command register itself does not occupy any addressable memory location; rather, it is composed of latches that store the com - mands, along with the address and data info rmation needed to execute the command. the contents of the register serve as input to the internal state machine; the state machine outputs dictate the function of the device. writing incorre ct address and data values or writing them in an improper sequence may place the device in an unknown state, in which case the system must write the reset command in order to return the device to the reading array data mode. 8.1 device operation table the device must be set up appr opriately for each operation. ta b l e 8 . 1 describes the required state of each control pin for any particular operation. legend: l = logic low = v il , h = logic high = v ih , x = don?t care. notes: 1. wp# controls the two outermost sectors of the top boot bl ock or the two outermost sectors of the bottom boot block. 2. dq0 reflects the sector ppb (or sect or group ppb) and dq1 reflects the dyb ta b l e 8 . 1 device bus operation operation ce# oe# we# reset# clk adv# addresses data (dq0?dq31) read ll h h x x a in d out asynchronous write lh l h x x a in d in synchronous write lh l h a in d in standby (ce#) hx x h x x x high z output disable l h h h x x high z high z reset xx x l x x x high z ppb protection status (note 2) ll h h x x sector address, a9 = v id , a7 ? a0 = 02h 00000001h, (protected) a6 = h 00000000h (unprotect) a6 = l burst read operations load starting burst address lx h h a in x advance burst to next address with appropriate data presented on the data bus l l h h h x burst data out terminate current burst read cycle hx h h xx high z terminate current burst read cycle with reset# xx h l x x x high z terminate current burst read cycle; start new burst read cycle lh h h a in x september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 21 preliminary 8.2 asynchronous read all memories require access time to output array data. in an asynchronous read operation, data is read from one memory location at a time. addresses are presented to the device in random order, and the propagation delay through the device causes the data on its outputs to arrive asynchronously with the address on its inputs. the internal state machine is set for asynchrono usly reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is nece ssary in this mode to obtain array data. stan - dard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. the device has two control functions which must be satisfied in order to obtain data at the out - puts. ce# is the power control and should be used for device selection (ce# must be set to v il to read data). oe# is the output control and should be used to gate data to the output pins if the device is selected (oe# must be set to v il in order to read data). we# should remain at v ih (when reading data). address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addr esses and stable ce# to valid data at the output pins. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output pins (assuming the ad dresses have been stable for at least a period of t acc -t oe and ce# has been asserted for at least t ce -t oe time). figure 8.1 shows the timing diagram of an asynchronous read operation. note: operation is shown for the 32-bit data bus. for the 16-bit data bus, a-1 is required. figure 8.1 asynchronous read operation refer to asynchronous operations on page 56 for timing specifications and to figure 18.2, con - ventional read operations timings, on page 56 for another timing diag ram. icc1 in the dc characteristics table represents the active current specification for reading array data. d0 d1 d2 d3 d3 ce# clk adv# addresses data oe# we# ind/wait# v ih float v oh address 0 address 1 address 2 address 3 float 22 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 8.3 hardware reset (reset#) the reset# pin is an active low signal that is used to reset the device under any circumstances. a logic ?0? on this input forces the device out of any mode that is currently executing back to the reset state. reset# may be tied to the system reset circuitry. a system reset would thus also reset the device. to avoid a potential bus contention during a system reset, the device is isolated from the dq data bus by tristating the data outputs for the duration of the reset pulse. all data outputs are ?don?t care? during the reset operation. if reset# is asserted during a program or eras e operation, the ry/by# output remains low until the reset operation is internally complete. the ry/by# pin can be used to determine when the reset operation is complete. since the device offers simultaneous read/write operation, the host system may read a bank after a period of t ready2 , if the bank was in the read/reset mode at the time reset# was asserted. if one of the banks wa s in the middle of either a program or erase operation when reset# was asserted, the user must wait a period of t ready before accessing that bank. asserting reset# during a program or erase operation leaves erroneous data stored in the ad - dress locations being operated on at the time of device reset. these locations need updating after the reset operation is complete. see section 18.4 for timing specifications. asserting reset# active during v cc and v io power-up is required to guarantee proper device initialization until v cc and v io have reached their steady state voltages. see section 18.1 . 8.4 synchronous (burst) read mode & configuration register when a series of adjacent addresses need to be read from the device, the synchronous (or burst read) mode can be used to significantly reduce th e overall time needed for the device to output array data. after an initial access time required for the data from the first address location, sub - sequent data is output synchronized to a clock input provided by the system. the device offers a linear method of burst read operation which is discussed in 2-, 4-, 8- double word linear burst operation on page 24 . since the device defaults to asynchronous read mode after power-up or a hardware reset, the configuration register must be set in order to enable the burst read mode. other configuration register settings include the number of wait states to insert before the initial word (t iacc ) of each burst access and when rdy indicates that data is ready to be read. prior to entering the burst mode, the system first determines the configurat ion register settings (and read the current reg - ister settings if desired via the read configurat ion register command sequence), then write the configuration register command sequence. see configuration register on page 26 , and ta b l e 20.1, memory array command definitions (x32 mode), on page 71 for further details. once the configuration register is written to en able burst mode operation, all subsequent reads from the array are returned using the burst mode protocols. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 23 preliminary figure 8.2 synchronous/asynchronous state diagram the device outputs the initial word subjec t to the following operational conditions: ? t iacc specification: the time from the rising edge of the first clock cycle after addresses are latched to valid data on the device out - puts. ? configuration register setting cr13-cr10: the total number of clock cycles (wait states) that occur before valid data appears on the device outputs. the effect is that t iacc is lengthened. like the main memory access, the secured silic on sector memory is accessed with the same burst or asynchronous timing as defined in the configuration register. however, the user must recognize burst operations past the 256 byte secured silicon boundary returns invalid data. burst read operations occur only to the main flash memory arrays. the configuration register and protection bits are treated as single cycle reads, even when burst mode is enabled. read operations to these locations results in th e data remaining valid while oe# is at v il , regardless of the number of clk cycles applied to the device. power-up/ hardware reset asynchronous read mode only synchronous read mode only set burst mode configuration register command for synchronous mode (d15 = 0) set burst mode configuration register command for asynchronous mode (d15 = 1) 24 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 8.4.1 2-, 4-, 8- double wo rd linear burst operation in a linear burst read operation, a fixed number of words (2, 4, or 8 double words) are read from consecutive addresses that are determined by the group within which the starting address falls. note that 1 double word = 32 bits. see table 8.2 for all valid burst output sequences. the ind/wait# signal, or end of burst indicator signal, transitions active (v il ) during the last transfer of data in a linear burst read before a wrap around. this transition indicates that the system should initiate another adv# to start th e next burst access. if the system continues to clock the device, the next access wraps around to the starting address of the previous burst ac - cess. the ind/wait# signal is floating when not active. the ind/wait# signal is controlled by the oe# signal. if oe# is at v ih , the ind/wait# signal floats and is not driven. if oe# is at v il , the ind/ wait# signal is driven at v ih until it transitions to v il , indicating the end of the burst sequence. table 8.3 lists the valid combinations of the con - figuration register bits that impact the ind/wait# timing. see figure 8.3 for the ind/wait# timing diagram. notes: 1. the default configuration in the control register for bit 6 is "1," indicating that the device delivers data on the rising ed ge of the clk signal. 2. the device is capable of holding data for one clk cycle. 3. if reset# is asserted low during a burst access, the burst access is immediately terminated and the device defaults back to asynchronous read mode. when this happens, the dq data bus signal floats and the configuration register contents are reset to their default conditions. 4. ce# must meet the required burst read setup time s for burst cycle initiation. if ce# is taken to v ih at any time during the burst linear or burst cycle, the device immediately exits the burst sequence and floats the dq bus signal. 5. restarting a burst cycle is accomplished by taking ce# and adv# to v il . 6. a burst access is initiated and the addre ss is latched on the first rising clk edge when adv# is active or upon a rising adv# edge, whichever occurs first. if the adv# signal is ta ken to vil prior to the end of a linear burst sequence, the previous address is discarded and subsequent burst transfers are invalid. a new burst is initiated when adv# transitions back to v ih before a clock edge. 7. the oe# (output enable) pin is used to enable the linear burst data on the dq data bus pin. de-asserting the oe# pin to v ih during a burst operation floats the data bus, but the device continues to operate internally as if the burst sequence continues until the linear burst is complete. the oe# pin does not halt the burst sequence, the dq bus remains in the float state until oe# is taken to v il . 8. halting the burst sequence is acco mplished by either taking ce# to v ih or re-issuing a new adv# pulse. ta b l e 8 . 2 32- bit linear and burst data order data transfer sequence (independent of the word# pin) output data sequence (initial access address) (x16) two linear data transfers 0-1 (a0 = 0) 1-0 (a0 = 1) four linear data transfers 0-1-2-3 (a0:a-1/a1-a0 = 00) 1-2-3-0 (a0:a-1/a1-a0 = 01) 2-3-0-1 (a:a-1/a1-a0 = 10) 3-0-1-2 (a0:a-1/a1-a0 = 11) eight linear data transfers 0-1-2-3-4-5-6-7 (a1:a-1a2-a0 = 000) 1-2-3-4-5-6-7-0 (a1:a-1/a2-a0 = 001) 2-3-4-5-6-7-0-1 (a1:a-1/a2-a0 = 010) 3-4-5-6-7-0-1-2 (a1:a-1/a2-a0 = 011) 4-5-6-7-0-1-2-3 (a1:a-1/a2-a0 = 100) 5-6-7-0-1-2-3-4 (a1:a-1/a2-a0 = 101) 6-7-0-1-2-3-4-5 (a1:a-1/a2-a0 = 110) 7-0-1-2-3-4-5-6 (a1:a-1/a2-a0 = 111) ta b l e 8 . 3 valid configuration register bit definition for ind/wait# cr9 (doc) cr8 (wc) cr6 (cc) definition 001 ind/wait# = v il for 1-clk cycle, active on last transfer, driven on rising clk edge 011 ind/wait# = v il for 1-clk cycle, active on second to last transfer, driven on rising clk edge september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 25 preliminary note: operation is shown for the 32-bit data bus. figure shown wi th 3-clk initial access delay configuration, linear address, 4-doubleword burst, output on rising cld edge, data hold for 1-clk, ind/wait# asserted on the last transfer before wrap- around. figure 8.3 end of burst indicator (ind/wait#) timi ng for linear 8-word burst operation 8.4.2 initial burst access delay initial burst access delay is defined as the number of clock cycles that must elapse from the first valid clock edge after adv# assertion (or the risi ng edge of adv#) until the first valid clk edge when the data is valid. burst access is initiated and the address is latched on the first rising clk edge when adv# is active or upon a rising ad v# edge, whichever comes first. the initial burst access delay is determined in the configuration register (cr13-cr10). refer to ta b l e 8 . 5 for the initial access delay configurations under cr13-cr10. see figure 8.4 for the initial burst delay control timing diagram. note that the initial access delay for a burst access has no effect on asynchronous read operations. ta b l e 8 . 4 burst initial access delay cr13 cr12 cr11 cr10 initial burst access (clk cycles) 0001 3 0010 4 0011 5 0100 6 0101 7 0 1 1 0 8 0111 9 ce# clk adv# addresses oe# data address 1 address 2 invalid d1 d2 d3 d0 address 1 latched 3 clock delay ind/wait# v il v ih 26 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary notes: 1. burst access starts with a rising clk edge and when adv# is active. 2. configurations register 6 is always set to 1 (cr6 = 1). burst starts and data outputs on the rising clk edge. 3. cr [13-10] = 1 or three clock cycles 4. cr [13-10] = 2 or four clock cycles 5. cr [13-10] = 3 or five clock cycles figure 8.4 initial burst delay control 8.4.3 configuration register the configuration register sets various operational parameters associated with burst mode. upon power-up or hardware reset, the device defaul ts to the asynchronous read mode and the con - figuration register settings are in their default state. (see table 8.6 for the default configuration register settings.) the host system determines the proper settings for the entire configuration register, and then execute the set configuration register command sequence before attempting burst operations. the configuration regist er is not reset after deasserting ce#. the configuration register does not occupy any addressable memory location, but rather, is ac - cessed by the configuration register commands. th e configuration register is readable at any time, however, writing the configuration register is restricted to times when the embedded al - gorithm? is not active. if the user attempts to write the configuration register while the embedded algorithm? is active, the write operat ion is ignored and the contents of the configu - ration register remain unchanged. the configuration register is a 16 bit data field which is accessed by dq15?dq0. during a read operation, dq31?dq16 returns all zeroes. also, the configuration register reads operate the same as the autoselect command reads. when the command is issued, the bank address is latched along with the command. read operations to the bank that was specified during the con - figuration register read command return configur ation register contents. read operations to the other bank return flash memory data. either ba nk address is permitted when writing the config - uration register read command. the configuration register can be read with a four-cycle command sequence. see command def - initions on page 71 for sequence details. clk adv# addresses dq31-dq0 3 dq31-dq0 4 dq31-dq0 5 valid address three clk delay 2nd clk 3rd clk 4th clk 5th clk 1st clk four clk delay address 1 latched five clk delay d0 d1 d2 d3 d0 d1 d2 d0 d1 d2 d3 d4 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 27 preliminary table 8.5 describes the configuration register settings. 8.5 autoselect the autoselect mode provides manufacturer and device identification, and sector protection ver - ification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its correspond - ing programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires vid on address pin a9. ad- dress pins a6, a1, and a0 must be as shown in ta b l e 8 . 7 . in addition, when verifying sector pro - tection, the sector address must appear on the appropriate highest order address bits. table 8.7 ta b l e 8 . 5 configuration register configuration register cr15 = read mode (rm) 0 = synchronous burst reads enabled 1 = asynchronous reads enabled (default) cr14 = reserved for future enhancements these bits are reserved for fu ture use. set these bits to 0 . cr13?cr10 = initial burst access delay configuration (iad3-iad0) 0000 = 2 clk cycle initial burst access delay 0001 = 3 clk cycle initial burst access delay 0010 = 4 clk cycle initial burst access delay 0011 = 5 clk cycle initial burst access delay 0100 = 6 clk cycle initial burst access delay 0101 = 7 clk cycle initial burst access delay 0110 = 8 clk cycle initial burst access delay 0111 = 9 clk cycle initial burst access delay?default cr9 = data output configuration (doc) 0 = hold data for 1-clk cycle?default 1 = reserved cr8 = ind/wait# configuration (wc) 0 = ind/wait# asserted during delay?default 1 = ind/wait# asserted one data cycle before delay cr7 = burst sequence (bs) 0 = reserved 1 = linear burst order?default cr6 = clock configuration (cc) 0 = reserved 1 = burst starts and data output on rising clock edge?default cr5?cr3 = reserved for future enhancements (r) these bits are reserved for fu ture use. set these bits to 0 . cr2?cr0 = burst length (bl2?bl0) 000 = reserved, burst accesses disabled (asynchronous reads only) 001 = 64 bit (8-byte) burst data transfer - x32 linear 010 = 128 bit (16-byte) burst data transfer - x32 linear 011 = 256 bit (32-byte) burst data transfer - x32 linear (device default) 100 = reserved, burst accesses disabled (asynchronous reads only) 101 = reserved, burst accesses disabled (asynchronous reads only) 110 = reserved, burst accesses disabled (asynchronous reads only) ta b l e 8 . 6 configuration register after device reset cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 rm reserve iad3 iad2 iad1 iad0 doc reserve 10011100 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 bs cc reserve reserve reserve bl2 bl1 bl0 11000100 28 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then re ad the corresponding identifier code on dq7? dq0. in order to access the autoselect codes in-system, the host system can issue the autoselect com - mand via the command. this method does not require vid. see command definitions on page 71 for details on using the autoselect mode. autoselect mode can be used in either syn - chronous (burst) mode or asynchronous (non burst) mode. the system must write the reset command to exit the autoselect mode and return to reading the array data. see table 8.7 for command sequence details. legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. note: the autoselect codes can also be accessed in-system via command sequences. see table 20.2 . 8.6 versatilei/o? (v io ) control the versatilei/o (v io ) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the v io pin. the output voltage generated on the device is determined based on the v io (v ccq ) level. for the 2.6 v (cd-j), a v io of 1.65 v - 3.6 v (cd032j has a v io of 1.65v to 2.75v) allows the device to interface with i/os lower than 2.5 v. for a 3.3 v v cc (cl- j), a v io of 1.65 v-3.60 v allows the device to interface with i/os lower than 3.0 v. 8.7 program/erase operations these devices are capable of several modes of programming and or erase operations which are described in detail in the following sections. however, prior to any programming and or erase operation, devices must be set up appropriately as outlined in the configuration register ( ta b l e 8.5 on page 27 ). during a synchronous write operation, to write a command or command sequence (including programming data to the device and erasing sectors of memory), the sys - tem must drive avd# and ce# to v il , and oe# to v ih when providing an address to the device, and drive we# and ce# to v il , and oe# to v ih when writing commands or programming data. 8.7.1 programming programming is a four-bus-cycle operation. the program command sequence is initiated by writ - ing two unlock write cycles, followed by the pr ogram setup command. the program address and data are written next, which in turn initiate th e embedded program algorithm. the system is not ta b l e 8 . 7 s29cd-j & s29cl-j flash family auto select codes (high voltage method) description ce# oe# we# a19 to a11 a10 a9 a8 a7 a6 a5 to a4 a3 a2 a1 a0 dq7 to dq0 manufacturer id : spansion ll hxxv id x x l x x x l l 0001h autoselect device code read cycle 1 ll hxxv id x l l x l l l h 007eh read cycle 2 ll hxxv id xlllhhhl 08h or 36h for cd016j 46h for cl016j 09h for cd032j 49h for cl032j read cycle 3 ll hxxv id x l l l hhhh 0000h to p b o o t o p t i o n 0001h bottom boot option ppb protection status ll hsaxv id xlllllhl 0000h (unprotected) 0001h (protected) september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 29 preliminary required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. command definitions on page 71 shows the ad - dress and data requirements fo r the program command sequence. note the following: ? when the embedded program algorithm is complete, the device returns to the read mode and address are no longer latched. an address change is required to begin reading valid array data. ? the system can determine the status of the program operation by using dq7, dq6 or ry/by#. refer to write operation status on page 33 for information on these status bits. ? a "0" cannot be programmed back to a "1." attempting to do so may halt the operation and set dq5 to 1, or cause the data# poll - ing algorithm to indicate the operation was successful. . a suc - ceeding read shows that the data is still "0." only erase operations can convert a "0" to a "1." ? any commands written to the device during the embedded pro - gram algorithm are ignored ex cept the program suspend com - mand. ? a hardware reset immediately terminates the program operation; the program command sequence should be re-initiated once the device has returned to the read mode, to ensure data integrity. note: see table 19.1 and table 20.2 for program command sequence. figure 8.5 program operation start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 30 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 8.7.2 sector erase the sector erase function erases one or more sectors in the memory array. (see ta b l e 20.1, memory array command definitions (x32 mode), on page 71 and figure 8.6, erase operation, on page 31 .) the device does not require the system to preprogram prior to erase. the embed - ded erase algorithm automatically programs and verifies the entire memory for an all-zero data pattern prior to electrical erase. after a successful sector erase, all locations within the erased sector contain ffffh. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of no less than 80 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 80 s. any sector erase address and comm and following the exceeded time-out (80 s) may or may not be accepted. a time-out of 80 s from the rising edge of the last we# (or ce#) initiates the execution of the sector erase com-mand(s). if another falling edge of the we# (or ce#) occurs within the 80 s time-out window, the timer is reset. any command other than sec - tor erase or erase suspend during the time-out pe riod resets that bank to the read mode. the system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timer on page 39 .) the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete , the bank returns to reading array data; ad - dresses are no longer latched. the system can determine the status of the erase operation by reading dq7 or dq6/dq2 in the erasing bank. refer to write operation status on page 33 for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be re-initiated once that bank has returned to reading array data , in order to ensure data integrity. figure 8.6 illustrates the algorithm for the erase operation. refer to program/erase operations on page 28 for parameters and timing diagrams. 8.7.3 chip erase chip erase is a six-bus cycle operation as indicated by command definitions on page 71 . the chip erase command is used to erase the entire flash memory contents of the chip by issuing a single command. however, chip erase does not erase protected sectors. this command invokes the embedded erase algorith m, which does not require the system to pre - program prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all-zero data pattern pr ior to electrical erase. after a successful chip erase, all locations of the chip contain ffffh. the system is not required to provide any controls or timings during these operations. command definitions on page 71 in the appendix shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and ad - dresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6 or the ry/by#. refer to write operation status on page 33 for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hard - ware reset immediately terminates the erase oper ation. if that occurs, the chip erase command sequence should be reinitiated once that bank ha s returned to reading array data, to ensure data integrity. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 31 preliminary notes: 1. see command definitions on page 71 for erase command sequence. 2. see ?dq3: sector erase timer? for more information. figure 8.6 erase operation 8.7.4 erase suspend / erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operatio n. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the min - imum 80-s time-out period during the sect or erase command sequence. the erase suspend command is ignored if written during the chip erase operation. when the erase suspend command is written after the 80-s time-out period has expired and during the sector erase operation, the device takes 20 s maximum to suspend the erase operation. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector that is not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) note that when the device is in the erase suspend mode, the reset command is not required for read operations and is ignored. further nesting of erase operation is not permitted. reading at any address within erase sus - pended sectors produces status information on dq7-dq0. the system can use dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to ta b l e 8.8 on page 37 for information on these status bits. a read operation from the erase-suspended bank returns polling data during the first 8 s after the erase suspend command is issued; read operations thereafter return array data. read op - erations from the other bank return array data with no latency. start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 32 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary after an erase-suspended program operation is co mplete, the bank returns to the erase-suspend read mode. the system can determine the status of the program operation using the dq7, dq6, and/or ry/by# status bits, just as in the standard program operation. to resume the sector erase operation, the system must write the erase resume command. the bank address of the erase-suspended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. the following are the allowable operations wh en erase suspend is issued under certain conditions: for the busy sectors, the host system may ? read status ? write the erase resume command for the non busy sectors, the system may ? read data ? program data or write the suspend/resume erase command 8.7.5 program suspend/pr ogram resume commands the program suspend command allows the system to interrupt an embedded programming op - eration so that data can read from any non-suspended sector. when the program suspend command is written during a programming process, the device halts the programming operation and updates the status bits. after the programming operation has been suspende d, the system can read array data from any non-suspended sector. if a read is needed from the secured silicon sector area, then user must use the proper command sequences to enter and ex it this region. the sector erase and program resume command is ignored if the se cured silicon sector is enabled. after the program resume command is written, the device reverts to programming. the system can determine the status of the program operatio n using the dq7, dq6, and/or ry/by# status bits, just as in the standard program operation. see write operation status on page 33 for more information. the system must write the program resume co mmand in order to exit the program suspend mode, and continue the programming operation. further writes of the program resume com - mand are ignored. another program suspend co mmand can be written after the device has resumed programming. the following are the allowable operations wh en program suspend is issued under certain conditions: ? for the busy sectors, the host system may write the program resume command ? for the non busy sectors, the system may read data 8.7.6 accelerated program and erase operations accelerated programming and erasing is enabled th rough the acc function. this method is faster than the standard program command sequences. the device offers accelerated program/erase operations through the acc pin. when the system asserts vhh (12v) on the acc pin, the device au tomatically enters the unlock bypass mode. the system may then write the two-cycle unlock by pass program command sequence to do acceler - ated programming. the device uses the higher voltage on the acc pin to accelerate the operation. any sector that is being protected with the wp# pin is still protected during acceler - ated program or erase. removing v hh from the acc input, upon completion of the embedded program or erase operation, returns the device to normal operation. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 33 preliminary notes: ? in this mode, the write protection function is bypassed unless the ppb lock bit = 1. ? the acc pin must not be at v hh for operations other than acceler - ated programming and accelerated chip erase, or device damage may result. ? the acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. ? the accelerated program command is not permitted if the secured silicon sector is enabled. 8.7.7 unlock bypass the device features an unlock bypass mode to facilitate faster programming, erasing (sector and chip erase), as well as cfi commands. once the device enters the unlock bypass mode, only two write cycles are required to program or eras e data, instead of the normal four cycles. this results in faster total programming/erasing time. command definitions on page 71 shows the requirements for the unlock bypass command sequences. during the unlock bypass mode only the read, unlock bypass program and unlock bypass reset commands are valid. to exit th e unlock bypass mode, the system must issue the two-cycle un - lock bypass reset command sequence, which returns the device to read mode. notes: 1. the unlock bypass command is ignored if the secured silicon sector is enabled. 2. unlike the standard program or erase commands, there is no unlock bypass program/erase suspend or program/erase resume command. 8.7.8 simultaneous read/write the simultaneous read/write feature allows the ho st system to read data from one bank of mem - ory while programming or erasing in another bank of memory. the simultaneous read/write feature can be used to perform the following: ? programming in one bank, while reading in the other bank ? erasing in one bank, while reading in the other bank ? programming a ppb, while reading data from th e large bank or status from the small bank ? erasing a pbb, while reading data from the large bank or status from the small bank ? any of the above situations while in the secured silicon sector mode the simultaneous r/w feature can not be performed during the following modes: ? cfi mode ? password program operation ? password verify operation as an alternative to using the simultaneous read/write feature, the user may also suspend an erase or program operation to read in another lo cation within the same bank (except for the sec - tor being erased). 8.8 write operation status the device provides several bits to determine the status of a program or erase operation. the following subsections describe the function of dq7, dq6, dq2, dq5, dq3, and ry/by#. 34 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 8.8.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whethe r a bank is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. note that data# polling returns invalid data for the address being programmed or erased. during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is comp lete, the device outputs the datum programmed to dq7. the system must provide the program addr ess to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approxi - mately 1 s, then that bank returns to the read mode without programming the sector. if an erase address falls within a protected sector, toggle bit (dq6) is active for 150 s, then the device returns to the read mode without erasing the se ctor. please note that data# polling (dq7) may give misleading status when an attempt is made to program or erase a protected sector. during the embedded erase algorithm, data# polling produces a "0" on dq7. when the embed - ded erase algorithm is complete data# polling prod uces a "1" on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. in asynchronous mode, just prior to the completi on of an embedded program or erase operation, dq7 may change asynchronously with dq6-dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq6-dq0 may be still invalid. valid data on dq7-d00 appears on successive read cycles. see the following for more information: ta b l e 8.9, write operation status on page 40 shows the outputs for data# polling on dq7. figure 8.7, data# polling algorithm, on page 35 shows the data# polling timing diagram. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 35 preliminary notes: 1. va = valid address for programming. during a sector erase op eration, a valid address is an address within any sector selected for erasure. during chip erase, a va lid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5 figure 8.7 data# polling algorithm 8.8.2 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address in the sa me bank, and is valid after the rising edge of the final we# pulse in the command sequence (p rior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, two immediate consecutive read cy - cles to any address cause dq6 to toggle. when the operation is complete, dq6 stops toggling. for asynchronous mode, either oe# or ce# can be used to control the read cycles. for synchro - nous mode, the rising edge of adv# is used or the rising edge of clock while adv# is low. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start 36 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sec - tors are protected, the embedded erase algorith m erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to dete rmine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops tog - gling. however, the system must also use dq2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use dq 7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embed - ded program algorithm is complete. see figure 18.12, toggle bit timings (during embedded algorithms), on page 64 for additional information. 8.8.3 dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase- suspended. toggle bit ii is valid after the risi ng edge of the final we# pulse in the command sequence. dq2 toggles when the system performs two consecutive reads at addresses within those sectors that have been selected for erasure. but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 8.8 to compare outputs for dq2 and dq6. see dq6: toggle bit i on page 35 for additional information. 8.8.4 reading toggle bits dq6/dq2 whenever the system initially begins reading togg le bit status, it must perform two consecutive reads of dq7-dq0 in a row in or der to determine whether a toggle bit is toggling. typically, the system notes and stores the value of the toggle bit after the first read. after the second read, the system compares the new value of the toggle bit with the first. if the toggle bit is not tog - gling, the device completes the program or erases operation. the system can read array data on dq7-dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still tog - gling, the system also notes whether the value of dq5 is high (see the section on dq5). if it is, the system then determines again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if th e toggle bit is no longer toggling, the device has successfully completed the program or erases op eration. if it is still toggling, the device had not completed the operation successfully, and the sy stem writes the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previous paragraph. alterna - tively, the system may choose to perform other syst em tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. refer to figure 8.8 for more on the toggle bit algorithm. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 37 preliminary ta b l e 8 . 8 dq6 and dq2 indications if device is and the system reads then dq6 and dq2 programming, at any address, toggles, does not toggle. actively erasing, at an address within a sector selected for erasure, toggles, also toggles. at an address within sectors not selected for erasure, toggles, does not toggle erase suspended, at an address within sectors selected for erasure, does not toggle, toggles. at an address within secotrs not selected for erasure, returns array data, returns array data. the system can read from any sector not selected for erasure. programming in erase suspend, at any address, toggles, is not applicable. 38 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary notes: 1. read toggle bit with two immediately consecutive reads to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1 . figure 8.8 to g g l e b i t a l g o r i t h m 8.8.5 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. th is is a failure condition that indicates the pro - gram or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. only an erase oper ation can change a 0 back to a 1. under this condition, the device halts the operation, and wh en the operation has exceeded the timing limits, dq5 produces a 1. under both these conditions, the system issues the reset command to return the device to read - ing array data. start no yes yes dq5 = 1? no yes dq6 = toggle? no read byte (dq0-dq7) address = va dq6 = toggle? read byte twice (dq 0-dq7) adrdess = va read byte (dq0-dq7) address = va fail pass (note 1) (notes 1, 2) september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 39 preliminary 8.8.6 dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase ti mer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each addi - tional sector erase command. when the time-out period is complete, dq3 switches from a "0" to a "1." if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see sector erase on page 30 for more details. after the sector erase command is written, the system reads the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, then reads dq3. if dq3 is "1," the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is "0," the device ac - cepts additional sector erase commands. to ensure the command has been accepted, the system software check the status of dq3 prior to and following each sub-sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e 8 . 9 shows the status of dq3 rel - ative to the other status bits. 8.8.7 ry/by#: ready/busy# the device provides a ry/by# open drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or have been completed. if the output of ry/ by# is low, the device is busy with either a program, erase, or reset operation. if the output is floating, the device is ready to accept any read /write or erase operation. when the ry/by# pin is low, the device will not accept any additional program or erase commands with the exception of the erase suspend command. if the device ha s entered erase suspend mode, the ry/by# out - put is floating. for programming, the ry/by# is valid (ry/by# = 0) after the rising edge of the fourth we# pulse in the four write pulse sequence . for chip erase, the ry/by# is valid after the rising edge of the sixth we# pulse in the six wr ite pulse sequence. for sector erase, the ry/by# is also valid after the rising edge of the sixth we# pulse. if reset# is asserted during a program or eras e operation, the ry/by# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is floating), the reset operation is completed in a time of t ready (not during embedded algo - rithms). the system can read data t rh after the reset# pin returns to v ih . since the ry/by# pin is an open-drain output, se veral ry/by# pins can be tied together in par - allel with a pull-up resistor to v cc . an external pull-up resistor is required to take ry/by# to a v ih level since the output is an open drain. ta b l e 8 . 9 shows the outputs for ry/by#, dq7, dq6, dq5, dq3 and dq2. figure 18.2 , figure 18.6 , figure 18.8 and figure 18.9 show ry/by# for read, reset, program, and erase operations, respectively. 40 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary notes: 1. dq5 switches to 1 when an embedded program or embedded erase oper ation has exceeded the maximum timing limits. see dq5: exceeded timing limits on page 38 for more information. 2. dq7 and dq2 require a valid address wh en reading status information. see dq7: data# polling on page 34 and dq2: toggle bit ii on page 36 for further details. 8.9 reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the cycles in an erase command sequence before erasing begins. this resets the device to the read mode. however, once erasure begins, the de - vice ignores the reset commands until the operation is complete. the reset command may be written between the cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command se - quence is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. however, once programming begins, the device ignores the reset commands until the operation is complete. the reset command may be written between the cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to exit the autoselect mode and return to the read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode or erase-suspend-read-m ode if the device was in erase suspend. when the reset command is written, before the embe dded operation starts, the device requires t rr be - fore it returns to the read or erase-suspend-read mode. ta b l e 8 . 1 0 reset command timing ta b l e 8 . 9 write operation status operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 parameter description max. unit t rr reset command to read mode or erase-suspend-read mode 250 ns september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 41 preliminary 9 advanced sector protection/unprotection the advanced sector protection/unprotection feat ure disables or enables programming or erase operations in any or all sectors and can be implemented through software and/or hardware methods, which are independent of each other. this section describes the various methods of protecting data stored in the memory array. an overview of these methods in shown in figure 9.1 . figure 9.1 advanced sector protection/unprotection hardware methods software methods wp# = v il (two outermost sectors locked in large bank) ppb lock bit 1,2,3 64-bit password (one time protect) 1 = ppbs unlocked 0 = ppbs locked memory array sector 0 sector 1 sector 2 sector n-2 sector n-1 sector n 3 ppb 0 ppb 1 ppb 2 ppb n-2 ppb n-1 ppb n persistent protection bit (ppb) 4,5 dyb 0 dyb 1 dyb 2 dyb n-2 dyb n-1 dyb n dynamic protection bit (dyb) 6,7,8 5. protect effective only if ppb lock bit is unlocked and corresponding ppb is ?0? (unprotected). 6. volatile bits. 4. ppbs programmed individually, but cleared collectively 1. bit is volatile, and defaults to ?1? on reset. 2. programming to ?0? locks all ppbs to their current state. 3. once programmed to ?0?, requires hardware reset to unlock. 3. n = highest address sector. password method (dq2) persistent method (dq1) 42 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 9.1 advanced sector protection overview as shipped from the factory, all devices default to the persistent mode when power is applied, and all sectors are unprotected. the device programmer or host system must then choose which sector protection method to use. programming (s etting to "0") any one of the following two one- time programmable, non-volatile bits lock s the device permanently in that mode: ? persistent protection mode lock bit ? password protection mode lock bit after selecting a sector protection method, each sector can operate in any of the following three states: 1. persistently locked. a sector is protected and cannot be changed. 2. dynamically locked. the selected sectors ar e protected and can be altered via software commands. 3. unlocked. the sectors are unprotected and can be erased and/or programmed. these states are controlled by the bit types described between page 42 and page 45. notes: 1. if the password mode is chosen, the password must be programmed before setting the cor- responding lock register bit. the user must be sure that the password is correct when the password mode locking bit is set, as there is no means to verify the password afterwards. 2. if both lock bits are selected to be programmed (to zeros) at the same time, the operation aborts. 3. once the password mode lock bit is programmed, the persistent mode lock bit is perma- nently disabled, and no changes to the protection scheme are allowed. similarly, if the persistent mode lock bit is programmed, the password mode is permanently disabled. 4. it is important that the mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is impossible for a system program or virus to later set the password mode locking bit, which would cause an unex- pected shift from the default persistent sector protection mode into the password protection mode. 5. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device retu rns to read mode without modifying the con- tents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s, after which the device returns to read mode without having erased the protected sector. 6. for the command sequence required for programming the lock register bits, refer to com- mand definitions on page 71 . 9.2 persistent protection bits the persistent protection bits are unique and nonvolatile. a single persistent protection bit is as - signed to a maximum for four sectors (see the sector address tables for specific sector protection groupings). all eight-kbyte boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. notes: 1. each ppb is individually programmed and all ar e erased in parallel. there are no means for individually erasing a specific ppb and no specif ic sector address is required for this opera- tion. 2. if a ppb requires erasure, all of the sector ppbs must first be programmed prior to ppb eras- ing. it is the responsibility of the user to pe rform the preprogramming operation. otherwise, an already erased sector ppb has the potential of being over-erased. there is no hardware mechanism to prevent sector ppb over-erasure. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 43 preliminary 3. if the ppb lock bit is set, the ppb program or erase command does not execute and times- out without programming or erasing the ppb. 9.2.1 programming ppb the ppb program command is used to program, or set, a given ppb. the first three cycles in the ppb program command are standard unlock cycles. the fourth cycle in the ppb program com - mand executes the pulse which programs the specified ppb. the user must wait either 100 s or until dq6 stops toggling before executing the fifth cycle, which is the read verify portion of the ppb program command. the sixth cycle output s the status of the ppb program operation. in the event that the program ppb operation was no t successful, the user can loop directly to the fourth cycle of the ppb program command to perform the program pulse and read verification again. after four unsuccessful loops through the program pulse and read verification cycles the ppb programming operation should be considered a failure. figure 9.2 pbb program operation 9.2.2 erasing ppb the all ppb erase command is used to erase all the ppbs in bulk. there are no means for indi - vidually erasing a specific ppb. the first three cycles of the ppb erase command are standard unlock cycles. the fourth cycle executes the erase pulse to all the pbbs. the user must wait ei - ther 20ms or until dq6 stops toggling before execut ing the fifth cycle, which is the read verify portion of the ppb erase comm and. the sixth cycle outputs the status of the ppb erase operation. in the event that the erase ppb operation was no t successful, the user can loop directly to the fourth cycle of the all ppb erase command to perform the erase pulse and read verification again. after four unsuccessful loops through the er ase pulse and read verification cycles, the ppb erasing operation should be considered a failure. note: either poll dq6 in the small bank and wait for it to stop toggling or wait 100us dq0=1? write 0x68 to sg+wp write 0x48 to sg+wp read from sg+wp yes no 5 th attempt? yes no note: reads from the small bank at this point return the status of the operation, not read array data. done error write 0xaa to 0x555 write 0x55 to 0x2aa write 0x60 to 0x555 44 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary ? all ppb must be preprogrammed prior to issuing the all ppb erase command. figure 9.3 ppb erase operation 9.3 persistent protection bit lock bit the persistent protection bit lock bit is a global volatile bit for all sectors. when set to "1", it locks all ppbs; when set to "0", it allows the ppb s to be changed. there is only one ppb lock bit per device. notes: 1. no software command sequence unlocks this bit unless the device is in the password pro- tection mode; only a hardware reset or a power-up clears this bit. 2. the ppb lock bit must be set only after a ll ppbs are configured to the desired settings. 9.4 dynamic protection bits a dynamic protection bit (dyb) is volatile and unique for each sector and can be individually modified. dybs only control the protection scheme for unprotected sectors that have their ppbs set to "0". by issuing the dyb set or clear co mmand sequences, the dybs are set or cleared, thus placing each sector in the protected or unprotected state respectively. this feature allows software to easily protect sectors against inad vertent changes, yet does not prevent the easy removal of protection when changes are needed. notes: 1. the dybs can be set or cleared as often as needed with the dyb write command. 2. when the parts are first shipped, the ppbs ar e cleared, the dybs are cleared, and ppb lock is defaulted to power up in the cleared state ? meaning the ppbs are changeable. the dyb are also always cleared after a power-up or reset. 3. it is possible to have sectors that are persistently locked with sectors that are left in the dy- namic state. write 0xaa to 0x555 write 0x55 to 0x2aa write 0x60 to 0x555 either poll dq6 in the small bank and wait for it to stop toggling or wait 20ms dq0=0? write 0x60 to wp write 0x40 to wp read from wp done yes no 5 th attempt ? error yes note: reads from the small bank at this point return the status of the operation, not read array data. no september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 45 preliminary 4. the dyb set or clear commands for the dynamic sectors signify the protected or unprotected state of the sectors respectively. however, if th ere is a need to change the status of the per- sistently locked sectors, a few more steps are required. first, the ppb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect th e desired settings. setting the ppb lock bit once again locks the ppbs, and the device operates normally again. 9.5 password protection method the password protection method allows an even hi gher level of security than the persistent sec - tor protection mode by requiring a 64-bit password for unlocking the devi ce ppb lock bit. in addition to this password requirement, after powe r-up and reset, the ppb lock bit is set "1" in order to maintain the password mode of operation. successful execution of the password unlock command by entering the entire password clears the ppb lock bit, allowing for sector ppbs modifications. notes: 1. there is no special addressing order requir ed for programming the password. once the pass- word is written and verified, the password mode locking bit must be set in order to prevent access. 2. the password program command is only capa ble of programming "0"s. programming a "1" after a cell is programmed as a "0" results in a time-out with the cell as a "0". (this is an otp area). 3. the password is all "1"s when shipped from the factory. 4. when the password is undergoing programming, simultaneous read/write operation is dis- abled. read operations to any memory location returns the programming status. once programming is complete, the user must issue a read/reset command to return the device to normal operation. 5. all 64-bit password combinations are valid as a password. 6. there is no means to read, program or erase the password is after it is set. 7. the password mode lock bit, once set, preven ts reading the 64-bit password on the data bus and further password programming. 8. the password mode lock bit is not erasable. 9. the exact password must be entered in or der for the unlocking function to occur. 10. there is a built-in 2-s delay for each passwor d check. this delay is intended to stop any efforts to run a program that tries all possible combinations in order to crack the password. 9.6 hardware data protection methods the device offers several methods of data protecti on by which intended or accidental erasure of any sectors can be prevented via hardware means. the following subsections describe these methods. ta b l e 9 . 1 sector protection schemes dyb ppb ppb lock sector state 00 0 unprotected?ppb and dyb are changeable 00 1 unprotected?ppb not changeable, dyb is changeable 01 0 protected?ppb and dyb are changeable 10 0 11 0 01 1 protected?ppb not changeable, dyb is changeable 10 1 11 1 46 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 9.6.1 wp# method the write protect feature provides a hardware me thod of protecting the two outermost sectors of the large bank. if the system asserts v il on the wp# pin, the device disables program and erase functions in the two "outermost" boot sectors (8-kbyte sectors) in the large bank. if the system asserts v ih on the wp# pin, the device reverts to whether the b oot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors depends on whether they were last protected or unprotected. note that the wp# pin must not be left floating or unconnected as inconsistent behavior of the device may result. the wp# pin must be held stable during a command sequence execution 9.6.2 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data dur - ing v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to reading array data. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control inputs to prevent unintentional writes when v cc is greater than v lko . 9.6.3 write pulse ?glitch protection? noise pulses of less than 5 ns (typical) on oe #, ce# or we# do not initiate a write cycle. 9.6.4 power-up write inhibit if we# = ce# = reset# = v il and oe# = v ih during power-up, the device does not accept commands on the rising edge of we#. the intern al state machine is automatically reset to the read mode on power-up. 9.6.5 v cc and v io power-up and powe r-down sequencing the device imposes no restrictions on vcc and vio power-up or power-down sequencing. as - serting reset# to v il is required during the entire vcc and vio power sequence until the respective supplies reach the operating voltages. once, vcc and vio attain the operating volt - ages, deassertion of reset# to v ih is permitted. 9.6.6 logical inhibit write cycles are inhibited by holding any one of oe # = vil, ce# = vih, or we# = vih. to initiate a write cycle, ce# and we# must be a logical zero (vil) while oe# is a logical one (vih). september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 47 preliminary 10 secured silicon sector flash memory region the secured silicon sector provides an extra fl ash memory region that enables permanent part identification through an electronic serial numb er (esn). the secured silicon sector is a 256- byte flash memory area that is either programm able at the customer, or by spansion at the re - quest of the customer. see table 10.1 for the secured silicon sector address ranges. all secured silicon reads outside of the 256 -byte address range return invalid data. the device allows simultaneous read/write operation while the secured silicon sector is en - abled. however, several restrictions are associat ed with simultaneous read/write operation and device operation when the secured silicon sector is enabled: 1. the secured silicon sector is not available for reading while the password unlock, any ppb program/erase operation, or password programming are in progress. reading to any location in the small bank will return the status of th ese operations until these operations have com- pleted execution. 2. programming the dyb associated with the overla id boot-block sector results in the dyb not being updated. this occurs only when th e secured silicon sector is not enabled. 3. reading the dyb associated with the overlaid boot-block sector when the ppb lock/dyb ver- ify command is issued, causes the read command to return invalid data. this function occurs only when the secured silicon sector is not enabled. 4. all commands are available for execution when the secured silicon sector is enabled, except the following: ? any unlock bypass command ? cfi ? accelerated program ? program and sector erase suspend ? program and sector erase resume issuing the above commands while the secured silic on sector is enabled results in the command being ignored. 5. it is valid to execute the sector erase command on any sector other than the secured silicon sector when the secured silicon sector is enab led. however, it is not possible to erase the secured silicon sector using the sector erase command, as it is a one-time programmable (otp) area that can not be erased. 6. executing the chip erase command is permitted when the secured silicon sector is enabled. the chip erase command erases all sectors in the memory array, except for sector 0 in top- boot block configuration, or sector 45 in bottom-boot block configuration. the secured sili- con sector is a one-time programmable memory area that cannot be erased. 7. executing the secured silicon sector entry co mmand during program or erase suspend mode is allowed. the sector erase/program resume command is disabled when the secured sili- con sector is enabled; the user cannot resu me programming of the memory array until the exit secured silicon sector command is written. 8. address range 00040h?007ffh for the top bootblock, and ff00h?fff7fh return invalid data when addressed with the secured silicon sector enabled. table 10.1 secured silicon sector addresses ordering option sector size (bytes) address range top boot 256 00000h-0003fh (16 mb & 32 mb) bottom boot 256 fffc0h?fffffh (32 mb) 7ffc0h?7ffffh (16 mb) 48 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 9. the secured silicon sector entry command is a llowed when the device is in either program or erase suspend modes. if the secured silicon sector is enabled, the program or erase sus- pend command is ignored. this prevents resu ming either programming or erasure on the secured silicon sector if the overlayed sector was undergoing programming or erasure. the host system must ensure that the device re sume any suspended program or erase operation after exiting the secured silicon sector. 10.1 secured silicon sector protection bit the secured silicon sector can be shipped unprote cted, allowing customers to utilize that sector in any manner they choose. please note the following: ? the secured silicon sector can be read any number of times, but can be programmed and locked only once. the secured silicon sector protection bit must be used with caution as once locked, there is no procedure available for unlocking the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. ? once the secured silicon sector is locked and verified, the system must write the exit secured silicon sector region command se - quence to return the device to the memory array. 10.2 secured silicon sector entry and exit commands the system can access the secured silicon sector region by issuing the three-cycle enter se - cured silicon sector command sequence. the device continues to access the secured silicon sector region until the system issues the four -cycle exit secured silicon sector command se - quence. see the ta b l e 20.1, memory array command definitions (x32 mode), on page 71 and ta b l e 20.2, sector protection command definitions (x32 mode), on page 72 for address and data requirements for both command sequences. the secured silicon sector entry command a llows the following commands to be executed ? read secured silicon areas ? program secured silicon sector (only once) after the system has written the enter secured silicon sector command sequence, it can read the secured silicon sector by using the addresses listed in ta b l e 10.1, secured silicon sector addresses on page 47 . this mode of operation continues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. 11 electronic marking electronic marking has been programmed into the device, prior to shipment from spansion, to ensure traceability of individual products. the el ectronic marking is stored and locked within a one-time programmable region. detailed informatio n on electronic marking will be provided in a datasheet supplement. 12 power conservation modes 12.1 standby mode when the system is not reading or writing to the device, it can place the device in standby mode. in this mode, current consumption is greatly re duced, and outputs are placed in a high imped - ance state, independent of oe# input. the devi ce enters cmos standby mode when the ce# and reset# inputs are both held at v cc 0.2 v. the device requires standard access time (t ce ) for read access before it is ready to read data. if the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 49 preliminary i cc5 in cmos compatible on page 52 represents the standby current specification. caution: entering standby mode via the reset# pin also resets the device to read mode and floats the data i/o pins. furthermore, entering icc7 during a program or erase operation leaves erroneous data in the a ddress locations being operated on at the time of the reset# pulse. these locations require updating after the device resumes standard operations. see hardware reset# input operation for further discussion of the reset# pin and its functions. 12.2 automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the automatic sleep mode is independent of the ce#, we# and oe# cont rol signals. while in sleep mode, output data is latched and always available to the system. while in asynchronous mode, the device automatically enables this mode when addresses re - main stable for t acc + 60 ns. standard address access timings provide new data when addresses are changed. while in synchronous mode, the de vice automatically enables this mode when ei - ther the first active clk level is greater than t acc or the clk runs slower than 5 mhz. a new burst operation is required to provide new data. i cc8 in cmos compatible on page 52 represents the automatic sleep mode current specification. 12.3 hardware reset# input operation the reset# input provides a hardware method of resetting the device to reading array data. when reset# is driven low, the device immediately terminates any operation in progress, tristates all outputs, resets the configuration re gister, and ignores all read/write commands for the duration of the reset# pulse. the device al so resets the internal state machine to reading array data. any operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, in order to ensure data integrity. when reset# is held at v ss 0.2 v, the device draws cmos standby current (icc4). if reset# is held at v il but not within v ss 0.2 v, the standby current is greater. reset# may be tied to the system reset circuitry, thus a system reset would also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset# is asserted during a program or er ase operation, the ry/by# pin remains low until the reset operation is internally complete. this ac tion requires between 1 s and 7 s for either chip erase or sector erase. the ry/by# pin ca n be used to determine whether the reset opera - tion is complete. otherwise, allow for the maximum reset time of 11 s. if reset# is asserted when a program or erase operation is not executing (ry/by# = 1), the reset operation completes within 500 ns. the simu ltaneous read/write feature of this device al - lows the user to read a bank after 500 ns if th e bank is in the read/reset mode at the time reset# is asserted. if one of the banks is in the middle of either a program or erase operation when reset# is asserted, the user must wait 11 s before accessing that bank. asserting reset# active during vcc and vio power up is required to guarantee proper device initialization until vcc and vio have reached steady state voltages. 12.4 output disable (oe#) when the oe# input is at v ih , output from the device is disabl ed. the outputs are placed in the high impedance state. 50 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 13 electrical specifications 13.1 absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . . . . . . . . . . . . ?65c to +145c v cc , v io (note 1) for 2.6 v devices (s29cd-j) . . . . . . . . . . . . . . . . . . . . . . .-0.5v to +3.6 v v cc , v io (note 1) for 3.3 v devices (s29cl-j) . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +3.6v acc, a9 , and reset# (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +13.0 v address, data, control signals (with the exception of clk) (note 1) . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6v (16mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +2.75v (32mb) all other pins (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to +3.6v (16mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +2.75v (32mb) output short circuit current (note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. duri ng voltage transitions, input at i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.2 . maximum dc voltage on output and i/o pins is 3.6 v. during voltage transitions output pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 13.2 . 2. minimum dc input voltage on pins acc, a9, and reset# is -0.5 v. during voltage transitions, a9 and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 13.1 . maximum dc input voltage on pin a9 is +13.0 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum ra ting conditions for extended periods may affe ct device reliability. figure 13.1 maximum negative overshoot waveform figure 13.2 maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 51 preliminary 14 operating ranges industrial devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c extended devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +125c v cc supply voltages v cc for 2.6 v regulated voltage range (s29cd-j devices) . . . . . . . . . . . . . . . 2.50 v to 2.75 v v cc for 3.3 v regulated voltage range (s29cl-j devices) . . . . . . . . . . . . . . . 3.00 v to 3.60 v v io supply voltages v io (s29cd-j devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65v to 2.75v v io (s29cl-j devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65v to 3.6v operating ranges define those limits between which the functionality of the device is guaranteed. 52 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 15 dc characteristics 15.1 cmos compatible notes: 1. the i cc current listed includes both the dc operating current and the frequency dependent component. 2. i cc active while embedded erase or embedded program is in progress. 3. not 100% tested. 4. maximum i cc specifications are tested with v cc = v ccmax . parameter description test conditions min typ max unit i li input load current v in = v ss to v io , v io = v io max 1.0 a i liwp wp# input load current v in = v ss to v io , v io = v io max ?25 a i lit a9, acc input load current v cc = v ccmax ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i ccb v cc active burst read current (1) ce# = v il , oe# = v il 56 mhz 8 double word 45 55 ma 66, 75 mhz i cc1 v cc active asynchronous read current ( 1 ) ce# = v il , oe# = v il 1 mhz 4ma i cc3 v cc active program current ( 2 , 3 , 4 ) ce# = v il , oe# = v ih , acc = v ih 40 50 ma i cc4 v cc active erase current (2 ,3, 4) ce# = v il , oe# = v ih , acc = v ih 20 50 ma i cc5 v cc standby current (cmos) v cc = v cc max , ce# = v cc 0.3 v 60 a i cc6 v cc active current (read while write) ( 3 ) ce# = v il , oe# = v il 30 90 ma i cc7 v cc reset current reset# = v il 60 a i cc8 automatic sleep mode current v ih = v cc 0.3 v, v il = v ss 0.3 v 60 a i acc v acc acceleration current acc = v hh 20 ma v il input low voltage ?0.5 0.3 x v io v v ih input high voltage 0.7 x v io v cc v v ilclk clk input low voltage ?0.2 0.3 x v io v v ihclk clk input high voltage 0.7 x v cc 2.75 v v id voltage for autoselect v cc = 2.5 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v i olrb ry/by#, output low current v ol = 0.4 v 8ma v hh accelerated (acc pin) high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 x v cc v v oh output high voltage i oh = ?100 a, v cc = v cc min v io ?0.1 v v lko low v cc lock-out voltage (3) 1.6 2.0 v september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 53 preliminary 15.2 zero power flash note: addresses are switching at 1 mhz figure 15.1 i cc1 current vs. time (showing active and automatic sleep currents) figure 15.2 typical i cc1 vs. frequency 0 500 1000 1500 2000 2500 3000 3500 4000 0 1 2 3 4 time in ns supply current in ma 2.7 v 1234 5 0 1 2 3 4 5 frequency in mhz supply current in ma 54 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 16 test conditions note: diodes are in3064 or equivalent figure 16.1 te s t s e t u p 17 test specifications ta b l e 1 7 . 2 . key to switching waveforms 17.1 switching waveforms figure 17.1 input waveforms and measurement levels table 17.1 test specifications test condition 54d, 64c 65a, 75e unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5ns input pulse levels 0.0 v ? v io v input timing measurement reference levels v io /2 v output timing measurement reference levels v io /2 v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) c l device under te s t v io v ss v io /2 v v io /2 v output measurement level input september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 55 preliminary 18 ac characteristics 18.1 v cc and v io power-up figure 18.1 v cc and v io power-up diagram ta b l e 1 8 . 1 v cc and v io power-up parameter description test setup speed unit t vcs v cc setup time min 50 s t vios v io setup time min 50 s t rsth reset# low hold time min 50 s v cc v iop reset# t vcs t rsth t vios 56 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 18.2 asynchronous operations notes: 1. not 100% tested. 2. see figure 16.1 and table 17.1 for test specifications. 3. toe during read array. figure 18.2 conventional read operations timings ta b l e 1 8 . 2 asynchronous read operations parameter description test setup speed options unit jedec std. 75mhz 0r 66mhz 0p 56mhz 0m 40mhz 0j t avav t rc read cycle time (note 1) min48545454ns t avqv t acc address to output delay ce# = v il oe# = v il max48545454ns t elqv t ce chip enable to output delay oe# = v il max52545454ns t glqv t oe output enable to output delay max 20 20 ns t ehqz t df chip enable to output high z (note 1) max 10 ns t ghqz t df output enable to output high z (note 1) min 2 ns max 10 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 2 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe 0 v ry/by# reset# t df t oh september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 57 preliminary figure 18.3 asynchronous command write timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/ reset command. only a single array access occurs after th e f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. adv# ce# valid data addresses data we# oe# ind/wait# clk stable address t cs t ch t as t ah t weh t ds t dh t oep t wc 58 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 18.3 synchronous operations notes: 1. using the max t aavs and min t advcs specs together will result in incorrect data output. 2. not 100% tested 3. recommended 50% duty cycle table 18.3 burst mode read for 32 mb and 16 mb parameter description speed options unit jedec std. 75mhz, or 66mhz, op 56mhz, om 40mhz, oj t bacc burst access time valid clock to output delay max 7.5 fbga 8 8 8 ns t advcs adv# setup time to rising edge of clk min 6 6 6 6 ns t advch adv# hold time from rising edge of clk min 1.5 ns t advp adv# pulse width min 7.5 8.5 9.5 10.5 ns t bdh valid data hold from clk (note 2) min 2 2 3 3 ns t inds clk to valid ind/wait# (note 2) max 7.5 fbga 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t indh ind/wait# hold from clk (note 2) min 2 2 3 3 ns t iacc adv or add valid (whichever occurs last) to valid data out, initial burst access max 48 54 54 54 ns t clk clk period min 13.3 15.15 17.85 25 ns max 60 t cr clk rise time (note 2) max 3 ns t cf clk fall time (note 2) max 3 ns t clkh clk high time (note 3) min 6.65 6.8 8.0 11.25 ns t clkl clk low time (note 3) min 6.65 27 27 27 ns t oe output enable to output valid max 20 20 ns t df t oez output enable to output high z (note 2) min 2 2 3 3 ns max 7.5 10 15 17 t ehqz t cez chip enable to output high z (note 2) max 7.5 10 15 17 ns t ces ce# setup time to clock min 4 4 5 6 ns t aavs adv# falling edge to address valid (note 1) max 6.5 6.5 6.5 6.5 ns t aavh address hold time from rising edge of avd# min 15 15 15 15 ns t rstz reset# low to output high z (note 2) max 7.5 10 15 17 ns t wadvh1 adv# falling edge to we# falling edge min 5 5 5 5 ns t wadvh2 adv# rising edge to we# rising edge min 10 10 10 10 ns september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 59 preliminary figure 18.4 burst mode read (x32 mode) figure 18.5 synchronous command write/read timing note: all commands have the same number of cycles in both asynchronous and synchronous modes, including the read/ reset command. only a single array access occurs after th e f0h command is entered. all subsequent accesses are burst mode when the burst mode option is enabled in the configuration register. d a d a +2 d a + 3 d a + 3 1 oe# d a t a addre ss e s a a ind# adv# clk ce# t ce s t advc s t aavh t oe t bacc t bdh t iacc t oez t cez d a +1 t aav s t ind s t indh t as clk adv# data in addresses data oe# data out valid address we# ind/wait# ce# valid address t ds t wavdh1 t wavdh2 t wp t ces t advp t advcs t oe t df t ehqz t dh t advch valid address 10 ns t wc 60 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 18.4 hardware reset (reset#) note: not 100% tested. figure 18.6 reset# timings table 18.4 hardware reset (reset#) parameter description test setup all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read or write (see note) max 11 s t ready2 reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width max 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by # recovery time min 0 ns t ready3 reset # active for bank not executing algorithm max 500 ns reset# ry/by# ry/by# t rp t ready reset timing to bank not executing embedded algorithm t ready ce#, oe# t rh ce#, oe# reset timing to bank executing embedded algorithm reset# t rp t rb september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 61 preliminary 18.5 write protect (wp#) figure 18.7 wp# timing program/erase command wp# data valid wp# t busy t ds t dh we# ry/by# t wpws t wprh t wp 62 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 18.6 erase/program operations notes: 1. not 100% tested. 2. see command definitions on page 71 for more information. 3. program erase parameters are the same, regardless of synchronous or asynchronous mode. note: pa = program address, pd = program data, d out is the true data at the program address. figure 18.8 program operation timings ta b l e 1 8 . 5 erase/program operations parameter description all speed options jedec std. unit t avav t wc write cycle time (note 1) min 60 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 25 ns t dvwh t ds data setup to we# rising edge min 18 ns t whdx t dh data hold from we# rising edge min 2 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) (note 1) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp we# width min 25 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) double-word ty p 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec. t vcs v cc setup time (note 1) min 50 s t rb recovery time from ry/by# (note 1) min 0 ns t busy ry/by# delay after we# rising edge (note 1) max 90 ns t wpws wp# setup to we# rising edge with command (note 1) min 20 ns t wprh wp# hold after ry/by# rising edge (note 1) max 2 ns oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs statu d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 63 preliminary note: sa = sector address (for sector erase), va = valid address for reading status data (see ?write operation status? ). figure 18.9 chip/sector erase operation timings figure 18.10 back-to-back cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w t wph 64 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary note: va = valid address. illustration shows first status cycle af ter command sequence, last status read cycle, and array data read cycle. figure 18.11 data# polling timings (dur ing embedded algorithms) note: va = valid address; not required for dq6. illustration show s first two status cycle after command sequence, last sta - tus read cycle, and array data read cycle. figure 18.12 toggle bit timings (during embedded algorithms) note: the system may use ce# or oe# to toggle dq2 and dq6. dq2 toggles only when read at an address within an erase-suspended sector. figure 18.13 dq2 vs. dq6 for erase/erase suspend operations we# ce# oe# high z t oe high z dq7 data ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc t wc we# ce# oe# high z t oe dq6/dq2 ry/by# t busy addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va we# dq6 dq2 enter embedded erasing erase suspend enter erase suspend program erase resume erase erase suspend read erase suspend program erase suspend read erase erase complete september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 65 preliminary notes: 1. the timings are similar to synchrono us read timings and asynchronous data polling timings/toggle bit timing. 2. va = valid address. two read cycles are required to de termine status. when the embedded algorithm operation is complete, the toggle bits will stop toggling. 3. rdy is active with data (a18 = 0 in the configuration regi ster). when a18 = 1 in the configuration register, rdy is active one clock cycle before data. 4. data polling requires burst access time delay. figure 18.14 synchronous data polling timing/toggle bit timings * valid address for sector protect: a[7:0] = 3ah. valid address for sector unprotect: a[7:0] = 3ah. ** command for sector protect is 68h. command for sector unprotect is 60h. *** command for sector protect verify is 48h. command for sector unprotect verify is 40h. figure 18.15 sector protect/unprot ect timing diagram ce# clk avd# addresses oe# data rdy status data status data va va t oe t oe sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h/68h** 40h/48h*** valid* valid* valid* status sector protect/unprotect verify v ih 66 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 18.7 alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see command definitions on page 71 for more information. notes: 1. pa = program address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 2. figure indicates the last two bus cycles of the command sequence. figure 18.16 alternate ce# controlled write operation timings parameter description all speed options unit jedec std. t avav t wc write cycle time (note 1) min 65 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 2 ns t ghel t ghel read recovery time before write(oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t wp we# width min 25 ns t eleh t cp ce# pulse width min 20 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) double-word typ 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t wadvs we# rising edge setu p to adv# falling edge min 11.75 ns t wcks we# rising edge setup to clk rising edge min 5 ns t ghel t ws oe# ce# we# reset# t ds data t ah t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy t wph t wp addresses september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 67 preliminary 18.8 erase and programming performance notes: 1. typical program and erase times a ssume the following conditions: 25 c, 2.5 v v cc , 100k cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 145c, v cc = 2.5 v, 1m cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 20.1 and table 20.2 for further information on command definitions. 6. ppbs have a program/erase cycle endurance of 100 cycles. 7. guaranteed cycles per sector is 100k minimum. 18.9 latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. 18.10 pqfp and fortified bga pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. ta b l e 1 8 . 6 erase and programming performance parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 5 s excludes 00h programming prior to erasure (note 4) chip erase time 16 mb = 46 32 mb = 78 16 mb = 230 32 mb = 460 s double word program time 8 130 s excludes system level overhead (note 5) accelerated double word program time 8 130 s accelerated chip program time 16 mb = 5 32 mb = 10 16 mb = 50 32 mb = 100 s chip program time (note 3) x32 16 mb = 12 32 mb = 24 16 mb = 120 32 mb = 240 s ta b l e 1 8 . 7 latchup characteristics description min max input voltage with respect to v ss on all pins except i/o pins (including a9, acc, and wp#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma ta b l e 1 8 . 8 pqfp and fortified bga pin capacitance parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf 68 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary 19 appendix 1 19.1 common flash memory interface (cfi) the common flash interface (cfi) specification out lines device and host system software inter - rogation handshake, which allows specific vendor -specified software algorithms to be used for entire families of devices. software support ca n then be device-independent, jedec id-indepen - dent, and forward- and backward -compatible for the specified flash device families. flash vendors can standardize existing interfaces for long-term compatibility. this device enters the cfi query mode when th e system writes the cfi query command, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in ta b l e 1 9 . 1 - ta b l e 19.3 . in order to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in ta b l e 1 9 . 1 - ta b l e 1 9 . 3 . the system must write the reset co mmand to return the device to the autoselect mode. for further information, please refer to the cf i specification and cfi publication 100, available via the world wide web at http://www.amd.com/products/nvd/overview/cfi.html or contact a spansion representative for copies of these documents. ta b l e 1 9 . 1 cfi query identification string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string qry 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 69 preliminary ta b l e 1 9 . 2 cfi system interface string addresses data description 1bh (see description) v cc min. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 0023h = s29cd-j devices 0030h = s29cl-j devices 1ch (see description) v cc max. (write/erase) dq7?dq4: volts, dq3?dq0: 100 millivolt 0027h = s29cd-j devices 0036h = s29cl-j devices 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single word/doubleword program 2 n s 20h 0000h typical timeout for min. size buffer program 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for word/doubleword program 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0007h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) ta b l e 1 9 . 3 device geometry definition addresses data description 27h (see description) device size = 2 n byte 0015h = 16 mb device 0016h = 32 mb device 28h 29h 0003h 0000h flash device interfac e description (for complete description, please refer to cfi publication 100) 0000 = x8-only asynchronous interface 0001 = x16-only asynchronous interface 0002 = supports x8 and x16 via byte# with asynchronous interface 0003 = x 32-only asynchronous interface 0005 = supports x16 and x32 via word# with asynchronous interface 2ah 2bh 0000h 0000h max. number of byte in multi-byte program = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h (see description) 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) address 31h data: 001dh = 16 mb device 003dh = 32 mb device 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100) 70 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary ta b l e 1 9 . 4 cfi primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string pri 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 0004h address sensitive unlock (dq1, dq0) 00 = required, 01 = not required silicon revision number (dq5?dq2) 0000 = cs49 0001 = cs59 0010 = cs99 0011 = cs69 0100 = cs119 46h 0002h erase suspend (1 byte) 00 = not supported 01 = to read only 02 = to read and write 47h 0001h sector protect (1 byte) 00 = not supported, x = number of sectors in per group 48h 0000h temporary sector unprotect 00h = not supported, 01h = supported 49h 0006h sector protect/unprotect scheme (1 byte) 01 =29f040 mode, 02 = 29f016 mode 03 = 29f400 mode, 04 = 29lv800 mode 05 = 29bds640 mode (softw are command locking) 06 = bdd160 mode (new sector protect) 07 = 29lv800 + pdl128 (new sector protect) mode 4ah 0037h simultaneous read/write (1 byte) 00h = not supported, x = number of sectors in all banks except bank 1 4bh 0001h burst mode type 00h = not supported, 01h = supported 4ch 0000h page mode type 00h = not supported, 01h = 4 word page, 02h = 8 word page 4dh 00b5h acc (acceleration) supply minimum 00h = not supported (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd) 4eh 00c5h acc (acceleration) supply maximum 00h = not supported, (dq7-dq4: volt in hex, dq3-dq0: 100 mv in bcd) 4fh 0001h top/bottom boot sector flag (1 byte) 00h = uniform device, no wp# control, 01h = 8 x 8 kb sectors at top and bottom with wp# control 02h = bottom boot device 03h = top boot device 04h = uniform, bottom wp# protect 05h = uniform, top wp# protect if the number of erase block regi ons = 1, then ignore this field 50h 0001h program suspend 00 = not supported 01 = supported 51h 0000h write buffer size 2 (n+1) word(s) 57h 0002h bank organization (1 byte) 00 = if data at 4ah is zero xx = number of banks 58h 0017h bank 1 region information (1 byte) xx = number of sectors in bank 1 59h 0037h bank 2 region information (1 byte) xx = number of sectors in bank 2 5ah 0000h bank 3 region information (1 byte) xx = number of sectors in bank 3 5bh 0000h bank 4 region information (1 byte) xx = number of sectors in bank 4 september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 71 preliminary 20 appendix 2 20.1 command definitions table 20.1 memory array command definitions (x32 mode) command (notes) cycles bus cycles (notes 1?4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (7) manufacturer id 4 555 aa 2aa 55 555 90 ba+x00 01 device id (11) 6 555 aa 2aa 55 555 90 ba+x01 7e ba+x0e 09 ba+x0f 00/01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (12) 1 ba b0 program/erase resume (13) 1 ba 30 cfi query (14, 15) 1 55 98 accelerated program (16) 2 xx a0 pa pd configuration register verify (15) 3 555 aa 2aa 55 ba+555 c6 ba+xx rd configuration register write (17) 4 555 aa 2aa 55 555 d0 xx wd unlock bypass entry (18) 3 555 aa 2aa 55 555 20 unlock bypass program (18) 2 xx a0 pa pd unlock bypass erase (18) 2 xx 80 xx 10 unlock bypass cfi (14, 18) 1 xx 98 unlock bypass reset (18) 2 xx 90 xx 00 legend: ba = bank address. the set of addresses that comprise a bank. the system may write any address within a bank to identify that bank for a command. pa = program address (amax?a0). addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = program data (dqmax?dq0) written to location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. ra = read address (amax?a0). rd = read data. data dqmax?dq0 at address location ra. sa = sector address. the set of addresses that comprise a sector. the system may write any address within a sector to identify that sector for a command. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see table 8.1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote re ad cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) when a bank is in the autosele ct mode, or if dq5 goes high (while the bank is provid ing status information). 7. the fourth cycle of the autoselect command sequence is a read cycle. the system must provide the bank address to obtain the manufacturer id or device id information. see ?autoselect? for more information. 8. this command cannot be executed until the unlock bypass command must be executed before writing this command sequence. the unlock bypass reset command must be executed to return to normal operation. 9. this command is ignored during any embedded program, erase or suspended operation. 10. valid read operations include asynchronous and burst read mode operations. 11. the device id must be read across the fourth, fifth, and sixth cycles. 00h in the sixth cycle indicates ordering option 00, 01h indicates ordering option 01. 12. the system may read and program in non-erasing sectors when in the program/erase suspend mode. the program/erase suspend command is valid only du ring a sector erase operation, and requires the bank address. 13. the program/erase resume command is valid only during the erase suspend mode, and requires the bank address. 14. command is valid when device is ready to read array data. 15. asynchronous read operations. 16. acc must be at v id during the entire operation of this command. 17. command is ignored during any embedded program, embedded erase, or suspend operation. 18. the unlock bypass entry command is required prior to any unlock bypass operation. the unlock bypass reset command is required to return to the read mode. 72 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary ta b l e 2 0 . 2 sector protection command definitions (x32 mode) command (notes) cycles bus cycles (notes 1 ? 4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secured silicon sector entry 3 555 aa 2aa 55 555 88 secured silicon sector exit 4 555 aa 2aa 55 555 90 xx 00 secured silicon protection bit program ( 5 , 6 ) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secured silicon protection bit status 6 555 aa 2aa 55 555 60 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 pwa[0-1] pwd[0-1] password verify 4 555 aa 2aa 55 555 c8 pwa[0-1] pwd[0-1] password unlock (7, 8) 5 555 aa 2aa 55 555 28 pwa[0-1] pwd[0-1] ppb program (5, 6) 6 555 aa 2aa 55 555 60 sg+wp 68 sg+wp 48 sg+wp rd(0) all ppb erase (5, 9, 10) 6 555 aa 2aa 55 555 60 wp 60 wp 40 wp rd(0) ppb status (11, 12) 4 555 aa 2aa 55 ba+555 90 sa+x02 00/01 ppb lock bit set 3 555 aa 2aa 55 555 78 ppb lock bit status 4 555 aa 2aa 55 ba+555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (12) 4 555 aa 2aa 55 ba+555 58 sa rd(0) ppmlb program (5, 6) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 6 555 aa 2aa 55 555 60 pl rd(0) spmlb program (5, 6) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 6 555 aa 2aa 55 555 60 sl rd(0) legend: dyb = dynamic protection bit ow = address (a5?a0) is (011x10). ppb = persistent protection bit pwa = password address. a0 selects between the low and high 32-bit portions of the 64-bit password pwd = password data. must be written over two cycles. pl = password protection mode lock address (a5?a0) is (001x10) rd(0) = read data dq0 protection indi cator bit. if protected, dq0= 1, if unprotected, dq0 = 0. rd(1) = read data dq1 protection indicator bit. if protected, dq1 = 1, if unprotected, dq1 = 0. sa = sector address. the set of addresses that comprise a sector. the system may write any address within a sector to identify that sector for a command. sg = sector group address ba = bank address. the set of addresses that comprise a bank. the system may write any address within a bank to identify that bank for a command. sl = persistent protection mode lock address (a5?a0) is (010x10) wp = ppb address (a5?a0) is (111010) x = don?t care ppmlb = password protec tion mode locking bit spmlb = persistent protection mode locking bit notes: 1. see table 8.1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock cycles, (lower address bits are 555 or 2aah as shown in table) address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns the device to reading the array. 6. the fourth cycle programs the addressed locking bit. the fifth and sixth cycles are used to validate whether the bit has been fully programmed. if dq0 (in the sixth cycle) reads 0, the program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. the entire four bus-cycle sequence must be entered for each portion of the password. 9. the fourth cycle erases all ppbs. the fifth and sixth cycles are used to validate whether the bits have been fully erased. if dq0 (in the sixth cycle) reads 1, the erase command must be issued and verified again. 10. before issuing the erase command, all ppbs should be programmed in order to prevent over-erasure of ppbs. 11. in the fourth cycle, 00h indicates ppb set; 01h indicates ppb not set. 12. the status of additional ppbs and dybs may be read (following the fourth cycle) without reissuing the entire command sequence. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 73 preliminary 21 revision summary revision a (march 1, 2005) initial release. revision a1 (april 15, 2005) ordering information and valid combinations tables updated to include lead (pb)-free options rev a2 (january 20, 2006) ordering information added "contact factory" for 75 mhz modified ordering options for ch aracters 15 & 16 to reflect autoselect id & top/bottom boot. changed ?n? for extended temperature range to ?m?. input/output descriptions removed logic symbol diagrams additional resources added additional resources section memory address map changed "bank 2" to "bank 1" simultaneous read/write operation removed ordering options table (tables 3 & 4) advanced sector protection/unprotection added figure: advanced sect or protection/unprotection added figures for ppb erase & program algorithm electronic marking added in electronic marking section absolute maximum ratings modified v cc ratings to reflect 2.6 v and 3.6 v devices modified v cc ratings to reflect 16 mb & 32 mb devices ac characteristics added note "t oe during read array" table: asynchronous read operation changed values of t avav , t avqv , t elqv , t glqv figure: conventional re ad operation timings moved t df line to 90% on the high-z output table: burst mode read for 32 mb & 16 mb added t aavs and t aavh timing parameters. changed t ch to t clkh changed t cl to t clkl removed the following timing parameters ? t ds (data setup to we# rising edge) 74 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary ? t dh (data hold from we# rising edge) ? t as (address setup to falling edge of we#) ? t ah (address hold from falling edge of we#) ? t cs (ce# setup time) ? t ch (ce# hold time) ? t acs (address setup time to clk) ? t ach (address hold time from adv# rising edge of clk while adv# is low) figure: burst mode read (x32 mode) added the following timing parameters ? t aavs ? t dvch ? t inds ? t indh figure: asynchronous command write timing changed t oeh to t weh change t wph to t oep figure: synchronous comm and write/read timing removed t wadvh and t wcks figure: wp# timing changed t ch to t busy table: erase/program operations added note 3: program/erase parameters are the same regardless of synchronous or asynchro - nous mode. add t oep (oe high pulse) alternative ce# controlled erase/program operations removed t oes added t wadvs and t wcks appendix 2: command definitions removed "or when device is in autoselect mode" from note 14 rev b0 (june 12, 2006) global changed document status to preliminary. distinctive characteristics changed cycling endurance fr om typical to guaranteed. performance characteristics updated max asynch. access time, max ce# access time, and max oe# access time in table. ordering information updated additional ordering options in designat or breakout table. updated valid combination tables. input/output descriptions and logic symbols changed ry/by# description. physical dimensions/connection diagrams changed note on connection diagrams. september 27, 2006 s29cd-j_cl-j_00_b1 s29cd-j & s29cl-j flash family 75 preliminary additional resources updated contact information. hardware reset (reset#) added section. autoselect updated third and fourth paragraphs in section. updated autoselect codes table. erase suspend / erase resume commands modified second paragraph. replaced allowable operations table with bulleted list. program suspend / program resume commands replaced allowable operations table with bulleted list. reset command added section. secured silicon sector flash memory region modified secured silicon sector addresses table. absolute maximum ratings modified v cc and v io ratings. modified note 1. operating ranges modified specification titles and descrip tions (no specification value changes). dc characteristics, cm os compatible table modified i ccb specification. deleted note 5. added note 3 references to table. burst mode read for 32 mb and 16 mb table modified t advcs , t clkh , t clkl , t aavs specifications. added t rstz , t wavdh1 , and t wavdh2 specifica - tions. added notes 2 and 3, and note references to table. bust mode read (x32 mode) figure added t aavh , deleted t dvch . synchronous command write/read timing figure added t wavdh1 and t wavdh2 to figure. deleted t acs and t ach from figure. hardware reset (reset#) added table to section. erase/program operations table added note references. deleted t oep specification. erase and programming performance changed double word program time specification. common flash memory interface (cfi) cfi system interface string table: changed description and data for addresses 1bh and 1ch. device geometry definition table: changed description and data for address 27h. rev b1 (september 27, 2006) distinctive characteristics changed cycling endurance specification to typical. performance characteristics changed t bacc specifications for 66 mhz, 56 mhz, 40 mhz speed options. 76 s29cd-j & s29cl-j flash family s29cd-j_cl-j_00_b1 september 27, 2006 preliminary ordering information added quantities to packing type descriptions, restructured table for easier reference. table 8.7 , s29cd-j & s29cl-j flash family autoselect codes (high voltage method) modified description of read cycle 3 dq7?dq0. table 8.8 , dq6 and dq2 indications corrected third column heading section 8.9, reset command added table. section 13.1, absolute maximum ratings deleted oe# from section. table 18.3 , burst mode read for 32 mb and 16 mb changed t advcs , t bdh specifications. modified description for t iacc . deleted minimum specifica - tions for t aavh . figure 18.4 , burst mode read (x32 mode) modified period for t iacc in drawing. colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and househol d use, but are not designed, deve loped and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuclear reaction control in nucle ar facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch co ntrol in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be lia ble to you and/or any third party for any claims or damages ari sing in connection with above-men- tioned uses of the products. any semiconductor device has an inherent chance of failure. you must protect against injury, damag e or loss from such failures by incorporating safety design measures in to your facility and equipment such as redu ndancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain re strictions on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior au- thorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion inc. pr oduct under development by spansion inc.. spansion inc. reserves the right to change or discontinue work on any product without notice. the information in this document is provided as is without warranty or guarantee of any kind as to its ac curacy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty , express, implied, or stat utory. spansion inc. assumes no liability for any damage s of any kind arising out of the use of the information in this document. copyright ?2005-2006 spansion inc. all rights reserved. spansion , the spansion logo, mirrorbit, ornand, hd-sim, and combination s thereof, are trade- marks of spansion inc. other company and product names used in this publication are for identification purposes only and may be trademarks of their re- spective companies. |
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