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august 2012 ? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 flxa2203 ? dual-mode, dual-si m-card level translator FXLA2203 dual-mode, dual-sim-card level translator features ? easy-to-use ?single pin? sim card swap control ? channel swap time: 130ns (typical) ? simultaneous dual-mode, dual-sim communication ? host ports: 1.65v to 3.6v voltage translation ? card ports: 1.65v to 3.6v voltage translation ? leverages the presence of existing pmic ldos ? iso7816 compliant ? power switch r on : 0.5 (typical) ? supports class b 3v sim / uim cards ? supports class c: 1.8v sim / uim cards ? non-preferential host v cc power-up sequencing ? activation / deactivati on timing compliant per iso7816-03 ? internal pull up resistors for bi-directional i/o pin ? outputs switch to 3-state if host v cc at gnd ? power-off protection ? packaged in 24-terminal umlp (2.5mm x 3.5mm) ? direction control not needed applications ? dual-mode dual-sim applications ? gsm, cdma, wcdma, tdscdma cdma2000, 3g cellular phones ? mobile tv: oma bcast description the FXLA2203 allows either two hosts to simultaneously communicate with two subscriber identity modules (sim), or two user identity modules (uim). dual mode refers to the mobile phones that are compatible with more than one form of data transmission or network (such as gsm, cdma, wcdma, tdscdma, or cdma2000), resulting in a dual-baseband processor configuration. in a dual-mode application, the FXLA2203 host ports interface directly with the baseband processors (see figure 9) . the bi-directional i/o open- drain channel features auto- direction and internal 10k pull-up resistors . rst and clk provide unidirectional translation from host to card only. either host can swap sim slot s with the assertion of a single control pin: ch_swap. the typical channel swap time is 130ns. the FXLA2203 does not contain internal low dropout regulator (ldos). instead, the FXLA2203 architecture incorporates two low-r on internal power switches for routing existing pmic (power management integrated circuit) ldos to individual sim slots. this reduces overall system power, leverages existing ldo system resources, and aligns with the philosophy that centralizing ldos in the pmic facilitates power management. since the FXLA2203 does not block the ldo function to the sim ca rd, existing activation / deactivation timing transparency is maintained between hosts, pmics, and sim cards. the device allows voltage translation from as high as 3.6v to as low as 1.65v. each port tracks its own port power supply. ordering information part number operating temperature range package packing method FXLA2203umx -40 to 85c 24-terminal, 2.5mm x 3.4 mm ultrathin molded leadless package (umlp), 0.4mm pitch tape and reel
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 2 flxa2203 ? dual-mode, dual-si m-card level translator block diagram figure 1. block diagram notes: 1. v cc must always be greater than or equal to ( ) v cc1 and v cc2 . 2. hybrid driver explained in detail in figure 12 - i/o pin functional diagram. 3. see table 2 for ch_swap truth table .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 3 flxa2203 ? dual-mode, dual-si m-card level translator pin configuration figure 2. top through view figure 3. bottom view pin definitions pin # name signal description 1 nc nc no connection 2 vcc1 i power supply 1 input: coming from pmic 1 ldo 3 vcc_card1 o power output for card slot 1 4 gnd gnd ground 5 vcc_card2 o power output for card slot 2 6 vcc2 i power supply 2 input: coming from pmic 2 ldo 7 rst_2 o reset output to card slot 2 8 i/o_2 i/o data i/o for card slot 2; open drain 9 clk_2 o clock output to card slot 2 10 clk_h_2 i clock input of host interface 2 11 rst_h_2 i reset input of host interface 2 12 i/o_h_2 i data i/o of host interface 2; open drain 13 vcc_h_2 supply power supply of host interface 2 14 gnd gnd ground 15 v cc supply power supply of control pins: en and ch_swap 16 en i gpio enable. low disables both sim card slots. high enables both sim card slots. connect to v cc if not used. default level after power up is low. 17 ch_swap i channel swap. ?1? host 1 to card slot 1, host 2 to card slot 2. ?0? host 1 to card slot 2, host 2 to card slot 1. connected to v cc if not used. default level after power up is low. 18 vcc_h_1 supply power supply of host interface 1 19 i/o_h_1 i/o data i/o of ho st interface 1; open drain 20 rst_h_1 i reset input of host interface 1 21 clk_h_1 i clock input of host interface 1 22 clk_1 o clock output to card slot 1 23 i/o_1 i/o data i/o for card slot 1; open drain 24 rst_1 o reset output to card slot 1
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 4 flxa2203 ? dual-mode, dual-si m-card level translator absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and st ressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter conditions min. max. unit v cc supply voltage v cc -0.5 5.0 v vcc_h_n, vccn -0.5 4.6 v v in dc input voltage host ports and card ports -0.5 4.6 v control input (en and ch_swap) -0.5 5.0 v o output voltage (4) output 3-state -0.5 4.6 v output active (host port) -0.5 v cc +0.5 output active (card port) -0.5 v cc +0.5 i ik dc input diode current v i <0v -50 ma i ok dc output diode current v o <0v -50 ma v o >v cc +50 i oh /i ol dc output source / sink current (4) -50 +50 ma i cc dc v cc or ground current (per supply pin) 100 ma t stg storage temperature range -65 +150 c p diss power dissipation at 5mhz 0.57 w esd electrostatic discharge capability human body model, jesd22-a114 (5) card side pins 3-5, 7-9, 14, 22-24 9 kv all other pins 3 charged device model, jesd22-c101 card side pins 3-5, 7-9, 14, 22-24 2 all other pins 2 notes: 4. i o absolute maximum ratings must be observed. 5. human body model (hbm): r=1500 , c=100pf. recommended operating conditions the recommended operating conditions table defines th e conditions for actual device operation. recommended operating conditions are specified to en sure optimal performance to the datash eet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. max. unit v cc power supply (6) v cc 1.65 4.35 v vcc_h_n, vccn 1.65 3.60 v v in input voltage (7) host port 0 3.6 v card port 0 3.6 v v out output voltage (7) host port 0 3.6 v card port 0 3.6 v host port i/o pin 0 vcc_h_n +0.3v v card port i/o pin 0 vccn +0.3v v t a operating temperature, free air -40 +85 c dt/dv input edge rate rst and clk 10 ns/v ja junction-to-ambient thermal resistance 52.1 c/w notes: 6. v cc must always be equal to, or greater than, v cc1 and v cc2 . 7. all unused inputs and input/outputs must be held at their respective v cc or gnd.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 5 flxa2203 ? dual-mode, dual-si m-card level translator dc electrical characteristics t a =-40 c to +85 c; pins i/o_1, i/o_2, i/o_h_1, i/o_h_2 (open drain). symbol parameter conditions v cc_h_n (v) v ccn (v) min. typ. max. unit v ih_host high-level input voltage data inputs of host interface 1.65 ? 3.60 1.65 - 3.60 0.7 x v cc_h_n v v ih_card data inputs of card interface 1.65 ? 3.60 1.65 - 3.60 0.7 x v ccn v v il_host low-level input voltage data inputs of host interface 1.65 ? 3.60 1.65 - 3.60 0.4 v v il_card data input of card interface 1.65 ? 3.60 1.65 - 3.60 0.15 x v ccn v v oh_host high-level output voltage i oh =-20a 1.65 ? 3.60 1.65 - 3.60 0.7 x v cc_h_n v v oh_card i oh =-20a 1.65 ? 3.60 1. 65 - 3.60 0.7 x v ccn v v ol_host low-level output voltage i ol =1ma, v il =0v 1.65 ? 3.60 1.65 - 3.60 0.05 v v ol_card i ol =1ma, v il =0v 1.65 ? 3.60 1.65 - 3.60 0.05 v v ol_host low-level output voltage i ol =1ma, v il =0.100v 1.65 ? 3.60 1.65 - 3.60 0.15 v v ol_card i ol =1ma, v il =0.100v 1.65 ? 3.60 1.65 - 3.60 0.15 v v ol_host low-level output voltage i ol =1ma, v il =0.250v 1.65 ? 3.60 1.65 - 3.60 0.3 v v ol_card i ol =1ma, v il =0.250v 1.65 ? 3.60 1.65 - 3.60 0.3 v i off power-off leakage current v o =0v to 3.6v host and card sides 3.60 0 1.0 a i oz 3-state output leakage v o =0v or 3.6v, en=gnd, host and card sides 3.60 3.60 1.0 a i oz 3-state output leakage v o =0v or 3.6v, en=1, host and card sides 0 3.60 1.0 a r pull_up internal pull-up resistor 1.65 ? 3.60 1.65 - 3.60 9 10 11 k
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 6 flxa2203 ? dual-mode, dual-si m-card level translator dc electrical characteristics t a =-40 c to +85 c; pins en, ch_swap. symbol parameter conditions v cc (v) min. max. unit v il low-level input voltage 3.60 0.65 v 1.80 0.45 v v ih high-level input voltage 3.60 1.2 v 1.80 0.9 v i l input leakage current v i =v cc or gnd, i/o floating 1.65 ? 3.60 1 a i cct increase in i cc per pin v in =1.8v 3.60 12 a v in =0.9v 1.80 10 a dc electrical characteristics t a =-40 c to +85 c; pins rst_1, rst_2, rst_h_1, rst_ h_2, clk_1, clk_2, clk_h_1, clk_h_2. symbol parameter conditions v cc_h_n (v) v ccn (v) min. typ. max. unit v il low-level input voltage 1.65 ? 3.60 1.65 ? 3.60 0.35 x v cc_h_n v v ih high-level input voltage 1.65 ? 3.60 1.65 ? 3.60 0.65 x v cc_h_n v v ol low-level output voltage i ol =20a 1.65 ? 3.60 1.65 ? 3.60 0.12 x v ccn v v oh high-level output voltage i oh =-20a 1.65 ? 3.60 1.65 ? 3.60 0.80 x v ccn v i i input leakage current v i =v cc or gnd 1.65 ? 3.60 3.60 1 a i off power-off leakage current v o =0v to 3.6v 3.60 0 1 a i oz 3-state output leakage v o =0v or 3.6v, en=gnd 3.60 3.60 1 a v o =0v or 3.6v, en=1 0 3.60 1 i cc quiescent supply current v i =v cc or gnd; i o =0, en=v cc , i/o floating 1.65 ? 3.60 1.65 ? 3.60 3 a i ccz power-down supply current v i =v cc or gnd; i o =0, en=gnd 1.65 ? 3.60 1.65 ? 3.60 3 a r onps power switch on resistance, en=1 i on =50ma, vccn to vcc_cardn 1.65 ? 3.60 1.65 ? 3.60 0.5 0.8 r ofps power switch off resistance, en=0 ch_swap=0 and 1, v cc1/2 =3.3v 1.65 ? 3.60 1.80 ? 3.60 50 m
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 7 flxa2203 ? dual-mode, dual-si m-card level translator ac characteristics card port (rst, clk) unless otherwise specified, output load: c l =30pf, r l 1m ? ; t a =-40 c to +85 c; v ccn =1.65v to 3.60v. symbol parameter typ. max. unit t r output rise time card port (8,10) 1 5 ns t f output fall time card port (9,10) 1 5 ns notes: 8. see figure 6 . 9. see figure 7 . 10. t r , t f guaranteed by characterization; not production tested. host and card port (i/o only) unless otherwise specified, output load: c l =30pf, r l 1m ? , and open-drain outputs; t a =-40 c to +85 c; v ccn =1.65v to 3.60v; and v cc_h_n =1.65v to 3.60v. symbol conditions parameter typ. max. unit t r (11,13) open drain inputs with 500a i sink (13) output rise time card port (10% - 90%) 200 500 ns t f (12,13) output fall time card port (90% - 10%) 2.5 4.0 ns t r (11,13) output rise time host port (10% - 90%) 200 500 ns t f (12,13) output fall time host port (90% - 10%) 2 3 ns notes: 11. see figure 6 . 12. see figure 7 . 13. t r , t f guaranteed by characterization; not production tested. v cc_h_n =1.65v to 3.60v (16) unless otherwise specified, t a =-40 c to +85 c and v ccn =1.65v to 3.60v. symbol ch_swap direction path typ. max. unit t swap hl, lh host ? card rst, clk, i/o and power switches 130 400 ns notes: 14. 15. 16. the power switch swap time assumes no decoupling capacitors on the vcc_card pins. 17. t swap is the time required for the ch_swap pin to swap host to sim slot connections. 18. the i/o pin swap time assumes a push / pull driver; other wise, the rise time (rc time constant) of an open-drain driver masks the actual i/o pin switch time. maximum frequency (19) unless otherwise specified, clk (host to card), t a =-40 c to +85 c, and card port v ccn =1.65v to 3.60v. host port: v cc_h_n ch_swap minimum unit 1.6v to 3.6v 1 30 mhz 0 30 note: 19. maximum frequency is guaranteed but not tested. power dissipation capacitance t a =+25c. symbol parameter conditions typical unit c pd power dissipation capacitance v cc_h_n =v ccn =v cc =3.3v, v i =0v or v cc , ch_swap=1, clk1 and clk2 switching at 5mhz 23 pf
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 8 flxa2203 ? dual-mode, dual-si m-card level translator test diagrams v cc dut c1 r1 test signal figure 4. test circuit table 1. ac test conditions v cco c1 r1 1.8v 0.15v 30pf 1m 2.5v 0.2v 30pf 1m 3.3 0.3v 30pf 1m v cci v cco gnd data in data out t pxx t pxx v mi v mo figure 5. input edge rates for rst and clk figure 6. active output rise time notes: 20. input t r =t f =2.0ns, 10% to 90% at v i =2.5v. 21. input t r =t f =2.5ns, 10% to 90% at v i =2.5v. v cci v cci /2 v cci /2 gnd data in t w maximum data rate, f = 1/t w figure 7. active output fall time figure 8. maximum data rate t fl 90% x cc 10% x cc v ol v oh v ot time t r 90% x cc 10% x cc v o v o l v ot time
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 9 flxa2203 ? dual-mode, dual-si m-card level translator application information figure 9 illustrates an FXLA2203 used in a dual-mode / dual-sim application. the fx la2203 does not contain any internal ldos. instead, the FXLA2203 architecture incorporates two low-r on internal power switches for routing existing power ma nagement integrated circuit (pmic) ldos to individual sim slot vcc pins. host 1 wcdma tdscdma host 2 gsm pmic ldo 1 pmic ldo 2 vcc h_1 vcc1 clk_h_1 rst_h_2 clk_h_2 i/o_h_2 rst_h_1 i/o_h_1 en ch_swap vcc2 vcc_h_2 vcc 1.8v / 3v 1.8v / 3v 1.8v / 3v 0.1f 0.1f 0.1f vcc_card1 vcc_ card2 rst_2 clk_2 i/o_2 clk_1 rst_1 i/o_1 gnd sim slot 1 1.8v / 3v 1.8v / 3v 1.8v / 3v sim slot 2 1.8v / 3v 0.1f 0.1f i/o clk vcc rst rst clk i/o vcc gnd gnd control can be either host host port card port figure 9. typical dual-mode application ch_swap truth table ch_swap controls simultaneous communication between host 1 or host 2, and either sim card according to table 2 ? dual-mode, dual-sim truth t able. either host can swap sim slots (130ns typical) with the assertion of the ch_swap pin. this simple solution is faster and less complicated than spi or i 2 c communication protocols. figure 10. ch_swap
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 10 flxa2203 ? dual-mode, dual-si m-card level translator table 2. dual-mode, dual-sim truth table enable ch_swap configuration 1 1 host 1 ? sim slot 1 1 1 host 2 ? sim slot 2 1 0 host 1 ? sim slot 2 1 0 host 2 ? sim slot 1 voltage translation description the FXLA2203 provides full voltage translation, or level shifting, from 1.65v ? 3.6v between host 1 or host 2 and either sim card (according to table 3). the host sides reference v cc_h_1 and v cc_h_2 , respectively, while each sim slot references the external pmic ldo voltage level determined by the ch_swap pin. this architecture offers a flexible solution for problematic v cc domain disagreements. for exam ple, if host 1 operates at 1.65v and host 2 operates at 2.5v, while slot 1 is populated with a 3.0v sim card and slot 2 is populated with a 1.8v sim card, the FXLA2203 provides seamless voltage translation across all four v cc domains. figure 11. voltage translation table 3. translation truth table enable ch_swap sim slot 1 voltage levels sim slot 2 voltage levels 1 1 pmic ldo1 / v cc1 pmic ldo2 / v cc2 1 0 pmic ldo2 / v cc2 pmic ldo1 / v cc1 note: 22. v cc must always be greater than or equal to ( ) v cc1 and v cc2 .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 11 flxa2203 ? dual-mode, dual-si m-card level translator i/o pin function the iso7816-3 specification, which governs the sim card physical layer requirem ents, identifies the i/o pin as a bi-directional open-drain pin. to provide auto- direction for the i/o pin, the FXLA2203 architecture (figure 12) implements two series npassgates and two dynamic drivers. this hybrid architecture is highly beneficial in a sim card interface. figure 12. i/o pin functional diagram the hybrid bi-directional i/o channel contains two series npassgates and two dynamic dr ivers. this architecture allows auto-direction functionality without the need for a direction pin from either the host or the sim card and accomplishes an automatic change in direction without the presence of an edge. due to open-drain technology, hosts and sim cards do not use push-pull dr ivers on the i/o pin. logic lows are pulled down (i sink ), while logic highs are ?let go? (3- state). during a logic low on the i/o pin, both series npassgates are turned on and act like a very low resistive short between the host and the sim card. when the host or card lets go of a previously held low on the i/o pin, the rise time is largely determined by the rc time constant, where r is the internal pull-up resistor (10k ) and c is the i/o signal trace capacitance. the FXLA2203 acts as a very low resistive short between the host and sim card (during a low) until either of the port?s v cc/2 thresholds are reached. after the rc time constant has reached the v cc/2 threshold of either port, the port?s edge detector triggers both dynamic drivers to drive their respective ports in the low-to-high (lh) direction, accelerating the rising edge. the resulting rise time resembles the ch2 waveform (blue) of figure 13. effectively, two distinct slew rates appear in the rise time. the first slew rate (slower) is the rc time const ant of the i/o signal trace. the second slew rate (faster) is the dynamic driver accelerating edge. if both the host and card ports of the i/o pin are high, a high-impedance path exists between the host and card ports because both of the seri es npassgates are turned off. if a host or sim card pulls the i/o pin low, that device?s driver pulls down (i sink ) the i/o pin until the high-to-low (hl) edge reaches the host or card port?s v cc/2 threshold. when either the host or card port threshold is reached, the port?s edge detectors trigger both dynamic drivers to drive their ports in the high-to- low (hl) direction, accelerating the falling edge. figure 13. scope shot of i/o and clock signals ch1: clk pin (yellow), ch2: i/o pin (blue) driven by the FXLA2203 activation / deactivation to ensure the sim card electrical circuits do not activate before the contacts of the sim card are mechanically connected, iso7816-3 2006 mandates the activation sequence of events described in figure 14. the FXLA2203 provides full transparency to the activation timing between host and sim card. figure 14. activation timing (iso 7816-3 2006) to ensure the sim card electrical circuits properly deactivate before the contac ts of the sim card are mechanically connected, is o7816-3 2006 mandates the sequence of events described in figure 15 the FXLA2203 provides full transparency to the deactivation timing between host and sim card. figure 15. deactivation (iso 7816-3 2006)
? 2010 fairchild semiconductor corporation www.fairchildsemi.com flxa2203 ? rev. 1.0.5 12 flxa2203 ? dual-mode, dual-si m-card level translator power-up / power-down sequence table 4. power supply pins pin name function 1 vcc en and ch_swap supply 2 vcc_h_1 host 1 supply 3 vcc_h_2 host 2 supply 4 vcc1 power switch 1 input 5 vcc2 power switch 2 input the v cc host power sequencing is non preferential; however, v cc must be higher or equal to v cc1 and v cc2 . the enable pin must be low while v cc1 and v cc2 ramp up to valid supply voltages or ramp down to 0v. a pull-up resistor tying enable to ground should be used to ensure that bus contention, excessive currents, or oscillations do not occur during power up or power down. the size of the pull-up resistor is based upon the current sinking capability of the device driving the enable pin. recommended power-up sequence (see figure 16) : 1. apply power to vcc. 2. assert en low (FXLA2203 disabled). 3. apply power to vcc1, vcc2, vcc_h_1, and vcc_h_2. 4. assert en high (FXLA2203 enabled). 5. begin activation timing (see figure 14) . recommended power-down sequence (see figure 17) : 1. complete deactivation timing (see figure 15) . 2. assert en low (FXLA2203 disabled). 3. ramp down power to vcc1, vcc2, vcc_h_1, and vcc_h_2. 4. once vcc1 and vcc2 ar e off, ramp down vcc. vcc_cardn rst_n clk_n i/o_n en ch_swap vcc1, vcc2 vcc_h_n rst_h_n clk_h_n i/o_h_n zzzz zzzz zzzz zzzz vcc ab c power-up sequencing begin activation timing per iso7816 3 2006 card ports host ports figure 16. power-up sequencing figure 17. power-down sequencing notes: 23. a=vcc becomes a valid voltage, en=low. 24. b=vcc1, vcc2, and vcc_h_n become valid voltages, en=low. 25. c=FXLA2203 enabled (en goes high), ready for activation (iso7816-3). notes: 26. a=disable FXLA2203, bring en low. 27. b=ramp down vcc1, vcc2, and vcc_h_n. 28. c=ramp down vcc once vcc1 and vcc2 are off.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com flxa2203 ? rev. 1.0.5 13 flxa2203 ? dual-mode, dual-si m-card level translator operation description table 5. power supply pins pin name function 6 vcc en and ch_swap supply 7 vcc_h_1 host 1 supply 8 vcc_h_2 host 2 supply 9 vcc1 power switch 1 input 10 vcc2 power switch 2 input the control pins en and ch_swap reference v cc . v cc can range from 1.65v to 3.6v and is independent from the other four power pins; however, v cc must always be higher or equal to vcc1 and vcc2. vcc_host_1 and vcc_host_2 can independently range from 1.65v to 3.6v a nd are the power supply pins for their respective host-side interfaces; including rst, i/o, and clk. vcc1 and vcc2 can independently range from 1.65v to 3.6v and are the inputs to the internal power switches. vcc1 and vcc2 should be connected to external pmic ldos. depending on the logic state of the ch_swap and en control pins, the external ldos are routed through the two power switches to either vcc_card1 or vcc_card2 (see table 6) . meanwhile, ch_swap also routes the host (1 or 2) signal pins; rst, i/o, and clk to the sim slot side (1 or 2). see section ?sim slot signals: active vs. 3-state? for details. the voltage reference of each sim slot is determined by the ldo voltage assigned to that sim slot. rst and clk are unidirectional pins always going in the sim slot direction. i/o is a bi -directional, open drain pin. internal 10k pull-up resistors are provided. the iso7816 standard identifies an algorithm that allows a host device to auto-detect the operating voltage of a sim card. the algorithm is called ?class selection? and the FXLA2203 is 100% transparent to class selection. if vcc1 and vcc_h_1 share the same voltage potential; these two pins can be tied together. likewise, if vcc2 and vcc_h_2 share the same voltage potential, these two pins ca n be tied together. under these conditions, and once ch_swap has been established, the host can power up or down the sim card along with the FXLA2203 host side solely by the ldo voltage. this feature is a convenient method for conserving power. note that v cc must always remain equal to or greater than v cc1 and v cc2 . the FXLA2203 i/o pins must be driven by open-drain drivers on the host sides and the card sides. sim slot power switch truth table if en=1 and ch_swap=1 ; then the v cc of sim slot 1 (vcc_card_1) tracks the vcc1 voltage (ext. ldo), while the v cc of sim slot 2 (vcc_card_2) tracks the vcc2 voltage (ext. ldo). if en=1 and ch_swap=0 ; then the v cc of sim slot 1 (vcc_card_1) tracks the vcc2 voltage (ext. ldo), while the vcc of sim slot 2 (vcc_card_2) tracks the v cc1 voltage (ext. ldo). see table 7. note that v cc must be > v cc1 and v cc2 . sim slot signal truth table if en=1 and ch_swap=1, the host 1 input signal pins (clk_h_1, rst_h_1, and i/o_ h_1) are translated to the sim slot 1 output signal pins (clk_1, rst_1, and i/o_1). the vcc1 voltage (ex t. ldo) sets the voltage levels of clk_1, rst_1, and i/o_1. host 2 input signal pins (clk_h_2, rst_h_2, and i/o_h_2) are translated to the sim slot 2 output signal pins (clk_2, rst_2, and i/o_2). the vcc2 (ext. ldo) voltage sets the voltage levels of clk_2, rst_2 and i/o_2. if en=1 and ch_swap=0, the host 1 input signal pins (clk_h_1, rst_h_1 and i/o_h_1) is translated to the sim slot 2 output signal pins (clk_2, rst_2, and i/o_2). the vcc1 voltage (ex t. ldo) sets the voltage levels of clk_2, rst_2, and i/o_2. host 2 input signal pins (clk_h_2, rst_h_2, and i/o_h_2) are translated to the sim slot 1 output signal pins (clk_1, rst_1, and i/o_1). the vcc2 (ext. ldo) voltage sets the voltage levels of cl k_1, rst_1, and i/o_1. table 6. power switch truth table vcc1 vcc2 en ch_swap vcc_card 1 vcc_card 2 0v ? 3.6v 0v ? 3.6v 1 1 vcc1 vcc2 0v ? 3.6v 0v ? 3.6v 1 0 vcc2 vcc1 table 7. signal truth table en ch_swap sim slot 1 sim slot 2 1 1 clk_h_1, rst_h_1, and i/o_h_1 clk_h_2, rst_h_2, and i/o_h_2 1 0 clk_h_2, rst_h_2, and i/o_h_2 clk_h_1, rst_h_1, and i/o_h_1
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 14 flxa2203 ? dual-mode, dual-s im-card level translator sim slot signals: active vs. 3-state the individual sim slot signals (clk, rst, and i/o) are active only if the appropriate vccn and vcc_h_n supplies are active (1.65v ? 3.6v). for example, if en=1 and ch_swap is 1, sim slot 1 signals (clk_1, rst_1, and i/o_1) are active only if vcc1 and vcc_h_1 are both active (1.65v ? 3.6v). vcc1 sets the voltage levels of clk_1, rst_1, and i/o_1. if either vcc1 or vcc_h_1 is below 1.65v, sim slot 1 signals (clk_1, rst_1, and i/o_1) are high impedance. likewise, sim slot 2 signals (clk_2, rst_2, and i/o_2) are active only if both vcc2 and vcc_h_2 are active (1.65v ? 3.6v). vcc2 sets the voltage levels of cl k_2, rst_2, and i/o_2. if en=1 and ch_swap is 0, sim slot 1 (clk_1, rst_1, and i/o_1) signals are active only if vcc2 and vcc_h_2 are active (1.65v ? 3.6v). vcc2 sets the voltage levels of clk_1, rst_1, and i/o_1. likewise, sim slot 2 signals (clk_2, rst_2, and i/o_2) are active only if both vcc1 and vcc_h_1 are active (1.65v ? 3.6v). vcc1 sets t he voltage levels of clk_2, rst_2, and i/o_2. for a complete listing of all the possible power switch and signal combinations, see table 8. table 8. complete power switch and signal truth table condition inputs outputs vcc en ch_swap vcc_h_1 vcc_h_2 vcc1 vcc2 clk_1, rst_1, i/o_1 clk_2, rst_2, i/o_2 vcc_card1 vcc_card2 1 off x x x x off off z z off off 2 on l x x x x x z z z z 3 on h 1 off off off off z z off off 4 on h 1 off off on off z z on off 5 on h 1 off off off on z z off on 6 on h 1 off off on on z z on on 7 on h 1 off on off off z z off off 8 on h 1 off on on off z z on off 9 on h 1 off on off on z a off on 10 on h 1 off on on on z a on on 11 on h 1 on off off off z z off off 12 on h 1 on off on off a z on off 13 on h 1 on off off on z z off on 14 on h 1 on off on on a z on on 15 on h 1 on on off off z z off off 16 on h 1 on on on off a z on off 17 on h 1 on on off on z a off on 18 on h 1 on on on on a a on on 19 on h 0 off off off off z z off off 20 on h 0 off off on off z z off on 21 on h 0 off off off on z z on off 22 on h 0 off off on on z z on on 23 on h 0 off on off off z z off off 24 on h 0 off on on off z z off on 25 on h 0 off on off on a z on off 26 on h 0 off on on on a z on on 27 on h 0 on off off off z z off off 28 on h 0 on off on off z a off on 29 on h 0 on off off on z z on off 30 on h 0 on off on on z a on on 31 on h 0 on on off off z z off off 32 on h 0 on on on off z a off on 33 on h 0 on on off on a z on off 34 on h 0 on on on on a a on on notes: 29. on=1.65v ? 3.6v. 30. off=powered down or 0v. 31. x=don?t care. 32. v cc > v cc1 and v cc2 .
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 15 flxa2203 ? dual-mode, dual-s im-card level translator physical dimensions top view bottom view recommended land pattern 0.10 c 0.08 c b a c 0.10 c 2x 2x side view seating plane 0.10 c 0.05 0.00 7 13 1 0.10 c a b 0.05 c 0.55 max. pin #1 ident 19 2.50 3.40 0.40 0.15 0.25 24x 0.45 0.55 0.35 0.45 23x 0.15 24 3.70 2.80 2.23 2.23 1 7 13 19 24 0.40 0.56 0.23 0.66 figure 18. 24-terminal 2.5mm x 3.4mm ul trathin molded leadless package (umlp) product-specific dimensions description nominal values (mm) description nominal values (mm) overall height 0.50 lead length 0.40 pkg standoff 0.012 lead pitch 0.40 lead thickness 0.15 body length (x) 2.50 lead width 0.20 body width (y) 3.40 package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . for current tape and reel specifications, visi t fairchild semiconductor?s online packaging area: http://www.fairchildsemi.com/packaging/micromlp24_tnr.pdf.
? 2010 fairchild semiconductor corporation www.fairchildsemi.com FXLA2203 ? rev. 1.0.5 16 flxa2203 ? dual-mode, dual-s im-card level translator

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