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intel ? pentium ? 4 processor in the 423-pin package at 1.30, 1.40, 1.50, 1.60, 1.70, 1.80, 1.90 and 2 ghz datasheet product features the intel ? pentium ? 4 processor is designed for high-performance desktops and entry level workstations. it is binary compatible with previous intel architecture processors. the pentium 4 processor provides great performance for applications running on advanced operating systems such as windows* 98, windows me, windows 2000 and unix*. this is achieved by the intel ? netburst? micro-architecture which brings a new level of performance for system buyers. the pentium 4 processor extends the power of the pentium iii processor with performance headroom for advanced audio and video internet capabilities. systems based on pentium 4 processors also include the latest features to simplify system management and lower the total cost of ownership for large and small business environments. the pentium 4 processor offers great performance for today?s and tomorrow?s applications. available at 1.30, 1.40,1.50, 1.60, 1.70, 1.80, 1.90 and 2 ghz binary compatible with applications running on previous members of the intel microprocessor line intel ? netburst? micro-architecture system bus frequency at 400 mhz rapid execution engine: arithmetic logic units (alus) run at twice the processor core frequency hyper pipelined technology advance dynamic execution ? very deep out-of-order execution ? enhanced branch prediction level 1 execution trace cache stores 12k micro-ops and removes decoder latency from main execution loops 8 kb level 1 data cache 256 kb advanced transfer cache (on-die, full speed level 2 (l2) cache) with 8-way associativity and error correcting code (ecc) 144 new streaming simd extensions 2 (sse2) instructions enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3d performance power management capabilities ? system management mode ? multiple low-power states optimized for 32-bit applications running on advanced 32-bit operating systems 8-way cache associativity provides improved cache hit rate on reads/store operations. order number: 249198-005 august 2001
information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties rela ting to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel ? pentium ? 4 processor may contain design defects or errors known as errata which may cause the product to deviate from published specifi cations. current characterized errata are available on request. intel, intel logo, pentium, and intel netburst are trademarks or registered trademarks of intel corporation or it subsidiaries in the united states and other countries. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001 *other brands and names may be claimed as the property of others.
contents 3 contents 1.0 introduction .................................................................................................................. 7 1.1 terminology........................................................................................................... 8 1.1.1 processor packaging terminology........................................................... 8 1.2 references ............................................................................................................ 9 2.0 electrical specifications ........................................................................................11 2.1 system bus and gtlref ...................................................................................11 2.2 power and ground pins ......................................................................................11 2.3 decoupling guidelines ........................................................................................11 2.3.1 vcc decoupling .....................................................................................12 2.3.2 system bus agtl+ decoupling.............................................................12 2.3.3 system bus clock (bclk[1:0]) and processor clocking .......................12 2.4 voltage identification ...........................................................................................12 2.4.1 phase lock loop (pll) power and filter...............................................13 2.5 reserved, unused pins, and testhi[10:0]........................................................15 2.6 system bus signal groups .................................................................................16 2.7 asynchronous gtl+ signals...............................................................................17 2.8 test access port (tap) connection....................................................................17 2.9 maximum ratings................................................................................................18 2.10 processor dc specifications...............................................................................18 2.11 agtl+ system bus specifications .....................................................................21 2.12 system bus ac specifications ............................................................................22 2.13 processor ac timing waveforms .......................................................................25 3.0 system bus signal quality specifications ....................................................31 3.1 bclk signal quality specifications and measurement guidelines.....................31 3.2 system bus signal quality specifications and measurement guidelines...........32 3.3 system bus signal quality specifications and measurement guidelines...........33 3.3.1 overshoot/undershoot guidelines .........................................................33 3.3.2 overshoot/undershoot magnitude .........................................................34 3.3.3 overshoot/undershoot pulse duration...................................................34 3.3.4 activity factor .........................................................................................34 3.3.5 reading overshoot/undershoot specification tables............................35 3.3.6 determining if a system meets the over/undershoot specifications .....35 4.0 package mechanical specifications .........................................................................43 4.1 package load specifications ..............................................................................46 4.2 processor insertion specifications ......................................................................47 4.3 processor mass specifications ...........................................................................47 4.4 processor materials.............................................................................................47 4.5 processor markings.............................................................................................48 4.6 processor pin-out coordinates...........................................................................48 5.0 pin listing and signal definitions ...........................................................................51 5.1 processor pin assignments ................................................................................51 5.1.1 pin listing by pin name .........................................................................51 5.1.2 pin listing by pin number ......................................................................57
contents 4 5.2 alphabetical signals reference .......................................................................... 63 6.0 thermal specifications and design considerations ................................. 71 6.1 thermal specifications........................................................................................ 72 6.2 thermal analysis................................................................................................. 72 6.2.1 measurements for thermal specifications............................................ 72 6.2.1.1 processor case temperature measurement ............................ 72 7.0 features ....................................................................................................................... 75 7.1 power-on configuration options ........................................................................ 75 7.2 clock control and low power states.................................................................. 75 7.2.1 normal state?state 1 ........................................................................... 75 7.2.2 autohalt powerdown state?state 2 .................................................. 75 7.2.3 stop-grant state?state 3 ..................................................................... 76 7.2.4 halt/grant snoop state?state 4 ........................................................ 77 7.2.5 sleep state?state 5.............................................................................. 77 7.2.6 deep sleep state?state 6 .................................................................... 78 7.3 thermal monitor .................................................................................................. 78 7.3.1 thermal diode........................................................................................ 79 8.0 boxed processor specifications ................................................................................ 81 8.1 introduction ......................................................................................................... 81 8.2 mechanical specifications................................................................................... 81 8.2.1 boxed processor fan heatsink dimensions .......................................... 82 8.2.2 boxed processor fan heatsink weight.................................................. 83 8.2.3 boxed processor retention mechanism and fan heatsink supports.... 83 8.3 boxed processor requirements ......................................................................... 84 8.3.1 fan heatsink power supply ................................................................... 84 8.4 thermal specifications........................................................................................ 85 8.4.1 boxed processor cooling requirements ............................................... 85 8.4.2 variable speed fan ............................................................................... 87 9.0 debug tools specifications ........................................................................................ 89 9.1 logic analyzer interface (lai)............................................................................ 89 9.1.1 mechanical considerations .................................................................... 89 9.1.2 electrical considerations........................................................................ 89
contents 5 figures 1 typical vcciopll, vcca and vssa power distribution ..................................14 2 phase lock loop (pll) filter requirements ......................................................15 3 ac test circuit ....................................................................................................26 4 tck clock waveform..........................................................................................26 5 differential clock waveform................................................................................27 6 system bus common clock valid delay timings...............................................27 7 system bus reset and configuration timings....................................................28 8 source synchronous 2x (address) timings .......................................................28 9 source synchronous 4x timings ........................................................................29 10 power-on reset and configuration timings.......................................................29 11 test reset timings .............................................................................................30 12 bclk[1:0] signal integrity waveform..................................................................32 13 low-to-high system bus receiver ringback tolerance.....................................33 14 high-to-low system bus receiver ringback tolerance.....................................33 15 maximum acceptable overshoot/undershoot waveform ...................................41 16 exploded view of processor components on a system board ..........................43 17 processor package .............................................................................................44 18 processor cross-section and keep-in ................................................................45 19 processor pin detail............................................................................................46 20 ihs flatness specification ..................................................................................46 21 processor markings.............................................................................................48 22 processor pinout diagram - bottom view ...........................................................49 23 example thermal solution (not to scale)............................................................71 24 guideline locations for case temperature (tcase) thermocouple placement73 25 technique for measuring with 0 degree angle attachment ................................73 26 technique for measuring with 90 degree angle attachment ..............................73 27 stop clock state machine ...................................................................................76 28 mechanical representation of the boxed pentium 4 processor .........................81 29 side view space requirements for the boxed processor ..................................82 30 top view space requirements for the boxed processor ...................................83 31 boxed processor fan heatsink power cable connector description.................84 32 acceptable system board power header placement relative to processor socket ..............................................................................85 33 boxed processor fan heatsink airspace keepout requirements (side 1 view).86 34 boxed processor fan heatsink airspace keepout requirements (side 2 view).86 35 boxed processor fan heatsink set points .........................................................87
contents 6 tables 1 references............................................................................................................ 9 2 voltage identification definition........................................................................... 13 3 system bus pin groups ...................................................................................... 16 4 processor dc absolute maximum ratings ......................................................... 18 5 voltage and current specifications..................................................................... 19 6 system bus differential bclk specifications ..................................................... 20 7 agtl+ signal group dc specifications ............................................................. 20 8 asynchronous gtl+ and tap signal group dc specifications ......................... 21 9 agtl+ bus voltage definitions........................................................................... 21 10 system bus differential clock specifications...................................................... 22 11 system bus common clock ac specifications .................................................. 22 12 system bus source synch ac specifications agtl+ signal group .................. 23 13 asynchronous gtl+ signals ac specifications ................................................. 24 14 system bus ac specifications (reset conditions) ............................................. 24 15 tap signals ac specifications ........................................................................... 25 16 bclk signal quality specifications .................................................................... 31 17 ringback specifications for agtl+, asynchronous gtl+, and tap signal groups ...................................................................................... 32 18 source synchronous (400mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) ......................................... 37 19 source synchronous (200mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) ......................................... 37 20 common clock (100mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) ......................................... 38 21 asynchronous gtl+ and tap signal groups overshoot/undershoot tolerance (1.7v processors) ......................................... 38 22 source synchronous (400mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) ........................................................................... 39 23 source synchronous (200mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) ............................................................................ 39 24 common clock (100mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) ............................................................................ 40 25 asynchronous gtl+ and tap signal groups overshoot/undershoot tolerance (1.75v processors) ............................................................................ 40 26 description table for processor dimensions ...................................................... 45 27 package dynamic and static load specifications .............................................. 47 28 processor mass .................................................................................................. 47 29 processor material properties............................................................................. 48 30 pin listing by pin name ...................................................................................... 51 31 pin listing by pin number................................................................................... 57 32 signal description ............................................................................................... 63 33 processor thermal design power ..................................................................... 72 34 power-on configuration option pins .................................................................. 75 35 thermal diode parameters ................................................................................. 79 36 thermal diode interface...................................................................................... 80 37 fan heatsink power and signal specifications................................................... 84 38 boxed processor fan heatsink set points ......................................................... 87
intel ? pentium ? 4 processor in the 423-pin package 7 1.0 introduction the intel ? pentium ? 4 processor in the 423-pin package socket with intel ? netburst ? micro- architechture is based on a new 32-bit micro-architecture that operates at significantly higher clock speeds and delivers performance levels that are significantly higher than previous generations of ia-32 processors. while based on the intel ? netburst ? micro-architecture, it still maintains the tradition of compatibility with ia-32 software. the intel netburst micro-architecture features include hyper pipelined technology, a rapid execution engine, a 400 mhz system bus, and an execution trace cache. the hyper pipelined technology doubles the pipeline depth in the pentium 4 processor, allowing the processor to reach much higher core frequencies. the rapid execution engine allows the two integer alus in the processor to run at twice the core frequency, which allows many integer instructions to execute in 1/2 clock tick. the 400 mhz system bus is a quad- pumped bus running off a 100 mhz system clock making 3.2 gb/sec data transfer rates possible. the execution trace cache is a level 1 cache that stores approximately 12k decoded micro- operations, which removes the decoder from the main execution path, thereby increasing performance. improved features within the intel netburst micro-architecture include advanced dynamic execution, advanced transfer cache, enhanced floating point and multi-media unit, and streaming simd extensions 2 (sse2). the advanced dynamic execution improves speculative execution and branch prediction internal to the processor. the advanced transfer cache is a 256kb, on-die level 2 cache with increased bandwidth over previous micro-architectures. the floating point and multi- media units have been improved by making the registers 128 bits wide and adding a separate register for data movement. finally, sse2 adds 144 new instructions for double-precision floating point, simd integer, and memory management. the streaming simd extensions 2 enable break-through levels of performance in multimedia applications including 3-d graphics, video decoding/encoding, and speech recognition. the new packed double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3-d geometry techniques, such as ray tracing. the pentium 4 processor supports uni-processor configurations only. as a result of this integration, the return to pin grid array (pga) style processor packaging is possible. the same manageability features which are included in intel ? pentium ? iii processors are included on pentium 4 processors with the addition of thermal monitor. the thermal monitor allows systems to be designed for anticipated processor thermals as opposed to worst case with no performance degradation expected. power management capabilities such as autohalt, stop-grant, sleep, and deep sleep have also been retained for power management capabilities. new heat sinks, heat sink retention mechanisms, and sockets are required for the pentium 4 processor in the 423-pin package. the socket for the pentium 4 processor in the 423-pin package is called the 423-pin socket in this and other documentation. through-hole zif technology will be used for the 423-pin socket. reference heat sink and retention mechanism designs have been developed with manufacturability as a high priority. hence, mechanical assembly can be completed from the top of the motherboard and should not require any special tooling. the pentium 4 processor in the 423-pin package uses a new scalable system bus protocol referred to as the ?system bus? in this document. the pentium 4 processor system bus utilizes a split- transaction, deferred reply protocol similar to that of the p6 processor family system bus, but is not compatible with the p6 processor family system bus. the system bus uses source-synchronous transfer (sst) of address and data to improve performance. whereas the p6 processor family transfers data once per bus clock, the pentium 4 processor transfers data four times per bus clock
intel ? pentium ? 4 processor in the 423-pin package 8 (4x data transfer rate, as in agp 4x). along with the 4x data bus, the address bus can deliver addresses two times per bus clock and is referred to as a ?double-clocked? or 2x address bus. in addition, the request phase completes in one clock cycle. working together, the 4x data bus and 2x address bus provide a data bus bandwidth of up to 3.2 gbytes/second (3200mbytes/sec). finally, the system bus also introduces transactions that are used to deliver interrupts. signals on the system bus use assisted gtl+ (agtl+) level voltages which are fully described in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide . 1.1 terminology a ?#? symbol after a signal name refers to an active low signal, indicating a signal is in the asserted state when driven to a low level. for example, when reset# is low, a reset has been requested. conversely, when nmi is high, a nonmaskable interrupt has occurred. in the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data ), the ?#? symbol implies that the signal is inverted. for example, d[3:0] = ?hlhl? refers to a hex ?a?, and d[3:0]# = ?lhlh? also refers to a hex ?a? (h= high logic level, l= low logic level). ?system bus? refers to the interface between the processor and system core logic (a.k.a. the chipset components). the system bus is a interface to the processor, memory, and i/o. for this document, ?system bus? is used as the generic term for the pentium 4 processor bus. 1.1.1 processor packaging terminology commonly used terms are explained here for clarification: intel ? pentium ? 4 processor in the 423-pin package ?the entire product including processor core, integrated heat spreader, and interposer. pentium 4 processor ?throughout this document ?pentium 4 processor? refers to the intel ? pentium ? 4 processor in the 423-pin package . interposer ?the structure on which the processor core package and i/o pins are mounted. processor core ?the processor?s execution engine. all ac timings and signal integrity specifications are to the silicon of the processor core. integrated heat spreader ?the surface used to make contact between a heatsink or other thermal solution and the processor. abbreviated as ihs. 423-pin socket ?the connector which mates the pentium 4 processor to the system board. retention mechanism ?the support structure that is mounted on the system board to provide added support and retention for heatsinks. olga (organic land grid array) package ?microprocessor packaging using ?flip chip? design, where the processor is attached to the substrate face-down for better signal integrity, more efficient heat removal and lower inductance.
intel ? pentium ? 4 processor in the 423-pin package 9 1.2 references material and concepts available in the following documents may be beneficial when reading this document: note: 1. contact your intel representative for the latest revision of the documents without order numbers. 2. the i/o buffer models are in ibis format. table 1. references document order number 1 intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide ap-485, intel processor identification and the cpuid instruction 241618 intel ? pentium ? 4 processor thermal design guidelines intel ? pentium ? 4 processor emi guidelines voltage regulator module (vrm) 9.0 dc-dc converter design guidelines 423-pin socket (pga423) design guidelines intel architecture software developer's manual 243193 volume i: basic architecture 243190 volume ii: instruction set reference 243191 volume iii: system programming guide 243192 intel ? pentium ? 4 processor i/o buffer models 2 intel ? pentium ? 4 processor overshoot checker tool 2
intel ? pentium ? 4 processor in the 423-pin package 10
intel ? pentium ? 4 processor in the 423-pin package 11 2.0 electrical specifications 2.1 system bus and gtlref most system bus signals of the intel ? pentium ? 4 processor in the 423-pin package system bus signals use assisted gunning transceiver logic (agtl+) signalling technology. as with the intel p6 family of microprocessors, this signalling technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. unlike the p6 processor family, the termination voltage level for the pentium 4 processor agtl+ signals is v cc , the operating voltage of the processor core. p6 family processors utilize a fixed 1.5v termination voltage known as v tt . because of the speed improvements to data and address busses, signal integrity and platform design methods become more critical than with previous processor families. design guidelines for the pentium 4 processor system bus are detailed in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide . the agtl+ inputs require a reference voltage (gtlref) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. gtlref must be generated on the system board (see table 13 for gtlref specifications). termination resistors are provided on the processor silicon and are terminated to its core voltage (v cc ). intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most agtl+ signals. some agtl+ signals do not include on-die termination and must be terminated on the system board. see table 4 for details regarding these signals. the agtl+ bus depends on incident wave switching. therefore timing calculations for agtl+ signals are based on flight time as opposed to capacitive deratings. analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. contact your intel field representative to obtain the buffer models, intel ? pentium ? 4 processor i/o buffer models. 2.2 power and ground pins for clean on-chip power distribution, pentium 4 processors have 111 v cc (power) and 112 v ss (ground) inputs. all power pins must be connected to v cc , while all v ss pins must be connected to a system ground plane.the processor v cc pins must be supplied the voltage determined by the vid (voltage id) pins. 2.3 decoupling guidelines due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. this may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in table 5. failure to do so can result in timing violations or reduced lifetime of the component. for further information and design guidelines, refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide .
intel ? pentium ? 4 processor in the 423-pin package 12 2.3.1 v cc decoupling regulator solutions need to provide bulk capacitance with a low effective series resistance (esr) and keep a low interconnect resistance from the regulator (or vrm pins) to the socket. bulk decoupling for the large current swings when the part is powering on, or entering/exiting low power states, must be provided by the voltage regulator solution (vrm). for more details on this topic, refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide. 2.3.2 system bus agtl+ decoupling pentium 4 processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. decoupling must also be provided by the system motherboard for proper agtl+ bus operation. for more information, refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide . 2.3.3 system bus clock (bclk[1:0]) and processor clocking bclk[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. as in previous generation processors, the pentium 4 processor core frequency is a multiple of the bclk[1:0] frequency. the pentium 4 processor bus ratio multiplier is set at its default ratio at manufacturing. no jumpers or user intervention is necessary, the processor will automatically run at the speed indicated on the package. unlike previous processors, the pentium 4 processor uses a differential clocking implementation. for more information on pentium 4 processor clocking, refer to the ck00 clock synthesizer/driver design guidelines . 2.4 voltage identification the vid specification for pentium 4 processors is different from that of previous generations and is supported by the vrm 9.0 dc-dc convertor design guidelines . the voltage set by the vid pins is the maximum voltage allowed by the processor. a minimum voltage is provided in table 5 and changes with frequency. this allows processors running at a higher frequency to have a relaxed minimum voltage specification. the specifications have been set such that one voltage regulator can work with all supported frequencies. pentium 4 processors use five voltage identification pins, vid[4:0], to support automatic selection of power supply voltages. table 2 specifies the voltage level corresponding to the state of vid[4:0]. a ?1? in this table refers to an open pin and a ?0? refers to low voltage level. the definition provided in table 2 is not related in any way to previous processors or vrms. if the processor socket is empty (vid[4:0] = 11111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. see the vrm 9.0 dc/dc converter design guidelines for more details . power source characteristics must be guaranteed to be stable whenever the supply to the voltage regulator is stable.
intel ? pentium ? 4 processor in the 423-pin package 13 2.4.1 phase lock loop (pll) power and filter v cca and v cciopll are power sources required by the pll clock generators on the pentium 4 processor silicon. since these plls are analog in nature, they require quiet power supplies for minimum jitter. jitter is detrimental to the system: it degrades external i/o timings as well as internal core timings (i.e., maximum frequency). to prevent this degradation, these supplies must be low pass filtered from v cc . a typical filter topology is shown in figure 1. the ac low-pass requirements, with input at v cc and output measured across the capacitor (c a or c io in figure 1), is as follows: table 2. voltage identification definition processor pins vid4 vid3 vid2 vid1 vid0 v cc_max 11111vrm output off 111101.100 111011.125 111001.150 110111.175 110101.200 110011.225 110001.250 101111.275 101101.300 101011.325 101001.350 100111.375 100101.400 100011.425 100001.450 011111.475 011101.500 011011.525 011001.550 010111.575 010101.600 010011.625 010001.650 001111.675 001101.700 001011.725 001001.750 000111.775 000101.800 000011.825 000001.850
intel ? pentium ? 4 processor in the 423-pin package 14 < 0.2 db gain in pass band < 0.5 db attenuation in pass band < 1 hz (see dc drop in next set of requirements) > 34 db attenuation from 1 mhz to 66 mhz > 28 db attenuation from 66 mhz to core frequency the filter requirements are illustrated in figure 2. for recommendations on implementing the filter refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide . figure 1. typical v cciopll , v cca and v ssa power distribution vcc r vcca vssa vcciopll r l l processor core pll c a c io
intel ? pentium ? 4 processor in the 423-pin package 15 . notes: 1. diagram not to scale. 2. no specification for frequencies beyond fcore (core frequency). 3. fpeak, if existent, should be less than 0.05 mhz. 2.5 reserved, unused pins, and testhi[10:0] all reserved pins must remain unconnected. connection of these pins to v cc , v ss , or to any other signal (including each other) can result in component malfunction or incompatibility with future pentium 4 processors. see chapter 5.0 for a pin listing of the processor and the location of all reserved pins. for reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. in a system level design, on-die termination has been included on the pentium 4 processor to allow signals to be terminated within the processor silicon. most unused agtl+ inputs should be left as no connects, as agtl+ termination is provided on the processor silicon. however, see table 3 for details on agtl+ signals that do not include on-die termination. unused active high inputs should be connected through a resistor to ground (v ss ). unused outputs can be left unconnected, however this may interfere with some tap functions, complicate debug probing, and prevent boudary scan testing. a resistor must be used when tying bidirectional signals to power or ground. when tying any signal to power or ground, a resistor will also allow for system testability. for unused agtl+ input or i/o signals, use pull-up resistors of the same value for the on-die termination resistors (r tt ). see table 9. figure 2. phase lock loop (pll) filter requirements 0 db -28 db -34 db 0.2 db forbidden zone -0.5 db forbidden zone 1 mhz 66 mhz f core f peak 1 hz dc passband high frequency band
intel ? pentium ? 4 processor in the 423-pin package 16 tap, asynchronous gtl+ inputs, and asynchronous gtl+ outputs do not include on-die termination. inputs and used outputs must be terminated on the system board. unused outputs may be terminated on the system board or left unconnected. note that leaving unused output not terminated may interfere with some tap functions, complicate debug probing, and prevent boudary scan testing. signal termination for these signal types is discussed in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide and itp700 debug port design guide. the testhi[10:0] pins must be connected to v cc via a pull-up resistor. testhi[10:0] may be connected individually to v cc via pull-up resistors between 1 k ? and 10 k ? value. alternately, testhi[1:0] may be tied together and pulled up to v cc with a single 1 k ? - 4.7 k ? resistor; testhi[7:2] may be tied together and pulled up to v cc with a single 1 k ? - 4.7 k ? resistor; and testhi[10:8] may be tied together and pulled up to v cc with a single 1 k ? - 4.7 k ? resistor. however, tying any of the testhi pins together will prevent the ability to perform boundary scan testing. 2.6 system bus signal groups in order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. agtl+ input signals have differential input buffers, which use gtlref as a reference level. in this document, the term ?agtl+ input? refers to the agtl+ input group as well as the agtl+ i/o group when receiving. similarly, ?agtl+ output? refers to the agtl+ output group as well as the agtl+ i/o group when driving. with the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. one set is for common clock signals which are dependant upon the rising edge of bclk0 (ads#, hit#, hitm#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of bclk0. asychronous signals are still present (a20m#, ignne#, etc.) and can become active at any time during the clock cycle. table 3 identifies which signals are common clock, source synchronous, and asynchronous. table 3. system bus pin groups (page 1 of 2) signal group type signals 1 agtl+ common clock input synchronous to bclk[1:0] bpri#, defer#, reset# 2 , rs[2:0]#, rsp#, trdy# agtl+ common clock i/o synchronous to bclk[1:0] ap[1:0]#, ads#, binit#, bnr#, bpm[5:0]# 2 , br0# 2 , dbsy#, dp[3:0]#, drdy#, hit#, hitm#, lock#, mcerr# agtl+ source synchronous i/o synchronous to assoc. strobe signals associated strobe req[4:0]#, a[16:3]# 5 adstb0# a[35:17]# 5 adstb1# d[15:0]#, dbi0# dstbp0#, dstbn0# d[31:16]#, dbi1# dstbp1#, dstbn1# d[47:32]#, dbi2# dstbp2#, dstbn2# d[63:48]#, dbi3# dstbp3#, dstbn3#
intel ? pentium ? 4 processor in the 423-pin package 17 note: 1. refer to section 5.2 for signal descriptions. 2. these agtl+ signals do not have on-die termination and must be terminated on the system board. 3. in processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. in systems with the debug port implemented on the system board, these signals are no connects. 4. these signal groups are not terminated by the processor. refer to section 2.5 and the intel? pentium? 4 processor and intel? 850 chipset platform design guide and itp700 debug port design guide for termination requirements and further details. 5. the value of these pins during the active-to-inactive edge of reset# determine processor configuration options. see section 7.1 for details. 2.7 asynchronous gtl+ signals pentium 4 processors do not utilize cmos voltage levels on any signals that connect to the processor. as a result, legacy input signals such as a20m#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, smi#, slp#, and stpclk# utilize gtl+ input buffers. legacy output ferr# and other non-agtl+ signals (thermtrip# and prochot#) utilize gtl+ output buffers. all of these signals follow the same dc requirements as agtl+ signals, however the outputs are not actively driven high (during a logical 0 to 1 transition) by the processor (the major difference between gtl+ and agtl+). these signals do not have setup or hold time specifications in relation to bclk[1:0]. however, all of the asynchronous gtl+ signals are required to be asserted for at least two bclks in order for the processor to recognize them. see section 2.10 and section 2.12 for the dc and ac specifications for the asynchronous gtl+ signal groups. see section section 7.2 for additional timing requirements for entering and leaving the low power states. 2.8 test access port (tap) connection due to the voltage levels supported by other components in the test access port (tap) logic, it is recommended that the pentium 4 processor be first in the tap chain and followed by any other components within the system. a translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate agtl+ strobes synchronous to bclk[1:0] adstb[1:0]#, dstbp[3:0]#, dstbn[3:0]# asynchronous gtl+ input 4 a20m#, dbr#, ignne#, init#, lint0/intr, lint1/nmi, pwrgood, smi#, slp#, stpclk# asynchronous gtl+ output 4 ferr#, ierr#, thermtrip#, prochot# tap input 4 synchronous to tck tck, tdi, tms, trst# tap output 4 synchronous to tck dbr 3 , tdo system bus clock clock bclk[1:0], itp_clk[1:0] 3 power/other v cc , v cca , v cciopll , vid[4:0], v ss , v ssa , gtlref[3:0], comp[1:0], reserved, sktocc#, testhi[10:0], thermda, thermdc, v cc_sense , v ss_sense table 3. system bus pin groups (page 2 of 2) signal group type signals 1
intel ? pentium ? 4 processor in the 423-pin package 18 voltage level. similar considerations must be made for tck, tms, and trst#. two copies of each signal may be required, with each driving a different voltage level. refer to chapter 9.0 for more detailed information. 2.9 maximum ratings table 4 lists the processor?s maximum environmental stress ratings. functional operation at the absolute maximum and minimum is neither implied nor guaranteed. the processor should not receive a clock while subjected to these conditions. functional operating parameters are listed in the ac and dc tables. extended exposure to the maximum ratings may affect device reliability. furthermore, although the processor contains protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static voltages or electric fields. note: 1. this rating applies to any processor pin. 2.10 processor dc specifications the processor dc specifications in this section are defined at the processor core silicon and not the package pins unless noted otherwise. see chapter 5.0 for the pin signal definitions and signal pin assignments. most of the signals on the processor system bus are in the agtl+ signal group. the dc specifications for these signals are listed in table 7. previously, legacy signals and test access port (tap) signals to the processor used low-voltage cmos buffer types. however, these interfaces now follow dc specifications similar to gtl+. the dc specifications for these signal groups are listed in table 8. table 5 through table 8 list the dc specifications for the pentium 4 processor and are valid only while meeting specifications for case temperature, clock frequency, and input voltages. care should be taken to read all notes associated with each parameter. table 4. processor dc absolute maximum ratings symbol parameter min max unit notes t storage processor storage temperature ?40 85 c v cc any processor supply voltage with respect to v ss ?0.5 2.1 v 1 v inagtl+ agtl+ buffer dc input voltage with respect to v ss -0.3 2.1 v v inasynch_gtl+ asynch gtl+ buffer dc input voltage with respect to v ss -0.3 2.1 v i vid max vid pin current 5 ma
intel ? pentium ? 4 processor in the 423-pin package 19 notes: 1. unless otherwise noted, all specifications in this table are based on estimates and simulations or early empirical data. these specifications will be updated with characterized data from silicon measurements at a later date. table 5. voltage and current specifications symbol parameter min typ max unit notes 1 v cc vid = 1.7v v cc for processor at 1.30 ghz 1.40 ghz 1.50 ghz 1.565 1.560 1.555 1.70 1.70 1.70 v v v 2, 3, 4, 9 2, 3, 4, 9 2, 3, 4, 9 v cc vid = 1.75v v cc for processor at 1.30 ghz 1.40 ghz 1.50 ghz 1.60 ghz 1.70 ghz 1.80 ghz 1.90 ghz 2 ghz 1.605 1.600 1.595 1.590 1.580 1.575 1.570 1.560 1.75 1.75 1.75 1.75 1.75 1.75 1.75 1.75 v v v v v v 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 2, 3, 4, 10 v cc_mid v cc for processor at maximum current (v cc_ max +v cc_ min )/2 v 4 i cc vid = 1.70v i cc for processor 1.30 ghz 1.40 ghz 1.50 ghz 38.1 40.6 43.0 a a a 4, 5, 9 4, 5, 9 4, 5, 9 i cc vid = 1.75v i cc for processor 1.30 ghz 1.40 ghz 1.50 ghz 1.60 ghz 1.70 ghz 1.80 ghz 1.90 ghz 2 ghz 39.8 42.2 45.0 47.7 50.2 50.6 52.7 55.0 a a a a a a a a 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 4, 5, 10 i sg nt i slp i cc stop-grant, i cc sleep 1.30 ghz 1.40 ghz 1.50 ghz 1.60 ghz 1.70 ghz 1.80 ghz 1.90 ghz 2 ghz 9.7 9.8 9.9 10.7 10.9 11.1 11.0 11.3 a a a a a a a a 6, 8 i dslp i cc deep sleep 8.7 a 8 i tcc i cc tcc active i cc a7 i cc_pll i cc for pll pins 30 ma
intel ? pentium ? 4 processor in the 423-pin package 20 2. these voltages are targets only. a variable voltage source should exist on systems in the event that a different voltage is required. see section 2.4 and table 2 for more information. 3. the voltage specification requirements are measured across v cc_ sense and v ss _ sense pins at the socket with a 100mhz bandwidth oscilloscope, 1.5 pf maximum probe capacitance, and 1 m ? minimum impedance. the maximum length of ground wire on the probe should be less than 5 mm. ensure external noise from the system is not coupled in the scope probe. 4. the processor should not be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_ mid + 0.055*(1 - i cc /i cc_ max ) [v]. moreover, v cc should never exceed v cc_max (vid). failure to adhere to this specification can shorten the processor lifetime. 5. maximum current is defined at v cc_mid . 6. the current specified is also for autohalt state. 7. the maximum instantaneous current the processor will draw while the thermal control circuit is active as indicated by the assertion of prochot# is the same as the maximum i cc for the processor. 8. i cc stop-grant, i cc sleep, and i cc deep sleep are specified at v cc_max. 9. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. 10.these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100?. notes: . 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. crossing voltage is defined as absolute voltage where rising edge of bclk0 is equal to the falling edge of bclk1. 3. the v l and v h used to calculate v cross are the actual v l and v h seen by the processor. 4. overshoot is defined as the absolute value of the maximum voltage allowed above the v h level. 5. undershoot is defined as the absolute value of the maximum voltage allowed below the v ss level. 6. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. 7. threshold region is defined as a region centered about the crossing voltage in which the differential receiver switches. it includes input threshold hysteresis. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. v il is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. table 6. system bus differential bclk specifications symbol parameter min typ max unit figure notes 1 v l input low voltage 0 v 5 v h input high voltage 0.660 0.710 0.850 v 5 v cross crossing voltage 0.45*(v h -v l )0.5*(v h -v l ) 0.55*(v h -v l )v 5 2, 3 v ov overshoot n/a n/a 0.3 v 5 4 v us undershoot n/a n/a 0.3 v 5 5 v rbm ringback margin 0.200 v 5 6 v th threshold region v cross -0.100 v cross +0.100 v 5 7 table 7. agtl+ signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage -0.150 gtlref - 100mv v 2, 6 v ih input high voltage gtlref + 100mv v cc v3, 4, 6 v oh output high voltage gtlref + 100mv v cc v4, 6 i ol output low current v cc / (0.5*rtt_min + r on_min ) ma 6 i li input leakage current 100 a i lo output leakage current 100 a r on buffer on resistance 5 11 ? 5
intel ? pentium ? 4 processor in the 423-pin package 21 3. v ih is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. v oh may experience excursions above v cc . however, input signal drivers must comply with the signal quality specifications in chapter 3.0. 5. refer to processor i/o buffer models for i/v characteristics. 6. the v cc referred to in these specifications is the instantaneous v cc . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. parameter will be measured at 9ma (for use with system inputs). 3. all outputs are open-drain. 4. v ih and v oh may experience excursions above v cc . however, input signal drivers must comply with the signal quality specifications in chapter 3.0. 5. the v cc referred to in these specifications is the instantaneous v cc . 6. these specifications apply to the asynchronous gtl+ signal group. 7. these specifications apply to the tap signal group. 2.11 agtl+ system bus specifications routing topology recommendations may be found in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide. termination resistors are not required for most agtl+ signals, as these are integrated into the processor silicon. valid high and low levels are determined by the input buffers which compare a signal?s voltage with a reference voltage called gtlref (known as v ref in previous documentation). table 9 lists the gtlref specifications. the agtl+ reference voltage (gtlref) should be generated on the system board using high precision voltage divider circuits. it is important that the system board impedance is held to the specified tolerance, and that the intrinsic trace capacitance for the agtl+ signal group traces is known and well-controlled. for more details on platform design see the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. table 8. asynchronous gtl+ and tap signal group dc specifications symbol parameter min max unit notes 1 v il input low voltage -0.150 gtlref - 100mv v 5 v il input low voltage -0.150 v cc /2 - 0.30 v ih input high voltage gtlref + 100mv v cc v4, 5 v ih input high voltage v cc /2 + 0.30 v cc v oh output high voltage v cc v3, 4, 5 i ol output low current 56 ma 6 i li input leakage current 100 a i lo output leakage current 100 a table 9. agtl+ bus voltage definitions symbol parameter min typ max units notes 1 gtlref bus reference voltage -2% 2/3 v cc +2% v 2, 3, 6 r tt termination resistance 36 41 46 ? 4 comp[1:0] comp resistance 42.77 43.2 45.45 ? 5, 7
intel ? pentium ? 4 processor in the 423-pin package 22 2. the tolerances for this specification have been stated generically to enable the system designer to calculate the minimum and maximum values across the range of v cc . 3. gtlref should be generated from v cc by a voltage divider of 1% resistors or 1% matched resistors. refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for implementation details. 4. r tt is the on-die termination resistance measured at v ol of the agtl+ output driver. refer to processor i/o buffer models for i/v characteristics. 5. comp resistance must be provided on the system board with 1% resistors. see the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for implementation details. 6. the v cc referred to in these specifications is the instantaneous v cc . 7. a comp resistance of 43.2 +/- 1% is the preferred value. 2.12 system bus ac specifications the processor system bus timings specified in this section are defined at the processor core silicon and are thus not measurable at the processor pins . see chapter 5.0 for the pentium 4 processor pin signal definitions. table 10 through table 15 list the ac specifications associated with the processor system bus. all agtl+ timings are referenced to gtlref for both ?0? and ?1? logic levels unless otherwise specified. the timings specified in this section should be used in conjunction with the i/o buffer models provided by intel. these i/o buffer models, which include package information, are available for the pentium 4 processor in ibis format. agtl+ layout guidelines are also available in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guidelines . care should be taken to read all notes associated with a particular timing parameter. notes: 1. unless otherwise noted, all specifications in this table apply to all processor core frequencies. 2. the period specified here is the average period. a given period may vary from this specification as governed by the period stability specification (t2). 3. for the clock jitter specification, refer to the ck00 clock synthesizer/driver design guidelines . 4. in this context, period stability is defined as the worst case timing difference between successive crossover voltages. in other words, the largest absolute difference between adjacent clock periods must be less than the period stability. 5. slew rate is measured between the 35% and 65% points of the clock swing (v l to v h ). table 10. system bus differential clock specifications t# parameter min nom max unit figure notes 1 system bus frequency 100 mhz t1: bclk[1:0] period 10.0 10.2 ns 5 2 t2: bclk[1:0] period stability 200 ps 3, 4 t3: bclk[1:0] high time 3.94 5 6.12 ns 5 t4: bclk[1:0] low time 3.94 5 6.12 ns 5 t5: bclk[1:0] rise time 175 700 ps 5 5 t6: bclk[1:0] fall time 175 700 ps 5 5
intel ? pentium ? 4 processor in the 423-pin package 23 . notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. not 100% tested. specified by design characterization. 3. all common clock ac timings for agtl+ signals are referenced to the crossing voltage (v cross ) of the bclk[1:0] at rising edge of bclk0. all common clock agtl+ signal timings are referenced at gtlref at the processor core. 4. valid delay timings for these signals are specified into the test circuit described in figure 3 and with gtlref at 2/3 v cc 2%. 5. specification is for a minimum swing defined between agtl+ v il_max to v ih_min . this assumes an edge rate of 0.4 v/ ns to 4.0v/ns. 6. reset# can be asserted asynchronously, but must be deasserted synchronously. 7. this should be measured after v cc and bclk[1:0] become stable. 8. maximum specification applies only while pwrgood is asserted. . note: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes. 2. not 100% tested. specified by design characterization. table 11. system bus common clock ac specifications t# parameter min max unit figure notes 1,2,3 t10: common clock output valid delay 0.20 1.45 ns 6 4 t11: common clock input setup time 0.65 ns 6 5 t12: common clock input hold time 0.40 ns 6 5 t13: reset# pulse width 1.00 10.00 ms 7 6, 7, 8 table 12. system bus source synch ac specifications agtl+ signal group t# parameter min typ max unit figure notes 1,2,3,4 t20: source synchronous data output valid delay (first data/address only) 0.20 1.30 ns 8, 9 5 t21: t vbd : source synchronous data output valid before strobe 0.85 ns 9 5, 8 t22: t vad : source synchronous data output valid after strobe 0.85 ns 9 5, 8 t23: t vba : source synchronous address output valid before strobe 1.88 ns 8 5, 8 t24: t vaa : source synchronous address output valid after strobe 1.88 ns 8 5, 9 t25: t suss : source synchronous input setup time to strobe 0.21 ns 8, 9 6 t26: t hss : source synchronous input hold time to strobe 0.21 ns 8, 9 6 t27: t succ : source synchronous input setup time to bclk[1:0] 0.65 ns 8, 9 7 t28: t fass : first address strobe to second address strobe 1/2 bclk 8 10 t29: t fdss : first data strobe to subsequent strobes n/4 bclk 9 11, 12 t30: data strobe ?n? (dstbn#) output valid delay 8.80 10.20 ns 9 13 t31: address strobe output valid delay 2.27 4.23 ns 8
intel ? pentium ? 4 processor in the 423-pin package 24 3. all source synchronous ac timings are referenced to their associated strobe at gtlref. source synchronous data signals are referenced to the falling edge of their associated data strobe. source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. all source synchronous agtl+ signal timings are referenced at gtlref at the processor core. 4. unless otherwise noted these specifications apply to both data and address timings. 5. valid delay timings for these signals are specified into the test circuit described in figure 3 and with gtlref at 2/3 v cc 2%. 6. specification is for a minimum swing defined between agtl+ v il_max to v ih_min . this assumes an edge rate of 0.3 v/ns to 4.0v/ns. 7. all source synchronous signals must meet the specified setup time to bclk as well as the setup time to each respective strobe. 8. this specification represents the minimum time the data or address will be valid before its strobe. refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for more information on the definitions and use of these specifications. 9. this specification represents the minimum time the data or address will be valid after its strobe. refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for more information on the definitions and use of these specifications. 10.the rising edge of adstb# must come approximately 1/2 bclk period (5 ns) after the falling edge of adstb#. 11.for this timing parameter, n = 1, 2, and 3 for the second, third, and last data strobes respectively. 12.the second data strobe (falling edge of dstbn#) must come approximately 1/4 bclk period (2.5 ns) after the first falling edge of dstbp#. the third data strobe (falling edge of dstbp#) must come approximately 2/4 bclk period (5 ns) after the first falling edge of dstbp#. the last data strobe (falling edge of dstbn#) must come approximately 3/4 bclk period (7.5 ns) after the first falling edge of dstbp#. 13.this specification applies only to dstbn[3:0]# and is measured to the second falling edge of the strobe. notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. all ac timings for the asynch gtl+ signals are referenced to the bclk0 rising edge at crossing voltage. all asynch gtl+ signal timings are referenced at gtlref. 3. these signals may be driven asynchronously. 4. refer to the pwrgood definition for more details regarding the behavior of this signal. 5. length of assertion for prochot# does not equal internal clock modulation time. time is allocated after the assertion and before the deassertion of prochot# for the processor to complete current instruction execution. 6. see section section 7.2 for additional timing requirements for entering and leaving the low power states. notes: 1. before the deassertion of reset#. 2. after clock that deasserts reset#. 3. after the assertion of reset#. table 13. asynchronous gtl+ signals ac specifications t# parameter min max unit figure notes 1,2,3,6 t35: asynch gtl+ input pulse width, except pwrgood 2bclks t36: pwrgood to reset# de-assertion time 110ms10 t37: pwrgood inactive pulse width 10 bclks 10 4 t38: prochot# pulse width 500 us 11 5 table 14. system bus ac specifications (reset conditions) t# parameter min max unit figure notes t45: reset configuration signals (a[31:3]#, br0#, init#, smi#) setup time 4bclks71 t46: reset configuration signals (a[31:3]#, br0#, init#, smi#) hold time 220bclks72
intel ? pentium ? 4 processor in the 423-pin package 25 notes: 1. unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. not 100% tested. specified by design characterization. 3. all ac timings for the tap signals are referenced to the tck signal at gtlref at the processor pins. all tap signal timings (tms, tdi, etc) are referenced at gtlref at the processor pins. 4. rise and fall times are measured from the 20% to 80% points of the signal swing. 5. referenced to the falling edge of tck. 6. referenced to the rising edge of fbo (tck) at the debug port connector. 7. trst# is synchronized to tck and is asserted for 5 tck periods while tms is asserted. 8. specification for a minimum swing defined between tap v il_max to v ih_min . this assumes a minimum edge rate of 0.5v/ns. 2.13 processor ac timing waveforms the following figures are used in conjunction with the ac timing tables, table 10 through table 15. note: for figure 4 through figure 11, the following apply: 1. all common clock ac timings for agtl+ signals are referenced to the crossing voltage (v cross ) of the bclk[1:0] at rising edge of bclk0. all common clock agtl+ signal timings are referenced at gtlref at the processor core. 2. all source synchronous ac timings for agtl+ signals are referenced to their associated strobe (address or data) at gtlref. source synchronous data signals are referenced to the falling edge of their associated data strobe. source synchronous address signals are referenced to the rising and falling edge of their associated address strobe. all source synchronous agtl+ signal timings are referenced at gtlref at the processor silicon. 3. all ac timings for agtl+ strobe signals are referenced to bclk[1:0] at v cross . all agtl+ strobe signal timings are referenced at gtlref at the processor silicon. 4. all ac timings for the tap signals are referenced to the tck signal at gtlref at the processor pins. all tap signal timings (tms, tdi, etc) are referenced at the processor pins. the circuit used to test the ac specifications is shown in figure 3. table 15. tap signals ac specifications parameter min max unit figure notes 1,2,3 t55: tck period 60.0 1000 ns 4 t56: tck rise time 9.5 ns 4 4 t57: tck fall time 9.5 ns 4 4 t58: tms rise time 8.5 ns 4 4 t59: tms fall time 8.5 ns 4 4 t60: tms clock to output delay -5 -2 ns 5 t61: tdi setup time 0 ns 5, 8 t62: tdi hold time 3 ns 5, 8 t63: tdo clock to output delay 0.5 3.5 ns 6 t64: trst# assert time 2 tck 11 7
intel ? pentium ? 4 processor in the 423-pin package 26 figure 3. ac test circuit figure 4. tck clock waveform 600 mils, 42 ohms, 169 ps/in 2.4nh 1.2pf v cc v cc rload rload = 50 ohms ac timings test measurements made here. tr = t56, t58 (rise time) tf = t57, t59 (fall time) tp = t55 (tck period) 80% 50% 20%
intel ? pentium ? 4 processor in the 423-pin package 27 . figure 5. differential clock waveform figure 6. system bus common clock valid delay timings crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage tph tpl tp tp = t1 (bclk[1:0] period) t2 = bclk[1:0] period stability (not shown) tph =t3 (bclk[1:0] pulse high time) tpl = t4 (bclk[1:0] pulse low time) t5 = bclk[1:0] rise time through the threshold region (not shown) t6 = bclk[1:0] fall time through the threshold region (not shown) bclk0 bclk1 common clock signal (@ driver) common clock signal (@ receiver) t0 t1 t2 t q t r valid valid valid t p t p = t10: t co (data valid output delay) t q = t11: t su (common clock setup) t r = t12: t h (common clock hold time)
intel ? pentium ? 4 processor in the 423-pin package 28 figure 7. system bus reset and configuration timings figure 8. source synchronous 2x (address) timings bclk[1:0]1 t y safe valid t z valid t v t w t x t u t t bclk reset# configuration (a20m#, ignne#, lint[1:0]) configuration (a[14:5]#, br0#, flush#, int#) t t = t9 (gtl+ input hold time) t u = t8 (gtl+ input setup time) t v = t10 (reset# pulse width) t w = t16 (reset configuration signals (a[14:5]#, br0#, flush#, init#) setup time) t x = t17 (reset configuration signals (a[14:5]#, br0#, flush#, init#) hold time) t20 (reset configuration signals (a20m#, ignne#, lint[1:0]) hold time) ty = t19 (reset configuration signals (a20m#, ignne#, lint[1:0]) delay time) tz = t18 (reset configuration signals (a20m# ignne# lint[1:0]) setup time) t v = t13 (reset# pulse width) t w = t45 (reset configuration signals setup time) t x = t46 (reset configuration signals hold time) (a[31:3], br0#, init#, smi#) t j bclk0 bclk1 adstb# (@ driver) a# (@ driver) a# (@ receiver) adstb# (@ receiver) t1 t2 2.5 ns 5.0 ns 7.5 ns t h t h t j t n t k t m valid valid valid valid t h = t23: source sync. address output valid before address strobe t j = t24: source sync. address output valid after address strobe t k = t27: source sync. input setup to bclk t m = t26: source sync. input hold time t n = t25: source sync. input setup time t p = t28: first address strobe to second address strobe t s = t20: source sync. output valid delay t r = t31: address strobe output valid delay t p t r t s
intel ? pentium ? 4 processor in the 423-pin package 29 figure 9. source synchronous 4x timings figure 10. power-on reset and configuration timings bclk0 bclk1 dstbp# (@ driver) dstbn# (@ driver) d# (@ driver) d# (@ receiver) dstbn# (@ receiver) dstbp# (@ receiver) t0 t1 t2 2.5 ns 5.0 ns 7.5 ns t a t a t b t c t e t e t g t g t d t a = t21: source sync. data output valid delay before data strobe t b = t22: source sync. data output valid delay after data strobe t c = t27: source sync. setup time to bclk t d = t30: source sync. data strobe 'n' (dstbn#) output valid delay t e = t25: source sync. input setup time t g = t26: source sync. input hold time t h = t29: first data strobe to subsequent strobes t j = t20: source sync. data output valid delay t j t h valid ratio t a bclk v cc , core, v ref configuration (a20m#, ignne#, lint[1:0]) t a = t15 (pwrgood inactive pulse width) t b = t10 (reset# pulse width) t c = t20 (reset configuration signals (a20m#, ignne#, lint[1:0]) hold time) t b t c pwrgood reset# vcc ta = t37 (pwrgood inactive pulse width) tb = t36 (pwrgood to reset# de-assertion time) tc = t46 (reset configuration signals hold time)
intel ? pentium ? 4 processor in the 423-pin package 30 figure 11. test reset timings trst# pcb - 773 1.25v t q t q t37 (trst# pulse width) = tq = t64, t38 (trst# pulse width, prochot# pulse width) gtlref
intel ? pentium ? 4 processor in the 423-pin package 31 3.0 system bus signal quality specifications source synchronous data transfer requires the clean reception of data signals and their associated strobes. ringing below receiver thresholds, non-monotonic signal edges, and excessive voltage swing will adversely affect system timings. ringback and signal non-monotonicity cannot be tolerated since these phenomena may inadvertently advance receiver state machines or cause incorrect latching of data. excessive signal swings (overshoot and undershoot) are detrimental to silicon gate oxide integrity, and can cause device failure if absolute voltage limits are exceeded. additionally, overshoot and undershoot can cause timing degradation due to the build up of inter- symbol interference (isi) effects. for these reasons, it is crucial that the designer work towards a solution that provides acceptable signal quality across all systematic variations encountered in volume manufacturing. this section documents signal quality metrics used to derive topology and routing guidelines through simulation, and all specifications are at the processor silicon and cannot be measured at the processor pins. the intel ? pentium ? 4 processor overshoot checker tool is to be utilized to determine pass/fail signal quality conditions found through simulation analysis with the intel ? pentium ? 4 processor i/o buffer models (ibis format). this tool takes into account the specifications contained in this section. specifications for signal quality are for measurements at the processor core only and are only observable through simulation. the same is true for all system bus ac timing specifications in section 2.12. therefore, proper simulation of the pentium 4 processor system bus is the only means to verify proper timing and signal quality metrics, and intel highly recommends simulation during system design and measurement during system analysis. 3.1 bclk signal quality specifications and measurement guidelines table 16 describes the signal quality specifications for the processor system bus clock (bclk) signals. figure 12 describes the signal quality waveform for the system bus clock at the processor silicon. specifications are measured at the processor silicon, not the 423-pin socket pins. notes: 1. unless otherwise noted, all specifications in this table apply to all pentium 4 processor frequencies. 2. the rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute voltage the bclk signal can dip back to after passing the v ih (rising) or v il (falling) voltage limits. this specification is an absolute value. table 16. bclk signal quality specifications parameter min max unit figure notes 1 bclk[1:0] overshoot n/a 0.30 v 12 bclk[1:0] undershoot n/a 0.30 v 12 bclk[1:0] ringback margin 0.20 n/a v 12 bclk[1:0] threshold region n/a 0.10 v 12 2
intel ? pentium ? 4 processor in the 423-pin package 32 3.2 system bus signal quality specifications and measurement guidelines many scenarios have been simulated to generate a set of agtl+ layout guidelines which are available in the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide . table 17 provides the signal quality specifications for all processor signals for use in simulating signal quality at the processor silicon. signal quality measurements cannot be made at the processor pins. the pentium 4 processor maximum allowable overshoot and undershoot specifications for a given duration of time are detailed in table 18 through table 21. figure 13 shows the system bus ringback tolerance for low-to-high transitions and figure 14 shows ringback tolerance for high-to- low transitions. notes: 1. all signal integrity specifications are measured at the processor silicon. 2. unless otherwise noted, all specifications in this table apply to all pentium 4 processor frequencies. 3. specifications are for the edge rate of 0.3 - 4.0v/ns. 4. all values specified by design characterization. 5. please see section 3.3 for maximum allowable overshoot. 6. ringback between gtlref + 100 mv and gtlref - 100 mv is not supported. 7. intel recommends simulations not exceed a ringback value of gtlref +/- 200 mv to allow margin for other sources of system noise. figure 12. bclk[1:0] signal integrity waveform crossing voltage threshold region vh vl overshoot undershoot ringback margin rising edge ringback falling edge ringback, bclk0 bclk1 crossing voltage table 17. ringback specifications for agtl+, asynchronous gtl+, and tap signal groups signal group transition maximum ringback (with input diodes present) unit figure notes all signals 0 1 gtlref + 0.100 v 13 1,2,3,4,5,6,7 all signals 1 0 gtlref - 0.100 v 14 1,2,3,4,5,6,7
intel ? pentium ? 4 processor in the 423-pin package 33 3.3 system bus signal quality specifications and measurement guidelines 3.3.1 overshoot/undershoot guidelines overshoot (or undershoot) is the absolute value of the maximum voltage above or below v ss . the overshoot/undershoot specifications limit transitions beyond v cc or v ss due to the fast signal edge rates. the processor can be damaged by repeated overshoot or undershoot events on any input, output, or i/o buffer if the charge is large enough (i.e., if the over/undershoot is great enough). determining the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse direction, and the activity factor (af) of the incident waveform. permanent damage to the processor is the likely result of excessive overshoot/undershoot. figure 13. low-to-high system bus receiver ringback tolerance gtlref v cc noise margin +100 mv -100 mv v ss figure 14. high-to-low system bus receiver ringback tolerance gtlref v cc noise margin +100 mv -100 mv v ss
intel ? pentium ? 4 processor in the 423-pin package 34 when performing simulations to determine impact of overshoot and undershoot, esd diodes must be properly modelled. esd protection diodes do not act as voltage clamps and will not provide overshoot or undershoot protection. esd diodes modelled within intel i/o buffer models do not clamp undershoot or overshoot and will yield correct simulation results. if other i/o buffer models are being used to characterize the pentium 4 processor system bus, care must be taken to ensure that esd models do not clamp extreme voltage levels. intel i/o buffer models also contain i/o capacitance characterization. therefore, removing the esd diodes from an i/o buffer model will impact results and may yield excessive overshoot/undershoot. 3.3.2 overshoot/undershoot magnitude magnitude describes the maximum potential difference between a signal and its voltage reference level. for the pentium 4 processor both overshoot and undershoot are referenced to v ss . it is important to note that overshoot and undershoot conditions are separate and their impacts must be determined independently. overshoot/undershoot magnitude levels must observe the absolute maximum specifications listed in table 18 through table 21. these specifications must not be violated at any time regardless of bus activity or system state. within these specifications are threshold levels that define different allowed pulse durations. provided that the magnitude of the overshoot/undershoot is within the absolute maximum specifications (2.3v for overshoot and -0.65v for undershoot), the pulse magnitude, duration and activity factor must all be used to determine if the overshoot/undershoot pulse is within specifications. 3.3.3 overshoot/undershoot pulse duration pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/ undershoot reference voltage. the total time could encompass several oscillations above the reference voltage. multiple overshoot/undershoot pulses within a single overshoot/undershoot event may need to be measured to determine the total pulse duration. note 1: oscillations below the reference voltage cannot be subtracted from the total overshoot/ undershoot pulse duration. 3.3.4 activity factor activity factor (af) describes the frequency of overshoot (or undershoot) occurrence relative to a clock. since the highest frequency of assertion of any common clock signal is every other clock, an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every other clock cycle. thus, an af = 0.01 indicates that the specific overshoot (or undershoot) waveform occurs one time in every 200 clock cycles. for source synchronous signals (address, data, and associated strobes), the activity factor is in reference to the strobe edge, since the highest frequency of assertion of any source synchronous signal is every active edge of its associated strobe. an af = 1 indicates that the specific overshoot (or undershoot) waveform occurs every strobe cycle. the specifications provided in table 18 through table 21 show the maximum pulse duration allowed for a given overshoot/undershoot magnitude at a specific activity factor. each table entry is independent of all others, meaning that the pulse duration reflects the existence of overshoot/ undershoot events of that magnitude only. a platform with an overshoot/undershoot that just
intel ? pentium ? 4 processor in the 423-pin package 35 meets the pulse duration for a specific magnitude where the af < 1, means that there can be no other overshoot/undershoot events, even of lesser magnitude (note that if af = 1, then the event occurs at all times and no other events can occur). note 1: activity factor for common clock agtl+ signals is referenced to bclk[1:0] frequency. note 2: activity factor for source synchronous (2x) signals is referenced to adstb[1:0]#. note 3: activity factor for source synchronous (4x) signals is referenced to dstbp[3:0]# and dstbn[3:0]#. 3.3.5 reading overshoot/undershoot specification tables the overshoot/undershoot specification for the pentium 4 processor is not a simple single value. instead, many factors are needed to determine the over/undershoot specification. in addition to the magnitude of the overshoot, the following parameters must also be known: the width of the overshoot and the activity factor (af). to determine the allowed overshoot for a particular overshoot event, the following must be done: 1. determine the signal group that the particular signal falls into. for agtl+ signals operating in the 4x source synchronous domain, use table 18. for agtl+ signals operating in the 2x source synchronous domain, use table 19. if the signal is an agtl+ signal operating in the common clock domain, use table 20. finally, all other signals reside in the 33mhz domain (asynchronous gtl+, tap, etc.) and are referenced in table 21. 2. determine the magnitude of the overshoot or the undershoot (relative to v ss ). 3. determine the activity factor (how often does this overshoot occur?). 4. next, from the appropriate specification table, determine the maximum pulse duration (in nanoseconds) allowed. 5. compare the specified maximum pulse duration to the signal being measured. if the pulse duration measured is less than the pulse duration shown in the table, then the signal meets the specifications. undershoot events must be analyzed separately from overshoot events as they are mutually exclusive. 3.3.6 determining if a system meets the over/undershoot specifications the overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single overshoot/undershoot event. however most systems will have multiple overshoot and/or undershoot events that each have their own set of parameters (duration, af and magnitude). while each overshoot on its own may meet the overshoot specification, when you add the total impact of all overshoot events, the system may fail. a guideline to ensure a system passes the overshoot and undershoot specifications is shown below. results from simulation may also be evaluated by utilizing the intel ? pentium ? 4 processor overshoot checker tool through the use of time-voltage data files. 1. ensure no signal ever exceeds v cc or -0.25v or 2. if only one overshoot/undershoot event occurs, ensure it meets the over/undershoot specifications in the following tables or 3. if multiple overshoots and/or multiple undershoots occur, measure the worst case pulse duration for each magnitude and compare the results against the af = 1 specifications. if all of
intel ? pentium ? 4 processor in the 423-pin package 36 these worst case overshoot or undershoot events meet the specifications (measured time < specifications) in the table (where af=1), then the system passes. the following notes apply to table 18 through table 21. notes: 1. absolute maximum overshoot magnitude of 2.3v must never be exceeded. 2. absolute maximum overshoot is measured relative to v ss , pulse duration of overshoot is measured relative to v cc . 3. absolute maximum undershoot and pulse duration of undershoot is measured relative to v ss . 4. ringback below v cc can not be subtracted from overshoots/undershoots. 5. lesser undershoot does not allocate longer or larger overshoot. 6. oem's are strongly encouraged to follow intel provided layout guidelines. 7. all values specified by design characterization.
intel ? pentium ? 4 processor in the 423-pin package 37 notes: 1. these specifications are specified at the processor silicon. 2. assumes a bclk period of 10 ns. 3. af is referenced to associated source synchronous strobes. 4. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. notes: 1. these specifications are specified at the processor silicon. 2. assumes a bclk period of 10 ns. table 18. source synchronous (400mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.65 0.07 0.65 5.00 2.25 -0.60 0.12 1.22 5.00 2.20 -0.55 0.23 2.25 5.00 2.15 -0.50 0.42 4.15 5.00 2.10 -0.45 0.74 5.00 5.00 2.05 -0.40 1.38 5.00 5.00 2.00 -0.35 2.50 5.00 5.00 1.95 -0.30 4.50 5.00 5.00 1.90 -0.25 5.00 5.00 5.00 1.85 -0.20 5.00 5.00 5.00 1.80 -0.15 5.00 5.00 5.00 1.75 -0.10 5.00 5.00 5.00 table 19. source synchronous (200mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.65 0.13 1.30 10.0 2.25 -0.60 0.24 2.44 10.0 2.20 -0.55 0.45 4.50 10.0 2.15 -0.50 0.83 8.30 10.0 2.10 -0.45 1.48 10.0 10.0 2.05 -0.40 2.76 10.0 10.0 2.00 -0.35 5.00 10.0 10.0 1.95 -0.30 5.00 10.0 10.0 1.90 -0.25 10.0 10.0 10.0 1.85 -0.20 10.0 10.0 10.0 1.80 -0.15 10.0 10.0 10.0 1.75 -0.10 10.0 10.0 10.0
intel ? pentium ? 4 processor in the 423-pin package 38 3. af is referenced to associated source synchronous strobes. 4. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. notes: 1. these specifications are specified at the processor silicon. 2. bclk period is 10 ns. 3. af is referenced to bclk[1:0]. 4. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. notes: 1. these specifications are specified at the processor silicon. table 20. common clock (100mhz) agtl+ signal group overshoot/undershoot tolerance (1.7v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.65 0.26 2.60 20.0 2.25 -0.60 0.49 4.88 20.0 2.20 -0.55 0.90 9.00 20.0 2.15 -0.50 1.66 16.60 20.0 2.10 -0.45 2.96 20.0 20.0 2.05 -0.40 5.52 20.0 20.0 2.00 -0.35 10.0 20.0 20.0 1.95 -0.30 18.0 20.0 20.0 1.90 -0.25 20.0 20.0 20.0 1.85 -0.20 20.0 20.0 20.0 1.80 -0.15 20.0 20.0 20.0 1.75 -0.10 20.0 20.0 20.0 table 21. asynchronous gtl+ and tap signal groups overshoot/undershoot tolerance (1.7v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3 2.30 -0.65 0.78 7.80 60.0 2.25 -0.60 1.46 14.64 60.0 2.20 -0.55 2.70 27.0 60.0 2.15 -0.50 4.98 49.8 60.0 2.10 -0.45 8.88 60.0 60.0 2.05 -0.40 16.56 60.0 60.0 2.00 -0.35 30.0 60.0 60.0 1.95 -0.30 54.0 60.0 60.0 1.90 -0.25 60.0 60.0 60.0 1.85 -0.20 60.0 60.0 60.0 1.80 -0.15 60.0 60.0 60.0 1.75 -0.10 60.0 60.0 60.0
intel ? pentium ? 4 processor in the 423-pin package 39 2. this table assumes a 33mhz time domain. 3. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. notes: 1. these specifications are specified at the processor pad. 2. assumes a bclk period of 10 ns. 3. af is referenced to associated source synchronous strobes. 4. these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100?. notes: 1. these specifications are specified at the processor pad. 2. assumes a bclk period of 10 ns. table 22. source synchronous (400mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.585 0.06 0.63 5.00 2.25 -0.535 0.11 1.10 5.00 2.20 -0.485 0.22 2.20 5.00 2.15 -0.435 0.41 4.10 5.00 2.10 -0.385 0.75 5.00 5.00 2.05 -0.335 1.35 5.00 5.00 2.00 -0.285 2.50 5.00 5.00 1.95 -0.235 4.70 5.00 5.00 1.90 -0.185 5.00 5.00 5.00 1.85 -0.135 5.00 5.00 5.00 1.80 -0.085 5.00 5.00 5.00 table 23. source synchronous (200mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.585 0.12 1.20 10.0 2.25 -0.535 0.22 2.20 10.0 2.20 -0.485 0.44 4.40 10.0 2.15 -0.435 0.82 8.20 10.0 2.10 -0.385 1.50 10.0 10.0 2.05 -0.335 2.70 10.0 10.0 2.00 -0.285 5.00 10.0 10.0 1.95 -0.235 9.40 10.0 10.0 1.90 -0.185 10.0 10.0 10.0 1.85 -0.135 10.0 10.0 10.0 1.80 -0.085 10.0 10.0 10.0
intel ? pentium ? 4 processor in the 423-pin package 40 3. af is referenced to associated source synchronous strobes. 4. these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100? notes: 1. these specifications are specified at the processor pad. 2. bclk period is 10 ns. 3. af is referenced to associated source synchronous strobes. 4. these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100?.. notes: 1. these specifications are specified at the processor pad. 2. this table assumes a 33mhz time domain. table 24. common clock (100mhz) agtl+ signal group overshoot/undershoot tolerance (1.75v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3,4 2.30 -0.585 0.24 2.40 20.0 2.25 -0.535 0.44 4.40 20.0 2.20 -0.485 0.88 8.80 20.0 2.15 -0.435 1.64 16.4 20.0 2.10 -0.385 3.00 20.0 20.0 2.05 -0.335 5.40 20.0 20.0 2.00 -0.285 10.0 20.0 20.0 1.95 -0.235 18.8 20.0 20.0 1.90 -0.185 20.0 20.0 20.0 1.85 -0.135 20.0 20.0 20.0 1.80 -0.085 20.0 20.0 20.0 table 25. asynchronous gtl+ and tap signal groups overshoot/undershoot tolerance (1.75v processors) absolute maximum overshoot (v) absolute maximum undershoot (v) pulse duration (ns) af = 1 pulse duration (ns) af = 0.1 pulse duration (ns) af = 0.01 notes 1,2,3 2.30 -0.585 0.72 7.20 60.0 2.25 -0.535 1.32 13.2 60.0 2.20 -0.485 2.64 26.4 60.0 2.15 -0.435 4.92 49.2 60.0 2.10 -0.385 9.00 60.0 60.0 2.05 -0.335 16.2 60.0 60.0 2.00 -0.285 30.0 60.0 60.0 1.95 -0.235 56.4 60.0 60.0 1.90 -0.185 60.0 60.0 60.0 1.85 -0.135 60.0 60.0 60.0 1.80 -0.085 60.0 60.0 60.0
intel ? pentium ? 4 processor in the 423-pin package 41 3. these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100?. figure 15. maximum acceptable overshoot/undershoot waveform 000588 v cc maximum a bsolute overshoot maximum a bsolute undershoot time-de p endent overshoot time-de p endent undershoot gtlref v ol v min v max v ss
intel ? pentium ? 4 processor in the 423-pin package 42
intel ? pentium ? 4 processor in the 423-pin package 43 4.0 package mechanical specifications the intel ? pentium ? 4 processor in the 423-pin package uses pin grid array (pga) package technology. components of the package include an integrated heat spreader, processor silicon, silicon mounting substrate or organic land grid array (olga), and an interposer which is the pincarrier. mechanical specifications for the processor are given in this section. see section 1.1 for a terminology listing. the processor socket which accepts the pentium 4 processor in the 423-pin package is referred to as a 423-pin socket. see the 423-pin socket (pga423) design guidelines for further details on the 423-pin socket. note: the drawing below is not to scale and is for reference only. the socket and system board are supplied as a reference only. figure 16. exploded view of processor components on a system board capacitors s y stem board interposer socket olga thermal interface die ihs
intel ? pentium ? 4 processor in the 423-pin package 44 figure 17. processor package pin a1
intel ? pentium ? 4 processor in the 423-pin package 45 notes: 1. all dimensions in inches unless otherwise noted. 2. nickel plated copper. 3. diameter figure 18 details the keep in specification for pin-side components. pentium 4 processors may contain pin side capacitors mounted to the processor olga package. the capacitors will be exposed within the opening of the interposer cavity. figure 20 details the flatness and tilt specifications for the ihs. tilt is measured with the reference datum set to the bottom of the processor interposer. table 26. description table for processor dimensions code letter min typ max notes 1 a 2.094 2.100 2.106 b 1.217 1.220 1.224 c 1.059 1.063 1.067 2 d 0.054 0.079 0.104 e 0.509 0.515 0.521 f 0.459 0.465 0.471 g 0.167 0.192 0.217 h 0.941 0.950 0.959 j 0.941 0.950 0.959 k 0.100 l 0.727 0.737 0.747 m 0.571 0.576 0.581 n 0.677 0.687 0.697 p 0.055 0.067 0.079 3 t 0.891 0.900 0.909 u 0.100 v 0.891 0.900 0.909 figure 18. processor cross-section and keep-in 0.050? ihs olga interposer .528? component keepin socket must allow clearance for pin shoulders and mate flush with this surface
intel ? pentium ? 4 processor in the 423-pin package 46 4.1 package load specifications table 27 provides dynamic and static load specifications for the pentium 4 processor in the 423-pin package ihs. these mechanical load limits should not be exceeded during heatsink assembly, mechanical stress testing, or standard drop and shipping conditions. the heatsink attach solutions figure 19. processor pin detail figure 20. ihs flatness specification 1. all dimensions in inches. 2. 8 microinches au over 80 microinches ni, min. 3. .010 diametric true position, pin to pin.
intel ? pentium ? 4 processor in the 423-pin package 47 must not induce continuous stress onto the processor with the exception of a uniform load to maintain the heat sink-to-processor thermal interface. it is not recommended to use any portion of the processor interposer as a mechanical reference or load bearing surface for thermal solutions. notes: note: this specification applies to a uniform load. 4. this is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and processor interface. 5. these parameters are based on design characterization and not tested. 6. dynamic load specifications are defined assuming a maximum duration of 11ms. 4.2 processor insertion specifications the pentium 4 processor in the 423-pin package can be inserted and removed 30 times from a 423- pin socket meeting the 423-pin socket design guidelines document. note that this specification is based on design characterization and is not tested. 4.3 processor mass specifications table 28 specifies the processor?s mass. this includes all components which make up the entire processor product. 4.4 processor materials the pentium 4 processor is assembled from several components. the basic material properties are described in table 29. table 27. package dynamic and static load specifications parameter max unit notes static 25 lbf 1, 2, 3 dynamic 100 lbf 1, 3, 4 table 28. processor mass processor mass (grams) pentium 4 processor, 31mm olga 23
intel ? pentium ? 4 processor in the 423-pin package 48 4.5 processor markings the following section details the processor top-side laser markings and is provided to aid in the identification of the pentium 4 processor. specific details regarding individual fields in the product markings will be provided in a future release of the emts. notes: 1. all characters will be in upper case. 4.6 processor pin-out coordinates figure 22 details the coordinates of the 423 processor pins as viewed from the bottom of the package. table 29. processor material properties component material notes integrated heat spreader nickel over copper interposer fr4 interposer pins gold over nickel figure 21. processor markings 1.5ghz/256/400/1.7v sl4sh malay 1234567 8 -1272 i m c ?00 int e l ? pentium ? bbb 1.5ghz/256/400/1.7v syyyy xxxxxx ffffffff-nnnn i m c ?00 int e l ? pentium ? bbb frequency/cache/bus/voltage s-spec/country of assy 2-d matrix mark fpo - serial #
intel ? pentium ? 4 processor in the 423-pin package 49 figure 22. processor pinout diagram - bottom view vid4 vid3 skto cc# a[32]# a[33]# a[27]# a[26]# a[20]# a[30]# a[22]# a[14]# a[13]# a[15]# vid1 vid2 vcc vss vcc vss vcc vss vcc vss vcc vss vcc vid0 vcc stpc lk# ierr# rsp# a[31]# bpm[4 ]# a[34]# a[21]# a[23]# a[29] # a[10]# a[12]# a[18]# vcc vss bpm[5 ]# init# mcer r# a[35]# ap[1]# br[3]# br[2]# br[1]# a[25]# a[16]# a[19]# vcc vss bpm[3 ]# vcc vss vcc vss vcc vss vcc vss vcc vss vss vcc vss bpm[0 ]# bpm[2 ]# bpm[1 ]# gtlr ef3 ap[0]# binit# a[28]# a[24]# comp [1] a[9]# vss vcc vss vcc vcc vss vcc vss vss vcc adst b[1]# vss adst b[0]# vss vcc vss vcc vss vcc vss vcc vss vss vcc vss vcc vss vcc vss vcc vss vcc vcc vss vcc vss vcc vss vss vcc vss vcc vss vcc vcc vss vcc vss vcc vss vss vcc vss vcc vss vcc vcc vss vcc vss vcc vss vss vcc vss vcc vcc vss vcc vss vcc vss vcc vss vss vcc vss vcc vss vcc vss vcc vcc vss vcc vss vcc vss vcc vss vss vcc vss vcc vss vcc vss vcc vcc vss vcc vss vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al 33 34 35 36 37 38 39 am an ap ar at au av aw vss_ sens e gtlr ef2 a20m# rs[2]# ther mtrip # vcc vss gtlr ef0 d[14]# vss d[1]# d[11]# vcc d[3]# d[9]# vss d[7]# vcc d[4]# d[12]# vss d[13]# vcc d[24]# d[17]# vss d[31]# vcc d[20]# vcc vss vcc vss vss vcc vss bclk[ 1]# vss vcc vss bclk[ 0]# vcc vss vcc vss vcc vss vcc vss vcc vss vcc vss vcc d[60]# d[57]# d[55]# d[53]# d[49]# d[45]# d[39]# d[33]# vss vcca d[59]# d[56]# d[54]# d[48]# d[50]# d[47]# d[34]# d[38]# vssa vcc vss vcc vss vcc vss vcc vss vcc vcc vss vcc vss d[51]# d[46]# d[44]# dp[2]# d[37]# d[32]# d[27]# vss d[23]# d[22]# vcc vcc vss d[25]# vss d[30]# d[16]# d[26]# d[36]# d[28]# dinv[ 1]# d[21]# vcc vss vcc dp[0]# dp[1]# d[19]# d[29]# vcc vss vss vcc vcc vss vss vcc vcc vss vss vcc gtlr ef1 d[63]# d[61]# d[41]# d[35]# d[43]# d[18]# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj ak al am an ap ar at au av aw bottom view
intel ? pentium ? 4 processor in the 423-pin package 50
intel ? pentium ? 4 processor in the 423-pin package 51 table 30. pin listing by pin name pin name pin number signal buffer type direction a3# f30 source synch input/output a4# c29 source synch input/output a5# d30 source synch input/output a6# c31 source synch input/output a7# f28 source synch input/output a8# d28 source synch input/output a9# f26 source synch input/output a10# c23 source synch input/output a11# a31 source synch input/output a12# c25 source synch input/output a13# a25 source synch input/output a14# a23 source synch input/output a15# a27 source synch input/output a16# d24 source synch input/output a17# a29 source synch input/output a18# c27 source synch input/output a19# d26 source synch input/output a20# a17 source synch input/output a21# c17 source synch input/output a22# a21 source synch input/output a23# c19 source synch input/output a24# f22 source synch input/output a25# d22 source synch input/output a26# a15 source synch input/output a27# a13 source synch input/output a28# f20 source synch input/output a29# c21 source synch input/output a30# a19 source synch input/output a31# c11 source synch input/output a32# a9 source synch input/output a33# a11 source synch input/output a34# c15 source synch input/output a35# d12 source synch input/output a20m# t38 asynch gtl+ input ads# f36 common clock input/output adstb0# g25 source synch input/output adstb1# g21 source synch input/output ap0# f16 common clock input/output ap1# d14 common clock input/output bclk0 ar7 bus clock input bclk1 ap8 bus clock input binit# f18 common clock input/output bnr# e35 common clock input/output bpm0# f8 common clock input/output bpm1# f12 common clock input/output bpm2# f10 common clock input/output bpm3# e7 common clock input/output bpm4# c13 common clock input/output bpm5# d6 common clock input/output bpri# l37 common clock input br0# b36 common clock input/output table 30. pin listing by pin name pin name pin number signal buffer type direction 5.0 pin listing and signal definitions 5.1 processor pin assignments section 5.1 contains the pinlist for the intel ? pentium ? 4 processor in the 423-pin package in table 30 and table 31. table 30 is a listing of all processor pins ordered alphabetically by pin name. table 31 is also a listing of all processor pins but ordered by pin number. 5.1.1 pin listing by pin name
intel ? pentium ? 4 processor in the 423-pin package 52 comp0 au27 power/other input/output comp1 f24 power/other input/output d0# y38 source synch input/output d1# ad36 source synch input/output d2# w37 source synch input/output d3# ae37 source synch input/output d4# ag39 source synch input/output d5# aa35 source synch input/output d6# v36 source synch input/output d7# af38 source synch input/output d8# w39 source synch input/output d9# ae39 source synch input/output d10# ab36 source synch input/output d11# ad38 source synch input/output d12# ah36 source synch input/output d13# aj37 source synch input/output d14# ac37 source synch input/output d15# aa39 source synch input/output d16# at36 source synch input/output d17# ak38 source synch input/output d18# ap34 source synch input/output d19# aw37 source synch input/output d20# am38 source synch input/output d21# au39 source synch input/output d22# ap36 source synch input/output d23# an39 source synch input/output d24# ak36 source synch input/output d25# ar37 source synch input/output d26# at38 source synch input/output d27# an35 source synch input/output d28# au35 source synch input/output d29# aw39 source synch input/output d30# at34 source synch input/output d31# al37 source synch input/output d32# aw31 source synch input/output d33# at32 source synch input/output d34# au29 source synch input/output d35# ap26 source synch input/output d36# au33 source synch input/output table 30. pin listing by pin name pin name pin number signal buffer type direction d37# aw29 source synch input/output d38# au31 source synch input/output d39# at30 source synch input/output d40# at28 source synch input/output d41# ap24 source synch input/output d42# au25 source synch input/output d43# ap28 source synch input/output d44# aw25 source synch input/output d45# at24 source synch input/output d46# aw23 source synch input/output d47# au23 source synch input/output d48# au19 source synch input/output d49# at20 source synch input/output d50# au21 source synch input/output d51# aw21 source synch input/output d52# aw19 source synch input/output d53# at18 source synch input/output d54# au17 source synch input/output d55# at16 source synch input/output d56# au15 source synch input/output d57# at14 source synch input/output d58# aw13 source synch input/output d59# au13 source synch input/output d60# at12 source synch input/output d61# ap14 source synch input/output d62# aw17 source synch input/output d63# ap12 source synch input/output dbi0# al39 source synch input/output dbi1# au37 source synch input/output dbi2# at22 source synch input/output dbi3# aw15 source synch input/output dbr# av2 asynch gtl+ output dbsy# b34 common clock input/output defer# j35 common clock input dp0# aw33 common clock input/output dp1# aw35 common clock input/output dp2# aw27 common clock input/output dp3# at26 common clock input/output drdy# g37 common clock input/output table 30. pin listing by pin name pin name pin number signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 53 dstbn0# ag35 source synch input/output dstbn1# ap32 source synch input/output dstbn2# ap22 source synch input/output dstbn3# ap18 source synch input/output dstbp0# aj35 source synch input/output dstbp1# ap30 source synch input/output dstbp2# ap20 source synch input/output dstbp3# ap16 source synch input/output ferr# p38 asynch gtl+ output gtlref ac35 power/other input gtlref ap10 power/other input gtlref f14 power/other input gtlref t36 power/other input hit# k36 common clock input/output hitm# d36 common clock input/output ierr# c7 common clock output ignne# m38 asynch gtl+ input init# d8 asynch gtl+ input itp_clk0 au1 tap input itp_clk1 aw1 tap input lint0 h36 asynch gtl+ input lint1 w35 asynch gtl+ input lock# a33 common clock input/output mcerr# d10 common clock input/output prochot# f38 asynch gtl+ output pwrgood aw9 asynch gtl+ input req0# c33 source synch input/output req1# d32 source synch input/output req2# f34 source synch input/output req3# d34 source synch input/output req4# f32 source synch input/output reserved at4 reset# aw11 common clock input rs0# m36 common clock input rs1# n35 common clock input rs2# u35 common clock input rsp# c9 common clock input sktocc# a5 power/other output slp# aw7 asynch gtl+ input table 30. pin listing by pin name pin name pin number signal buffer type direction smi# k38 asynch gtl+ input stpclk# c5 asynch gtl+ input tck r37 tap input tdi j39 tap input tdo p36 tap output testhi0 a7 power/other input testhi1 at10 power/other input testhi2 at6 power/other input testhi3 at8 power/other input testhi4 au7 power/other input testhi5 au9 power/other input testhi6 au11 power/other input testhi7 aw5 power/other input testhi8 d16 power/other input testhi9 d18 power/other input testhi10 d20 power/other input thermda h38 power/other thermdc e39 power/other thermtrip# u37 asynch gtl+ output tms d38 tap input trdy# a35 common clock input trst# r35 tap input vcc a37 power/other vcc a39 power/other vcc aa1 power/other vcc aa5 power/other vcc ab38 power/other vcc ab4 power/other vcc ab8 power/other vcc ac3 power/other vcc ac7 power/other vcc ad2 power/other vcc ad6 power/other vcc ae1 power/other vcc ae35 power/other vcc ae5 power/other vcc af4 power/other vcc af8 power/other vcc ag3 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 54 vcc ag37 power/other vcc ag7 power/other vcc ah2 power/other vcc ah6 power/other vcc aj1 power/other vcc aj39 power/other vcc aj5 power/other vcc ak4 power/other vcc ak8 power/other vcc al3 power/other vcc al7 power/other vcc am2 power/other vcc am36 power/other vcc am6 power/other vcc an1 power/other vcc an5 power/other vcc ap38 power/other vcc ap4 power/other vcc ar13 power/other vcc ar17 power/other vcc ar21 power/other vcc ar25 power/other vcc ar29 power/other vcc ar3 power/other vcc ar33 power/other vcc ar9 power/other vcc at2 power/other vcc av10 power/other vcc av14 power/other vcc av18 power/other vcc av22 power/other vcc av26 power/other vcc av30 power/other vcc av34 power/other vcc av38 power/other vcc av6 power/other vcc b10 power/other vcc b14 power/other vcc b18 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction vcc b22 power/other vcc b26 power/other vcc b30 power/other vcc b6 power/other vcc c3 power/other vcc c37 power/other vcc d2 power/other vcc e1 power/other vcc e13 power/other vcc e17 power/other vcc e21 power/other vcc e25 power/other vcc e29 power/other vcc e33 power/other vcc e5 power/other vcc e9 power/other vcc f4 power/other vcc g13 power/other vcc g19 power/other vcc g29 power/other vcc g3 power/other vcc g33 power/other vcc g39 power/other vcc g7 power/other vcc g9 power/other vcc h2 power/other vcc h6 power/other vcc j1 power/other vcc j37 power/other vcc j5 power/other vcc k4 power/other vcc k8 power/other vcc l3 power/other vcc l35 power/other vcc l7 power/other vcc m2 power/other vcc m6 power/other vcc n1 power/other vcc n5 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 55 vcc p4 power/other vcc p8 power/other vcc r3 power/other vcc r7 power/other vcc t2 power/other vcc t6 power/other vcc u1 power/other vcc u39 power/other vcc u5 power/other vcc v4 power/other vcc v8 power/other vcc w3 power/other vcc w7 power/other vcc y2 power/other vcc y36 power/other vcc y6 power/other vcc_sense n39 power/other output vcca au5 power/other vcciopll aw3 power/other vid0 c1 power/other output vid1 b2 power/other output vid2 b4 power/other output vid3 a3 power/other output vid4 a1 power/other output vss aa3 power/other vss aa37 power/other vss aa7 power/other vss ab2 power/other vss ab6 power/other vss ac1 power/other vss ac39 power/other vss ac5 power/other vss ad4 power/other vss ad8 power/other vss ae3 power/other vss ae7 power/other vss af2 power/other vss af36 power/other vss af6 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction vss ag1 power/other vss ag5 power/other vss ah38 power/other vss ah4 power/other vss ah8 power/other vss aj3 power/other vss aj7 power/other vss ak2 power/other vss ak6 power/other vss al1 power/other vss al35 power/other vss al5 power/other vss am4 power/other vss am8 power/other vss an3 power/other vss an37 power/other vss an7 power/other vss ap2 power/other vss ap6 power/other vss ar1 power/other vss ar11 power/other vss ar15 power/other vss ar19 power/other vss ar23 power/other vss ar27 power/other vss ar31 power/other vss ar35 power/other vss ar39 power/other vss ar5 power/other vss au3 power/other vss av12 power/other vss av16 power/other vss av20 power/other vss av24 power/other vss av28 power/other vss av32 power/other vss av36 power/other vss av8 power/other vss b12 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 56 vss b16 power/other vss b20 power/other vss b24 power/other vss b28 power/other vss b32 power/other vss b38 power/other vss b8 power/other vss c35 power/other vss c39 power/other vss d4 power/other vss e11 power/other vss e15 power/other vss e19 power/other vss e23 power/other vss e27 power/other vss e3 power/other vss e31 power/other vss e37 power/other vss f2 power/other vss f6 power/other vss g1 power/other vss g11 power/other vss g15 power/other vss g17 power/other vss g23 power/other vss g27 power/other vss g31 power/other vss g35 power/other vss g5 power/other vss h4 power/other vss h8 power/other vss j3 power/other vss j7 power/other vss k2 power/other vss k6 power/other vss l1 power/other vss l39 power/other vss l5 power/other vss m4 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction vss m8 power/other vss n3 power/other vss n37 power/other vss n7 power/other vss p2 power/other vss p6 power/other vss r1 power/other vss r5 power/other vss t4 power/other vss t8 power/other vss u3 power/other vss u7 power/other vss v2 power/other vss v38 power/other vss v6 power/other vss w1 power/other vss w5 power/other vss y4 power/other vss y8 power/other vss_sense r39 power/other output vssa av4 power/other table 30. pin listing by pin name pin name pin number signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 57 table 31. pin listing by pin number pin number pin name signal buffer type direction a1 vid4 power/other output a3 vid3 power/other output a5 sktocc# power/other output a7 testhi0 power/other input a9 a32# source synch input/output a11 a33# source synch input/output a13 a27# source synch input/output a15 a26# source synch input/output a17 a20# source synch input/output a19 a30# source synch input/output a21 a22# source synch input/output a23 a14# source synch input/output a25 a13# source synch input/output a27 a15# source synch input/output a29 a17# source synch input/output a31 a11# source synch input/output a33 lock# common clock input/output a35 trdy# common clock input a37 vcc power/other a39 vcc power/other b2 vid1 power/other output b4 vid2 power/other output b6 vcc power/other b8 vss power/other b10 vcc power/other b12 vss power/other b14 vcc power/other b16 vss power/other b18 vcc power/other b20 vss power/other b22 vcc power/other b24 vss power/other b26 vcc power/other b28 vss power/other b30 vcc power/other b32 vss power/other b34 dbsy# common clock input/output b36 br0# common clock input/output b38 vss power/other c1 vid0 power/other output c3 vcc power/other c5 stpclk# asynch gtl+ input c7 ierr# common clock output c9 rsp# common clock input c11 a31# source synch input/output c13 bpm4# common clock input/output c15 a34# source synch input/output c17 a21# source synch input/output c19 a23# source synch input/output c21 a29# source synch input/output c23 a10# source synch input/output c25 a12# source synch input/output c27 a18# source synch input/output c29 a4# source synch input/output c31 a6# source synch input/output c33 req0# source synch input/output c35 vss power/other c37 vcc power/other c39 vss power/other d2 vcc power/other d4 vss power/other d6 bpm5# common clock input/output d8 init# asynch gtl+ input table 31. pin listing by pin number pin number pin name signal buffer type direction 5.1.2 pin listing by pin number table 31 contains a listing of the pentium 4 processor pins in order by pin number.
intel ? pentium ? 4 processor in the 423-pin package 58 d10 mcerr# common clock input/output d12 a35# source synch input/output d14 ap1# common clock input/output d16 testhi8 power/other input d18 testhi9 power/other input d20 testhi10 power/other input d22 a25# source synch input/output d24 a16# source synch input/output d26 a19# source synch input/output d28 a8# source synch input/output d30 a5# source synch input/output d32 req1# source synch input/output d34 req3# source synch input/output d36 hitm# common clock input/output d38 tms tap input e1 vcc power/other e3 vss power/other e5 vcc power/other e7 bpm3# common clock input/output e9 vcc power/other e11 vss power/other e13 vcc power/other e15 vss power/other e17 vcc power/other e19 vss power/other e21 vcc power/other e23 vss power/other e25 vcc power/other e27 vss power/other e29 vcc power/other e31 vss power/other e33 vcc power/other e35 bnr# common clock input/output e37 vss power/other e39 thermdc power/other f2 vss power/other f4 vcc power/other f6 vss power/other f8 bpm0# common clock input/output table 31. pin listing by pin number pin number pin name signal buffer type direction f10 bpm2# common clock input/output f12 bpm1# common clock input/output f14 gtlref power/other input f16 ap0# common clock input/output f18 binit# common clock input/output f20 a28# source synch input/output f22 a24# source synch input/output f24 comp1 power/other input/output f26 a9# source synch input/output f28 a7# source synch input/output f30 a3# source synch input/output f32 req4# source synch input/output f34 req2# source synch input/output f36 ads# common clock input/output f38 prochot# asynch gtl+ output g1 vss power/other g3 vcc power/other g5 vss power/other g7 vcc power/other g9 vcc power/other g11 vss power/other g13 vcc power/other g15 vss power/other g17 vss power/other g19 vcc power/other g21 adstb1# source synch input/output g23 vss power/other g25 adstb0# source synch input/output g27 vss power/other g29 vcc power/other g31 vss power/other g33 vcc power/other g35 vss power/other g37 drdy# common clock input/output g39 vcc power/other h2 vcc power/other h4 vss power/other h6 vcc power/other h8 vss power/other table 31. pin listing by pin number pin number pin name signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 59 h36 lint0 asynch gtl+ input h38 thermda power/other j1 vcc power/other j3 vss power/other j5 vcc power/other j7 vss power/other j35 defer# common clock input j37 vcc power/other j39 tdi tap input k2 vss power/other k4 vcc power/other k6 vss power/other k8 vcc power/other k36 hit# common clock input/output k38 smi# asynch gtl+ input l1 vss power/other l3 vcc power/other l5 vss power/other l7 vcc power/other l35 vcc power/other l37 bpri# common clock input l39 vss power/other m2 vcc power/other m4 vss power/other m6 vcc power/other m8 vss power/other m36 rs0# common clock input m38 ignne# asynch gtl+ input n1 vcc power/other n3 vss power/other n5 vcc power/other n7 vss power/other n35 rs1# common clock input n37 vss power/other n39 vcc_sense power/other output p2 vss power/other p4 vcc power/other p6 vss power/other p8 vcc power/other table 31. pin listing by pin number pin number pin name signal buffer type direction p36 tdo tap output p38 ferr# asynch gtl+ output r1 vss power/other r3 vcc power/other r5 vss power/other r7 vcc power/other r35 trst# tap input r37 tck tap input r39 vss_sense power/other output t2 vcc power/other t4 vss power/other t6 vcc power/other t8 vss power/other t36 gtlref power/other input t38 a20m# asynch gtl+ input u1 vcc power/other u3 vss power/other u5 vcc power/other u7 vss power/other u35 rs2# common clock input u37 thermtrip# asynch gtl+ output u39 vcc power/other v2 vss power/other v4 vcc power/other v6 vss power/other v8 vcc power/other v36 d6# source synch input/output v38 vss power/other w1 vss power/other w3 vcc power/other w5 vss power/other w7 vcc power/other w35 lint1 asynch gtl+ input w37 d2# source synch input/output w39 d8# source synch input/output y2 vcc power/other y4 vss power/other y6 vcc power/other y8 vss power/other table 31. pin listing by pin number pin number pin name signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 60 y36 vcc power/other y38 d0# source synch input/output aa1 vcc power/other aa3 vss power/other aa5 vcc power/other aa7 vss power/other aa35 d5# source synch input/output aa37 vss power/other aa39 d15# source synch input/output ab2 vss power/other ab4 vcc power/other ab6 vss power/other ab8 vcc power/other ab36 d10# source synch input/output ab38 vcc power/other ac1 vss power/other ac3 vcc power/other ac5 vss power/other ac7 vcc power/other ac35 gtlref power/other input ac37 d14# source synch input/output ac39 vss power/other ad2 vcc power/other ad4 vss power/other ad6 vcc power/other ad8 vss power/other ad36 d1# source synch input/output ad38 d11# source synch input/output ae1 vcc power/other ae3 vss power/other ae5 vcc power/other ae7 vss power/other ae35 vcc power/other ae37 d3# source synch input/output ae39 d9# source synch input/output af2 vss power/other af4 vcc power/other af6 vss power/other af8 vcc power/other table 31. pin listing by pin number pin number pin name signal buffer type direction af36 vss power/other af38 d7# source synch input/output ag1 vss power/other ag3 vcc power/other ag5 vss power/other ag7 vcc power/other ag35 dstbn0# source synch input/output ag37 vcc power/other ag39 d4# source synch input/output ah2 vcc power/other ah4 vss power/other ah6 vcc power/other ah8 vss power/other ah36 d12# source synch input/output ah38 vss power/other aj1 vcc power/other aj3 vss power/other aj5 vcc power/other aj7 vss power/other aj35 dstbp0# source synch input/output aj37 d13# source synch input/output aj39 vcc power/other ak2 vss power/other ak4 vcc power/other ak6 vss power/other ak8 vcc power/other ak36 d24# source synch input/output ak38 d17# source synch input/output al1 vss power/other al3 vcc power/other al5 vss power/other al7 vcc power/other al35 vss power/other al37 d31# source synch input/output al39 dbi0# source synch input/output am2 vcc power/other am4 vss power/other am6 vcc power/other am8 vss power/other table 31. pin listing by pin number pin number pin name signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 61 am36 vcc power/other am38 d20# source synch input/output an1 vcc power/other an3 vss power/other an5 vcc power/other an7 vss power/other an35 d27# source synch input/output an37 vss power/other an39 d23# source synch input/output ap2 vss power/other ap4 vcc power/other ap6 vss power/other ap8 bclk1 system bus clk input ap10 gtlref power/other input ap12 d63# source synch input/output ap14 d61# source synch input/output ap16 dstbp3# source synch input/output ap18 dstbn3# source synch input/output ap20 dstbp2# source synch input/output ap22 dstbn2# source synch input/output ap24 d41# source synch input/output ap26 d35# source synch input/output ap28 d43# source synch input/output ap30 dstbp1# source synch input/output ap32 dstbn1# source synch input/output ap34 d18# source synch input/output ap36 d22# source synch input/output ap38 vcc power/other ar1 vss power/other ar3 vcc power/other ar5 vss power/other ar7 bclk0 bus clk input ar9 vcc power/other ar11 vss power/other ar13 vcc power/other ar15 vss power/other ar17 vcc power/other ar19 vss power/other ar21 vcc power/other table 31. pin listing by pin number pin number pin name signal buffer type direction ar23 vss power/other ar25 vcc power/other ar27 vss power/other ar29 vcc power/other ar31 vss power/other ar33 vcc power/other ar35 vss power/other ar37 d25# source synch input/output ar39 vss power/other at2 vcc power/other at4 reserved at6 testhi2 power/other input at8 testhi3 power/other input at10 testhi1 power/other input at12 d60# source synch input/output at14 d57# source synch input/output at16 d55# source synch input/output at18 d53# source synch input/output at20 d49# source synch input/output at22 dbi2# source synch input/output at24 d45# source synch input/output at26 dp3# common clock input/output at28 d40# source synch input/output at30 d39# source synch input/output at32 d33# source synch input/output at34 d30# source synch input/output at36 d16# source synch input/output at38 d26# source synch input/output au1 itp_clk0 tap input au3 vss power/other au5 vcca power/other au7 testhi4 power/other input au9 testhi5 power/other input au11 testhi5 power/other input au13 d59# source synch input/output au15 d56# source synch input/output au17 d54# source synch input/output au19 d48# source synch input/output au21 d50# source synch input/output table 31. pin listing by pin number pin number pin name signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 62 au23 d47# source synch input/output au25 d42# source synch input/output au27 comp0 power/other input/output au29 d34# source synch input/output au31 d38# source synch input/output au33 d36# source synch input/output au35 d28# source synch input/output au37 dbi1# source synch input/output au39 d21# source synch input/output av2 dbr# asynch gtl+ output av4 vssa power/other av6 vcc power/other av8 vss power/other av10 vcc power/other av12 vss power/other av14 vcc power/other av16 vss power/other av18 vcc power/other av20 vss power/other av22 vcc power/other av24 vss power/other av26 vcc power/other av28 vss power/other av30 vcc power/other av32 vss power/other av34 vcc power/other av36 vss power/other av38 vcc power/other aw1 itp_clk1 tap input aw3 vcciopll power/other aw5 testhi7 power/other input aw7 slp# asynch gtl+ input aw9 pwrgood asynch gtl+ input aw11 reset# common clock input aw13 d58# source synch input/output aw15 dbi3# source synch input/output aw17 d62# source synch input/output aw19 d52# source synch input/output aw21 d51# source synch input/output table 31. pin listing by pin number pin number pin name signal buffer type direction aw23 d46# source synch input/output aw25 d44# source synch input/output aw27 dp2# common clock input/output aw29 d37# source synch input/output aw31 d32# source synch input/output aw33 dp0# common clock input/output aw35 dp1# common clock input/output aw37 d19# source synch input/output aw39 d29# source synch input/output table 31. pin listing by pin number pin number pin name signal buffer type direction
intel ? pentium ? 4 processor in the 423-pin package 63 5.2 alphabetical signals reference table 32. signal description (page 1 of 8) name type description a[35:3]# input/ output a[35:3]# (address) define a 2 36 -byte physical memory address space. in sub- phase 1 of the address phase, these pins transmit the address of a transaction. in sub-phase 2, these pins transmit transaction type information. these signals must connect the appropriate pins of all agents on the pentium 4 processor in the 423- pin package system bus. a[35:3]# are protected by parity signals ap[1:0]#. a[35:3]# are source synchronous signals and are latched into the receiving buffers by adstb[1:0]#. on the active-to-inactive transition of reset#, the processor samples a subset of the a[35:3]# pins to determine power-on configuration. see section 7.1 for more details. a20m# input if a20m# (address-20 mask) is asserted, the processor masks physical address bit 20 (a20#) before looking up a line in any internal cache and before driving a read/ write transaction on the bus. asserting a20m# emulates the 8086 processor's address wrap-around at the 1-mbyte boundary. assertion of a20m# is only supported in real mode. a20m# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. ads# input/ output ads# (address strobe) is asserted to indicate the validity of the transaction address on the a[35:3]# and req[4:0]# pins. all bus agents observe the ads# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply id match operations associated with the new transaction. adstb[1:0]# input/ output address strobes are used to latch a[35:3]# and req[4:0]# on their rising and falling edges. strobes are associated with signals as shown below. ap[1:0]# input/ output ap[1:0]# (address parity) are driven by the request initiator along with ads#, a[35:3]#, and the transaction type on the req[4:0]#. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. this allows parity to be high when all the covered signals are high. ap[1:0]# should connect the appropriate pins of all pentium 4 processor system bus agents. the following table defines the coverage model of these signals. bclk[1:0] input the differential pair bclk (bus clock) determines the system bus frequency. all processor system bus agents must receive these signals to drive their outputs and latch their inputs. all external timing parameters are specified with respect to the rising edge of bclk0 crossing v cross . signals associated strobe req[4:0]#, a[16:3]# adstb0# a[35:17]# adstb1# request signals subphase 1 subphase 2 a[35:24]# ap0# ap1# a[23:3]# ap1# ap0# req[4:0]# ap1# ap0#
intel ? pentium ? 4 processor in the 423-pin package 64 binit# input/ output binit# (bus initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. if the binit# driver is enabled during power-on configuration, binit# is asserted to signal any bus condition that prevents reliable future operation. if binit# observation is enabled during power-on configuration, and binit# is sampled asserted, symmetric agents reset their bus lock# activity and bus request arbitration state machines. the bus agents do not reset their ioq and transaction tracking state machines upon observation of binit# activation. once the binit# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and ioq entries. if binit# observation is disabled during power-on configuration, a central agent may handle an assertion of binit# as appropriate to the error handling architecture of the system. bnr# input/ output bnr# (block next request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. during a bus stall, the current bus owner cannot issue any new transactions. bpm[5:0]# input/ output bpm[5:0]# (breakpoint monitor) are breakpoint and performance monitor signals. they are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. bpm[5:0]# should connect the appropriate pins of all pentium 4 processor system bus agents. bpm4# provides prdy# (probe ready) functionality for the tap port. prdy# is a processor output used by debug tools to determine processor debug readiness. bpm5# provides preq# (probe request) functionality for the tap port. preq# is used by debug tools to request debug operation of the processor. please refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for more detailed information. these signals do not have on-die termination. refer to section 2.5 and the (product) itp700 debug port design guide for termination requirements. bpri# input bpri# (bus priority request) is used to arbitrate for ownership of the processor system bus. it must connect the appropriate pins of all processor system bus agents. observing bpri# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. the priority agent keeps bpri# asserted until all of its requests are completed, then releases the bus by deasserting bpri#. br0# input/ output br0# drives the breq0# signal in the system and is used by the processor to request the bus. during power-on configuration this pin is sampled to determine the agent id = 0. this signal does not have on-die termination and must be terminated. comp[1:0] analog comp[1:0] must be terminated on the system board using precision resistors. refer to table 9 in chapter 2.0. table 32. signal description (page 2 of 8) name type description
intel ? pentium ? 4 processor in the 423-pin package 65 d[63:0]# input/ output d[63:0]# (data) are the data signals. these signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. the data driver asserts drdy# to indicate a valid data transfer. d[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. d[63:0]# are latched off the falling edge of both dstbp[3:0]# and dstbn[3:0]#. each group of 16 data signals correspond to a pair of one dstbp# and one dstbn#. the following table shows the grouping of data signals to data strobes and dbi#. furthermore, the dbi# pins determine the polarity of the data signals. each group of 16 data signals corresponds to one dbi# signal. when the dbi# signal is active, the corresponding data group is inverted and therefore sampled active high. dbi[3:0]# input/ output dbi[3:0]# are source synchronous and indicate the polarity of the d[63:0]# signals. the dbi[3:0]# signals are activated when the data on the data bus is inverted. the bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. dbr# output dbr# is used only in processor systems where no debug port is implemented on the system board. dbr# is used by a debug port interposer so that an in-target probe can drive system reset. if a debug port is implemented in the system, dbr# is a no connect in the system. dbr# is not a processor signal. dbsy# input/ output dbsy# (data bus busy) is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use. the data bus is released after dbsy# is deasserted. this signal must connect the appropriate pins on all processor system bus agents. defer# input defer# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. assertion of defer# is normally the responsibility of the addressed memory or input/output agent. this signal must connect the appropriate pins of all processor system bus agents. dp[3:0]# input/ output dp[3:0]# (data parity) provide parity protection for the d[63:0]# signals. they are driven by the agent responsible for driving d[63:0]#, and must connect the appropriate pins of all pentium 4 processor system bus agents. table 32. signal description (page 3 of 8) name type description quad-pumped signal groups data group dstbn#/ dstbp# dbi# d[15:0]# 0 0 d[31:16]# 1 1 d[47:32]# 2 2 d[63:48]# 3 3 dbi[3:0] assignment to data bus bus signal data bus signals dbi3# d[63:48]# dbi2# d[47:32]# dbi1# d[31:16]# dbi0# d[15:0]#
intel ? pentium ? 4 processor in the 423-pin package 66 drdy# input/ output drdy# (data ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. in a multi-common clock data transfer, drdy# may be deasserted to insert idle clocks. this signal must connect the appropriate pins of all processor system bus agents. dstbn[3:0]# input/ output data strobe used to latch in d[63:0]#. dstbp[3:0]# input/ output data strobe used to latch in d[63:0]#. ferr# output ferr# (floating-point error) is asserted when the processor detects an unmasked floating-point error. ferr# is similar to the error# signal on the intel 387 coprocessor, and is included for compatibility with systems using ms-dos*-type floating-point error reporting. gtlref input gtlref determines the signal reference level for agtl+ input pins. gtlref should be set at 2/3 v cc . gtlref is used by the agtl+ receivers to determine if a signal is a logical 0 or logical 1. refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for more information. hit# hitm# input/ output input/ output hit# (snoop hit) and hitm# (hit modified) convey transaction snoop operation results. any system bus agent may assert both hit# and hitm# together to indicate that it requires a snoop stall, which can be continued by reasserting hit# and hitm# together. ierr# output ierr# (internal error) is asserted by a processor as the result of an internal error. assertion of ierr# is usually accompanied by a shutdown transaction on the processor system bus. this transaction may optionally be converted to an external error signal (e.g., nmi) by system core logic. the processor will keep ierr# asserted until the assertion of reset#, binit#, or init#. this signal does not have on-die termination. refer to section 2.5 for termination requirements. ignne# input ignne# (ignore numeric error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. if ignne# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. ignne# has no effect when the ne bit in control register 0 (cr0) is set. ignne# is an asynchronous signal. however, to ensure recognition of this signal following an input/output write instruction, it must be valid along with the trdy# assertion of the corresponding input/output write bus transaction. table 32. signal description (page 4 of 8) name type description signals associated strobe d[15:0]#, dbi0# dstbn0# d[31:16]#, dbi1# dstbn1# d[47:32]#, dbi2# dstbn2# d[63:48]#, dbi3# dstbn3# signals associated strobe d[15:0]#, dbi0# dstbp0# d[31:16]#, dbi1# dstbp1# d[47:32]#, dbi2# dstbp2# d[63:48]#, dbi3# dstbp3#
intel ? pentium ? 4 processor in the 423-pin package 67 init# input init# (initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. the processor then begins execution at the power-on reset vector configured during power-on configuration. the processor continues to handle snoop requests during init# assertion. init# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. if init# is sampled active on the active to inactive transition of reset#, then the processor executes its built-in self-test (bist). itp_clk[1:0] input itp_clk[1:0] are copies of bclk that are used only in processor systems where no debug port is implemented on the system board. itp_clk[1:0] are used as bclk[1:0] references for a debug port implemented on an interposer. if a debug port is implemented in the system, itp_clk[1:0] are no connects in the system. these are not processor signals. lint[1:0] input lint[1:0] (local apic interrupt) must connect the appropriate pins of all apic bus agents. when the apic is disabled, the lint0 signal becomes intr, a maskable interrupt request signal, and lint1 becomes nmi, a nonmaskable interrupt. intr and nmi are backward compatible with the signals of those names on the pentium processor. both signals are asynchronous. both of these signals must be software configured via bios programming of the apic register space to be used either as nmi/intr or lint[1:0]. because the apic is enabled by default after reset, operation of these pins as lint[1:0] is the default configuration. lock# input/ output lock# indicates to the system that a transaction must occur atomically. this signal must connect the appropriate pins of all processor system bus agents. for a locked sequence of transactions, lock# is asserted from the beginning of the first transaction to the end of the last transaction. when the priority agent asserts bpri# to arbitrate for ownership of the processor system bus, it will wait until it observes lock# deasserted. this enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. mcerr# input/ output mcerr# (machine check error) is asserted to indicate an unrecoverable error without a bus protocol violation. it may be driven by all processor system bus agents. mcerr# assertion conditions are configurable at a system level. assertion options are defined by the following options: enabled or disabled. asserted, if configured, for internal errors along with ierr#. asserted, if configured, by the request initiator of a bus transaction after it observes an error. asserted by any bus agent when it observes an error in a bus transaction. for more details regarding machine check architecture, please refer to the ia-32 software developer?s manual, volume 3: system programming guide . prochot# output prochot# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum tested operating temperature. this indicates that the processor thermal control circuit has been activated, if enabled. see section 7.3 for more details. table 32. signal description (page 5 of 8) name type description
intel ? pentium ? 4 processor in the 423-pin package 68 pwrgood input pwrgood (power good) is a processor input. the processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ?clean? implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. the signal must then transition monotonically to a high state. figure 10 illustrates the relationship of pwrgood to the reset# signal. pwrgood can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of pwrgood. it must also meet the minimum pulse width specification in table 13, and be followed by a 1 to 10 ms reset# pulse. the pwrgood signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. it should be driven high throughout boundary scan operation. req[4:0]# input/ output req[4:0]# (request command) must connect the appropriate pins of all processor system bus agents. they are asserted by the current bus owner to define the currently active transaction type. these signals are source synchronous to adstb0#. refer to the ap[1:0]# signal description for a details on parity checking of these signals. reset# input asserting the reset# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. for a power-on reset, reset# must stay active for at least one millisecond after v cc and bclk have reached their proper specifications. on observing active reset#, all system bus agents will deassert their outputs within two clocks. reset# must not be kept asserted for more than 10 ms while pwrgood is asserted. a number of bus signals are sampled at the active-to-inactive transition of reset# for power-on configuration. these configuration options are described in the section 7.1. this signal does not have on-die termination and must be terminated on the system board. rs[2:0]# input rs[2:0]# (response status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. rsp# input rsp# (response parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of rs[2:0]#, the signals for which rsp# provides parity protection. it must connect to the appropriate pins of all processor system bus agents. a correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. while rs[2:0]# = 000, rsp# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity. sktocc# output sktocc# (socket occupied) will be pulled to ground by the processor. system board designers may use this pin to determine if the processor is present. slp# input slp# (sleep), when asserted in stop-grant state, causes the processor to enter the sleep state. during sleep state, the processor stops providing internal clock signals to all units, leaving only the phase-locked loop (pll) still operating. processors in this state will not recognize snoops or interrupts. the processor will recognize only assertion of the reset# signal, deassertion of slp#, and removal of the bclk input while in sleep state. if slp# is deasserted, the processor exits sleep state and returns to stop-grant state, restarting its internal clock signals to the bus and processor core units. if the bclk input is stopped while in the sleep state the processor will exit the sleep state and transition to the deep sleep state. table 32. signal description (page 6 of 8) name type description
intel ? pentium ? 4 processor in the 423-pin package 69 smi# input smi# (system management interrupt) is asserted asynchronously by system logic. on accepting a system management interrupt, the processor saves the current state and enter system management mode (smm). an smi acknowledge transaction is issued, and the processor begins program execution from the smm handler. if smi# is asserted during the deassertion of reset# the processor will tristate its outputs. stpclk# input stpclk# (stop clock), when asserted, causes the processor to enter a low power stop-grant state. the processor issues a stop-grant acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and apic units. the processor continues to snoop bus transactions and service interrupts while in stop-grant state. when stpclk# is deasserted, the processor restarts its internal clock to all units and resumes execution. the assertion of stpclk# has no effect on the bus clock; stpclk# is an asynchronous input. tck input tck (test clock) provides the clock input for the processor test bus (also known as the test access port). tdi input tdi (test data in) transfers serial test data into the processor. tdi provides the serial input needed for jtag specification support. tdo output tdo (test data out) transfers serial test data out of the processor. tdo provides the serial output needed for jtag specification support. testhi[10:0] input testhi[10:0] must be connected to a v cc power source through 1-10 k ? resistors for proper processor operation. see section 2.5 for more details. thermda other thermal diode anode. see section 7.3.1. thermdc other thermal diode cathode. see section 7.3.1. thermtrip# output the processor protects itself from catastrophic overheating by use of an internal thermal sensor. this sensor is set well above the normal operating temperature to ensure that there are no false trips. the processor will stop all execution when the junction temperature exceeds approximately 135c. this is signalled to the system by the thermtrip# (thermal trip) pin. once activated, the signal remains latched, and the processor stopped, until reset# goes active. there is no hysteresis built into the thermal sensor itself; as long as the die temperature drops below the trip level, a reset# pulse will reset the processor and execution will continue. if the temperature has not dropped below the trip level, the processor will continue to drive thermtrip# and remain stopped. tms input tms (test mode select) is a jtag specification support signal used by debug tools. trdy# input trdy# (target ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. trdy# must connect the appropriate pins of all system bus agents. trst# input trst# (test reset) resets the test access port (tap) logic. trst# must be driven low during power on reset. this can be done with a 680 ? pull-down resistor. v cca input v cca provides isolated power for the internal processor core pll?s. refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for complete implementation details. v cciopll input v cciopll provides isolated power for internal processor system bus pll?s. follow the guidelines for v cca , and refer to the intel ? pentium ? 4 processor and intel ? 850 chipset platform design guide for complete implementation details. v ccsense output v ccsense is an isolated low impedance connection to processor core power (v cc ). it can be used to sense or measure power near the silicon with little noise. table 32. signal description (page 7 of 8) name type description
intel ? pentium ? 4 processor in the 423-pin package 70 vid[4:0] output vid[4:0] (voltage id) pins can be used to support automatic selection of power supply voltages. these pins are not signals, but are either an open circuit or a short circuit to vss on the processor. the combination of opens and shorts defines the voltage required by the processor. the vid pins are needed to cleanly support processor voltage specification variations. see table 2 for definitions of these pins. the power supply must supply the voltage that is requested by these pins, or disable itself. v ssa input v ssa is the isolated ground for internal pll?s. v sssense output v sssense is an isolated low impedance connection to processor core v ss . it can be used to sense or measure ground near the silicon with little noise table 32. signal description (page 8 of 8) name type description
intel ? pentium ? 4 processor in the 423-pin package 71 6.0 thermal specifications and design considerations intel ? pentium ? 4 processor in the 423-pin package use an integrated thermal heat spreader for heatsink attachment which is intended to provide for multiple types of thermal solutions. this section will provide data necessary for development of a thermal solution. see figure 23 for an exploded view of an example pentium 4 processor thermal solution. this is for illustration purposes only. for further thermal solution design details, please refer to the intel ? pentium ? 4 processor thermal design guidelines . note: the processor is either shipped by itself or with a heatsink for boxed processors. see chapter 8.0 for details on boxed processors. figure 23. example thermal solution (not to scale) retention mechanism 423-pin socket processor heatsink retention clip
intel ? pentium ? 4 processor in the 423-pin package 72 6.1 thermal specifications table 33 specifies the thermal design power dissipation envelope for pentium 4 processors. analysis indicates that real applications are unlikely to cause the processor to consume its maximum possible power consumption. intel recommends that system thermal designs target the ?thermal design power? indicated in table 33. the thermal monitor feature (refer to section 7.3) is intended to protect the processor from overheating when running high power code that exceeds the recommendations in this table. for more details on the usage of this feature, refer to section 7.3. in all cases the thermal monitor feature must be enabled for the processor to be in specification. table 33 also lists the maximum and minimum processor temperature specifications for t case . a thermal solution should be designed to ensure the temperature of the processor never exceeds these specifications. notes: 1. these values are specified at v cc_ mid for the processor. systems must be designed to ensure that the processor not be subjected to any static v cc and i cc combination wherein v cc exceeds v cc_ mid + 0.055*(1 - i cc /i cc_ max ) [v] 2. the numbers in this column reflect intel?s recommended design point and are not indicative of the maximum power the processor can dissipate under worst case conditions. for more details refer to the intel ? pentium ? 4 processor thermal design guidelines . 3. these specifications apply to ?1.7v? processors, i.e., those with a vid = ?00110?. 4. these specifications apply to ?1.75v? processors, i.e., those with a vid = ?00100?. table 33. processor thermal design power processor and core frequency (ghz) thermal design power (w) 2 minimum t case (c) maximum t case (c) notes 1.7v processors 1.30 ghz 1.40 ghz 1.50 ghz 48.9 51.8 54.7 5 5 5 69 70 72 1, 3 1, 3 1, 3 1.75v processors 1.30 ghz 1.40 ghz 1.50 ghz 1.60 ghz 1.70 ghz 1.80 ghz 1.90 ghz 2 ghz 51.6 54.7 57.8 61.0 64.0 66.7 69.2 71.8 5 5 5 5 5 5 5 5 70 72 73 75 76 78 73 74 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4
intel ? pentium ? 4 processor in the 423-pin package 73 6.2 thermal analysis 6.2.1 measurements for thermal specifications 6.2.1.1 processor case temperature measurement the maximum and minimum case temperature (t case ) for the pentium 4 processor is specified in table 33. this temperature specification is meant to ensure correct and reliable operation of the processor. figure 24 illustrates where intel recommends that t case thermal measurements should be made. figures 25 and 26 illustrate two possible measuring techniques. refer to the intel ? pentium ? 4 processor thermal design guidelines for more information. figure 24. guideline locations for case temperature (t case ) thermocouple placement figure 25. technique for measuring with 0 degree angle attachment 000874b measure from edge of processor measure t at this point. case thermal grease should cover the entire surface of the integrated heat spreader 1.125? 1.075?
intel ? pentium ? 4 processor in the 423-pin package 74 figure 26. technique for measuring with 90 degree angle attachment
intel ? pentium ? 4 processor in the 423-pin package 75 7.0 features 7.1 power-on configuration options several configuration options can be configured by hardware. the intel ? pentium ? 4 processor in the 423-pin package sample its hardware configuration at reset, on the active-to-inactive transition of reset#. for specifications on these options, please refer to table 34. the sampled information configures the processor for subsequent operation. these configuration options cannot be changed except during another reset. all resets reconfigure the processor; for reset purposes, the processor does not distinguish between a ?warm? reset and a ?power-on? reset. note: 1. asserting this signal during reset# will select the corresponding option. 7.2 clock control and low power states the use of autohalt, stop-grant, sleep, and deep sleep states is allowed in pentium 4 processor based systems to reduce power consumption by stopping the clock to internal sections of the processor, depending on each particular state. see figure 27 for a visual representation of the processor low power states. 7.2.1 normal state?state 1 this is the normal operating state for the processor. 7.2.2 autohalt powerdown state?state 2 autohalt is a low power state entered when the processor executes the halt instruction. the processor will transition to the normal state upon the occurrence of smi#, binit#, init#, or lint[1:0] (nmi, intr). reset# will cause the processor to immediately initialize itself. the return from a system management interrupt (smi) handler can be to either normal mode or the autohalt power down state. see the intel architecture software developer's manual, volume iii: system programmer's guide for more information. table 34. power-on configuration option pins configuration option pin 1 output tristate smi# execute bist init# in order queue pipelining (set ioq depth to 1) a7# disable mcerr# observation a9# disable binit# observation a10# apic cluster id (0-3) a[12:11]# disable bus parking a15# symmetric agent arbitration id br0#
intel ? pentium ? 4 processor in the 423-pin package 76 the system can generate a stpclk# while the processor is in the autohalt power down state. when the system deasserts the stpclk# interrupt, the processor will return execution to the halt state. while in autohalt power down state, the processor will process bus snoops. 7.2.3 stop-grant state?state 3 when the stpclk# pin is asserted, the stop-grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued stop grant acknowledge special bus cycle. once the stpclk# pin has been asserted, it may only be deasserted once the processor is in the stop grant state. since the agtl+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to v cc ) for minimum power drawn by the termination resistors in this state. in addition, all other input pins on the system bus should be driven to the inactive state. binit# will not be serviced while the processor is in stop-grant state. the event will be latched and can be serviced by software upon exit from the stop grant state. figure 27. stop clock state machine 2. auto halt power down state bclk running. snoops and interrupts allowed. halt instruction and halt bus cycle generated init#, binit#, intr, nmi, smi#, reset# 1. normal state normal execution. stpclk# asserted stpclk# de-asserted 3. stop grant state bclk running. snoops and interrupts allowed. slp# asserted slp# de-asserted 5. sleep state bclk running. no snoops or interrupts allowed. bclk input stopped bclk input restarted 6. deep sleep state bclk stopped. no snoops or interrupts allowed. 4. halt/grant snoop state bclk running. service snoops to caches. snoop event occurs snoop event serviced snoop event occurs snoop event serviced s t p c l k # a s s e r t e d s t p c l k # d e - a s s e r t e d
intel ? pentium ? 4 processor in the 423-pin package 77 reset# will cause the processor to immediately initialize itself, but the processor will stay in stop-grant state. a transition back to the normal state will occur with the de-assertion of the stpclk# signal. when re-entering the stop grant state from the sleep state, stpclk# should only be de-asserted one or more bus clocks after the de-assertion of slp#. a transition to the halt/grant snoop state will occur when the processor detects a snoop on the system bus (see section 7.2.4). a transition to the sleep state (see section 7.2.5) will occur with the assertion of the slp# signal. while in the stop-grant state, smi#, init#, binit# and lint[1:0] will be latched by the processor, and only serviced when the processor returns to the normal state. only one occurrence of each event will be recognized upon return to the normal state. while in stop-grant state, the processor will process a system bus snoop. 7.2.4 halt/grant snoop state?state 4 the processor will respond to snoop transactions on the system bus while in stop-grant state or in autohalt power down state. during a snoop transaction, the processor enters the halt/grant snoop state. the processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus). after the snoop is serviced, the processor will return to the stop-grant state or autohalt power down state, as appropriate. 7.2.5 sleep state?state 5 the sleep state is a very low power state in which the processor maintains its context, maintains the phase-locked loop (pll), and has stopped all internal clocks. the sleep state can only be entered from stop-grant state. once in the stop-grant state, the processor will enter the sleep state upon the assertion of the slp# signal. the slp# pin should only be asserted when the processor is in the stop grant state. slp# assertions while the processor is not in the stop grant state is out of specification and may result in illegal operation. snoop events that occur while in sleep state or during a transition into or out of sleep state will cause unpredictable behavior. in the sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals (with the exception of slp# or reset#) are allowed on the system bus while the processor is in sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behaviour. if reset# is driven active while the processor is in the sleep state, and held active as specified in the reset# pin specification, then the processor will reset itself, ignoring the transition through stop-grant state. if reset# is driven active while the processor is in the sleep state, the slp# and stpclk# signals should be deasserted immediately after reset# is asserted to ensure the processor correctly executes the reset sequence. while in the sleep state, the processor is capable of entering its lowest power state, the deep sleep state, by stopping the bclk[1:0] inputs. (see section 7.2.6). once in the sleep or deep sleep states, the slp# pin must be de-asserted if another asynchronous system bus event needs to occur. the slp# pin has a minimum assertion of one bclk period. when the processor is in sleep state, it will not respond to interrupts or snoop transactions.
intel ? pentium ? 4 processor in the 423-pin package 78 7.2.6 deep sleep state?state 6 deep sleep state is the lowest power state the processor can enter while maintaining context. deep sleep state is entered by stopping the bclk[1:0] inputs (after the sleep state was entered from the assertion of the slp# pin). the processor is in deep sleep state immediately after blck[1:0] is stopped. to provide maximum power conservation hold the blck0 input at v ol and the bclk1 input at v oh during the deep sleep state. stopping the bclk input lowers the overall current consumption to leakage levels. to re-enter the sleep state, the blck input must be restarted. a period of 1 ms (to allow for pll stabilization) must occur before the processor can be considered to be in the sleep state. once in the sleep state, the slp# pin can be deasserted to re-enter the stop-grant state. while in deep sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. no transitions or assertions of signals are allowed on the system bus while the processor is in deep sleep state. any transition on an input signal before the processor has returned to stop-grant state will result in unpredictable behavior. the processor has to stay in deep sleep mode for a minimum of 25 ms. when the processor is in deep sleep state, it will not respond to interrupts or snoop transactions. 7.3 thermal monitor thermal monitor is a new feature found in the pentium 4 processor which allows system designers to design lower cost thermal solutions, without compromising system integrity or reliability. by using a factory-tuned, precision on-die thermal sensor, and a fast acting thermal control circuit (tcc), the processor, without the aid of any additional software or hardware, can keep the processors' die temperature within factory specifications under typical real world operating conditions. thermal monitor thus allows the processor and system thermal solutions to be designed much closer to the power envelopes of real applications, instead of being designed to the much higher maximum theoretical processor power envelopes. thermal monitor controls the processor temperature by modulating the internal processor core clocks. the processor clocks are modulated when the tcc is activated. thermal monitor uses two modes to activate the tcc. automatic mode and on-demand mode. automatic mode is required for the processor to operate within specifications and must first be enabled via bios. once automatic mode is enabled, the tcc will activate only when the internal die temperature is very near the temperature limits of the processor. when tcc is enabled, and a high temperature situation exists (i.e. tcc is active), the clocks will be modulated by alternately turning the clocks off and on at a a 50% duty cycle. clocks will not be off more than 3 s when tcc is active. cycle times are processor speed dependent and will decrease as processor core frequencies increase. a small amount of hysteresis has been included to prevent rapid active/inactive transitions of the tcc when the processor temperature is near the trip point. once the temperature has returned to a non-critical level, and the hysteresis timer has expired, modulation ceases and tcc goes inactive. processor performance will be decreased by ~50% when the tcc is active (assuming a 50% duty cycle), however, with a properly designed and characterised thermal solution the tcc most likely will only be activated briefly when the system is near maximum temperature and during the most power intensive applications. for automatic mode, the 50% duty cycle is factory configured and cannot be modified. also, automatic mode does not require any additional hardware, software drivers or interrupt handling routines.
intel ? pentium ? 4 processor in the 423-pin package 79 the tcc may also be activated via on-demand mode. if bit 4 of the acpi thermal monitor control register is written to a ?1? the tcc will be activated immediately, independent of the processor temperature. when using on-demand mode to activate the tcc, the duty cycle of the clock modulation is programmable via bits 3:1 of the same acpi thermal monitor control register. in automatic mode, the duty cycle is fixed at 50% on, 50% off, however in on-demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. on-demand mode may be used at the same time automatic mode is enabled, however, if the system tries to enable the tcc via on-demand mode at the same time automatic mode is enabled and a high temperature condition exists, the 50% duty cycle of the automatic mode will override the duty cycle selected by the on-demand mode. an external signal, prochot# (processor hot) is asserted any time the tcc is active (either in automatic or on-demand mode). bus snooping and interrupt latching are also active while the tcc is active. the temperature at which the thermal control circuit activates is not user configurable and is not software visible. besides the thermal sensor and thermal control circuit, the thermal monitor feature also includes one acpi register, one performance counter register, three model specific registers (msr), and one i/o pin (prochot#). all are available to monitor and control the state of the thermal monitor feature. thermal monitor can be configured to generate an interrupt upon the assertion or de- assertion of prochot# (i.e. upon the activation/deactivation of tcc). if automatic mode is disabled the processor will be operating out of specification and cannot be guaranteed to provide reliable results. regardless of enabling of the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 135 c. at this point the system bus signal thermtrip# will go active and stay active until the processor has cooled down and reset# has been initiated. thermtrip# activation is independent of processor activity and does not generate any bus cycles. 7.3.1 thermal diode the pentium 4 processor incorporates an on-die thermal diode. a thermal sensor located on the system board may monitor the die temperature of the pentium 4 processor for thermal management/long term die temperature change purposes. table 35 and table 36 provide the diode parameter and interface specifications. this thermal diode is separate from the thermal monitor?s thermal sensor and cannot be used to predict the behavior of the thermal monitor. notes: 1. not 100% tested. specified by design characterization. 2. intel does not support or recommend operation of the thermal diode under reverse bias. 3. at room temperature with a forward bias of 630 mv. 4. n_ideality is the diode ideality factor parameter, as represented by the diode equation: i=io(e (vd*q)/(nkt) - 1). table 35. thermal diode parameters symbol min typ max unit notes 1 i forward bias 5 450 ua 2 n_ideality 0.9933 1.0045 1.0368 3, 4
intel ? pentium ? 4 processor in the 423-pin package 80 table 36. thermal diode interface pin name pin number pin description thermda h38 diode anode thermdc e39 diode cathode
intel ? pentium ? 4 processor in the 423-pin package 81 8.0 boxed processor specifications 8.1 introduction the intel ? pentium ? 4 processor in the 423-pin package is also offered as an intel boxed processor. intel boxed processors are intended for system integrators who build systems from system boards and components. the boxed pentium 4 processor will be supplied with a cooling solution. this chapter documents platform and system requirements for the cooling solution that will be supplied with the boxed pentium 4 processor. this chapter is particularly important for oems that manufacture platforms for system integrators. unless otherwise noted, all figures in this chapter are dimensioned in millimeters and in inches [in brackets]. figure 28 shows a mechanical representation of a boxed pentium 4 processor. *note* drawings in this section reflect only the specifications on the intel boxed processor product. these dimensions should not be used as a generic keep-out zone for all cooling solutions. it is the system designer's responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platform and chassis. note: the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. 8.2 mechanical specifications this section documents the mechanical specifications of the boxed pentium 4 processor fan heatsink. figure 28. mechanical representation of the boxed pentium 4 processor
intel ? pentium ? 4 processor in the 423-pin package 82 8.2.1 boxed processor fan heatsink dimensions the boxed processor will be shipped with an unattached fan heatsink. clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling (see figure 33 and figure 34). the physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in figure 29 (side views), and figure 30 (top view). the airspace requirements for the boxed processor fan heatsink must also be incorporated into new platform and system designs. airspace requirements are shown in figure 33 and figure 34. note that some figures have datum shown (marked with alphabetic designations) to clarify relative dimensioning. figure 29. side view space requirements for the boxed processor
intel ? pentium ? 4 processor in the 423-pin package 83 8.2.2 boxed processor fan heatsink weight the boxed processor fan heatsink will not weigh more than 450 grams. see chapter 4.0 and the intel ? pentium ? 4 processor thermal design guidelines for details on the processor weight and heatsink requirements. the boxed pentium 4 processor requires direct-attach of the retention mechanism to the chassis wall, as described in the intel ? pentium ? 4 processor thermal- mechanical design guide . 8.2.3 boxed processor retention mechanism and fan heatsink supports the boxed processor requires processor retention mechanisms to secure the processor in the baseboard socket. the boxed processor will not ship with retention mechanisms, or cooling solution retention clips. platforms designed for use by system integrators should include retention mechanisms, and clips that support the boxed pentium 4 processor. system board documentation should include appropriate retention mechanism installation instructions. figure 30. top view space requirements for the boxed processor
intel ? pentium ? 4 processor in the 423-pin package 84 8.3 boxed processor requirements 8.3.1 fan heatsink power supply the boxed processor's fan heatsink requires a +12v power supply. a fan power cable will be shipped with the boxed processor to draw power from a power header on the system board. the power cable connector and pinout are shown in figure 31. platforms must provide a matched power header to support the boxed processor. table 37 contains specifications for the input and output signals at the fan heatsink connector. the fan heatsink outputs a sense signal, which is an open-collector output that pulses at a rate of two pulses per fan revolution. a system board pull-up resistor provides voh to match the system board-mounted fan speed monitor requirements, if applicable. use of the sense signal is optional. if the sense signal is not used, pin 3 of the connector should be tied to gnd. the power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. the power header identification and location should be documented in the platform documentation, or on the system board itself. figure 32 shows the location of the fan power connector relative to the processor socket. the system board power header should be positioned within 4.33 inches from the center of the processor socket. note: 1. system board should pull this pin up to v cc with a resistor. figure 31. boxed processor fan heatsink power cable connector description table 37. fan heatsink power and signal specifications description min typ max unit notes +12v: 12 volt fan power supply 10.2 12 13.8 v ic: fan current draw 300 ma sense: sense frequency 2 pulses/ rev 1
intel ? pentium ? 4 processor in the 423-pin package 85 8.4 thermal specifications this section describes the cooling requirements of the fan heatsink solution utilized by the boxed processor. 8.4.1 boxed processor cooling requirements the boxed processor may be directly cooled with a fan heatsink. however, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. the processor temperature specification is found in chapter 6.0 of this document. the boxed processor fan heatsink is able to keep the processor temperature within the specifications (see table 33) in chassis that provide good thermal management. for the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. figure 33 and figure 34 illustrate an acceptable airspace clearance for the fan heatsink. the air temperature entering the fan should be kept below 40c. again, meeting the processor's temperature specification is the responsibility of the system integrator. figure 32. acceptable system board power header placement relative to processor socket
intel ? pentium ? 4 processor in the 423-pin package 86 figure 33. boxed processor fan heatsink airspace keepout requirements (side 1 view) figure 34. boxed processor fan heatsink airspace keepout requirements (side 2 view)
intel ? pentium ? 4 processor in the 423-pin package 87 8.4.2 variable speed fan the boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. this allows the processor fan to operate at a lower speed while internal chassis temperatures are low. if internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the upper set point is reached. at that point, the fan speed is at its maximum. as fan speed increases, so does fan noise levels. systems should be designed to provide adequate air around the boxed processor fan heatsink that remains below the lower set point. these set points, represented in figure 35 and table 38, can vary by a few degrees from fan heatsink to fan heatsink. notes: 1. set points may vary 1 c. the internal chassis temperature should be kept below 40c. when the internal chassis temperature increases above 45c, the thermal monitor may become active (see section 7.3). meeting the processor's temperature specification (see chapter 6.0) is the responsibility of the system integrator. figure 35. boxed processor fan heatsink set points table 38. boxed processor fan heatsink set points boxed processor fan heatsink set point ( c) boxed processor fan speed 36 when the internal chassis temperature is below this set point the fan operates at its lowest speed. recommended maximum internal chassis temperature for nominal operating environment. 40 when the internal chassis temperature is at this point the fan operates between its lowest and highest speeds. recommended maximum internal chassis temperature for worst case operating environment. 45 when the internal chassis temperature is above this set point the fan operates at its highest speed.
intel ? pentium ? 4 processor in the 423-pin package 88
intel ? pentium ? 4 processor in the 423-pin package 89 9.0 debug tools specifications 9.1 logic analyzer interface (lai) intel is working with two logic analyzer vendors to provide logic analyzer interfaces (lais) for use in debugging pentium 4 processor systems. tektronix* and agilent* should be contacted to get specific information about their logic analyzer interfaces. the following information is general in nature. specific information must be obtained from the logic analyzer vendor. due to the complexity of pentium 4 processor systems, the lai is critical in providing the ability to probe and capture system bus signals. there are two sets of considerations to keep in mind when designing a pentium 4 processor system that can make use of an lai: mechanical and electrical. 9.1.1 mechanical considerations the lai is installed between the processor socket and the pentium 4 processor. the lai pins plug into the socket, while the pentium 4 processor pins plug into a socket on the lai. cabling that is part of the lai egresses the system to allow an electrical connection between the pentium 4 processor and a logic analyzer. the maximum volume occupied by the lai, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. system designers must make sure that the keepout volume remains unobstructed inside the system. note that it is possible that the keepout volume reserved for the lai may include space normally occupied by the pentium 4 processor heatsink. if this is the case, the logic analyzer vendor will provide a cooling solution as part of the lai. 9.1.2 electrical considerations the lai will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. contact the logic analyzer vendor for electrical specifications and load models for the lai solution they provide.
intel ? pentium ? 4 processor in the 423-pin package 90

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