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exar coporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7200 ? www.exar.com ? ? ? ? preliminary XRT73L02A 2 channel e3/ds3/sts-1 line interface unit november 2001 rev. 2.0.0 general description the XRT73L02A dual channel e3/ds3/sts-1 trans- ceiver is an improved version of the xrt73l02 and consists of two fully integrated transmitter and receiv- er line transceivers designed for e3, ds3 or sonet sts-1 applications. each channel can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or the sonet sts-1 (51.84 mbps) rates. each channel can be con- figured to operate in a mode/data rate that is indepen- dent of the other channel. in the transmit direction, each channel in the XRT73L02A encodes input data to either b3zs or hdb3 format and converts the data into the appropri- ate pulse shapes for transmission over coaxial cable via a 1:1 transformer. in the receive direction, the XRT73L02A can perform equalization on incoming signals, perform clock re- covery, decode data from either b3zs or hdb3 for- mat, convert the receive data into ttl/cmos format, check for los or lol conditions and detect and de- clare the occurrence of line code violations. features ? incorporates an improved timing recovery circuit and is pin and functional compatible to xrt73l02 ? meets e3/ds3/sts-1 jitter tolerance require- ments ? contains a 4-wire microprocessor serial interface ? full loop-back capability ? transmit and receive power down modes ? full redundancy support ? single +3.3v power supply ? uses minimum external components ? operates over -40c to +85c temperature range ? available in an 80 pin tqfp package applications ? digital cross connect systems ? csu/dsu equipment ? routers ? fiber optic terminals ? multiplexers ? atm switches XRT73L02A block diagram agc/ equalizer serial processor interface peak detector los detector pulse shaping hdb3/ b3zs encoder transmit logic duty cycle adjust slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder sdi sdo sclk cs regr ttip_(n) tring_(n) rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) e3_ch_(n) sts-1/ds3_ch_(n) host/hw rlol_(n) exclk_(n) rxclkinv channel 0 channel 1 device monitor tx control txlev_(n) txoff_(n) dmo_(n) mtip_(n) mring_(n) endecdis notes: 1. (n) = 0 or 1 for the respective channel. 2. serial processor interface pins are shared by both channels in host mode and are redefined in hardware mode. losthr_(n) rxoff_(n)
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 2 transmit interface characteristics ? accepts either single-rail or dual-rail data from terminal equipment and generates a bipolar signal ? integrated pulse shaping circuit ? built-in b3zs/hdb3 encoder (which can be dis- abled) ? contains transmit clock duty cycle correction cir- cuit on-chip ? generates pulses that comply with the itu-t g.703 pulse template (e3 applications) ? generates pulses that comply with the dsx-3 pulse template, as specified in bellcore gr-499 -core and ansi t1.102_1993 ? generates pulses that comply with the stsx-1 pulse template, as specified in bellcore gr-253- core ? transmitter can be turned off in order to support redundancy designs receive interface characteristics ? integrated adaptive receive equalization (optional) and timing recovery ? declares and clears the los alarm per itu-t g.775 requirements for e3 and ds3 applications ? meets jitter tolerance requirements, as specified in itu-t g.823_1993 for e3 applications ? meets jitter tolerance requirements, as specified in bellcore gr-499-core for ds3 applications ? declares loss of signal (los) and loss of lock (lol) alarms ? built-in b3zs/hdb3 decoder (which can be dis- abled) ? recovered data can be automatically muted while the los condition is declared ? outputs either single-rail or dual-rail data to the terminal equipment ? receiver can be powered down in order to con- serve power in redundancy designs pin out of the XRT73L02A txlev_0 taos_0 dvdd_0 dmo_0 dgnd_0 agnd_0 dvdd_0 host/(hw) rxclk_0 rneg_0 rpos_0 dgnd_0 rlos_0 lcv_0 rlol_0 exclk_0 cs/(endecdis) sclk/(rxoff_1) sdi/(rxoff_0) sdo/(e3_ch_0) sts-1/ds3_ch_0 ict losthr_0 llb_0 rlb_0 avdd_0 rring_0 rtip_0 agnd_0 reqen_0 reqen_1 agnd_1 rtip_1 rring_1 avdd_1 rlb_1 llb_1 losthr_1 e3_ch_1 sr/dr txlev_1 taos_1 dvdd_1 dmo_1 dgnd_1 agnd_1 dvdd_1 losmuten rxclk_1 rneg_1 rpos_1 dgnd_1 rlos_1 lcv_1 rlol_1 exclk_1 vdd gnd regr/(rxclkinv) sts-1/ds3_ch_1 XRT73L02A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 txoff_0 txclk_0 tpdata_0 tndata_0 mtip_0 mring_0 avdd_0 ttip_0 tring_0 agnd_0 agnd_1 tring_1 ttip_1 avdd_1 mring_1 mtip_1 tndata_1 tpdata_1 txclk_1 txoff_1
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XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 i table of contents general description ........................................................................................................... 1 features ...................................................................................................................... .......................... 1 applications .................................................................................................................. ....................... 1 XRT73L02A block diagram ....................................................................................................... .......... 1 transmit interface characteristics ........................................................................................ 2 receive interface characteristics ........................................................................................... 2 pin out of the XRT73L02A ...................................................................................................... ............ 2 t able of c ontents ......................................................................................................................... i pin descriptions .............................................................................................................. ... 3 electrical characteristics ................................................................................. 13 absolute maximum ratings ................................................................................................... 1 3 figure 1.transmit pulse amplitude test circuit for e3, ds3 and sts-1 rates (typical channel shown) ...... 15 figure 2.timing diagram of the transmit terminal input interface .............................................................. .. 15 figure 3.timing diagram of the receive terminal output interface .............................................................. 15 figure 4.itu-t g.703 transmit output pulse template for e3 applications .................................................. 19 figure 5.bellcore gr-499-core transmit output pulse template for ds3 applications ............................. 19 figure 6.bellcore gr-253-core transmit output pulse template for sonet sts-1 applications ............ 20 figure 7.microprocessor serial interface data structure ....................................................................... ........ 20 figure 8.timing diagram for the microprocessor serial interface ............................................................... ... 21 system description ................................................................................................... 22 the transmit section - channels 0 and 1 ................................................................................ 22 the receive section - channels 0 and 1 ................................................................................... 22 the microprocessor serial interface ................................................................................... 22 table 1:role of microprocessor serial interface pins when the XRT73L02A is in the hardware mode ......... 22 figure 9.functional block diagram of the XRT73L02A ............................................................................ ...... 23 1.0 selecting the data rate ................................................................................................... ............ 23 1.1 c onfiguring c hannel ( n ) ................................................................................................................. 23 table 2:addresses and bit formats of the XRT73L02A command registers ............................................... 24 table 3:selecting the data rate for channel (n) of the XRT73L02A, via the e3_ch_(n) and sts-1/ds3_ch_(n) input pins (hardware mode) .................................................................................................... .......... 24 command register cr4-(n) .................................................................................................... 25 table 4:selecting the data rate for channel (n) of the XRT73L02A via the sts-1/ds3_ch_(n) and the e3_ch_(n) bit-fields in the appropriate command register (host mode) ...................................... 25 2.0 the transmit section ...................................................................................................... ................ 25 2.1 t he t ransmit l ogic b lock ............................................................................................................... 25 2.1.1accepting dual-rail data from the terminal equipment ........................................................ 25 figure 10. the typical interface for data transmission in dual-rail format from the transmitting terminal equipment to the transmit section of a channel of the XRT73L02A ............................................... 26 figure 11.how the XRT73L02A samples the data on the tpdata and tndata input pins ............................ 26 2.1.2configure channel (n) to accept single-rail data from the terminal equipment .................. 26 command register cr1-(n) ..................................................................................................... 26 figure 12.the behavior of the tpdata and txclk input signals while the transmit logic block is accepting sin- gle-rail data from the terminal equipment ..................................................................................... 27 2.2 t he t ransmit c lock d uty c ycle a djust c ircuitry ....................................................................... 27 2.3 t he hdb3/b3zs e ncoder b lock ..................................................................................................... 27
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 ii 2.3.1b3zs encoding ............................................................................................................ ........... 27 figure 13.an example of b3zs encoding ......................................................................................... ............. 28 2.3.2hdb3 encoding ............................................................................................................ ........... 28 figure 14.an example of hdb3 encoding ......................................................................................... ............. 28 2.3.3disabling the hdb3/b3zs encoder ........................................................................................ 2 8 command register cr2-(n) ..................................................................................................... 28 2.4 t he t ransmit p ulse s haping c ircuitry ........................................................................................... 29 figure 15.the bellcore gr-499-core transmit output pulse template for ds3 applications .................... 29 figure 16.the bellcore gr-253-core transmit output pulse template for sonet sts-1 applications .... 30 2.4.1enabling the transmit line build-out circuit .......................................................................... 30 command register cr1-(n) ..................................................................................................... 30 2.4.2disabling the transmit line build-out circuit ......................................................................... 30 command register cr1-(n) ..................................................................................................... 31 2.4.3design guideline for setting the transmit line build-out circuit ........................................... 31 2.4.4the transmit line build-out circuit and e3 applications ....................................................... 31 2.5 i nterfacing the t ransmit s ections of the XRT73L02A to the l ine ............................................. 31 figure 17.recommended schematic for interfacing the transmit section of the XRT73L02A to the line .... 31 transformer recommendations ........................................................................................ 32 3.0 the receive section ....................................................................................................... .................. 33 3.1 i nterfacing the r eceive s ections of the XRT73L02A to the l ine ............................................... 33 figure 18.recommended schematic for transformer-coupling the receive section of the XRT73L02A to the line .......................................................................................................................... ......................... 33 figure 19.recommended schematic for capacitive-coupling the receive section of the XRT73L02A to the line 33 3.2 t he r eceive e qualizer b lock .......................................................................................................... 34 figure 20.the typical application for the system installer .................................................................... ......... 34 command register cr2_(n)) ................................................................................................... 35 3.3 p eak d etector and s licer ............................................................................................................... 35 3.4 c lock r ecovery pll ........................................................................................................................ 3 5 3.4.1the training mode ........................................................................................................ .......... 35 3.4.2the data/clock recovery mode ............................................................................................. 35 3.5 t he hdb3/b3zs d ecoder ................................................................................................................. 35 3.5.1b3zs decoding ds3/sts-1 applications ............................................................................... 35 figure 21.an example of b3zs decoding ......................................................................................... ............. 36 3.5.2hdb3 decoding e3 applications ............................................................................................ . 36 figure 22.an example of hdb3 decoding ......................................................................................... ............. 36 3.5.3configuring the hdb3/b3zs decoder ..................................................................................... 36 command register cr2-(n) ..................................................................................................... 37 3.6 los d eclaration /c learance ........................................................................................................... 37 3.6.1the los declaration/clearance criteria for e3 applications .................................................. 37 figure 23.the signal levels at which the XRT73L02A declares and clears los .......................................... 38 figure 24.the behavior of the los output indicator in response to the loss of signal and the restoration of signal ........................................................................................................................ ........................ 38 3.6.2the los declaration/clearance criteria for ds3 and sts-1 applications ............................. 39 table 5:the alos (analog los) declaration and clearance thresholds for a given setting of losthr and
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XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 iii reqen for ds3 and sts-1 applications .......................................................................................... 39 command register cr0-(n) ..................................................................................................... 39 command register cr2-(n) ..................................................................................................... 40 command register cr0-(n) ..................................................................................................... 40 command register cr2-(n) ..................................................................................................... 40 3.6.3muting the recovered data while the los is being declared ................................................ 40 command register cr3-(n) ..................................................................................................... 41 3.7 r outing r ecovered t iming and d ata i nformation to the r eceiving t erminal e quipment ......... 41 3.7.1routing dual-rail format data to the receiving terminal equipment .................................. 41 figure 25.the typical interface for the transmission of data in a dual-rail format from the receive section of the XRT73L02A to the receiving terminal equipment .................................................................... 41 figure 26.how the XRT73L02A outputs data on the rpos and rneg output pins ...................................... 42 figure 27.the behavior of the rpos, rneg and rxclk signals when rxclk is inverted ............................. 42 command register cr3-(n) ..................................................................................................... 43 3.7.2routing single-rail format (binary data stream) data to the receive terminal equipment 43 command register cr3-(n) ..................................................................................................... 43 figure 28.the typical interface for data transmission in a single-rail format from the receive section of the XRT73L02A to the receiving terminal equipment .......................................................................... 43 figure 29.the behavior of the rpos and rxclk output signals while the XRT73L02A is transmitting single-rail data to the receiving terminal equipment ...................................................................................... 44 3.8 s hutting off the r eceive s ection ................................................................................................. 44 command register cr3-(n) ..................................................................................................... 44 4.0 diagnostic features of the XRT73L02A ................................................................................... 45 4.1 t he a nalog l ocal l oop -b ack m ode ............................................................................................... 45 figure 30. a channel in the XRT73L02A operating in the analog local loop-back mode ............................ 45 command register cr4-(n) ..................................................................................................... 45 4.2 t he d igital l ocal l oop -b ack m ode . ............................................................................................... 46 figure 31.the digital local loop-back path in a given channel of the XRT73L02A ...................................... 46 command register cr4-(n) ..................................................................................................... 46 4.3 t he r emote l oop -b ack m ode .......................................................................................................... 47 figure 32.the remote loop-back path in a given XRT73L02A channel ...................................................... 47 command register cr4-( n ) ..................................................................................................... 47 4.4 t x off f eatures .............................................................................................................................. . 47 command register cr1-(n) ..................................................................................................... 48 table 6:the relationship between the txoff input pin, the txoff bit field and the state of the transmitter 48 4.5 t he t ransmit d rive m onitor f eatures .......................................................................................... 48 figure 33.the XRT73L02A employing the transmit drive monitor features ................................................. 48 4.6 t he taos (t ransmit a ll o ne s) f eature ........................................................................................ 49 5.0 the microprocessor serial interface ................................................................................... 49 5.1 d escription of the c ommand r egisters ........................................................................................ 49 command register cr1-(n) ..................................................................................................... 49 table 7:addresses and bit formats of XRT73L02A command registers ..................................................... 50
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 iv 5.2 d escription of b it -f ields for each c ommand r egister ................................................................ 50 5.2.1command register - cr0-(n) ............................................................................................... .. 50 command register cr0-(n) ..................................................................................................... 50 command register cr1-(n) ..................................................................................................... 51 5.2.3command register cr2-(n) ................................................................................................. .. 52 command register cr2-(n) ..................................................................................................... 52 command register cr3-(n) ..................................................................................................... 52 command register cr4-(n) ..................................................................................................... 53 table 8:contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for channel (n) ........... 54 5.3 o perating the m icroprocessor s erial i nterface . ........................................................................ 54 figure 34.microprocessor serial interface data structure ...................................................................... ........ 55 figure 35.timing diagram for the microprocessor serial interface .............................................................. ... 56 ordering information ...................................................................................................... 57 package dimensions ....................................................................................................... 57 revision history .............................................................................................................. ................. 58
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 3 pin descriptions pin description p in #s ignal n ame t ype d escription 1 txlev_0 i transmit line build-out enable/disable select - channel 0: this input pin is used to enable or disable the transmit line build-out circuit of channel 0. setting this pin to "high" disables the line build-out circuit of channel 0. in this mode, channel 0 outputs partially-shaped pulses onto the line via the ttip_0 and tring_0 output pins. setting this pin to "low" enables the line build-out circuit of channel 0. in this mode, channel 0 outputs shaped pulses onto the line via the ttip_0 and tring_0 output pins. to comply with the isolated dsx-3/stsx-1 pulse template requirements per bellcore gr-499-core or bellcore gr-253-core: 1. set this input pin to "1" if the cable length between the cross-connect and the transmit output of channel 0 is greater than 225 feet. 2. set this input pin to "0" if the cable length between the cross-connect and the transmit output of channel 0 is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT73L02A is configured to operate in either the ds3 or sonet sts- 1 modes. b. the XRT73L02A is configured to operate in the hardware mode . n ote : if the XRT73L02A is going to be operating in the host mode , this pin should be tied to gnd. 2taos_0i transmit all ones select - channel 0: a high" on this pin causes the transmit section of channel 0 to generate and transmit a continuous ami all 1s" pattern onto the line. the frequency of this "1s" pattern is determined by txclk_0. n otes : 1. this input pin is ignored if the XRT73L02A is operating in the host mode . 2. if the XRT73L02A is going to be operating in the host mode , this pin should be tied to gnd. 3 dvdd_0 **** transmit digital vdd (for transmitter 0) 4dmo_0o drive monitor output - channel 0: if no transmitted ami signal is present on mtip_0 and mring_0 input pins for 12832 txclk periods, then dmo_0 toggles and remains "high" until the next ami signal is detected. 5 dgnd_0 **** transmit digital gnd (for transmitter 0) 6agnd_0 analog gnd (substrate connection) - channel 0 7 dvdd_0 **** receive digital vdd (for receiver 0) 8host/(hw )i host/hardware mode select: this input pin is used to enable or disable the microprocessor serial interface (e.g., consisting of the sdi, sdo, sclk, and cs pins). setting this input pin "high" enables the microprocessor serial interface (e.g. configures the XRT73L02A to operate in the host mode ). in this mode, con- figure the XRT73L02A via the microprocessor serial interface. when the XRT73L02A is operating in the host mode , it ignores the states of many of the discrete input pins. setting this input pin "low" disables the microprocessor serial interface (e.g., configures the XRT73L02A to operate in the hardware mode ). in this mode, many of the external input control pins are functional.
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 4 9 rxclk_0 o receive clock output pin - channel 0: this output pin is the recovered clock signal from the incoming line signal for channel 0. the receive section of channel 0 outputs data via the rpos_0 and rneg_0 output pins on the rising edge of this clock signal. n ote : the receive section of channel 0 is configured to update the data on the rpos_0 and rneg_0 output pins on the falling edge of rxclk_0 by doing one of the following: a. operating in the hardware mode pull the rclkinv pin to "high". b. operating in the host mode write a "1" into the rclkinv bit-field within the command register. 10 rneg_0 o receive negative data output - channel 0: this output pin pulses "high" whenever channel 0 of the XRT73L02A has received a negative polarity pulse in the incoming line signal at the rtip_0/ rring_0 inputs. n ote : if the channel 0 b3zs/hdb3 decoder is enabled, then the zero sup- pression patterns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") are not reflected at this output. 11 rpos_0 o receive positive pulse output - channel 0: this output pin pulses "high" whenever channel 0 of the XRT73L02A has received a positive polarity pulse in the incoming line signal at the rtip_0/ rring_0 inputs. n ote : if the channel 0 b3zs/hdb3 decoder is enabled, the zero suppression patterns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") are not reflected at this output. 12 dgnd_0 **** receive digital gnd - channel 0 13 rlos_0 o receive loss of signal output indicator - channel 0: this output pin toggles "high" if channel 0 in the XRT73L02A has detected a loss of signal condition in the incoming line signal. the criteria the XRT73L02A uses to declare an los condition depends upon whether it is operating in the e3 or sts-1/ds3 mode. 14 lcv_0 o line code violation indicator - channel 0: whenever the receive section of channel 0 detects a line code violation, it pulses this output pin "high". this output pin remains "low" at all other times. n ote : the XRT73L02A outputs an nrz pulse via this output pin. it is advis- able to sample this output pin via the rxclk_0 clock output signal. 15 rlol_0 o receive loss of lock output indicator - channel 0: this output pin toggles "high" if channel 0 of the XRT73L02A has detected a loss of lock condition. channel 0 declares an lol (loss of lock) condition if the recovered clock frequency deviates from the reference clock frequency (available at the exclk_(n) input pin) by more than 0.5%. 16 exclk_0 i external reference clock input - channel 0: apply a 34.368 mhz clock signal for e3 applications, a 44.736 mhz clock sig- nal for ds3 applications or a 51.84 mhz clock signal for sonet sts-1 appli- cations. n otes : 1. it is permissible to use the same clock which is also driving the txclk input pin. 2. it is permissible to operate the two channels at different data rates. pin description p in #s ignal n ame t ype d escription
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 5 17 cs /(endecdis) i microprocessor serial interface - chip select input/encoder-decoder dis- able input: this pins functionality depends on whether the XRT73L02A is operating in the host or hardware mode. host mode - chip select input the local microprocessor must assert this pin (set it to "0") in order to enable communication with the XRT73L02A via the microprocessor serial interface. n ote : this pin is internally pulled high". hardware mode - encoder/decoder disable input setting this input pin "high" disables the b3zs/hdb3 encoder & decoder blocks in the XRT73L02A and configures it to transmit and receive the line sig- nal in an ami format. setting this input pin "low" enables the b3zs/hdb3 encoder & decoder blocks and configures it to transmit and receive the line signal in the b3zs for- mat for sts-1/ds3 operation or in the hdb3 format for e3 operation. n ote : if the XRT73L02A is operating in the hardware mode , this pin setting configures the b3zs/hdb3 encoder and decoder blocks for both channels. 18 sclk/(rxoff_1) i microprocessor serial interface clock signal/channel 1 receiver shut off input: the function of this pin depends on whether the XRT73L02A is operating in the host mode or in the hardware mode . host mode - microprocessor serial interface clock signal: this signal is used to sample the data on the sdi pin on the rising edge of this signal. additionally, during read operations the microprocessor serial inter- face updates the sdo output on the falling edge of this signal. hardware mode - channel 1 receiver shut off input pin: setting this input pin "high" shuts off the channel 1 receiver. setting this input pin "low" enables the receive section for full operation. 19 sdi/(rxoff_0) i serial data input for the microprocessor serial interface/channel 0 - receiver shut off input pin: the function of this input pin depends on whether the XRT73L02A is operating in the host mode or in the hardware mode . host mode - serial data input for the microprocessor serial interface: to read or write data into the command registers over the microprocessor serial interface, apply the read/write bit, the address values of the command registers and data value to be written during write operations to this pin. this input is sampled on the rising edge of the sclk pin. hardware mode - channel 0 receiver shut off input pin: setting this input pin high shuts off the channel 0 receiver. setting this input pin low enables the receive section for full operation. pin description p in #s ignal n ame t ype d escription
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 6 20 sdo/(e3_ch_0) i/o serial data output from the microprocessor serial interface/e3_mode select - channel 0: the function of this pin depends on whether the XRT73L02A is operating in the host mode or in the hardware mode . host mode operation - serial data output for the microprocessor serial inter- face: this pin serially outputs the contents of the specified command register dur- ing read operations. the data is updated on the falling edge of the sclk input signal and tri-stated upon completion of data transfer. hardware mode operation - e3 mode select - channel 0: this input pin is used to configure channel 0 in the XRT73L02A to operate in the e3 or sts/ds3 modes. setting this input pin to "high" configures channel 0 to operate in the e3 mode. setting this input pin to "low" configures channel 0 to operate in either the ds3 or sts-1 modes, depending upon the state of the sts-1/ds3 _ch_0 input pin. 21 sts-1/ds3 _ch_0 i sts-1/ds3 select input - channel 0: set this input pint to high for sts-1 and low for ds3 operation. the XRT73L02A ignores this pin if the e3_ch_0 pin is set to 1". this input pin is ignored if the XRT73L02A is operating in the host mode . if the XRT73L02A is operating in the host mode , the pin should be tied to gnd. 22 ict i in-circuit test input : setting this pin "low" causes all digital and analog outputs to go into a high- impedance state to allow for in-circuit testing. for normal operation, set this pin "high". n ote : this pin is internally pulled high". 23 losthr_0 i loss of signal threshold control - channel 0 : the voltage forced on this pin controls the input loss of signal threshold for channel 0. forcing the losthr_0 pin to gnd or vdd provides two settings. this pin must be set to the desired level upon power up and should not be changed during operation. n ote : this pin is only applicable during ds3 or sts-1 operations. 24 llb_0 i local loop-back - channel 0 : this input pin along with rlb_0 dictates the loop-back mode in which chan- nel 0 in the XRT73L02A is operating. a "high" on this pin with rlb_0 set to "low" configures channel 0 of the XRT73L02A to operate in the analog local loop-back mode. a "high" on this pin with rlb_0 set to "high" configures channel 0 of the XRT73L02A to operate in the digital local loop-back mode. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 25 rlb_0 i remote loop-back - channel 0: this input pin along with llb_0 dictates the loop-back mode in which chan- nel 0 in the XRT73L02A is operating. a "high" on this pin with llb_0 being set to low" configures channel 0 of the XRT73L02A to operate in the remote loop-back mode. a "high" on this pin with llb_0 also being set to "high" configures channel 0 of the XRT73L02A to operate in the digital local loop-back mode. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 26 avdd_0 **** receive analog vdd - channel 0: 27 rring_0 i receive ring input - channel 0: this input pin along with rtip_0 is used to receive the bipolar line signal from the remote ds3/e3 terminal. pin description p in #s ignal n ame t ype d escription
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 7 28 rtip_0 i receive tip input - channel 0: this input pin along with rring_0 is used to receive the bipolar line signal from the remote ds3/e3/sts-1 terminal. 29 agnd_0 **** receive analog gnd - channel 0 30 reqen_0 i receive equalization enable input - channel 0: setting this input pin "high" enables the internal receive equalizer of channel 0. setting this pin "low" disables the internal receive equalizer. the guide- lines for enabling and disabling the receive equalizer are described in section 3.2. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 31 reqen_1 i receive equalization enable input - channel 1: setting this input pin "high" enables the internal receive equalizer of channel 1. setting this pin "low" disables the internal receive equalizer. the guide- lines for enabling and disabling the receive equalizer are described in section 3.2. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 32 agnd_1 **** receive analog gnd - channel 1 33 rtip_1 i receive tip input - channel 1: this input pin along with rring_1 is used to receive the bipolar line signal from the remote ds3/e3/sts-1 terminal. 34 rring_1 i receive ring input - channel 1: this input pin along with rtip_1 is used to receive the bipolar line signal from the remote ds3/e3 terminal. 35 avdd_1 **** receive analog vdd - channel 1 36 rlb_1 i remote loop-back - channel 1: this input pin along with llb_1 dictates the loop-back mode in which chan- nel 1 in the XRT73L02A is operating. a "high" on this pin with llb_1 being set to low" configures channel 1 of the XRT73L02A to operate in the remote loop-back mode. a "high" on this pin with llb_1 also being set to "high" configures channel 1 of the XRT73L02A to operate in the digital local loop-back mode. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 37 llb_1 i local loop-back - channel 1 : this input pin along with rlb_1 dictates the loop-back mode in which chan- nel 1 of the XRT73L02A is operating. a "high" on this pin with rlb_1 set to "low" configures channel 1 of the XRT73L02A to operate in the analog local loop-back mode. a "high" on this pin with rlb_1 set to "high" configures channel 1 of the XRT73L02A to operate in the digital local loop-back mode. n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 38 losthr_1 i loss of signal threshold control - channel 1 : the voltage forced on this pin controls the input loss of signal threshold for channel 1. forcing the losthr_1 pin to gnd or vdd provides two settings. this pin must be set to the desired level upon power up and should not be changed during operation. n ote : this pin is only applicable during ds3 or sts-1 operations. pin description p in #s ignal n ame t ype d escription
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 8 39 e3_ch_1 i e3 select input - channel 1: a "high" on this pin configures channel 1 of the XRT73L02A to operate in the e3 mode. a "low" on this pin configures channel 1 of the XRT73L02A to check the state of the sts-1/ds3 _ch_1 input pin n ote : this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 40 sr/dr i receive output single-rail/dual-rail select: setting this pin "high" configures the receive sections of all channels to out- put data in a single-rail mode to the terminal equipment. setting this pin "low" configures the receive section of all channels to output data in a dual-rail mode to the terminal equipment. 41 sts-1/ds3 _ch_1 i sts-1/ds3 select input - channel 1: set this pin to high for sts-1 and low for ds3 operation. the XRT73L02A ignores this pin if the e3_ch_1 pin is set to 1". this input pin is ignored if the XRT73L02A is operating in the host mode . if the XRT73L02A is operating in the host mode , the pin should be tied to gnd. 42 regr / (rxclknv) i register reset input pin (invert rxclk_(n)) output - select): the function of this pin depends upon whether the XRT73L02A is operating in the host mode or in the hardware mode . n ote : this pin is internally pulled "high". in the host-mode - register reset input pin: setting this input pin "low" causes the XRT73L02A to reset the contents of the command registers to their default settings and default operating configura- tion. in the hardware mode - invert rxclk output select: setting this input pin "high" configures the receive section of all channels in the XRT73L02A to invert their rxclk_(n) clock output signals and configures channel (n) to output the recovered data via the rpos_(n) and rneg_(n) output pins on the falling edge of rxclk_(n). setting this pin "low" configures channel (n) to output the recovered data via the rpos_(n) and rneg_(n) output pins on the rising edge of rxclk_(n). 43 gnd **** exclk reference gnd 44 vdd **** exclk reference vdd 45 exclk_1 i external reference clock input - channel 1: apply a 34.368 mhz clock signal for e3 applications, a 44.736 mhz clock sig- nal for ds3 applications or a 51.84 mhz clock signal for sonet sts-1 appli- cations. the clock recovery pll in channel 1 uses this signal as a reference signal for declaring and clearing the receive loss of lock alarm. n otes : 1. it is permissible to use the same clock which is also driving the txclk input pin. 2. it is permissible to operate the two channels at different data rates 46 rlol_1 o receive loss of lock output indicator - channel 1: this output pin toggles "high" if channel 1 of the XRT73L02A has detected a loss of lock condition. channel 1 declares an lol (loss of lock) condition if the recovered clock frequency deviates from the reference clock frequency (available at the exclk_(n) input pin) by more than 0.5%. pin description p in #s ignal n ame t ype d escription
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 9 47 lcv_1 o line code violation indicator - channel 1: whenever the receive section of channel 1 detects a line code violation, it pulses this output pin "high". this output pin remains "low" at all other times. n ote : the XRT73L02A outputs an nrz pulse via this output pin. it is advis- able to sample this output pin via the rxclk_1 clock output signal. 48 rlos_1 o receive loss of signal output indicator - channel 1: this output pin toggles "high" if channel 1 in the XRT73L02A has detected a loss of signal condition in the incoming line signal. the criteria the XRT73L02A uses to declare an los condition depends upon whether it is operating in the e3 or sts-1/ds3 mode. 49 dgnd_1 **** receive digital ground - channel 1 50 rpos_1 o receive positive data output - channel 1: this output pin pulses high" whenever channel 1 of the XRT73L02A has received a positive polarity pulse in the incoming line signal at the rtip_1/ rring_1 inputs. n ote : if the channel 1 b3zs/hdb3 decoder is enabled, then the zero sup- pression patterns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") is not reflected at this output. 51 rneg_1 o receive negative data output - channel 1: this output pin pulses "high" whenever channel 1 of the XRT73L02A has received a negative polarity pulse in the incoming line signal at the rtip_1/ rring_1 inputs. n ote : if the channel 1 b3zs/hdb3 decoder is enabled, then the zero sup- pression patterns in the incoming line signal (such as: "00v", "000v", "b0v", "b00v") is not reflected at this output. 52 rxclk_1 o receive clock output pin - channel 1: this output pin is the recovered clock signal from the incoming line signal for channel 1. the receive section of channel 1 outputs data via the rpos_1 and rneg_1 output pins on the rising edge of this clock signal. n ote : the receive section of channel 1 is configured to update the data on the rpos_1 and rneg_1 output pins on the falling edge of rxclk_1 by doing one of the following: a. operating in the hardware mode pull the rxclkinv pin to "high". b. operating in the host mode write a "1" into the rxclkinv bit-field of the command register. 53 losmuten i mute-upon-los enable input (hardware mode): this input pin is used to configure the XRT73L02A while it is operating in the hardware mode to mute the recovered data via the rpos_(n), rneg_(n) output pins whenever one of the channels declares an los condition. setting this input pin "high" configures all channels to automatically pull the rpos_(n) and rneg_(n) output pins to gnd whenever it is declaring an los condition, muting the data being output to the terminal equipment. setting this input pin "low" configures all channels to not automatically mute the recovered data whenever an los condition is declared. n otes : 1. this input pin is ignored and should be connected to gnd if the XRT73L02A is operating in the host mode . 2. this pin is internally pulled "high". 54 dvdd_1 **** receive digital vdd - channel 1 pin description p in #s ignal n ame t ype d escription
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 10 55 agnd_1 **** analog ground (substrate connection) - channel 1 56 dgnd_1 **** transmit digital gnd - channel 1 57 dmo_1 o drive monitor output - channel 1: if no transmitted ami signal is present on mtip_1 and mring_1 input pins for 12832 txclk periods, then dmo_1 toggles and remains "high" until the next ami signal is detected. 58 dvdd_1 **** transmit digital vdd - channel 1 59 taos_1 i transmit all ones select - channel 1: a high" on this pin causes the transmit section of channel 1 to generate and transmit a continuous ami all 1s" pattern onto the line. the frequency of this "1s" pattern is determined by txclk_1. n otes : 1. this input pin is ignored if the XRT73L02A is operating in the host mode . 2. if the XRT73L02A is going to be operating in the host mode , this pin should be tied to gnd. 60 txlev_1 i transmit line build-out enable/disable select - channel 1: this input pin is used to enable or disable the transmit line build-out circuit of channel 1. setting this pin to "high" disables the line build-out circuit of channel 1. in this mode, channel 1 outputs partially-shaped pulses onto the line via the ttip_1 and tring_1 output pins. setting this pin to "low" enables the line build-out circuit of channel 1. in this mode, channel 1 outputs shaped pulses onto the line via the ttip_1 and tring_1 output pins. to comply with the isolated dsx-3/stsx-1 pulse template requirements per bellcore gr-499-core or bellcore gr-253-core: 1. set this input pin to "1" if the cable length between the cross-connect and the transmit output of channel 1 is greater than 225 feet. 2. set this input pin to "0" if the cable length between the cross-connect and the transmit output of channel 1 is less than 225 feet. this pin is active only if the following two conditions are true: a. the XRT73L02A is configured to operate in either the ds3 or sonet sts- 1 modes. b. the XRT73L02A is configured to operate in the hardware mode . n ote : if the XRT73L02A is going to be operating in the host mode , this pin should be tied to gnd. 61 txoff_1 i transmitter off input - channel 1: setting this input pin "high" configures the XRT73L02A to turn off the transmit section of channel 1. in this mode, the ttip_1 and tring_1 outputs is tri- stated. n otes : 1. this input pin controls the ttip_1 and tring_1 outputs even when the XRT73L02A is operating in the host mode . 2. for host mode operation, tie this pin to gnd if the transmitter is intended to be turned off via the microprocessor serial interface. pin description p in #s ignal n ame t ype d escription
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 11 62 txclk_1 i transmit clock input for tpdata and tndata - channel 1: this input pin must be driven at 34.368 mhz for e3 applications, 44.736 mhz for ds3 applications or 51.84 mhz for sonet sts-1 applications. the XRT73L02A uses this signal to sample the tpdata_1 and tndata_1 input pins. by default, the XRT73L02A is configured to sample these two pins on the falling edge of this signal. if operating in the host mode , the XRT73L02A can be configured to sample the tpdata_1 and tndata_1 input pins on either the rising or falling edge of txclk_1. 63 tpdata_1 i transmit positive data input - channel 1 : the XRT73L02A samples this pin on the falling edge of txclk_1. if it samples a "1", then it generates and transmits a positive polarity pulse to the line. n otes : 1. the data should be applied to this input pin if the transmit section is configured to accept single-rail data from the terminal equipment. 2. if operating in the host mode , the XRT73L02A can be configured to sample the tpdata_1 pin on either the rising or falling edge of txclk_1. 64 tndata_1 i transmit negative data input - channel 1: the XRT73L02A samples this pin on the falling edge of txclk_1. if it samples a "1", then it generates and transmits a negative polarity pulse to the line. n otes : 1. this input pin is ignored and tied to gnd if the transmit section is con- figured to accept single-rail data from the terminal equipment. 2. if operating in the host mode , the XRT73L02A can be configured to sample the tndata_1 pin on either the rising or falling edge of txclk_1. 65 mtip_1 i monitor tip input - channel 1: the bipolar line output signal from ttip_1 is connected to this pin via a 270- ohm resistor to check for line driver failure. this pin is internally pulled "high". 66 mring_1 i monitor ring input - channel 1: the bipolar line output signal from tring_1 is connected to this pin via a 270- ohm resistor to check for line driver failure. this pin is internally pulled "high". 67 avdd_1 **** transmit analog vdd - channel 1: 68 ttip_1 o transmit ttip output - channel 1: the XRT73L02A uses this pin with tring_1 to transmit a bipolar line signal via a 1:1 transformer. 69 tring_1 o transmit ring output - channel 1: the XRT73L02A uses this pin with ttip_1 to transmit a bipolar line signal via a 1:1 transformer. 70 agnd_1 **** transmit analog gnd - channel 1 71 agnd_0 **** transmit analog gnd - channel 0 72 tring_0 o transmit ring output - channel 0: the XRT73L02A uses this pin with ttip_0 to transmit a bipolar line signal via a 1:1 transformer. 73 ttip_0 o transmit ttip output - channel 0: the XRT73L02A uses this pin with tring_0 to transmit a bipolar line signal via a 1:1 transformer. 74 avdd_0 **** transmit analog vdd - channel 0 pin description p in #s ignal n ame t ype d escription
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 12 75 mring_0 i monitor ring input - channel 0: the bipolar line output signal from tring_0 is connected to this pin via a 270- ohm resistor to check for line driver failure. this pin is internally pulled "high". 76 mtip_0 i monitor tip input - channel 0: the bipolar line output signal from ttip_0 is connected to this pin via a 270- ohm resistor to check for line driver failure. this pin is internally pulled "high". 77 tndata_0 i transmit negative data input - channel 0: the XRT73L02A samples this pin on the falling edge of txclk_0. if it samples a "1", then it generates and transmits a negative polarity pulse to the line. n otes : 1. this input pin is ignored and tied to gnd if the transmit section is con- figured to accept single-rail data from the terminal equipment. 2. if operating in the host mode , it can be configured to sample the tndata_0 pin on either the rising or falling edge of txclk_0. 78 tpdata_0 i transmit positive data input - channel 0 : the XRT73L02A samples this pin on the falling edge of txclk_0. if it samples a "1", then it generates and transmits a positive polarity pulse to the line. n otes : 1. the data should be applied to this input pin if the transmit section is configured to accept single-rail data from the terminal equipment. 2. if the XRT73L02A is operating in the host mode it can be configured to sample the tpdata_0 pin on either the rising or falling edge of txclk_0. 79 txclk_0 i transmit clock input for tpdata and tndata - channel 0: this input pin must be driven at 34.368 mhz for e3 applications, 44.736 mhz for ds3 applications or 51.84 mhz for sonet sts-1 applications. the XRT73L02A uses this signal to sample the tpdata_0 and tndata_0 input pins. by default, the XRT73L02A is configured to sample these two pins on the falling edge of this signal. if operating in the host mode , the XRT73L02A can be configured to sample the tpdata_0 and tndata_0 input pins on either the rising or falling edge of txclk_0. 80 txoff_0 i transmitter off input - channel 0: setting this input pin "high" configures the XRT73L02A to turn off the transmit section of channel 0. in this mode, the ttip_0 and tring_0 outputs is tri- stated. n otes : 1. this input pin controls the ttip_0 and tring_0 outputs even when the XRT73L02A is operating in the host mode . 2. for host mode operation, tie this pin to gnd if the transmitter is intended to be turned off via the microprocessor serial interface. pin description p in #s ignal n ame t ype d escription
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 13 electrical characteristics n ote : * not applicable to pins with pull-down resistors. absolute maximum ratings storage temperature - 65c to + 150c operating temperature - 40c to + 85c supply voltage range -0.5v to +6.0v theta-ja 23 c/w theta-jc 5.32 c/w e lectrical c haracteristics (t a = 25c, v dd = 3.3v + 5%, unless otherwise specified ) s ymbol p arameter m in . typ .m ax .u nits dc electrical characteristics v ddd dc supply voltage (digital) 3.135 3.3 3.465 v v dda dc supply voltage (analog) 3.135 3.3 3.465 v i cc supply current (measured while transmitting and receiving all "1s" ) 310 ma v il input low voltage 0.8 v v ih input high voltage 2.0 5.0 v v ol output low voltage, iout = -4.0ma 0 0.4 v v oh output high voltage, iout = 4.0ma 2.8 v i l input leakage current* 10 a
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 14 e lectrical c haracteristics (c ontinued ) (t a = 25c, v dd = 3.3v + 5%, unless otherwise specified ) ac e lectrical c haracteristics (s ee ? igure 1) t erminal s ide t iming p arameters ( see ? igure 2 and ? igure 3) s ymbol p arameter m in . typ .m ax .u nits txclk_(n) clock duty cycle (ds3/sts-1) 30 50 70 % txclk_(n) clock duty cycle (e3) 30 50 70 % txclk_(n) frequency (sonet sts-1) 51.84 mhz txclk_(n) frequency (ds3) 44.736 mhz txclk_(n) frequency (e3) 34.368 mhz t rtx txclk_(n) clock rise time (10% to 90%) 3.0 5.0 ns t ftx txclk_(n) clock fall time (90% to 10%) 3.0 5.0 ns t tsu tpdata/tndata to txclk_(n) falling set up time 3.0 1.5 ns t tho tpdata/tndata to txclk_(n) falling hold time 3.0 1.5 ns t lcvo rxclk_(n) to rising edge of lcv_(n) output delay 2.5 ns t tdy ttip_(n)/tring_(n) to txclk_(n) rising propagation delay time 8.0 ns rxclk_(n), rxclk_(n)clock duty cycle 50 % rxclk_(n), rxclk_(n) frequency (sonet sts-1) 51.84 mhz rxclk_(n), rxclk_(n) frequency (ds3) 44.736 mhz rxclk_(n), rxclk_(n) frequency (e3) 34.368 mhz t co rxclk_(n) to rpos_(n)/rneg_(n) delay time 2.5 ns t rrx rxclk_(n), rxclk_(n) clock rise time (10% to 90%) 1.5 ns t frx rxclk_(n), rxclk_(n) clock fall time (10% to 90%) 1.5 ns c i input capacitance 10 pf c l load capacitance 10 pf
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 15 f igure 1. t ransmit p ulse a mplitude t est c ircuit for e3, ds3 and sts-1 r ates ( typical channel shown ) f igure 2. t iming d iagram of the t ransmit t erminal i nput i nterface txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpos_(n) tneg_(n) txclk_(n) channel (n) t1 r1 31.6 w r2 31.6 w 1:1 75 w r3 tpdata or tndata ttip or tring tclk t tsu t tho t rtx t ftx t tdy f igure 3. t iming d iagram of the r eceive t erminal o utput i nterface rclk t rrx t frx rpos or rneg lcv t lcvo t co
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 16 e lectrical c haracteristics (c ontinued ), (t a = 25c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters e3 a pplication s ymbol p arameter m in .t yp .m ax u nits t ransmit c haracteristics ( see ? igure 1) transmit output pulse amplitude (measured at secondary output of transformer) 0.9 1.0 1.1 vpk transmit output pulse amplitude ratio 0.95 1.00 1.05 transmit output pulse width 12.5 14.55 16.5 ns transmit output pulse width ratio 0.95 1.00 1.05 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 uipp receive line characteristics receive sensitivity (length of cable) 1200 1400 feet interference margin -20 -15 db signal level to declare loss of signal -35 db signal level to clear loss of signal -15 db occurrence of los to los declaration time 10 255 ui termination of los to los clearance time 10 255 ui intrinsic jitter (all 1s pattern) 0.01 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 30 ui jitter tolerance @ jitter frequency = 10khz 4 ui jitter tolerance @ jitter frequency = 800khz 0.15 0.20 ui
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 17 e lectrical c haracteristics (c ontinued ), (t a = 25c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters s onet sts-1 a pplication s ymbol p arameter m in .t yp .m ax u nits transmit characteristics (see ?igure 1) transmit output pulse amplitude (measured with txlev=0) 0.68 0.75 0.85 vpk transmit output pulse amplitude (measured with txlev=1) 0.93 0.98 1.08 vpk transmit output pulse width 8.6 9.65 10.6 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 ui receive line characteristics receive sensitivity (length of cable) 900 1100 feet signal level to declare or clear loss of signal (see ta b l e 5 )mv intrinsic jitter (all 1s pattern) 0.03 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 400khz 0.15 0.35 ui
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 18 e lectrical c haracteristics (c ontinued ), (t a = 25 0 c, v dd = 3.3v + 5%, unless otherwise specified ) l ine s ide p arameters ds3 a pplication s ymbol p arameter m in .t yp .m ax u nits t ransmit c haracteristics ( see ? igure 1) transmit output pulse amplitude (measured at 0 feet, txlev=0) 0.68 0.75 0.85 vpk transmit output pulse amplitude (measured at 0 feet, txlev=1) 0.9 1.0 1.1 vpk transmit output pulse width 10.10 11.18 12.28 ns transmit output pulse amplitude ratio 0.9 1.0 1.1 transmit output jitter with jitter-free input @ txclk_(n) 0.02 0.05 ui receive line characteristics receive sensitivity (length of cable) 900 1100 feet receive intrinsic jitter (all 1s pattern) 0.01 ui receive intrinsic jitter (using prbs 2 23-1 pattern) 0.02 ui signal level to declare or clear loss of signal (see table 5) mv intrinsic jitter (all 1s pattern) 0.01 ui jitter tolerance @ jitter frequency = 100hz 64 ui jitter tolerance @ jitter frequency = 1khz 64 ui jitter tolerance @ jitter frequency = 10khz 5 ui jitter tolerance @ jitter frequency = 300khz -- (cat ii) 0.35 0.45 ui
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 19 ?igure 4, ?igure 5 and ?igure 6 present the pulse template requirements for the e3, ds3 and sts-1 rates. f igure 4. itu-t g.703 t ransmit o utput p ulse t emplate for e3 a pplications 0% 50% v = 100% 14.55ns nominal pulse 12.1ns (14.55 - 2.45) 17 ns (14.55 + 2.45) 8.65 ns 10% 10% 20% f igure 5. b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 20 n otes : 1. a4 and a5 are always "0". 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations 4. a shaded pulse, denotes a dont care value. f igure 6. b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a pplications sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve f igure 7. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 0 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 21 e lectrical c haracteristics (c ontinued ), (t a = 25 c, v dd = 3.3 + 5%, unless otherwise specified ) m icroprocessor s erial i nterface t iming (s ee ? igure 8) s ymbol p arameter m in .t yp .m ax u nits t 21 cs low to rising edge of sclk setup time 5 ns t 22 cs high to rising edge of sclk hold time 5 ns t 23 sdi to rising edge of sclk setup time 5 ns t 24 sdi to rising edge of sclk hold time 5 ns t 25 sclk "low" time 65 80 ns t 26 sclk "high" time 65 80 ns t 27 sclk period 160 ns t 28 cs low to rising edge of sclk hold time 5 ns t 29 cs "inactive" time 160 ns t 30 falling edge of sclk to sdo valid time 80 ns t 31 falling edge of sclk to sdo invalid time 65 ns t 32 falling edge of sclk, or rising edge of cs to high z 100 ns t 33 rise/fall time of sdo output 20 ns f igure 8. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 22 system description a functional block diagram of the XRT73L02A e3/ ds3/sts-1 transceiver ic is presented in figure 9. the XRT73L02A contains three independent trans- mitter and receiver sections and a common micropro- cessor interface section. the transmit section - channels 0 and 1 the transmit section of each channel accepts ttl/ cmos level signals from the terminal equipment in either a single-rail or dual-rail format. the transmit section takes this data and does the following: ? encode this data into the b3zs format if the ds3 or sonet sts-1 modes have been selected, or into the hdb3 format if the e3 mode has been selected. ? convert the cmos level b3zs or hdb3 encoded data into pulses with shapes that are compliant with the various industry standard pulse template requirements. ? drive these pulses onto the line via the ttip_(n) and tring_(n) output pins across a 1:1 trans- former. n ote : the transmit section drives a "1" (or a mark) onto the line by driving either a positive or negative polarity pulse across the 1:1 transformer in a given bit period. the trans- mit section drives a "0" (or a space) onto the line by driving no pulse onto the line. the receive section - channels 0 and 1 the receive section of each channel receives a bi- polar signal from the line via the rtip and rring sig- nals across a 1:1 transformer or a 0.01f capacitor. the receive section will do the following: ? adjust the signal level through an agc circuit. ? optionally equalize this signal for cable loss. ? route the sliced data to the hdb3/b3zs decoder, during which the original data content as transmit- ted by the remote terminal equipment is restored to its original content. ? the recovered clock and data outputs to the local terminal equipment in the form of cmos level sig- nals via the rpos_(n), rneg_(n) and rxclk_(n) output pins. the microprocessor serial interface the XRT73L02A contains two identical channels. the microprocessor interface inputs are common to both channels. the descriptions that follow refer to chan- nel (n) where (n) represents channel 0 or channel 1. the XRT73L02A can be configured to operate in ei- ther the hardware mode or the host mode. a. operating in the hardware mode the XRT73L02A can be configured to operate in the hardware mode by tying the host/(hw ) input pin to gnd. when the XRT73L02A is operating in the hardware mode, the following is true: 1. the microprocessor serial interface block is dis- abled. 2. the XRT73L02A is configured via input pin set- tings. each of the pins associated with the microprocessor serial interface takes on their alternative role as de- fined in table 1. when the XRT73L02A is operating in the hardware mode, all of the remaining input pins become active. b. operating in the host mode the XRT73L02A can be configured to operate in the host mode by tying the host/(hw ) input pin to vdd. when the XRT73L02A is operating in the host mode, the following is true: 1. the microprocessor serial interface block is enabled. writing the appropriate data into the on-chip command registers makes many config- uration selections. 2. all of the following input pins are disabled and should be connected to gnd. ? pins 1, 60 - txlev_(n) ? pins 2, 59 - taos_(n) ? pins 30, 31 - reqen_(n) ? pins 25, 36 - rlb_(n) ? pins 24, 37 - llb_(n) ? pin 39 - e3_ch_(n) ? pins 21, 41 - sts1/ds3 _ch_(n) t able 1: r ole of m icroprocessor s erial i nterface pins when the XRT73L02A is in the h ardware m ode p in #p in n ame f unction while in hardware mode 17 cs /(endecdis) endecdis 18 sclk/(rxoff_1) rxoff_1 19 sdi/(rxoff_0) rxoff_0 20 sdo/(e3_ch_0) e3_ch_0 42 regr /(rxclkinv) rxclkinv
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 23 in host mode operation, the txoff_(n) input pins can still be used to turn on or turn off the transmit output drivers in channels 0 and 1, respectively. the intent behind this feature is to permit a system designed for redundancy to quickly switch out a de- fective line card and switch-in the back-up line card. 1.0 selecting the data rate each channel in the XRT73L02A can be configured to support the e3 (34.368 mbps), ds3 (44.736 mbps) or sonet sts-1 (51.84 mbps) rates and to operate in a mode/data rate that is independent of the other chan- nel. two methods are available to select the data rate for each channel of the XRT73L02A. 1.1 c onfiguring c hannel (n) refer to table 2 to determine the appropriate address for each command register of each chan- nel in the XRT73L02A. the command register description refers to cr(m)-(n), where (m) = 0 to 7 and (n) refers to a particular channel of the XRT73L02A. f igure 9. f unctional b lock d iagram of the XRT73L02A endecdis rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) txlev_(n) txoff_(n) agc/ equalizer serial processor interface peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs regr rtip_(n) rring_(n) reqen_(n) channel 0 channel 1 notes: 1. (n) = 0 or 1 for the respective channel 2. serial processor interface input pins are shared by both channels in host mode and are redefined in hardware mode. device monitor mtip_(n) mring_(n) dmo_(n) transmit logic duty cycle adjust ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder e3_ch_(n) sts-1/ds3_ch_(n) host/(hw) rlol_(n) exclk_(n) rxoff rxclkinv rxclk_(n) rpos_(n) rneg_(n) lcv_(n) tx control
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 24 address: the register addresses presented in the hexadeci- mal format. type: the command registers are either read-only (ro) or read/write (r/w) type of registers. the default value for each of the bit-fields in these registers is "0". a. operating in the hardware mode to configure individual channel data rate, set the e3_ch_(n) and the sts-1/ds3 _ch_(n) input pins (where n = 0 or 1) to the appropriate logic states referenced in table 3. t able 2: a ddresses and b it f ormats of the XRT73L02A c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 c hannel 0 0x00 cr0-0 ro rlol_0 rlos_0 alos_0 dlos_0 dmo_0 0x01 cr1-0 r/w txoff_0 taos_0 txclkinv_0 txlev_0 txbin_0 0x02 cr2-0 r/w reserved endecdis_0 alosdis_0 dlosdis_0 reqen_0 0x03 cr3-0 r/w sr/(dr )_0 losmut_0 rxoff_0 rxclk_0inv reserved 0x04 cr4-0 r/w reserved sts-1/ds3 _ch_0 e3_ch_0 llb_0 rlb_0 0x05 cr5-0 r/w reserved reserved reserved reserved reserved 0x06 cr6-0 r/w reserved reserved reserved reserved reserved 0x07 cr7-0 r/w reserved reserved reserved reserved reserved c hannel 1 0x08 cr0-1 ro rlol_1 rlos_1 alos_1 dlos_1 dmo_1 0x09 cr1-1 r/w txoff_1 taos_1 txclkinv_1 txlev_1 txbin_1 0x0a cr2-1 r/w reserved endecdis_1 alosdis_1 dlosdis_1 reqen_1 0x0b cr3-1 r/w sr/(dr )_1 losmut_1 rxoff_1 rxclk_1inv reserved 0x0c cr4-1 r/w reserved sts-1/ds3_ ch_1 e3_ch_1 llb_1 rlb_1 0x0d cr5-1 r/w reserved reserved reserved reserved reserved 0x0e cr6-1 r/w reserved reserved reserved reserved reserved 0x0f cr7-1 r/w reserved reserved reserved reserved reserved t able 3: s electing the d ata r ate for c hannel (n) of the XRT73L02A, via the e3_c h _(n) and sts-1/ ds3 _c h _(n) input pins (h ardware m ode ) d ata r ate s tate of e3_c h _ (n) p in (p in 20 or 39) s tate of sts-1/ds3 _ch_ (n) p in (p in 21 or 41) m ode of b3zs/hdb3 e ncoder / d ecoder b locks e3 (34.368 mbps) 1 x (don't care) hdb3 ds3 (44.736 mbps) 0 0 b3zs sts-1 (51.84 mbps) 0 1 b3zs
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 25 b. operating in the host mode. to configure the data rate of a channel, write the appropriate values into the sts-1/ds3 _ch_(n) and e3_ch_(n) bit-fields in command register cr4-(n). n ote : reference table 2 for the correct address of each channel. table 4 relates the values of these two bit-fields to the selected data rates. making these selections does the following: ? configure the vco center frequency of channel (n) of the clock recovery phase-locked loop to match the selected data rate. ? if the ds3 or sts-1 data rates are selected, it con- figures the b3zs/(hdb3) encoder and decoder blocks to support b3zs encoding/decoding. ? if the e3 data rate is selected, it configures the b3zs/(hdb3) encoder and decoder blocks to sup- port hdb3 encoding/decoding. ? configure the on-chip pulse-shaping circuitry to generate transmit output pulses of the appropriate shape and width to meet the applicable pulse tem- plate requirement. ? establishes the los declaration/clearance criteria for channel (n) (section 3.5). 2.0 the transmit section figure 9 shows the transmit section in each channel of the XRT73L02A, consisting of the following blocks: ? transmit logic block ? txclk_(n) duty cycle adjust block ? hdb3/(b3zs) encoder ? pulse shaping block the purpose of the transmit section in each channel of the XRT73L02A is to take ttl/cmos level data from the terminal equipment and encode it into a for- mat that can: 1. be efficiently transmitted over coaxial cable at e3, ds3 or sts-1 data rates, 2. be reliably received by the remote terminal equipment at the other end of the e3, ds3 or sts-1 data link, and 3. comply with the applicable pulse template requirements. the circuitry that the transmit section in each chan- nel of the XRT73L02A takes to accomplish this goal is discussed below. 2.1 t he t ransmit l ogic b lock the purpose of the transmit logic block is to accept either dual-rail or single-rail (binary data stream) ttl/cmos level data and timing information from the terminal equipment. 2.1.1 accepting dual-rail data from the termi- nal equipment whenever the XRT73L02A accepts dual-rail data from the terminal equipment, it does so via the fol- lowing input signals: ? tpdata_(n) ? tndata_(n) ? txclk_(n) figure 10 illustrates the typical interface for the trans- mission of data in a dual-rail format between the terminal equipment and the transmit section of the XRT73L02A. command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/(ds3 )_(n) e3_ch_(n) llb_(n) rlb_(n) x x xxx t able 4: s electing the d ata r ate for c hannel (n) of the XRT73L02A via the sts-1/ds3 _c h _(n) and the e3_c h _(n) bit - fields in the a ppropriate c ommand r egister (host m ode ) s elected d ata r ate sts-1/ds3 _c h _(n) (d3) e3_c h _(n) (d2) e3 x (don't care) 1 ds3 0 0 sts-1 1 0
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 26 the manner that the liu handles dual-rail data is described below and illustrated in figure 11. the transmit section of a channel typically samples the data on the tpdata and tndata input pins on the fall- ing edge of txclk_(n). txclk_(n) is the clock signal that is of the selected data rate frequency for e3 = 34.368 mhz, ds3 = 44.736 mhz and sts-1 = 51.84 mhz. if the transmit section samples a 1" on the tpdata input pin, the transmit section of the XRT73L02A generates a pos- itive polarity pulse via the ttip_(n) and tring_(n) output pins across a 1:1 transformer. if the transmit section samples a "1" on the tndata input pin, then the transmit section ultimately generates a negative polarity pulse via the ttip_(n) and tring_(n) output pins across a 1:1 transformer. 2.1.2 configure channel (n) to accept single- rail data from the terminal equipment to transmit data in a single-rail data from the termi- nal equipment, configure the XRT73L02A in the host mode. write a "1" into the txbin_(n) (transmit binary) bit-field of command register cr1-(n) shown below. n ote : please refer to table 2 for the address of the individ- ual channel (n). the transmit section of each channel samples this input pin on the falling edge of the txclk_(n) clock signal and encodes this data into the appropriate bi- polar line signal across the ttip_(n) and tring_(n) output pins. f igure 10. t he typical interface for d ata t ransmission in d ual -r ail f ormat from the t ransmitting t erminal e quipment to the t ransmit s ection of a channel of the XRT73L02A terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu transmit logic block txpos txneg txlineclk tpdata tndata txclk f igure 11. h ow the XRT73L02A s amples the data on the tpd ata and tnd ata input pins txclk tpdata tndata data 1 1 0 command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) xx x x 1
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 27 n otes : 1. in this mode the transmit logic block ignores the tndata input pin. 2. if the transmit section of a given channel is config- ured to accept single-rail data from the terminal equipment, the b3zs/hdb3 encoder must be enabled. figure 12 illustrates the behavior of the tpdata and txclk_(n) signals when the transmit logic block has been configured to accept single-rail data from the terminal equipment. 2.2 t he t ransmit c lock d uty c ycle a djust c ir - cuitry the on-chip pulse-shaping circuitry in the transmit section of each channel of the XRT73L02A gener- ates pulses of the appropriate shapes and width to meet the applicable pulse template requirements. the widths of these output pulses are defined by the width of the half-period pulses in the txclk_(n) signal. however, if the widths of the pulses in the txclk_(n) clock signal are allowed to vary significantly, this could jeopardize the chip's ability to generate trans- mit output pulses of the appropriate width, thereby not meeting the pulse template requirement specifi- cation. consequently, the chip's ability to generate compliant pulses could depend upon the duty cycle of the clock signal applied to the txclk_(n) input pin. the transmit clock duty cycle adjust circuitry ac- cepts clock pulses via the txclk_(n) input pin at duty cycles ranging from 30% to 70% and converts them to a 50% duty cycle. 2.3 t he hdb3/b3zs e ncoder b lock the purpose of the hdb3/b3zs encoder block is to aid in the clock recovery process at the remote ter- minal equipment by ensuring an upper limit on the number of consecutive zeros that can exist in the line signal. 2.3.1 b3zs encoding if the XRT73L02A has been configured to operate in the ds3 or sonet sts-1 modes, the hdb3/b3zs encoder blocks operate in the b3zs mode. when the encoder is operating in this mode it parses through and searches the transmit binary data stream from the transmit logic block for the occurrence of three (3) consecutive zeros (e.g., "000"). if the b3zs en- coder finds an occurrence of three consecutive zeros, then it substitutes these three "0s" with either a "00v" or a "b0v" pattern. "b" represents a bipolar pulse that is compliant with the alternating polarity requirements of the ami (al- ternate mark inversion) line code. "v" represents a bipolar violation (e.g., a bipolar pulse that violates the alternating polarity require- ments of the ami line code). the b3zs encoder decides whether to substitute with either the "00v" or the "b0v" pattern in order to insure that an odd number of bipolar pulses exist be- tween any two consecutive violation pulses. figure 13 illustrates the b3zs encoder at work with two separate strings of three or more consecutive ze- ros. f igure 12. t he b ehavior of the tpd ata and t x c lk i nput s ignals while the t ransmit l ogic b lock is a ccepting s ingle -r ail d ata from the t erminal e quipment txclk tpdata data 1 1 0
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 28 2.3.2 hdb3 encoding if the XRT73L02A has been configured to operate in the e3 mode, the hdb3/b3zs encoder blocks oper- ate in the hdb3 mode. when the encoder is operat- ing in this mode it parses through and searches the transmit data stream from the transmit logic block for the occurrence of four (4) consecutive zeros ("0000"). if the hdb3 encoder finds an occurrence of four consecutive zeros then it substitutes these four "0s" with either a "000v" or a "b00v" pattern. the hdb3 encoder decides whether to substitute with ei- ther the "000v" or the "b00v" pattern in order to in- sure that an odd number of bipolar pulses exist be- tween any two consecutive violation pulses. figure 14 illustrates the hdb3 encoder at work with two separate strings of four or more consecutive ze- ros. 2.3.3 disabling the hdb3/b3zs encoder the XRT73L02A hdb3/b3zs encoder can be dis- abled by two methods. a. operating in the hardware mode. the hbd3/b3zs encoder blocks of all channels are disabled by setting the endecdis (encoder/ decoder disable) input pin to 0". n ote : by executing this step the hdb3/b3zs encoder and decoder blocks in all channels of the XRT73L02A are glo- bally disabled. b. operating in the host mode. when the XRT73L02A is operating in the host mode the hdb3/b3zs encoders in each channel can be individually enabled or disabled. disable the hdb3/b3zs encoder block in channel (n) by setting the endecdis_(n) bit-field in command register (cr2-(n)), to "1". f igure 13. a n e xample of b3zs e ncoding tclk tpos sr data encoded pdata encoded ndata 100 1 01 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 111 1 0 0 00 00000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 f igure 14. a n e xample of hdb3 e ncoding tclk tpos sr data encoded pdata encoded ndata 100 1 01 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 001 1 0 1 0 1 1 1 0 001 1 00 01 0100 0 0 0 00 0 0 0 1 11 11 000000000 0 1 0 0 0 0 01 01 01 01 01 01 01 01 1 10 10 1 0 10 1 0 1 line signal bv 0 v 0 0 0 0 command register cr2-(n) d4 d3 d2 d1 d0 reserved endecdis_(n) alosdis_(n) dlosdis_(n) reqen_(n) x 1xxx
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 29 if either of these two methods is used to disable the hdb3/b3zs encoder, the liu transmits the data as received via the tpdata and tndata input pins. 2.4 t he t ransmit p ulse s haping c ircuitry the transmit pulse shaper circuitry consists of a transmit line build-out circuit which can be enabled or disabled by setting the txlev_(n) input pin or txlev_(n) bit-field to "high" or "low". the purpose of the transmit line build-out circuit is to permit con- figuration of each channel in the XRT73L02A to trans- mit an output pulse which is compliant to either of the following pulse template requirements when mea- sured at the digital cross connect system. each of these bellcore specifications state that the cable length between the transmit output and the digital cross connect system can range anywhere from 0 to 450 feet. the isolated dsx-3 pulse template requirement per bellcore gr-499-core is illustrated in figure 15 and the isolated stsx-1 pulse template requirement per bellcore gr-253-core is illustrated in figure 16. f igure 15. t he b ellcore gr-499-core t ransmit o utput p ulse t emplate for ds3 a pplications ds3 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 tim e , in ui norm alized am plitude lower curve upper curve
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 30 . 2.4.1 enabling the transmit line build-out cir- cuit if the transmit line build-out circuit is enabled, the transmit section of channel (n) of the XRT73L02A outputs shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. enable the transmit line build-out circuit for each channel in the XRT73L02A by doing the following: a. operating in the hardware mode set the txlev_(n) input pin to "low" b. operating in the host mode set the txlev_(n) bit-field to "0". 2.4.2 disabling the transmit line build-out cir- cuit if the transmit line build-out circuit is disabled, the XRT73L02A outputs partially-shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. to disable the transmit line build-out circuit, do the following: a. operating in the hardware mode set the txlev_(n) input pin to "high". b. operating in the host mode set the txlev_(n) bit-field to "1" as illustrated below. f igure 16. t he b ellcore gr-253-core t ransmit o utput p ulse t emplate for sonet sts-1 a ppli - cations sts-1 pulse template -0.2 0 0.2 0.4 0.6 0.8 1 1.2 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 time, in ui normalized amplitude lower curve upper curve command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) 0x x 0x
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 31 2.4.3 design guideline for setting the transmit line build-out circuit the txlev_(n) input pins or bit-fields should be set based upon the overall cable length between the transmitting terminal and the digital cross connect system where the pulse template measurements are made. if the cable length between the transmitting ter- minal and the dsx-3 or stsx-1 is less than 225 feet, enable the transmit line build-out circuit by setting the txlev_(n) input pin or bit-field to "0". n ote : in this case, the configured channel outputs shaped (e.g., not square-wave) pulses onto the line via its ttip_(n) and tring_(n) output pins. the shape of this output pulse is such that it complies with the pulse template require- ments even when subjected to cable loss ranging from 0 to 225 feet. if the cable length between the transmitting ter- minal and the dsx-3 or stsx-1 is greater than 225 feet, disable the transmit line build-out circuit by setting the txlev_(n) input pin or bit-field to "1". n ote : in this case, the configured channel in the XRT73L02A outputs partially-shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. the cable loss that these pulses experience over long cable lengths (e.g., greater than 225 feet) causes these pulses to be properly shaped and comply with the appropriate pulse template requirement. 2.4.4 the transmit line build-out circuit and e3 applications the itu-t g.703 pulse template requirements for e3 states that the e3 transmit output pulse should be measured at the secondary side of the transmit out- put transformer for pulse template compliance. in other words, there is no digital cross connect sys- tem pulse template requirement for e3. consequent- ly, the transmit line build-out circuit in a given chan- nel in the XRT73L02A is disabled whenever that channel has been configured to operate in the e3 mode. 2.5 i nterfacing the t ransmit s ections of the XRT73L02A to the l ine the e3, ds3 and sonet sts-1 specification docu- ments all state that line signals transmitted over coax- ial cable are to be terminated with 75 ohm resistor. interface the transmit section of the XRT73L02A in the manner illustrated in figure 17 to accomplish this. command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) 0x x 1x f igure 17. r ecommended s chematic for i nterfacing the t ransmit s ection of the XRT73L02A to the l ine r1 31.6 w r2 31.6 w channel (n) txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpdata_(n) tndata_(n) txclk_(n) only one channel shown 1:1 j1 bnc
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 32 transformer vendor information pulse corporate office 12220 world trade drive san diego, ca 92128 tel: (858)-674-8100 fax: (858)-674-8262 europe 1 & 2 huxley road the surrey research park guildford, surrey gu2 5re united kingdom tel: 44-1483-401700 fax: 44-1483-401701 asia 150 kampong ampat #07-01/02 ka centre singapore 368324 tel: 65-287-8998 fax: 65-280-0080 website: http://www.pulseeng.com halo electronics corporate office p.o. box 5826 redwood city, ca 94063 tel: (650)568-5800 fax: (650)568-6165 email: info@haloelectronics.com website: http://www.haloelectronics.com transpower technologies, inc. corporate office park center west building 9805 double r blvd, suite # 100 reno, nv 89511 (800)500-5930 or (775)852-0140 email: info@trans-power.com website: http://www.trans-power.com transformer recommendations p arameter v alue turns ratio 1:1 primary inductance 40 m h isolation voltage 1500vrms leakage inductance 0.6 m h p art n umber v endor i nsulation p ackage t ype pe-68629 pulse 3000v large thru-hole pe-65966 pulse 1500v small thru-hole pe-65967 pulse 1500v small smt t3001 pulse 1500v small smt tg01-0406ns halo 1500v small smt tti 7601-sm trans-power 1500v small smt
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 33 3.0 the receive section figure 9 indicates that the receive section in the XRT73L02A consists of the following blocks: ? agc/equalizer ? peak detector ? slicer ? clock recovery pll ? data recovery ? hdb3/b3zs decoder the purpose of each receive section of the XRT73L02A is to take an incoming attenuated/distort- ed bipolar signal from the line and encode it back into the ttl/cmos format where it can be received and processed by the terminal equipment. 3.1 i nterfacing the r eceive s ections of the XRT73L02A to the l ine the design of the receive circuitry in the XRT73L02A allows for transformer-coupling or ca- pacitive-coupling of the receive section to the line. as mentioned earlier, the specification documents for e3, ds3 and sts-1 all specify 75 ohm termination loads when transmitting over coaxial cable. the rec- ommended method of transformer-coupling the re- ceive section of the XRT73L02A to the line is shown in figure 18 and the capacitive-coupling method is shown in figure 19. f igure 18. r ecommended s chematic for t ransformer -c oupling the r eceive s ection of the XRT73L02A to the l ine j1 bnc t1 1:1 r1 37.5 w r2 37.5 w channel (n) rxpos_(n) rxneg_(n) rxclk_(n) rtip_(n) rring_(n) rpos_(n) rneg_(n) rxclk_(n) c1 0.01uf only one channel shown f igure 19. r ecommended s chematic for c apacitive -c oupling the r eceive s ection of the XRT73L02A to the l ine r1 75 w j1 bnc channel (n) rxpos_(n) rxneg_(n) rxclk_(n) rtip_(n) rring_(n) rpos_(n) rneg_(n) rxclk_(n) c1 0.01uf only one channel shown c2 0.01uf
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 34 3.2 t he r eceive e qualizer b lock the purpose of this block is to equalize the incoming distorted signal due to cable loss. the receive equalizer attempts to restore the shape of the line signal so that the transmitted data and clock can be recovered reliably. ? design considerations for ds3 and sts-1 applications when installing equipment into environments depict- ed in figure 20, we recommend that the receive equalizer be enabled by setting the reqen_(n) input pin for channel (n) or the respective bit-fields to "1". the only time that the receive equalizer should be disabled is when an off-chip equalizer is in the re- ceive path between the digital cross-connect system and the rtip/rring input pins, or in applications where the receiver is monitoring the transmit output signal directly. ? design considerations for e3 applications or if the overall cable length is known figure 20 indicates the following: a. the length of cable between the transmitting ter- minal and the digital cross-connect system can range between 0 and 450 feet. b. the length of cable between the digital cross-con- nect system and the receive terminal can range be- tween 0 and 450 feet. consequently, the overall cable length between the transmitting terminal and the receiving terminal can range between very short cable length (e.g., near 0 feet) up to 900 feet. if during system installation the overall cable length is known, to optimize the performance of the XRT73L02A in terms of receive jitter performance, etc., enable or disable the receive equalizer based upon the following recommendations: the receive equalizer should be turned on if the receive section of a given channel is going to re- f igure 20. t he t ypical a pplication for the s ystem i nstaller digital cross-connect system transmitting terminal receiving terminal 0 to 450 feet of cable pulses that are compliant to the isolated dsx-3 or stsx-1 pulse template requirement 0 to 450 feet of cable dsx-3 or stsx-1
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 35 ceive a line signal with an overall cable length of 300 feet or greater. conversely, turn off the receive equalizer if the receive section of a given channel is going to receive a line signal with an overall cable length of less than 300 feet. n otes : 1. if the receive equalizer block is turned on when it is receiving a line signal over short cable length the received line signal may be over-equalized, which could degrade performance by increasing the amount of jitter that exists in the recovered data and clock signals or by creating bit-errors. 2. the receive equalizer has been designed to counter the frequency-dependent cable loss that a line signal experiences as it travels from the trans- mitting terminal to the receiving terminal. however, the receive equalizer was not designed to counter flat loss where all of the fourier frequency compo- nents within the line signal are subject to the same amount of attenuation. flat loss is handled by the agc block. disable the receive equalizer block by doing either of the following: a. operating in the hardware mode set the reqen_(n) input pin "low". b. operating in the host mode write a "0" to the reqen_(n) bit-field in command register cr2. 3.3 p eak d etector and s licer after the incoming line signal has passed through the receive equalizer block, it is routed to the slicer block. the slicer block quantifies a given bit-period (or symbol) within the incoming line signal as either a 1 or a 0. 3.4 c lock r ecovery pll the purpose of the clock recovery pll is to track the incoming dual-rail data stream and to derive and generate a recovered clock signal. it is important to note that the clock recovery pll re- quires a line rate clock signal at the exclk input pin. the clock recovery pll operates in one of two modes: ? the training mode ? the data/clock recovery mode 3.4.1 the training mode if a given channel in the XRT73L02A is not receiving a line signal via the rtip and rring input pins, or if the frequency difference between the line signal and that applied via the exclk input pin exceeds 0.5%, the channel operates in the training mode. when the channel is operating in the training mode, it does the following: a. declare a loss of lock indication by toggling its respective rlol_(n) output pin high". b. output a clock signal via the rxclk_(n) output pin which is derived from the signal applied to the exclk_(n) input pin. 3.4.2 the data/clock recovery mode if the frequency difference between the line signal and that applied via the exclk input pin is less than 0.5%, the channel operates in the data/clock recov- ery mode. in this mode, the clock recovery pll locks onto the line signal via the rtip and rring in- put pins. 3.5 t he hdb3/b3zs d ecoder the remote transmitting terminal typically encodes the line signal into some sort of zero suppression line code (e.g., hdb3 for e3 and b3zs for ds3 and sts-1). the purpose of this encoding activity was to aid in the clock recovery process of this data from the near-end receiving terminal. however, once the data has made it across the e3, ds3 or sts-1 trans- port medium and has been recovered by the clock recovery pll, it is now necessary to restore the orig- inal content of the data. the purpose of the hdb3/ b3zs decoding block is to restore the data transmit- ted over the e3, ds3 or sts-1 line to its original con- tent prior to zero suppression coding. 3.5.1 b3zs decoding ds3/sts-1 applications if the XRT73L02A is configured to operate in the ds3 or sts-1 modes, then the hdb3/b3zs decoding blocks perform b3zs decoding. when the decoders are operating in this mode, each of the decoders parses through its respective incoming dual-rail data command register cr2_(n)) d4 d3 d2 d1 d0 reserved endecdis_(n) alosdis_(n) dlosdis_(n) reqen_(n) xxxx 0
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 36 and checks for the occurrence of either a "00v" or a "b0v" pattern. if the b3zs decoder detects this par- ticular pattern, it substitutes these bits with a "000" pattern. n ote : if the b3zs decoder detects any bipolar violations that is not in accordance with theb3zs line code format or if the b3zs decoder detects a string of 3 or more consecu- tive "0s" in the incoming line signal, the b3zs decoder flags this event as a line code violation by pulsing the lcv output pin high". figure 21 illustrates the b3zs decoder at work with two separate zero suppression patterns in the in- coming dual-rail data stream. 3.5.2 hdb3 decoding e3 applications if the XRT73L02A is configured to operate in the e3 mode, then each of the hdb3/b3zs decoding blocks performs hdb3 decoding. when the decoders are operating in this mode, they each parse through the incoming dual-rail data and check for the occurrence of either a "000v" or a "b00v" pattern. if the hdb3 decoder detects this particular pattern, it substitutes these bits with a "0000" pattern. figure 22 illustrates the hdb3 decoder at work with two separate zero suppression patterns in the in- coming dual-rail data stream. n ote : if the hdb3 decoder detects any bipolar violation (e.g., "v") pulses that is not in accordance with the hdb3 line code format, or if the hdb3 decoder detects a string of 4 or more "0's" in the incoming line signal, the hdb3 decoder flags this event as a line code violation by puls- ing the lcv output pin high". 3.5.3 configuring the hdb3/b3zs decoder the XRT73L02A can enable or disable the hdb3/ b3zs decoder blocks of each channel by either of the following means. a. operating in the host mode enable the hdb3/b3zs decoder block of channel (n) by writing a "0" into the endecdis_(n) bit-field in command register cr2-(n). f igure 21. a n e xample of b3zs d ecoding data 0 1 0 1 1 0 0 0 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 rpos rneg 0 0 v line signal b 0 v rclk f igure 22. a n e xample of hdb3 d ecoding data 0 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 v line signal b 0 0 v rpos rneg rclk
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 37 b. operating in the hardware mode to globally enable all hdb3/b3zs decoder blocks in the XRT73L02A, pull the endec_dis input pin low". to globally disable all hdb3/b3zs decoder blocks in the XRT73L02A and configure the XRT73L02A to transmit and receive in an ami format, pull the endec_dis input pin "high". 3.6 los d eclaration /c learance each channel of the XRT73L02A contains circuitry that monitors the following two parameters associat- ed with the incoming line signals. 1. the amplitude of the incoming line signal via the rtip and rring inputs. 2. the number of pulses detected in the incoming line signal within a certain amount of time. if a given channel of the XRT73L02A determines that the incoming line signal is missing due to either insuf- ficient amplitude or a lack of pulses in the incoming line signal, it declares a loss of signal (los) condi- tion. the channel declares the los condition by tog- gling its respective rlos_(n) output pin high and by setting its corresponding rlos_(n) bit field in command register 0 or command register 8 to "1". conversely, if the channel determines that the incom- ing line signal has been restored (e.g., there is suffi- cient amplitude and pulses in the incoming line sig- nal), it clears the los condition by toggling its re- spective rlos_(n) output pin "low" and setting its corresponding rlos_(n) bit-field to "0". in general, the los declaration/clearance scheme that is employed in the XRT73L02A is based upon itu-t recommendation g.775 for both e3 and ds3 applications. 3.6.1 the los declaration/clearance criteria for e3 applications when the XRT73L02A is operating in the e3 mode, a given channel declares an los condition if its re- ceive line signal amplitude drops to -35db or below. further, the channel clears the los condition if its receive line signal amplitude rises back to -15db or above. figure 23 illustrates the signal levels at which each channel of the XRT73L02A declares and clears los. command register cr2-(n) d4 d3 d2 d1 d0 reserved endec_dis alosdis_(n) dlosdis_(n) reqen_(n) x 0xx1
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 38 timing requirements associated with declaring and clearing the los indicator the XRT73L02A was designed to meet the itu-t g.775 specification timing requirements for declaring and clearing the los indicator. in particular, a chan- nel of the XRT73L02A declares an los between 10 and 255 ui (or e3 bit-periods) after the actual time the los condition occurred. the channel clears the los indicator within 10 to 255 ui after restoration of the incoming line signal. figure 24 illustrates the los declaration and clearance behavior in response to the loss of signal event and then the restoration of the signal. f igure 23. t he s ignal l evels at which the XRT73L02A declares and clears los 0 db -12 db -15db -35db maximum cable loss for e3 los signal must be declared los signal must be cleared los signal may be cleared or declared f igure 24. t he b ehavior of the los o utput i ndicator in response to the l oss of s ignal and the r es - toration of s ignal actual occurrence of los condition line signal is restored time range for los declaration time range for los clearance g.775 compliance g.775 compliance 0 ui 10 ui 0 ui 10 ui 255 ui 255 ui rtip/ rring rlos output pin
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 39 3.6.2 the los declaration/clearance criteria for ds3 and sts-1 applications when the XRT73L02A is operating in the ds3 or sts-1 mode, each channel in the XRT73L02A de- clares and clears los based upon the following two criteria: ? analog los (alos) declaration/clearance crite- ria ? digital los (dlos) declaration/clearance crite- ria in the ds3 mode, the los output (rlos) is simply the logical "or" of the alos and dlos states. 1. the analog los (alos) declaration/clearance criteria a channel in the XRT73L02A declares an analog los (alos_(n)) condition if the amplitude of the in- coming line signal drops below a specific amplitude as defined by the voltage at the losthr input pin and whether the receive equalizer is enabled or not. table 5 presents the various voltage levels at the losthr input pin, the state of the receive equalizer, and the corresponding alos (analog los) threshold amplitudes. declaring alos a channel (n) in the XRT73L02A declares alos_(n) whenever the amplitude of the receive line signal falls below the signal levels to declare alos, as specified in table 5. clearing alos_(n) a channel (n) clears alos_(n) whenever the ampli- tude of the receive line signal increases above the signal levels to declare alos, as specified in table 5. there is approximately a 2db hysteresis in the re- ceived signal level that exists between declaring and clearing alos_(n) in order to prevent chattering in the rlos_(n) output signal. monitoring the state of alos_(n) if the XRT73L02A is operating in the host mode, the state of alos_(n) of channel (n) can be polled or monitored by reading in the contents of command register cr0. if the alos_(n) bit-field contains a "1", then the cor- responding channel (n) is currently declaring an alos condition. if the alos_(n) bit-field contains a "0", then the channel is not currently declaring an alos condition. t able 5: t he alos (a nalog los) d eclaration and c learance t hresholds for a given setting of losthr and reqen for ds3 and sts-1 a pplications a pplication reqen s etting losthr s etting s ignal l evel to d eclare alos s ignal l evel to c lear alos ds3 11< 22mv > 90mv 01< 17mv < 70mv sts-1 11< 25mv > 115mv 01< 20mv < 90mv command register cr0-(n) d4 d3 d2 d1 d0 rlol_(n) rlos_(n) alos_(n) dlos_(n) dmo_(n) read only read only read only read only read only
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 40 disabling the alos detector for debugging purposes it may be useful to disable the alos detector in the XRT73L02A. if the XRT73L02A is operating in the host mode, the alos detector can be disabled by writing a "1" into the alosdis_(n) bit-field in command register cr2. 2. the digital los (dlos) declaration/clearance criteria a given channel (n) in the XRT73L02A declares a digital los (dlos_(n)) condition if the XRT73L02A detects 16032 or more consecutive "0s" in the in- coming data. the channel clears dlos if it detects four consecu- tive sets of 32 bit-periods, each of which contains at least 10 "1s" (e.g., average pulse density of greater than 33%). monitoring the state of dlos if the XRT73L02A is operating in the host mode the state of dlos_(n) of channel (n) can be polled or monitored by reading in the contents of command register cr0. if the dlos_(n) bit-field contains a 1, then the cor- responding channel (n) is currently declaring a dlos condition. if the dlos_(n) bit-field contains a 0, the channel (n) is currently declaring the dlos condi- tion. disabling the dlos detector for debugging purposes, it is useful to be able to dis- able the dlos_(n) detector in the XRT73L02A. if the XRT73L02A is operating in the host mode, the dlos detector can be disabled by writing a 1 into the dlosdis_(n) bit-field of command register cr2. n ote : setting both the alosdis_(n) and dlosdis_(n) bit-fields to "1" disables los declaration by channel (n). 3.6.3 muting the recovered data while the los is being declared in some applications it is not desirable for a channel of the XRT73L02A to recover data and route it to the receiving terminal while the channel is declaring an los condition. consequently, the XRT73L02A in- cludes a los muting feature. this feature if enabled causes a given channel to halt transmission of the re- covered data to the receiving terminal while the los condition is "true". in this case, the rpos_(n) and rneg_(n) output pins are forced to "0". once the los condition has been cleared, the channel re- sumes normal transmission of the recovered data to the receiving terminal. this feature is available whenever the XRT73L02A is operating in the host or hardware mode. a. operating in the hardware mode. to enable the muting upon los feature for all chan- nels of the XRT73L02A, pull the losmuten output pin "high". b. operating in the host mode. command register cr2-(n) d4 d3 d2 d1 d0 reserved endecdis_(n) alosdis_(n) dlosdis_(n) reqen_(n) xx 1xx command register cr0-(n) d4 d3 d2 d1 d0 rlol_(n) rlos_(n) alos_(n) dlos_(n) dmo_(n) read only read only read only read only read only command register cr2-(n) d4 d3 d2 d1 d0 reserved endecdis_(n) alosdis_(n) dlosdis_(n) reqen_(n) xxx 1x
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 41 the muting upon los feature for each channel can be enabled by writing a "1" into the losmut_(n) bit- field in command register 3. n otes : 1. this step only enables the muting upon los fea- ture in channel (n). 2. each channel (n) automatically declares an los (loss of signal) condition anytime it has been conf- gured to operate in either the analog local loop- back or digital local loop-back modes. to config- ure the chip to operate in either of these modes, disable the muting-upon-los feature. 3.7 r outing r ecovered t iming and d ata i nfor - mation to the r eceiving t erminal e quipment each channel in the XRT73L02A takes the recov- ered timing and data information, converts it into cmos levels and routes it to the receiving terminal equipment via the rpos_(n), rneg_(n) and rxclk_(n) output pins. each channel of the XRT73L02A can deliver the re- covered data and clock information to the receiving terminal in either a single-rail or dual-rail format. 3.7.1 routing dual-rail format data to the receiving terminal equipment whenever a channel of the XRT73L02A delivers du- al-rail format to the terminal equipment, it does so via the following signals: ? rpos_(n) ? rneg_(n) ? rxclk_(n) figure 25 illustrates the typical interface for the trans- mission of data in a dual-rail format from the re- ceive section of a channel to the receiving terminal equipment . the manner that a given channel transmits dual-rail data to the receiving terminal equipment is de- scribed below and illustrated in figure 26. each channel (n) of the XRT73L02A typically updates the data on the rpos_(n) and rneg_(n) output pins on the rising edge of rxclk_(n). command register cr3-(n) d4 d3 d2 d1 d0 sr/(dr )_(n) losmut_(n) rxoff_(n) rxclk_(n)inv reserved x 1x x x f igure 25. t he typical interface for the t ransmission of d ata in a d ual -r ail f ormat from the r eceive s ection of the XRT73L02A to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block receive logic block rxpos rxneg rxclk rpos rneg rxclk
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 42 rxclk_(n) is the recovered clock signal from the in- coming received line signal. as a result, these clock signals are typically 34.368 mhz for e3 applications, 44.736 mhz for ds3 applications and 51.84 mhz for sonet sts-1 applications. in general, if a given channel received a positive-po- larity pulse in the incoming line signal via the rtip_(n) and rring_(n) input pins, then the channel pulses its corresponding rpos_(n) output pin "high". if the channel received a negative-polarity pulse in the incoming line signal via the rtip_(n) and rring_(n) input pins, then the channel (n) pulses its corresponding rneg_(n) output pin "high". inverting the rxclk_(n) outputs both channels can invert the rxclk_(n) signals with respect to the delivery of the rpos_(n) and rneg_(n) output data to the receiving terminal equipment. this feature may be useful for those cus- tomers whose receiving terminal equipment is de- signed such that the rpos_(n) and rneg_(n) data must be sampled on the rising edge of rxclk_(n). figure 27 illustrates the behavior of the rpos_(n), rneg_(n) and rxclk_(n) signals when the rxclk_(n) signal has been inverted. a. operating in the hardware mode setting the rxclkinv pin high results in all chan- nels of the XRT73L02A to output the recovered data on rpos_(n) and rneg_(n) on the falling edge of rxclk_(n). setting this pin low results in the recov- ered data on rpos_(n) and rneg_(n) to output on the rising edge of rxclk_(n). b. operating in the host mode in order to configure a channel of the XRT73L02A to invert the rxclk_(n) output signal, the XRT73L02A must be operating in the host mode. to invert rxclk_(n) associated with channel (n), write a "1" into the rxclk_(n)inv bit-field in command register cr-3 as illustrated below. f igure 26. h ow the XRT73L02A outputs data on the rpos and rneg output pins rxclk rpos rneg f igure 27. t he b ehavior of the rpos, rneg and r x c lk signals when r x c lk is inverted rxclk rpos rneg
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit preliminary rev. 2.0.0 43 inverting the rxclk_(n) signals via the hardware mode setting the rxclkinv input pin high" inverts all the rxclk_(n) output signals. 3.7.2 routing single-rail format (binary data stream) data to the receive terminal equipment a. operating in the host mode configure channel (n) to output single-rail data to the terminal equipment by writing a "1" into the sr/ (dr )_(n) bit-field of command register cr3-(n). the configured channel outputs single-rail data to the receiving terminal equipment via its correspond- ing rpos_(n) and rxclk_(n) output pins as illustrat- ed in figure 28 and figure 29. b. operating in the hardware mode configure the XRT73L02A to output single-rail data from the receive sections of all channels by pulling the sr/(dr) pin to vdd. n ote : when the XRT73L02A is operating in the hardware mode, the setting of the sr/(dr ) input pin applies globally to both channels. . command register cr3-(n) d4 d3 d2 d1 d0 sr/(dr) _(n) losmut_(n) rxoff_(n) rxclk_(n)inv reserved xxx 1x command register cr3-(n) d4 d3 d2 d1 d0 sr/(dr) _(n) losmut_(n) rxoff_(n) rxclk_(n)inv reserved 1xx x x f igure 28. t he typical interface for d ata t ransmission in a s ingle -r ail f ormat from the r eceive s ection of the XRT73L02A to the r eceiving t erminal e quipment terminal equipment (e3/ds3 or sts-1 framer) terminal equipment (e3/ds3 or sts-1 framer) exar e3/ds3/sts-1 liu receive logic block receive logic block rxpos rxclk rpos rxclk
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 preliminary 44 n ote : the rneg_(n) output pin is internally tied to ground whenever this feature is implemented. 3.8 s hutting off the r eceive s ection the receiver section in each channel of the XRT73L02A can be shut off. this feature may be useful in some redundant system designs. particular- ly, in those designs where the receive termination in the secondary liu line card has been switched-out and is not receiving any traffic in parallel with the pri- mary line card. in this case, it is a waste of power if the liu on the secondary line card is consuming the normal amount of current. this feature can permit powering down the receive section of the lius on the secondary line card which reduces their power consumption by approximately 80%. a. operating in the hardware mode shut off the receive section of channel (n) by pulling the rxoff_(n) input pin high". turn on the receive section of channel (n) by pulling the rxoff_(n) in- put pin to "low". b. operating in the host mode shut off the receive section of channel (n) by writing a "1" into the rxoff_(n) bit-field in command regis- ter cr3-(n). turn on the receive section of channel (n) by writing a "0" into the rxoff_(n) bit-field in command register cr3-(n). f igure 29. t he behavior of the rpos and r x c lk output signals while the XRT73L02A is transmit - ting s ingle -r ail data to the r eceiving t erminal e quipment rxclk rpos command register cr3-(n) d4 d3 d2 d1 d0 sr/(dr )_(n) losmut_(n) rxoff_(n) rxclk_(n)inv reserved xx 1x x
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 45 4.0 diagnostic features of the XRT73L02A the XRT73L02A supports equipment diagnostic ac- tivities by supporting the following loop-back modes in each channel in the XRT73L02A: ? analog local loop-back ? digital local loop-back ? remote loop-back 4.1 t he a nalog l ocal l oop -b ack m ode when a given channel in the XRT73L02A is config- ured to operate in the analog local loop-back mode, it ignores any signals that are input to its rtip_(n) and rring_(n) input pins. the transmitting terminal equipment transmits clock and data into this channel via the tpdata_(n), tndata_(n) and txclk_(n) input pins. this data is processed through the transmit clock duty cycle adjust pll and the hdb3/b3zs encoder. finally, this data outputs to the line via the ttip_(n) and tring_(n) output pins. additionally, this data loops back into the attenuator/receive equalizer block. this data is processed through the entire re- ceive section of the channel. after this post-loop- back data has been processed through the receive section, it outputs to the near-end receiving termi- nal equipment via the rpos_(n), rneg_(n) and rxclk_(n) output pins. figure 30 illustrates the path the data takes in a given channel of the XRT73L02A when it is configured to operate in the analog local loop-back mode. a given channel in the XRT73L02A can be configured to operate in the analog local loop-back mode by employing either one of the following two steps: n ote : see table 2 for a description of command registers and addresses for the different channels. a. operating in the host mode to configure channel (n) to operate in the analog lo- cal loop-back mode, write a "1" into the llb_(n) bit- field and a "0" into the rlb_(n) bit-field in command register cr4. b. operating in the hardware mode f igure 30. a channel in the XRT73L02A operating in the a nalog l ocal l oop -b ack m ode agc/ equalizer peak detector los detecto r slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) endecdis rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) notes: 1. (n) = 0 or 1 for respective channels 2. serial processor interface input pins are shared by the two channels in host mode and redefined in hardware mode. rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface analog local loop-back path command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _ ch_(n) e3_ ch_(n) llb_(n) rlb_(n) xx x 1 0
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 46 to configure channel (n) to operate in the analog lo- cal loop-back mode, set the llb_(n) input pin high" and the rlb_(n) input pin low". n ote : the analog local loop-back mode does not work if the transmitter is turned off via the txoff feature. 4.2 t he d igital l ocal l oop -b ack m ode . when a given channel in the XRT73L02A is config- ured to operate in the digital local loop-back mode, the channel ignores any signals that are input to the rtip and rring input pins. the transmitting termi- nal equipment transmits clock and data into the XRT73L02A via the tpdata, tndata and txclk input pins. this data is processed through the transmit clock duty cycle adjust pll and the hdb3/b3zs encoder block. at this point, this data loops back to the hdb3/b3zs decoder block. after this post-loop- back data has been processed through the hdb3/ b3zs decoder block, it outputs to the near-end re- ceiving terminal equipment via the rpos, rneg and rxclk output pins. figure 31 illustrates the path the data takes in the XRT73L02A when the chip is configured to operate in the digital local loop-back mode. to configure a channel to operate in the digital local loop-back mode, employ either one of the following two-steps: a. operating in the host mode to configure channel (n), write a 1" into both the llb and rlb bit-fields in command register cr4- (n). b. operating in the hardware mode to configure channel (n), pull both the llb input pin and the rlb input pin high". n ote : the digital local loop-back mode works even if the transmitter is turned off via the txoff feature. f igure 31. t he d igital l ocal l oop -b ack path in a given channel of the XRT73L02A agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) endecdis rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface digital local loop-back path notes: 1. (n) = 0 or 1 for respective channels 2. serial processor interface input pins are shared by the two channels in host mode and redefined in hardware mode. command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _ch_(n) e3_ch_(n) llb_(n) rlb_(n) xx x 1 1
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 47 4.3 t he r emote l oop -b ack m ode when a given channel of the XRT73L02A is config- ured to operate in the remote loop-back mode, the channel ignores any signals that are input to the tp- data and tndata input pins. the channel receives the incoming line signal via the rtip and rring input pins. this data is processed through the entire re- ceive section of the channel and outputs to the re- ceive terminal equipment via the rpos, rneg and rxclk output pins. additionally, this data is internally looped back into the pulse-shaping block in the transmit section. at this point, this data is routed through the remainder of the transmit section of the channel and transmitted out onto the line via the ttip_(n) and tring_(n) output pins. figure 32 illustrates the path the data takes in the XRT73L02A when the chip is configured to operate in the remote loop-back mode. to configure a channel to operate in the remote loop-back mode employ either one of the following two steps a. operating in the host mode to configure channel (n), write a "1" into the rlb bit- field and a "0" into the llb bit-field in command reg- ister cr4. b. operating in the hardware mode to configure channel (n), pull both the rlb input pin to high" and the llb input pin to "low". 4.4 t x off f eatures the transmit section of each channel in the XRT73L02A can be shut off. when this feature is in- voked, the transmit section of the configured channel is shut-off and the transmit output signals ttip_(n) and tring_(n) are tri-stated. this feature is useful for system redundancy conditions or during diagnostic testing. a. operating in the hardware mode shut off the channel (n) transmit driver by toggling the txoff_(n) input pin "high". turn on the transmit driver by toggling the txoff_(n) input pin "low". b. operating in the host mode f igure 32. t he r emote l oop -b ack path in a given XRT73L02A c hannel agc/ equalizer peak detector los detector slicer clock recovery data recovery invert loop mux hdb3/ b3zs decoder losthr_(n) sdi sdo sclk cs regr rtip_(n) rring_(n) reqen_(n) rxclk_(n) rpos_(n) rneg_(n) lcv_(n) endecdis rlos_(n) llb_(n) rlb_(n) taos_(n) tpdata_(n) tndata_(n) txclk_(n) rlol_(n) exclk_(n) device monitor mtip_(n) mring_(n) transmit logic duty cycle adjust txlev_(n) txoff_(n) dmo_(n) ttip_(n) tring_(n) pulse shaping hdb3/ b3zs encoder serial processor interface remote loop-back path notes: 1. (n) = 0 or 1 for respective channels 2. serial processor interface input pins are shared by the two channels in host mode and redefined in hardware mode. command register cr4-(n) d4 d3 d2 d1 d0 x sts-1/ds3 _ch_(n) e3_ch_(n) llb_(n) rlb_(n) xx x 0 1
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 48 turn off the channel (n) transmit driver by setting the txoff_(n) bit-field in command register cr1-(n) to "1". writing a "0" into this bit-field enables the channel (n) transmit driver. n ote : in order to permit a system designed for redundancy to quickly shut-off a defective line card and turn-on the back-up line card, the XRT73L02A was designed such that either transmitter can quickly be turned-on or turned-off by toggling the txoff_(n) input pins. this approach is much quicker then setting the txoff_(n) bit-fields via the micro- processor serial interface. table 6 presents a truth table which relates the set- ting of the txoff external pin and bit-field for a chan- nel to the state of the transmitter. this table applies to both channels of the XRT73L02A. to control the state of each transmitter via the micro- processor serial interface, connect the txoff_(n) in- put pins to gnd. 4.5 t he t ransmit d rive m onitor f eatures the transmit drive monitor is used to monitor the line in the transmit direction for the occurrence of fault conditions such as a short circuit on the line, a defec- tive transmit drive in the XRT73L02A or another liu. activate the channel (n) transmit drive monitor by connecting the mtip_(n) pin to the ttip_(n) line through a 270 ohm resistor connected in series, and connecting the mring_(n) pin to the tring_(n) line through a 270 ohm resistor connected in series. such an approach is illustrated in figure 33. command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) 1x x xx t able 6: t he r elationship b etween the t x off i nput p in , the t x off b it f ield and the s tate of the t ransmitter s tate of the t x off i nput p in s tate of the t x off b it f ield s tate of the t ransmitter low 0 on (transmitter is active) low 1 off (transmitter is tri-stated) high 0 off (transmitter is tri-stated) high 1 off (transmitter is tri-stated) f igure 33. t he XRT73L02A employing the t ransmit d rive m onitor f eatures r1 = 31.6 w r2 = 31.6 w channel (n) txpos_(n) txneg_(n) txlineclk_(n) ttip_(n) tring_(n) tpdata_(n) tndata_(n) txclk_(n) only one channel shown 1:1 j1 bnc mtip_(n) mring_(n) r3 = 270 w r4 = 270 w
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 49 when the transmit drive monitor circuitry in a given line is connected to the line as illustrated in figure 33, then it monitors the line for transitions. as long as the transmit drive monitor circuitry detects transitions on the line via the mtip_(n) and mring_(n) pins, it keeps the dmo (drive monitor output) signal "low". however, if the transmit drive monitor circuit detects no transitions on the line for 128+ 32 txclk periods, the dmo (drive monitor output) signal toggles "high". n ote : the transmit drive monitor circuit does not have to be used to operate the transmit section of the XRT73L02A. this is purely a diagnostic feature. 4.6 t he tao s ( t ransmit a ll o ne s) f eature the XRT73L02A can command any channel to trans- mit an all 1s pattern onto the line by toggling a sin- gle input pin or by setting a single bit-field in one of the command registers to "1". n ote : when this feature is activated, the transmit section of the configured channel in the XRT73L02A overwrites the terminal equipment data with an all 1s pattern. a. operating in the hardware mode configure channel (n) to transmit an all 1s pattern by toggling the taos_(n) input pin high". terminate the all 1s pattern by toggling the taos_(n) input pin "low". b. operating in the host mode configure channel (n) to transmit an all 1s pattern by writing to command register cr1-(n) and setting the taos_(n) bit-field (d3) to "1". terminate the all 1s pattern by writing to command register cr1-(n) and setting the taos_(n) bit-field (d3) to "0". 5.0 the microprocessor serial inter- face the on-chip command registers of XRT73L02A ds3/e3/sts-1 line interface unit ic are used to con- figure the XRT73L02A into a wide-variety of modes. this section discusses the following: 1. the description of the command registers. 2. a description on how to use the microprocessor serial interface. 5.1 d escription of the c ommand r egisters table 7 lists the command registers, their addresses and their bit-formats. command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) 0 1xxx
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 50 address the register addresses are presented in the hexa- decimal format. type: the command registers are either read-only (ro) or read/write (r/w) registers. each channel of the XRT73L02A has eight command registers, cr0-(n) through cr7-(n) where (n) = 0 or 1. the associated addresses for each channel is presented in table 7. n ote : the default value for each of the bit-fields in these registers is "0". 5.2 d escription of b it -f ields for each c om - mand r egister 5.2.1 command register - cr0-(n) the bit-format and default values for command reg- ister cr0-(n) are listed below followed by the function of these bit-fields. bit d4 - rlol_(n) (receive loss of lock status - channel (n)) this read-only bit-field reflects the lock status of the channel (n) clock recovery phase-locked-loop in the XRT73L02A. this bit-field is set to 0" if the clock recovery pll is in lock with the incoming line signal. this bit-field is t able 7: a ddresses and b it f ormats of XRT73L02A c ommand r egisters r egister b it -f ormat address command register type d4 d3 d2 d1 d0 c hannel 0 0x00 cr0-0 ro rlol_0 rlos_0 alos_0 dlos_0 dmo_0 0x01 cr1-0 r/w txoff_0 taos_0 txclkinv_0 txlev_0 txbin_0 0x02 cr2-0 r/w reserved endecdis_0 alosdis_0 dlosdis_0 reqen_0 0x03 cr3-0 r/w sr/dr _0 losmut_0 rxoff_0 rxclk_0inv reserved 0x04 cr4-0 r/w reserved sts-1/ds3 _ch_0 e3_ch_0 llb_0 rlb_0 0x05 cr5-0 r/w reserved reserved reserved reserved reserved 0x06 cr6-0 r/w reserved reserved reserved reserved reserved 0x07 cr7-0 r/w reserved reserved reserved reserved reserved c hannel 1 0x08 cr0-1 ro rlol_1 rlos_1 alos_1 dlos_1 dmo_1 0x09 cr1-1 r/w txoff_1 taos_1 txclkinv_1 txlev_1 txbin_1 0x0a cr2-1 r/w reserved endecdis_1 alosdis_1 dlosdis_1 reqen_1 0x0b cr3-1 r/w sr/dr _1 losmut_1 rxoff_1 rxclk_1inv reserved 0x0c cr4-1 r/w reserved sts-1/ds3 _ch_1 e3_ch_1 llb_1 rlb_1 0x0d cr5-1 r/w reserved reserved reserved reserved reserved 0x0e cr6-1 r/w reserved reserved reserved reserved reserved 0x0f cr7-1 r/w reserved reserved reserved reserved reserved command register cr0-(n) d4 d3 d2 d1 d0 rlol rlos alos dlos dmo 11111
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 51 set to "1" if the clock recovery pll is out of lock with the incoming line signal. bit d3 - rlos_(n) (receive loss of signal status - channel (n)) this read-only bit-field indicates whether or not channel (n) of the receiver is currently declaring an los (loss of signal) condition. this bit-field is set to "0" if channel (n) is not cur- rently declaring the los condition or, this bit-field is set to "1" if channel (n) is declaring an los condi- tion. bit d2 - alos_(n) (analog loss of signal status - channel (n)) this read-only bit-field indicates whether or not the channel (n) analog los detector is currently declar- ing an los condition. this bit-field is set to "0" if the analog los detector is not currently declaring an los condition. this bit- field is set to "1" if the analog los detector is cur- rently declaring an los condition. n ote : the purpose is to isolate the detector (e.g., either the analog los or the digital los detector) that is declar- ing the los condition. this feature may be useful for trou- bleshooting/debugging purposes. bit d1 - dlos_(n) (digital loss of signal status - channel (n)) this read-only bit-field indicates whether or not the channel (n) digital los detector is currently declar- ing an los condition. this bit-field is set to "0" if the digital los detector is not currently declaring an los condition. this bit- field is set to "1" if the digital los detector is current- ly declaring an los condition. n ote : the purpose is to isolate the detector (e.g., either the analog los or the digital los detector) that is declar- ing the los condition. this feature may be useful for trou- bleshooting/debugging purposes. bit d0 - dmo_(n) (drive monitor output status - channel (n)) this read-only bit-field reflects the status of the dmo output pin. 5.2.2 command register cr1 the bit-format and default values for command reg- ister cr1-(n) are listed below followed by the function of these bit-fields. bit d4 - txoff_(n) (transmitter off - channel (n)) this read/write bit-field is used to turn off the chan- nel (n) transmitter. writing a "1" to this bit field turns off the transmitter and tri-state the transmit output. writing a "0" to this bit-field turns on the transmitter. bit d3 - taos_(n) (transmit all ones - channel (n)) this read/write bit-field is used to command the channel (n) transmitter to generate and transmit an all 1s pattern onto the line. writing a "1" to this bit-field commands the transmit- ter to transmit an all 1s pattern onto the line. writ- ing a "0" to this bit-field commands normal operation. bit d2 - txclkinv_(n) (transmit clock invert - channel (n)) this read/write bit-field is used to configure the transmitter in the XRT73L02A to sample the signal at the tpdata and tndata pins on the rising edge or falling edge of txclk (the transmit line clock signal). writing a "1" to this bit-field configures the transmitter to sample the tpdata and tndata input pins on the rising edge of txclk. writing a "0" to this bit-field con- figures the transmitter to sample the tpdata and tndata input pins on the falling edge of txclk. bit d1 - txlev_(n) (transmit line build-out en- able/disable select - channel (n)) this read/write bit-field is used to enable or disable the channel (n) transmit line build-out circuit in the XRT73L02A. setting this bit-field "high disables the channel (n) line build-out circuit. in this mode, channel (n) out- puts partially-shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. setting this bit-field "low" enables the channel (n) line build-out circuit. in this mode, channel (n) out- puts shaped pulses onto the line via the ttip_(n) and tring_(n) output pins. in order to comply with the isolated dsx-3/stsx-1 pulse template requirements (per bellcore gr-499- core or gr-253-core): command register cr1-(n) d4 d3 d2 d1 d0 txoff_(n) taos_(n) txclkinv_(n) txlev_(n) txbin_(n) 00000
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 52 a. set this bit-field to "1" if the cable length between the cross-connect and the transmit output of chan- nel (n) is greater than 225 feet. b. set this bit-field to "0" if the cable length between the cross-connect and the transmit output of chan- nel (n) is less than 225 feet. n ote : this bit-field is active only if the XRT73L02A is con- figured to operate in the ds3 or sonet sts-1 modes. if the cable length is greater than 225 feet, set this bit- field to "1" in order to increase the amplitude of the transmit output signal. if the cable length is less than 225 feet, set this bit-field to "0". n ote : this option is only available when the XRT73L02A is operating in the ds3 or sts-1 mode. bit d0 - txbin_(n) (transmit binary data - chan- nel (n)) this read/write bit-field is used to configure the channel (n) transmitter to accept an un-encoded bi- nary data stream via the tpdata input and convert this data into the appropriate bipolar signal for the line. writing a "1" configures the transmitter to accept a bi- nary data stream via the tpdata input. the tndata input is ignored. this form of data acceptance is sometimes referred to as single-rail mode operation. the transmitter then encodes this data into the appropriate line code (e.g., b3zs or hdb3) prior to its transmission over the line. writing a "0" configures the transmitter to accept data in a dual-rail manner via tpdata and tndata inputs. 5.2.3 command register cr2-(n) the bit-format and default values for command reg- ister cr2-(n) are listed below followed by the function of each of these bit-fields. bit d4 - reserved bit d3 - endecdis (b3zs/hdb3 encoder/decod- er-disable - channel (n)) this read/write bit-field is used to enable or disable the channel (n) b3zs/hdb3 encoder and decoder blocks. writing a "1" to this bit-field disables the b3zs/hdb3 encoder and decoder blocks. writing a "0" to this bit- field enables the b3zs/hdb3 encoder and decoder blocks. n ote : this encoder/decoder performs hdb3 encoding/ decoding if the XRT73L02A is operating in the e3 mode. otherwise, it performs b3zs encoding/decoding. bit d2 - alosdis (analog los disable - channel (n)) this read/write bit-field is used to enable or disable the channel (n) analog los detector. writing a "0" to this bit-field enables the analog los detector. writing a "1" to this bit-field disables the analog los detector. n ote : if the analog los detector is disabled, then the rlos input pin is only asserted by the dlos (digital los detector). bit d1 - dlosdis (digital los disable - channel (n)) this read/write bit-field to used to enable or disable the channel (n) digital los detector . writing a "0" to this bit-field enables the digital los detector. writing a "1" to this bit-field disables the digital los detector. n ote : if the digital los detector is disabled, then the rlos input pin is only asserted by the alos (analog los detector). bit d0 - reqen (receive equalization enable - channel (n)) this read/write bit-field is used to either enable or disable the channel (n) internal receive equalizer of the XRT73L02A. writing a "1" to this bit-field enables the internal equalizer. writing a "0" to this bit-field disables the internal equalizer. 5.2.4 command register cr3-(n) the bit-format and default values for command reg- ister cr3 are listed below followed by the function of these bit-fields. bit d4 - sr/dr _(n) (single-rail/dual-rail data output - channel (n)) this read/write bit-field is used to configure channel (n) in the XRT73L02A to output the received data from the remote terminal in a binary or dual-rail for- mat. command register cr2-(n) d4 d3 d2 d1 d0 reserved endecdis alosdis dlosdis reqen x0 000 command register cr3-(n) d4 d3 d2 d1 d0 sr/dr _(n) losmut_(n) rxoff_(n) rxclk_(n)inv reserved 01000
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 53 writing a "1" to this bit-field configures channel (n) to output data to the terminal equipment in a binary single-rail format via the rpos_(n) output pin. rneg_(n) is grounded. writing a "0" to this bit-field configures channel (n) to output data to the terminal equipment in a dual-rail format via both the rpos_(n) and rneg_(n) output pins. bit d3 - losmut_(n) (recovered data muting dur- ing los condition - channel (n)) this read/write bit-field is used to configure channel (n) in the XRT73L02A to not output any recovered data from the line while it is declaring an los condi- tion. writing a "0" to this bit-field configures the chip to out- put recovered data even while the XRT73L02A is de- claring an los condition. writing a "1" to this bit-field configures the chip to not output the recovered data while an los condition is being declared. n ote : in this mode, rpos_(n) and rneg_(n) is set to "0" asynchronously. bit d2 - rxoff_(n) (receive section - shut off select) this read/write bit-field is used to shut-off the re- ceive section of channel (n) in the XRT73L02A. the purpose of this feature is to permit conservation of power consumption when this is the back-up device in a redundancy system. writing a "1" into this bit-field shuts off the receive section of channel (n). writing a "0" into this bit-field turns on the receive section of channel (n). bit d1 - rxclk_(n)inv (invert rxclk_(n)) this read/write bit-field is used to configure the re- ceiver of channel (n) of the XRT73L02A) to output the recovered data on either the rising edge or the falling edge of the rxclk_(n) clock signal. writing a "0" to this bit-field configures the receiver to output the recovered data on the rising edge of the rxclk_(n) output signal. writing a "1" to this bit-field configures the receiver to output the recovered data on the falling edge of the rxclk_(n) output signal. bit d0 - reserved this bit-field has no defined functionality. command register cr4-(n) the bit-format and default values for command reg- ister cr4 are listed below followed by the function of each of these bit fields. bit d4 - reserved this bit-field has no defined functionality. command register cr4-(n) d4 d3 d2 d1 d0 reserved sts-1/ds3 _ ch_(n) e3_ch_(n) llb_(n) rlb_(n) 00000
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 54 bit d3 - sts-1/(ds3 _(n)) - channel (n) - mode se- lect this read/write bit field is used to configure channel (n) to operate in either the sonet sts-1 mode or the ds3 mode. writing a "0" into this bit-field configures channel (n) to operate in the ds3 mode. writing a "1" into this bit-field configures channel (n) to operate in the so- net sts-1 mode. n ote : this bit-field is ignored if the e3_ch_(n) bit-field (e.g., d2 in this command register) is set to "1". bit d2 - e3 mode select - channel (n) this read/write bit-field is used to configure channel (n) to operate in the e3 mode. writing a "0" into this bit-field configures channel (n) to operate in either the ds3 or sonet sts-1 mode as specified by the setting of the ds3 bit-field in this command register. writing a "1" into this bit-field configures channel (n) to operate in the e3 mode. bit d1 - llb_(n) (local loop-back - channel (n)) this read/write bit-field along with rlb_(n) is used to configure channel (n) to operate in any one of a variety of loop-back modes. table 8 relates the contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for channel (n). bit d0 - rlb_(n) (remote loop-back - channel (n)) this read/write bit-field along with llb_(n) is used to configure channel (n) to operate in any one of a variety of loop-back modes. table 8 relates the contents of llb_(n) and rlb_(n) and the corresponding loop-back mode for channel (n). 5.3 o perating the m icroprocessor s erial i nterface . the XRT73L02A serial interface is a simple four wire interface that is compatible with many of the micro- controllers available in the market. this interface consists of the following signals: ? cs - chip select (active low) ? sclk - serial clock ? sdi - serial data input ? sdo - serial data output using the microprocessor serial interface the following instructions for using the microproces- sor serial interface are best understood by referring to the diagram in figure 34 and the timing diagram in figure 35. in order to use the microprocessor serial interface, a clock signal must be first applied to the sclk input pin. then, initiate a read or write operation by asserting the active-low chip select input pin cs . it is impor- tant to assert the cs pin (e.g., toggle it low") at least 50ns prior to the very first rising edge of the clock sig- nal. once the cs input pin has been asserted, the type of operation and the target register address must now be specified. provide this information to the micro- processor serial interface by writing eight serial bits of data into the sdi input. n ote : each of these bits is clocked into the sdi input on the rising edge of sclk. bit 1- r/w (read/write) bit this bit is clocked into the sdi input on the first rising edge of sclk after cs has been asserted. this bit in- dicates whether the current operation is a read or write operation. a "1" in this bit specifies a read op- eration, a "0" in this bit specifies a write operation. bits 2 through 5: the four (4) bit address values (labeled a0, a1, a2 and a3) the next four rising edges of the sclk signal clocks in the 4-bit address value for this particular read or write operation. the address selects the command register in the XRT73L02A that the user either be reading data from or writing data to. the address bits must be applied to the sdi input pin in ascending or- der with the lsb (least significant bit) first. bit 6 and 7: t able 8: c ontents of llb_(n) and rlb_(n) and the c orresponding l oop -b ack m ode for c hannel (n) llb _(n) rlb _(n) l oop -b ack m ode ( for c hannel (n) ) 0 0 none 1 0 analog loop-back mode (see section 4.1 for details) 1 1 digital loop-back mode (see section 4.2 for details) 0 1 remote loop-back mode (see section 4.3 for details)
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 55 a4 and a5 must be set to "0" as shown in figure 34. bit 8 - a6: the value of "a6" is a don't care. once these first 8 bits have been written into the mi- croprocessor serial interface, the subsequent action depends upon whether the current operation is a read or write operation. read operation once the last address bit (a3) has been clocked into the sdi input, the read operation proceeds through an idle period lasting three sclk periods. on the fall- ing edge of sclk cycle #8 (see figure 34) the serial data output signal (sdo) becomes active. at this point, reading the data contents of the addressed command register at address [a3, a2, a1, a0] via the sdo output pin can begin. the microprocessor serial interface outputs this five bit data word (d0 through d4) in ascending order with the lsb first, on the falling edges of the sclk pin. consequently, the data on the sdo output pin is sufficiently stable for reading by the microprocessor on the very next rising edge of the sclk pin. write operation once the last address bit (a3) has been clocked into the sdi input, the write operation proceeds through an idle period lasting three sclk periods. prior to the rising edge of sclk cycle # 9 (see figure 34). apply the desired eight bit data word to the sdi input pin via the microprocessor serial interface. the micropro- cessor serial interface latches the value on the sdi input pin on the rising edge of sclk. apply this word (d0 through d7) serially, in ascending order with the lsb first. simplified interface option the design of the circuitry connecting to the micro- processor serial interface can be simplified by tying both the sdo and sdi pins together and reading data from and/or writing data to this combined signal. this simplification is possible because only one of these signals are active at any given time. the inactive sig- nal is tri-stated. n otes : 1. a4 and a5 is always "0" 2. r/w = "1" for "read" operations 3. r/w = "0" for "write" operations 4. shaded blocks denotes a "don't care" value f igure 34. m icroprocessor s erial i nterface d ata s tructure d0 d1 d2 0 0 0 d4 d3 high z sdo a0 d0 r/w d1 a6 0 0 a3 a2 a1 d7 d6 d5 d4 d3 d2 sdi 12345678910111213141516 sclk cs high z
XRT73L02A ? ? ? ? 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 56 f igure 35. t iming d iagram for the m icroprocessor s erial i nterface sdi r/w a1 a0 cs sclk cs sclk sdi sdo d0 d1 d2 d7 t22 t21 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 hi-z hi-z
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 57 ordering information package dimensions p art #p ackage o perating temperature r ange XRT73L02Aiv 80 pin tqfp -40 o c to +85 o c thermal information theta - j a = 23 c/w theta j c = 5.32 c/w 60 41 40 21 1 2 0 61 80 d d1 d d1 b e a2 a a1 a seating plane l c 80 lead thin quad flat pack (14 x 14 x 1.4 mm) tqfp n ote : the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.009 0.015 0.22 0.38 c 0.004 0.008 0.09 0.20 d 0.622 0.638 15.80 16.20 d 1 0.547 0.555 13.90 14.10 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 a0 7 0 7
? ? ? ? XRT73L02A 2 channel e3/ds3/sts-1 line interface unit rev. 2.0.0 58 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2001 exar corporation datasheet november 2001 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history p1.1.1 removed heat slug from package drawing. p1.1.2 removed note referencing heat slug in the electrical characteristics (page 14). 2.0.0 redesigned 73l02 with improved performance and added timing recovery circuit. added typical jit- ter tolerance @800khz. receiver sensitivity (cable length) increased. part number changed to XRT73L02A, ordering information changed to XRT73L02Aiv. updated transformer recommendations. removed preliminary designation.

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