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tmp91cw11 2001-08-06 91cw11-1 low voltage/low power cmos 16-bit microcontrollers TMP91CW11F 1. outline and features tmp91cw11 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. tmp91cw11 is housed in a 100-pin flat package (p-lqfp100-1414-0.50c). listed below are the features. (1) high-speed 16-bit cpu (900/l1 cpu) ? instruction mnemonics are upward-compatible with tlcs-90/900 ? 16 mbytes of linear address space ? general-purpose registers and register banks ? 16-bit multiplication and division instructions; bit transfer and arithmetic instructions ? micro dma: 4 channels (640 ns/ 2 bytes at 25 mhz) (800 ns/ 2 bytes at 20 mhz) (1.28 ns/ 2 bytes at 12.5 mhz) (2) minimum instruction execution time: ? 160 ns (at 25 mhz, v cc = 5 v without external bus) ? 200 ns (at 20 mhz, v cc = 5 v) ? 320 ns (at 12.5 mhz, v cc = 3 v) (3) internal ram: 4 kbytes rom: 128 kbytes (4) external memory expansion ? expandable up to 16 mbytes (for both programs and data) ? can simulatneously support 8-/16-bit width external data bus ... dynamic data bus sizing purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ? for adiscussion of how the reliability of microcontrollers can be predicted, please refer to section 1.3 of the chapter entitl ed quality and reliability assurance / handling precautions. ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibi lity of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to a void situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage t o property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the mos t recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the handling gui de fo r semiconductor devices, or toshiba semiconductor reliability handbook etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfun ction or failure of which may cause loss of human life or bodily injury (unintended usage). unintended usage include atomic energy con trol instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control inst ruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be m ade at the customers own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assum ed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from i ts use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation o r others. ? the information contained herein is subject to change without notice. 000707 ebp1
tmp91cw11 2001-08-06 91cw11-2 (5) 8-bit timer: 2 channels (6) 8-bit pwm timer: 2 channels (7) 16-bit timer: 2 channels (8) general-purpose serial interface: 6 channels ? for uart/8-bit sio: 2channels ? for uart: 1 channel ? for 8-bit sio: 2 channels ? for i 2 c bus (multi-master)/8-bit sio: 1 channel (9) 10-bit ad converter: 8 channels (10) watchdog timer (11) chip select/wait controller: 3 blocks (12) interrupts: 39 interrupts ? 9 cpu interrupts: sofware interrupt instruction and illegal instruction ? 24 internal interrupts: ? 6 external interrupts: (13) input/output ports 79 pins ? large current output: 6 pors, led direct drive (14) standby mode ? 4 halt modes: run, idle2, idle1, stop (15) clock gear function ? high-frequency clock can be changed from fc to fc/16. ? dual clock operation (16) real time counter (17) operating voltage ? v cc = 2.7 to 5.5 v (18) package: p-lqfp100-1414-0.50c 7-level priority can be set.
tmp91cw11 2001-08-06 91cw11-3 w / r (p36) busrq (p34) busak (p35) sck0 (p95) si0 (p94) so0 (p93) vrefh vrefl avss avcc 8-bit timer (timer 1) 8-bit timer (timer 0) serial bus interface controller serial i/o (ch. 4) serial i/o (ch. 3) serial i/o (ch. 2) serial i/ o (ch.1) serial i/ o (ch.0) vss [3] vcc [3] cs/wait controller (3 blocks) interrupt controller watchdog timer port a port 2 port 1 port 0 port 3 osc2 clock gear osc1 x2 x1 real time counter 128-kb rom 4-kb ram pc sr f 32 bits ix iy iz sp a c e l w b d h xwa xbc xde xhl xix xiy xiz xsp cpu (tlcs-900l1) 10-bit 8ch ad converter adtrg (p53) an0 to an7 (p50 to p57) sck1 (p40) si1 (p41) so1 (p42) sck3 (p65) rxd3 (p64) txd3 (p63) rxd4 (p67) txd4 (p66) sck5 (p92) scl/si5 (91) to3 (p73)) to2(p72) to1 (p71) ti0 (p70) sda/so5 (p90) to4 (p82) to5 (p83) int5/ti5 (p81) int4/ti4 (p80) to6 (p86) int7/ti7 (p85) int6/ti6 (p84) 8-bit timer (timer 3) 8-bit timer (timer 2) 16-bit timer (timer 5) 16-bit timer (timer 4) xt2 (p97) xt1 (p96) ale clk 16 am8/ wr (p31) rd (p30) wait (p33) hwr (p32) wdtout scout (pa7) pa0 to pa6 a0/a16 to a7/a23 (p20 to p27) ad8/a8 to ad15/a15 (p10 to p17) ad0 to ad7 (p00 to p07) p37 int0 (p87) nmi cs0 (p40) cs1(p41) cs2 (p42) sck2 (p62) rxd2 (p61) txd2 (p60) ea reset figure 1.1 tmp91cw11 block diagram
tmp91cw11 2001-08-06 91cw11-4 2. pin assignment and pin functions the assignment of input/output pins for the TMP91CW11F, their names and outline functions are described below. 2.1 pin assignment figure 2.1.1 shows pin assignment of TMP91CW11F. vss 91 p67/rxd4 90 85 p62/cts2/slck2 86 p63/txd3 87 p64/rxd3 88 p65/cts3/slck3 p66/txd4 89 pin no. tmp91cw11 pull down pull up programmable clock mode memory interface sio sio timer adc p52/an2 94 p51/an1 93 p50/an0 92 p55/an5 97 p54/an4 96 p53/an3/adtrg 95 vrefh 100 p57/an7 99 p56/an6 98 avcc 3 avss 2 vrefl 1 p71/to1 6 p70/ti0 5 nmi 4 p80/int4/ti4 9 p73/to3 8 p72/to2 7 p83/to5 12 p82/to4 11 p81/int5/ti5 10 p86/to6 15 p85/int7/ti7 14 p84/int6/ti6 13 p91/scl/si5 18 p90/sda/so5 17 p87/int0 16 p94/si0 21 p93/so0 20 p92/sck5 19 vcc 25 clk 24 am8/16 23 p95/sck0 22 vss 26 ea 29 x2 28 x1 27 p97/xt2 32 p96/xt1 31 reset 30 pa2 37 pa1 36 pa0 35 test2 34 test1 33 pin no. tmp91cw11 pull down pull up programmable 81 p41/cs1//si1 82 p42/cs2/so1 83 p60/txd2 84 p61/rxd2 80 p40/cs0/sck1 76 p34/busrq 77 p35/busak 78 p36/r/w 79 p37 72 p30/rd 73 p31/wr 74 p32/hwr 75 p33/wait 68 p24/a4/a20 69 p25/a5/a21 70 p26/a6/a22 71 p27/a7/a23 64 p20/a0/a16 65 p21/a1/a17 66 p22/a2/a18 67 p23/a3/a19 60 p17/ad15/a15 61 wdtout 62 vss 63 vcc 58 p15/ad13/a13 59 p16/ad14/a14 54 p11/ad9/a9 55 p12/ad10/a10 56 p13/ad11/a11 57 p14/ad12/a12 49 p04/ad4 48 p03/ad3 50 p05/ad5 51 p06/ad6 52 p07/ad7 53 p10/ad8/a8 46 p01/ad1 45 p00/ad0 47 p02/ad2 43 ale 42 pa7/scout 44 vcc 40 pa5 38 pa3 39 pa4 41 pa6 top view lqfp100 figure 2.1.1 pin assignment
tmp91cw11 2001-08-06 91cw11-5 2.2 pin names and functions the names of input/output pins and their functions are described below. table 2.2.1 pin names and functions (1/4) pin name number of pins i/o function p00 to p07 ad0 to ad7 8 i/o tri-state port 0: i/o port that allows selection of i/o on a bit basis address/data (lower): bits 0 to 7 of address/data bus p10 to p17 ad8 to ad15 a8 to a15 8 i/o tri-state output port 1: i/o port that allows selection of i/o on a bit basis address data (upper): bits 8 to 15 of address/data bus address: 8 to 15 of address bus p20 to p27 a0 to a7 a16 to a23 8 i/o output output port 2: i/o port that allows selection of i/o on a bit basis (with pull-up resistor) address: bits 0 to 7 of address bus address: bits 16 to 23 of address bus p30 rd 1 output output port 30: output port read: strobe signal for reading external memory p31 wr 1 output output port 31: output port write: strobe signal for writing data on pins ad0 to 7 p32 hwr 1 i/o output port 32: i/o port (with pull-up resistor) high write: strobe signal for writing data on pins ad8 to 15 p33 wait 1 i/o input port 33: i/o port (with pull-up resistor) wait: pin used to request cpu bus wait p34 busrq 1 i/o input port34: i/o port(with pull-up resistor) bus request: signal used to request high impedance for ad0 to 15, a0 to 23, rd , wr , hwr , w / r , ras , cs0 , cs1 , and cs2 pins. (for external dmac) p35 busak 1 i/o output port 35: i/o port (with pull-up resistor) bus acknowledge: signal indicating that ad0 to 15, a0 to 23, rd , wr , hwr , w / r , ras , cs0 , cs1 , and cs2 pins are at high impedance after receiving busrq. (for external dmac) p36 w / r 1 i/o output port 36: i/o port (with pull-up resistor) read/write: 1 represents read or dummy cycle; 0, write cycle. p37 1 i/o port 37: i/o port (with pull-up resistor) p40 cs0 sck1 1 i/o output i/o port 40: i/o port (with pull-up resistor) chip select 0: outputs 0 when address is within specified address area. serial clock i/o 1 note: this devices built-in memory or built-in i/o cannot be accessed with the external dma controller, using the busrq and busak signals.
tmp91cw11 2001-08-06 91cw11-6 table 2.2.2 pin names and functions (2/4) pin name number of pins i/o function p41 cs1 si1 1 i/o output input port 41: i/o port (with pull-up resistor) chip select 1: outputs 0 if address is within specified address area. serial receive data 1 p42 cs2 so1 1 i/o output output port 42: i/o port (with pull-down resistor) chip select 2: outputs 0 if address is within specified address area. serial send data 1 p50 to p52 an0 to an2 3 input input port5: input port analog input: analog signal input for ad converter p53 an3 adtrg 1 input input input port 53: input port analog input = analog signal input for ad converter ad external trigger p54 to p57 an4 to an7 4 input input port 5: input port analog input: analog signal input for ad converter vrefh 1 input pin for high level reference voltage input to ad converter vrefl 1 input pin for low level reference voltage input to ad converter p60 txd2 1 i/o output port 60: i/o port (programmable open drain) serial send data 2 p61 rxd2 1 i/o input port 61: i/o port serial receive data 2 p62 cts2 sclk2 1 i/o input i/o port 62: i/o port serial data send enable 2 (clear to send) serial clock i/o 2 p63 txd3 1 i/o output port 63: i/o port serial send data 3 p64 rxd3 1 i/o input port 64: i/o port serial receive data 3 p65 cts3 sclk3 1 i/o input i/o port 65: i/o port serial data send enable 3 (clear to send) serial clock i/o 3 p66 txd4 1 i/o output port 66: i/o port serial send data 4 p67 rxd4 1 i/o input port 67: i/o port serial receive data 4 p70 ti0 1 i/o input port 70: i/o port timer input 0: timer 0 input p71 to1 1 i/o output port 71: i/o port timer output 1: timer 0 or 1 output p72 to2 1 i/o output port 72: i/o port pwm output 2: 8-bit pwm timer 2 output p73 to3 1 i/o output port 73: i/o port pwm output 3: 8-bit pwm timer 3 output
tmp91cw11 2001-08-06 91cw11-7 table 2.2.3 pin names and functions (3/4) pin name number of pins i/o function p80 ti4 int4 1 i/o input input port 80: i/o port timer input 4: timer 4 count/capture trigger signal input interrupt request pin 4: interrupt request pin with programmable rising/falling edge p81 ti5 int5 1 i/o input input port 81: i/o port timer input 5: timer 4 count/capture trigger signal input interrupt request pin 5: interrupt request pin with rising edge p82 to4 1 i/o output port 82: i/o port timer output4: timer 4 output pin p83 to5 1 i/o output port 83: i/o port timer output 5: timer 4 output pin p84 ti6 int6 1 i/o input input port 84: i/o port timer input 6: timer 5 count/capture trigger signal input interrupt request pin 6: interrupt request pin with programmable rising/falling edge p85 ti7 int7 1 i/o input input port 85: i/o port timer input 7: timer 5 count/capture trigger signal input interrupt request pin 7: interrupt request pin with rising edge p86 to6 1 i/o output port 86: i/o port timer output 6: timer 5 output pin p87 int0 1 i/o input port 87: i/o port interrupt request pin 0: interrupt request pin with programmable level/rising edge p90 sda so5 1 i/o i/o output port 90: i/o port (programmable open-drain) sbi i 2 c bus mode channel data serial send data 5 p91 scl si5 1 i/o i/o input port 91: i/o port (programmable open-drain) sbi i 2 c bus mode clock serial receive data 5 p92 sck5 1 i/o i/o port 92: i/o port serial clock i/o 5 p93 so0 1 i/o output port 93: i/o port (programmable open-drain) serial send data 0 p94 si0 1 i/o input port 94: i/o port serial receive data 0 p95 sck0 1 i/o i/o port 95: i/o port serial clock i/o 0 pa0 to pa5 6 i/o port a0 to a5: i/o ports (large current output) pa6 1 i/o port a6: i/o port
tmp91cw11 2001-08-06 91cw11-8 table 2.2.4 pin names and functions (4/4) pin name number of pins i/o function pa7 scout 1 i/o output port a7: i/o port system clock output: outputs system clock or 2 times oscillation clock for synchronizing to external circuit. wdtout 1 output watchdog timer output pin nmi 1 input non-maskable interrupt request pin: interrupt request pin with falling edge. can also be operated at rising edge by program. clk 1 output clock output: outputs [system clock 2] clock. pulled-up during reset. can be disabled for reducing noise. ea 1 input fixed to 1. am8/ 16 1 input fixed to 1. ale 1 output address latch enable (can be disabled for reducing noise.) reset 1 input reset: initializes lsi. (with pull-up resistor) x1/x2 2 i/o high frequency oscillator connecting pin xt1 p96 1 input i/o low frequency oscillator connecting pin port 96: i/o port (open-drain output) xt2 p97 1 output i/o low frequency oscillator connecting pin port 97: i/o port (open-drain output) test1/test2 2 output /input test1 should be connected with test2 pin. vcc 3 power supply pin (all vcc pins are connected to the power supply source.) vss 3 gnd pin (all vss pins are connected to the gnd (0 v).) avcc 1 power supply pin for ad converter avss 1 gnd pin for ad converter (0 v) note: built-in pull-up/pull-down resistors can be released from the pins other than the reset pin by software.
tmp91cw11 2001-08-06 91cw11-9 3. operation the following describes block by block the functions and basic operation of tmp91cw11. notes and restrictions for each block are outlined in 7, ?use precautions and restrictions? at the end of this manual. 3.1 cpu tmp91cw11 incorporates a high-performance 16-bit cpu (900/l1-cpu). for cpu operation, see the ?tlcs-900/l1 cpu?. the following describes the unique functions of the cpu used in tmp91cw11; these functions are not covered in the tlcs-900/l1 cpu section. 3.1.1 reset when resetting the tmp91cw11 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. then hold the reset input to low level for at least 10 system clocks (ten states: 16 s at 20 mhz), resetting initializes the clock gear to fc/16. when the reset is accepted, the cpu sets as follows: ? sets as follows the program counter (pc) in accordance with the reset vector stored at address ffff00h to ffff02h: pc (7 to 0) data located at ffff00h pc (15 to 8) data located at ffff01h pc (23 to 16) data located at ffff02h ? sets the stack pointer (xsp) to 100h. ? sets bits of the status register (sr) to 111 (sets the interrupt level mask register to level 7). ? sets the bit of the status register to 1 (max mode). (note: as this product does not support a min mode, don?t write 0 to .) ? clears bits of the status register to 000 (sets the register bank to 0). when reset is released, the cpu starts executing instructions in accordance with the program counter settings. cpu internal registers not mentioned above do not change when the reset is released. when the reset is accepted, the cpu sets internal i/o, ports, and other pins as follows. ? initializes the internal i/o registers. ? sets the port pins, including the pins that also act as internal i/o, to general-purpose input or output port mode. ? sets wdtout pin to 0. (resetting enables the watchdog timer.) ? pulls up the clk pin to high level. (note: during reset, do not reduce the external voltage level as this can cause malfunction.) ? sets ale pin to high impedance (high-z). note 1: by resetting, register in the cpu except program counter (pc), status register (sr) and stack pointer (xsp) and the data in internal ram are not changed. note 2: the clk pin is pulled up during reset. when the voltage is put down externally, there is possible to cause malfunctions. figure 3.1.1 shows the reset timing chart of tmp91cw11.
tmp91cw11 2001-08-06 91cw11-11 3.2 memory map the tmp91cw11 uses an address space of 128 bytes as an internal i/o area, which is allocated to addresses 000000h to 00007fh. the cpu can access this internal i/o area with short instruction code using the direct addressing mode. figure 3.2.1 shows the memory map and the access ranges corresponding to the cpu addressing modes. ffffffh ffff00h fe0000h 010000h 001080h 000100h 000080h internal rom (128 kbytes) vector table (256 bytes) external memory internal ram (4 kbytes) = internal area) ( 16-mbyte area (r32) ( ? r32) (r32 + ) (r32 + r8/16) (r32 + d8/16) (nnn) 64-kbyte area (nn) 256-byte direct area (n) internal i/o (128 bytes) 000000h note: after reset, the stack pointer xsp is set to 100h. figure 3.2.1 memory map
tmp91cw11 2001-08-06 91cw11-247 4. electrical characteristics 4.1 absolute maximum ratings x used in an expression shows a frequency of clock f fph selected by syscr1 . if a clock gear or a low speed oscillator is selected, a value of x is different. the value as an example is calculated at fc, gear = 1/fc (syscr1 = 0000). parameter symbol pin rating unit power supply voltage v cc ? 0.5 to 6.5 v input voltage v in ? 0.5 to v cc + 0.5 v output voltage v out p96, p97, pa0 to a5, p60, p91 to 93 (for open-drain) ? 0.5 to v cc + 0.5 v output current (per pin) i out1 only pa0 to a5 20 ma i out2 except pa0 to a5 2 ma i out3 ? 2ma output current (total) i out1 total 120 ma i out2 pa0 to a5 80 ma i out3 total ? 80 ma power dissipation (ta = 85c) p d 600 mw soldering temperature tsolder 260 c storage temperature t stg ? 65 to 150 c operating temperature topr ? 40 to 85 c note: the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded.
tmp91cw11 2001-08-06 91cw11-248 4.2 dc characteristics (1/2) (vss = 0 v, ta = ? 40 to 85c) parameter symbol condition min typ. (note) max unit fc = 4 to 25 mhz 4.5 power supply voltage avcc = vcc avss = vss vcc fc = 4 to 12.5 mhz fs = 30 to 34 khz 2.7 5.5 v v cc 4.5 v 0.8 ad0 to 15 vil v cc < 4.5 v 0.6 p20 to 27, p32 to 37, p42, p50 to 57, p60 to 67, p70 to 73, p80 to 86, p93, p96, p97 to 37, pa0 to a7 vil1 0.3 v cc reset , nmi , p40 to 41, p87, p90 to 92, p94, p95 vil2 0.25 v cc ea , am8 / 16 vil3 0.3 input low voltage x1 vil4 v cc = 2.7 to 5.5 v ? 0.3 0.2 v cc v cc 4.5 v 2.2 ad0 to 15 vih v cc < 4.5 v 2.0 p20 to 27, p32 to 37, p42, p50 to 57, p60 to 67, p70 to 73, p80 to 86, p93, p96, p97 to 37, pa0 to a7 vih1 0.7 v cc reset , nmi , p40 to 41, p87, p90 to 92, p94, p95 vih2 0.75 v cc ea , am8 / 16 vih3 v cc ? 0.3 input high voltage x1 vih4 v cc = 2.7 to 5.5 v 0.8 v cc v cc + 0.3 v note: typical values are for ta = 25 c and vcc = 5 v unless other wise noted.
tmp91cw11 2001-08-06 91cw11-249 4.2 dc characteristic (2/2) (vss = 0 v, ta = ? 40 to 85c) parameter symbol condition min typ. (note 1) max unit output low voltage (except pa0 to pa5) v ol i ol = 1.6 ma (vcc = 2.7 to 5.5 v) 0.45 v vol = 1.0 v (vcc = 3 v 10%) 7 output low current (pa0 to 5) i ola vol = 1.0 v (vcc = 5 v 10%) 16 ma v oh1 i oh = ? 400 a (vcc = 3 v 10%) 2.4 output high voltage v oh2 i oh = ? 400 a (vcc = 5 v 10%) 4.2 v darlington drive current (8 output pins max.) i dar (note 2) v ext = 1.5 v r ext = 1.1 k ? (vcc = 5 v 10% only) ? 1.0 ? 3.5 ma input leakage current i li 0.0 v in v cc 0.02 5 output leakage current i lo 0.2 v in v cc ? 0.2 0.05 10 a power down voltage (at stop, ram back up) v stop vil2 = 0.2 vcc, vih 2 = 0.8 vcc 2.0 6.0 v vcc = 5 v 10% 50 150 reset pull up resistor r rst vcc = 3 v 10% 80 200 k ? pin capacitance c io fc = 1 mhz 10 pf schmitt width reset , nmi , p40, p41, p87, p90 to 92, p94, p95 v th 0.4 1.0 v vcc = 5 v 10% 10 80 programmable pull down resistor r kl vcc = 3 v 10% 30 150 vcc = 5 v 10% 50 150 programmable pull up resistor r kh vcc = 3 v 10% 100 300 k ? normal 45 55 run 25 40 idle2 15 30 idle1 vcc = 5 v 10% fc = 25 mhz 310 ma normal 13 20 run 711 idle2 47.5 idle1 vcc = 3 v 10% fc = 12.5 mhz (typ: vcc = 3.0 v) 0.8 1.8 ma slow 110 200 run 22 52 a idle2 14 52 idle1 vcc = 3 v 10% fs = 32.768 khz (typ: vcc = 3.0 v) 640 ta 50c 10 ta 70c 20 stop icc ta 85c vcc = 2.7 to 5.5 v 0.2 50 a note 1: typical values are for ta = 25c and vcc = 5 v unlesss otherwise noted. note 2: i-dar is guranteed for total of up to 8 ports.
tmp91cw11 2001-08-06 91cw11-250 external-bus access isn?t supported in over 20 mhz. 4.3 ac characteristics (1) vcc = 5 v 10% (fc = 4 to 20 mhz) (fs = 30 to 34 khz) variable 16 mhz 20 mhz no. parameter symbol min max min max min max unit 1 osc. period ( = x) t osc 50 33.3 s 62.5 50 ns 2 clk width t clk 2x ? 40 85 60 ns 3 a0 to 23 valid clk hold t ak 0.5x ? 20 11 5 ns 4 clk valid a0 to 23 hold t ka 1.5x ? 70 24 5 ns 5 a0 to 15 valid ale fall t al 0.5x ? 15 16 10 ns 6 ale fall a0 to 15 hold t la 0.5x ? 20 11 5 ns 7 ale high pulse width t ll x ? 40 23 10 ns 8 ale fall wr / rd fall t lc 0.5x ? 25 6 0 ns 9 wr / rd rise ale rise t cl 0.5x ? 20 11 5 ns 10 a0 to 15 valid wr / rd fall t acl x ? 25 38 25 ns 11 a0 to 23 valid wr / rd fall t ach 1.5x ? 50 44 25 ns 12 wr / rd rise a0 to 23 hold t ca 0.5x ? 25 6 0 ns 13 a0 to 15 valid d0 to 15 input t adl 3.0x ? 55 133 95 ns 14 a0 to 23 valid d0 to 15 input t adh 3.5x ? 65 154 110 ns 15 rd fall d0 to 15 input t rd 2.0x ? 60 65 40 ns 16 rd low pulse width t rr 2.0x ? 40 85 60 ns 17 rd rise d0 to 15 hold t hr 000ns 18 rd rise a0 to 15 output t rae x ? 15 48 35 ns 19 wr low pulse width t ww 2.0x ? 40 85 60 ns 20 d0 to 15 valid wr rise t dw 2.0x ? 55 70 45 ns 21 wr rise d0 to 15 hold t wd 0.5x ? 15 16 10 ns 22 a0 to 23 valid wait input (1wait + n mode) t awh 3.5x ? 90 129 85 ns 23 a0 to 15 valid wait input (1wait + n mode) t awl 3.0x ? 80 108 70 ns 24 wr / rd fall wait hold (1wait + n mode) t cw 2.0x + 0 125 100 ns 25 a0 to 23 valid port input t aph 2.5x ? 120 36 5 ns 26 a0 to 23 valid port hold t a ph2 2.5x + 50 206 175 ns 27 wr rise port valid t cp 200 200 200 ns ac measuring conditions ? output level: high 2.2 v /low 0.8 v, cl = 50 pf (however cl = 100 pf for ad0 to ad15, a0 to a23, ale, rd , wr , hwr , w r/ , clk) ? input level: high 2.4 v / low 0.45 v (ad0 to ad15) high 0.8 vcc / low 0.2 vcc (except for ad0 to ad15)
tmp91cw11 2001-08-06 91cw11-251 (2) vcc = 3 v 10% (fc = 4 to 12.5 mhz) (fs = 30 to 34 khz) variable 12.5 mhz no. parameter symbol min max min max unit 1 osc. period ( = x) t osc 80 33.3 s80 ns 2 clk width t clk 2x ? 40 120 ns 3 a0 to 23 valid clk hold t ak 0.5x ? 30 10 ns 4 clk valid a0 to 23 hold t ka 1.5x ? 80 40 ns 5 a0 to 15 valid ale fall t al 0.5x ? 35 5 ns 6 ale fall a0 to 15 hold t la 0.5x ? 35 5 ns 7 ale high width t ll x ? 60 20 ns 8 ale fall wr / rd fall t lc 0.5x ? 35 5 ns 9 wr / rd rise ale rise t cl 0.5x ? 40 0 ns 10 a0 to 15 valid wr / rd fall t acl x ? 50 30 ns 11 a0 to 23 valid wr / rd fall t ach 1.5x ? 50 70 ns 12 wr / rd rise a0 to 23 hold t ca 0.5x ? 40 0 ns 13 a0 to 15 valid d0 to 15 input t adl 3.0x ? 110 130 ns 14 a0 to 23 valid d0 to 15 input t adh 3.5x ? 125 155 ns 15 rd fall d0 to 15 input t rd 2.0x ? 115 45 ns 16 rd low pulse width t rr 2.0x ? 40 120 ns 17 rd rise d0 to 15 hold t hr 00ns 18 rd rise a0 to 15 output t rae x ? 25 55 ns 19 wr low pulse width t ww 2.0x ? 40 120 ns 20 d0 to 15 valid wr rise t dw 2.0x ? 120 40 ns 21 wr rise d0 to 15 hold t wd 0.5x ? 40 0 ns 22 a0 to 23 valid wait input (1wait + n mode) t awh 3.5x ? 130 150 ns 23 a0 to 15 valid wait input (1wait + n mode) t awl 3.0x ? 100 140 ns 24 wr / rd fall wait hold (1wait + n mode) t cw 2.0x + 0 160 ns 25 a0 to 23 valid port input t aph 2.5x ? 120 80 ns 26 a0 to 23 valid port hold t aph2 2.5x + 50 250 ns 27 wr rise port valid t cp 200 200 ns ac measuring conditions ? output level: high 0.7 vcc / low 0.3 vcc, cl = 50 pf ? input level: high 0.9 vcc / low 0.1 vcc
tmp91cw11 2001-08-06 91cw11-252 (1) read cycle cs0 to 2 a0 to 23 clk x1/xt1 r/w t rsh t ras t rd t adl t rae t lc t la t al t ll t acl t ach t adh t cl t hr t ca t rr t aph t aph2 t cw t awl t awh t ak t ka t osc t clk wait port input ale d0 to 15 a0 to 15 ad0 to 15 rd
tmp91cw11 2001-08-06 91cw11-253 (2) write cycle cs0 to 2 a0 to 23 clk x1/xt1 r/w t wd t dw t ww t cp wait port output ale d0 to 15 ad0 to 15 wr, hwr a0 to 15
tmp91cw11 2001-08-06 91cw11-254 4.4 ad conversion characteristics (vss = 0 v, avcc = vcc, avss = vss, ta = ? 40 to 85c) vcc = + 5v 10%, (fc = 4 to 25 mhz) vcc = + 3v 10%, (fc = 4 to 12.5 mhz) parameter symbol test conditions min typ. max unit ad analog reference supply voltage ( + )v refh vcc ? 0.2 vcc ad analog reference supply voltage ( ? )v refl vss vss + 0.2 analog reference voltage av cc vcc ? 0.2 vcc analog reference voltage av ss vss vss + 0.2 analog input voltage v a in v refl v refh v analog input impedance r ain 5k ? vcc = 5 v 10% 3.7 = 1 vcc = 3 v 10% 2.2 ma analog reference voltage supply current = 0 i ref vcc = 2.7 to 5.5 v 0.02 5.0 a vcc = 5 v 10% 3 total tolerance (excludes quantization error) e t vcc = 3 v 10% 3 lsb note 1: 1lsb = (vrefh -vrefl)/2 10 [v] note 2: power supply current icc from the vcc pin includes the power supply current from the avcc pin. 4.5 serial channel timing (serial channel 2, 3 and 4) (1) sclk input mode variable 32.768 mhz (note) 12.5 mhz 20 mhz parameter symbol min max min max min max min max sclk cycle t scy 16x 488 s 1.28 s0.8 s output data rising edge of sclk t oss t s cy /2 ? 5x ? 50 91.5 s 190 ns 100 ns sclk edge * output data hold t ohs 5x ? 100 152 s 300 ns 150 ns sclk edge * input data hold t hsr 0 000 sclk edge * effective data input t srd t s cy ? 5x ? 100 336 s 780 ns 450 ns * it is rising edge in using rising edge mode and falling edge in using falling edge mode. (2) sclk output mode variable 32.768 mhz (note) 12.5 mhz 20 mhz parameter symbol min max min max min max min max sclk cycle (programmable) t scy 16x 8192x 488 s 250 ms 1.28 s 655.36 s 0.8 s 409.6 s output data sclk rising edge t oss t s cy ? 2x ? 150 427 s 970 ns 550 ns sclk rising edge output data hold t ohs 2x ? 80 60 s 80 ns 20 ns sclk rising edge input data hold t hsr 0000 sclk rising edge effective data input t srd t s cy ? 2x ? 150 428 s 970 ns 550 ns (3) sclk input mode (uart mode) variable 32.768 mhz (note) 12.5 mhz 20 mhz symbol parameter min max min max min max min max t scy sclk cycle 4x + 20 122 s 340 ns 220 ns t scyl low level sclk pulse width 2x + 56 s 165 ns 105 ns t scyh high level sclk pulse width 2x + 56 s 165 ns 105 ns note: fs is used as system clock or input clock to prescaler.
tmp91cw11 2001-08-06 91cw11-255 timing chart for i/o interface mode valid 3 2 1 0 t hsr valid valid valid t ohs t oss t srd sclk output data txd input data rxd t scy note: sclk is reversed in sclk input falling mode.
tmp91cw11 2001-08-06 91cw11-256 4.6 timer/counter input clock (ti0, ti4, ti5, ti6, ti7) variable 12.5 mhz 20 mhz unit parameter symbol min max min max min max clock cycle t vck 8x + 100 740 500 ns low level pulse width t vckl 4x + 40 360 240 ns high level pulse width t vckh 4x + 40 360 240 ns 4.7 interrupt and capture (1) nmi , int0 interrupts variable 12.5 mhz 20 mhz unit parameter symbol min max min max min max nmi , int0 low level pulse width t intal 4x 320 200 ns nmi , int0 high level pulse width t intah 4x 320 200 ns (2) int4 to 7 variable 12.5 mhz 20 mhz unit parameter symbol min max min max min max int4 to int7 low level pulse width t intbl 4x + 100 420 300 ns int4 to int7 high level pulse width t intbh 4x + 100 420 300 ns 4.8 serial bus interface timing (1) i 2 c bus mode variable unit parameter symbol min typ max start command sda fall t gsta 3x s hold time start condition t hd: sta 2 n xs scl low level pulse width t low 2 n xs scl high level pulse width t h igh 2 n x + 8x s data hold time (input) t hd: idat 0ns data set-up time (input) t su: idat 250 ns data hold time (output) t hd: odat 7x 11x s data output scl rising edge t odat 2 n x ? t hd: odat s stop command sda falling edge t fsda 3x s sda falling edge scl rising edge t fdrc 2 n xs set-up time stop condition t su: sto 2 n x + 16x s note: n value is set by sbicr1 stop command start command scl sda t fsda t fdrc t odat t high t gsta t low t su:idat t hd:idat t hd:odat t hd:sta t su:st
tmp91cw11 2001-08-06 91cw11-257 (2) clocked-synchronous 8-bit sio mode a. sck input mode variable unit parameter symbol min max sck cycle t scy2 2 5 xs sck falling edge output data hold t ohs2 6x s output data sck rising edge t oss2 t scy2 /2 ? 6x s sck rising edge input data hold t hsr2 6x ns input data sck rising edge t iss2 0ns b. sck output mode variable unit parameter symbol min max sck cycle t scy2 2 5 x2 11 xs sck falling edge output data hold t ohs2 2x s output data sck rising edge t oss2 t scy2 /2 ? 2x s sck rising edge input data hold t hsr2 2x s input data sck rising edge t iss2 0ns so (output data) sck (input/output mode) si (input data) t scy2 t ohs2 t hsr2 t iss2 t oss2
tmp91cw11 2001-08-06 91cw11-258 4.9 timing chart for sirial channel 0,1 a. sck input mode variable unit parameter symbol min max sck cycle t scy 16x ns sck falling edge output data hold t skdo 6x ns sck rising edge effective data input t srd t scy ? 2x ns sck rising edge input data hold t hsr 6x ns b. sck output mode variable unit parameter symbol min max sck cycle t scy 16x ns sck falling edge output data hold t skdo 2x ns sck rising edge effective data input t srd t scy ? 2x ns sck rising edge input data hold t hsr 2x ns so (output data) valid valid valid valid sck si (input data) t srd t skdo t scy t scl t sch t hsr
tmp91cw11 2001-08-06 91cw11-259 4.10 scout pin ac characteristics variable 12.5 mhz 20 mhz parameter symbol min max min max min max unit high-level pulse width vcc = 5 v 10% 0.5x ? 10 30 15 ns vcc = 3 v 10% t sch 0.5x ? 20 20 ? ns low-level pulse width vcc = 5 v 10% 0.5x ? 10 30 15 ns vcc = 3 v 10% t scl 0.5x ? 20 20 ? ns measurement condition ? output level: high 2.2 v / low 0.8 v, cl = 10 pf scout t scl t sch
tmp91cw11 2001-08-06 91cw11-260 4.11 timing chart for bus request ( busrq )/bus acknowledge ( busak ) busak busrq ale clk t brc t aba t cbal t baa t cbah t brc (note 2) (note 2) (note 1) ad0 to ad15, a0 to a23, cs0 to cs2, r/w rd, wr, hwr variable 12.5 mhz 20 mhz unit parameter symbol min max min max min max busrq set-up time to clk t brc 120 120 120 ns clk busak falling edge t cbal 1.5x + 120 240 195 ns clk busak rising edge t cbah 0.5x + 40 80 65 ns output buffer is off to busak t aba 080080080ns busak to output buffer is on. t baa 080080080ns note 1: the bus will be released after the wait request is inactive, when the busrq is set to 0 during wait cycle. note 2: this line shows the output buffer is off-state. it doent indicate the signal level is fixed. just after the bus is released, the signal level which is set before the bus is released is kept dynamically by the external capacitance. therefore, to fix the signal level by an external resistor during bus releasing, designing is executed carefully because the level - fix will be delayed. the internal programmable pull-up/pull-down resistor is switched active/non-active by an internal signal.

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