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STLC7545 enhanced v.34 bis analog front-end november 1998 . full echo cancelling capability . fully compatible with the st7544 . 16-bit oversampling a/d and d/a con- verters - programmable down-sampling frequency from 7200 to 22khz. - sampling frequency can be 3, 4, 6, 8, 12, 16 x symbol rate. - programmableoversampling frequency(128, 160 or 192 x sampling frequency). - the STLC7545 can work with external over- sampling clocks. - programmable symbol rate (600, 1200, 1600, 2400, 2560, 2743, 2800, 2954, 3000, 3200, 3429 and 3491). - bit rates of 300bps, 600bps, 1200 and all multiples of 2400bps up to 38400bps can be generated. - dynamic range : 92db with a sampling fre- quency 9600hz, oversampling ratio 160. - total harmonic distortion : -89db. . on chip reference voltage . three programmable digital filters sections (up to 14th order each, coefficients loaded into ram) : - tx interpolation filter - rx decimation filter - rx reconstruction filter . ancillary converters for eye-dia- gram monitoring . clock system based on digital phase locked loops - separate tx dpll and rx dpll - terminal clock input for tx synchronizationon all multiples of 2400hz (vfast synchronization mode) or on sub-multiple of baud rate (7544 synchronization mode) - bit, baud, sampling and highest synchronous clock outputs - maximum master clock frequency is 38mhz . single or dual synchronous serial interface to dsp . analog power supply voltage : +5v . digital power supply from 3.3v to 5v . low power consumption : - 100mw operating power at the nominal crystal frequencyof 36.864mhz(digitalsupplyat 3.3v) - less than 5mw in the low-power reset mode . 0.7 m m cmos process . plcc44 or tqfp44 (1.4mm body thickness) description theSTLC7545is a single chip analogfront-end(afe) designed to implement high speed voice-grade mo- dems up to 384kbpswith echo cancelling capability. associated with one or several digital signal proces- sors (dsp), it provides a powerful solution for the implementation of multi-mode modems meeting ccitt (v.17, v.21, v.22, v.22 bis, v.23, v.26, v.27, v.29,v.32,v.32bis,v.33,v.34andv.34bis)andbell (103, 202, 212a...) recommendations. it is fully com- patiblewith the st7544 and is also well suited emerg- ing applications involving bit rates up to 38400bps (in the vfast synchronization mode). the transmit section includes a 16-bit over-sampling d/a converter with a programmable interpolating filter. the receive section includesa 16-bit oversampling a/d converter with two programmable filters (one for deci- mation andtheotherforreconstruction).oversampling ratio is selectable to either 128, 160 or 192. two addi- tional8-bitd/a convertersalloweyediagrammonitoring on a scope for modem performance adjustment. two independantclock generator systems are pro- vided, one synchronized on the tx rate and the other on the rx rate. in external clock mode, external oversampling clocks can be provided to the chip. two independant synchronous serial interfaces (ssi) allow several versatile ways of communicat- ing with standard dsps. to save power, e.g. in lap-top modem applications, the lowpower reset mode can be used to reduce the power consumption to less than 5mw. plcc44 (plastic leaded chip carrier) order code : STLC7545cfn tqfp44 (10 x 10 x 1.4mm) (thin full plastic quad flat pack) order code : STLC7545tqfp4y 1/53
table of contents page i pin description ................................................... 5 i.1 pin connections (top view) . ........................................ 5 i.2 pin list. . . . . . . . . . . . . . . . . . . . . . . . .................................... 6 i.3 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 7 ii block diagram .................................................... 10 iii functional description ........................................... 11 iii.1 signal transfer block diagram . .................................. 11 iii.2 transmit d/a section . . . . .......................................... 12 iii.2.1 interpolation filters. . . . ................................................ 12 iii.2.1.1 programmable interpolation filter (iir1) . . . . . . . . . . . . . . . . . . . . . . . .......... 12 iii.2.1.2 fir filter (fir1) . . . . ................................................ 12 iii.2.2 d/a converter. ....................................................... 12 iii.3. receive a/d section. . . . . . . . . . . . . . . . . . . . . . ............................. 12 iii.3.1 a/d converter. ....................................................... 12 iii.3.2 decimation filters. .................................................... 12 iii.3.2.1 fir filter (fir2) . . . . ................................................ 12 iii.3.2.2 programmable decimation filter (iir2) . . . . . . . . . ......................... 13 iii.3.3 eye-diagram display . ................................................. 13 iii.4 receive reconstruction section . . . . . . . . . . . . . . . . . . . . . . . .......... 13 iii.4.1 programmable interpolation filter (iir3) . .................................. 13 iii.4.2 fir filter (fir3) . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 13 iii.5 clock generation. . . . . . . . . ........................................ 14 iii.5.1 transmit dpll . . . . ................................................... 15 iii.5.2 transmit clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 15 iii.5.2.1 internal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 15 iii.5.2.2 external mode. . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 15 iii.5.3 receive dpll. ....................................................... 16 iii.5.4 receive clocks. . . . ................................................... 16 iii.5.4.1 internal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 16 iii.5.4.2 external mode. . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 16 iii.6 serial input/output synchronous interfaces . . . . . . .............. 16 iii.6.1 tx clock related registers . . . . . . . . . . . . . . . . . . . . . . . ...................... 17 iii.6.2 rx clock related registers . . . . . . . . . . . . . . . . . . . . . . . ...................... 17 iv serial interface operation ....................................... 18 iv.1 dual serial interface mode (ssia, ssib) . . . . . . . . . ................... 18 iv.2 single serial interface mode . . . . ................................. 19 iv.3 coefficient loading mode. ........................................ 20 iv.4 coefficient reading . . . . .......................................... 21 iv.5 crystal selection (xtal10, xtal11) . . . . . . .......................... 21 iv.6 frame frequency programming. .................................. 21 iv.7 initialization and low-power reset mode . . . . . . .................... 21 STLC7545 2/53
table of contents (continued) page v circuit programming ............................................. 23 v.1 mode field . ....................................................... 23 v.2 address field. .................................................... 23 v.2.1 ram address field. . . . ................................................ 23 v.2.2 transmit control register address field . .................................. 23 v.2.3 receive control register address field. . . . . . . ............................. 24 v.3 control register data field. ..................................... 24 v.3.1 transmit control register programming . .................................. 24 v.3.2 receive control register programming. . . . . . . ............................. 24 v.3.3 control bit function summary . . . . ....................................... 25 v.3.3.1 txctrl word. . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 25 v.3.3.2 rxctrl word . .................................................... 25 vi programmable functions ........................................ 26 vi.1 transmit section . . . . ............................................. 26 vi.1.1 transmit bit rate clock frequency programming with fq=36.864mhz . . . . . . ..... 27 vi.1.2 transmit bit rate clock frequency programming with fq=25.8048mhz . . . . . . . . . . 27 vi.1.3 transmit bit rate clock frequency programming with fq=18.432mhz . . . . . . ..... 28 vi.1.4 transmit bit clock frequency programming. divisor rank . . . . . . . . . . . . . . . . . . . . . 29 vi.1.5 transmit sampling clock frequency programming with fq=36.864mhz . . . . . . . . . . 30 vi.1.6 transmit sampling clock frequency programming with fq=25.8048mhz . . . . . . . . . 30 vi.1.7 transmit sampling clock frequency programming with fq=18.432mhz . . . . . . . . . . 30 vi.1.8 transmit sampling clock frequency programming. divisor rank. . . . . . . . . ....... 31 vi.1.9 transmit baud rate frequency programming. divisor rank. . . . . . .............. 31 vi.1.10 highest synchronous transmit frequency programming. divisor rank . . . . . . ..... 31 vi.1.11 band split mode . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 31 vi.1.12 transmit synchronization signal programming . . . . . . . . . . . . . . . . . . . . . . . ....... 32 vi.1.13 clock mode programming & r2 divisor . . . . . . . ............................. 32 vi.1.14 transmit attenuator programming . . . . .................................... 32 vi.1.15 phase comparator frequency and decimation or interpolation ratio . . . . . . . . . .... 32 vi.1.16 phase shift frequency . . . . ............................................. 33 vi.1.17 transmit test programming. . . . . . . . . . . . . . . . . . . . . . . ...................... 33 vi.2 receive section. . . . . . . . . . . . . . . . . . . . . . ............................. 34 vi.2.1 receive bit rate clock frequency programming with fq=36.864mhz. . . . . . . . . . . . 35 vi.2.2 receive bit rate clock frequency programming with fq=25.8048mhz. . . . . . ..... 35 vi.2.3 receive bit rate clock frequency programming with fq=18.432mhz. . . . . . . . . . . . 36 vi.2.4 receive bit rate clock frequency programming. divisor rank . . . . . . ........... 37 vi.2.5 receive sampling clock frequency programming with fq=36.864mhz . . . . . . . . . . 38 vi.2.6 receive sampling clock frequency programming with fq=25.8048mhz . . . . . . . . . 38 vi.2.7 receive sampling clock frequency programming with fq=18.432mhz . . . . . . . . . . 38 vi.2.8 receive sampling clock frequency programming. divisor rank . . . . . . . . . ....... 39 vi.2.9 receive baud rate frequency programming. divisor rank . . . . . . .............. 39 vi.2.10 highest synchronous transmit bit frequency programming. divisor rank. . . . . . . . . 39 vi.2.11 receive fine phase shift programming. . . . . . . ............................ 40 vi.2.12 receive coarse phase shift programming . . . . . . . . . . . . . . . . . . . . . . . .......... 40 vi.2.13 interpolation ratio . . . . ................................................ 41 vi.2.14 receive test programming & r2 divisor . .................................. 41 STLC7545 3/53
table of contents (continued) page vii electrical specifications ........................................ 42 vii.1 absolute maximum ratings (referenced to gnd) . . . . . . ................. 42 vii.2 dc characteristics . .............................................. 42 vii.2.1 power supply and common mode voltage . . . . . . . . . . . . . . . . . . . . . . . .......... 42 vii.2.2 digital interface. . . . ................................................... 42 vii.2.3 crystal oscillator interface (xtal10,xtal11). . . . . . . . . ...................... 42 vii.2.4 analog interface . . . . . . . . . . . . . . . . . . . . . . . . . . . ........................... 43 vii.3 ac electrical specifications. ..................................... 44 vii.3.1 serial channel timing . . . . ............................................. 44 viii transmit characteristics ........................................ 45 viii.1 test conditions. . . . . . . . . . . . . . . . . . . . . . ............................. 45 viii.2 performance of the tx chain . . . . ................................. 45 viii.3 smoothing filter transfer characteristics. . . . . . . . . ............. 45 ix receive characteristics .......................................... 46 ix.1 test conditions. . . . . . . . . . . . . . . . . . . . . . ............................. 46 ix.2 performance of the rx chain . . . . ................................. 46 x typical applications .............................................. 47 x.1 multi-standard modem with echo cancelling . . . . . . . . . . . . . . . . . . . . . 47 x.2 line interface . . . . ................................................ 47 x.3 common mode voltage generation and decoupling . . . . . . . . . . . . . . . 48 x.4 crystal oscillator . .............................................. 48 xi annexe a .......................................................... 49 xi.1 iir filter operation . .............................................. 49 xi.1.1 coefficient rounding . . . . . . . . . . . . . . . . . . . . . . . ...................... 49 xi.1.2 detailed operation . .............................................. 49 xii package mechanical data ........................................ 52 STLC7545 4/53
18 19 20 21 22 23 24 25 26 27 28 9 10 11 12 13 14 15 16 17 29 30 31 32 33 34 35 36 37 7 8 38 39 40 41 42 43 44 1 2 3 4 5 6 txdi txdo fsx bclkx eyey dgnd2 eyex rxclk rxhsclk rxsync agndt v cm rxa2 rxa1 agndr rxoclk (test3) eocmode (test1) nlpr (nreset) rxdi rxdo fsr bclkr dgnd1 ssim bfrs txoclk (test2) txa1 txa2 dv dd2 dv dd1 av dd v refp v refn txsync txhsclk dgnd3 dv dd3 txsclk xtal2 xtal10 xtal11 rxrclk txrclk txclk note : the pin names in the parenthesis are the corresponding for the st7544. 7545-01.eps plcc44 i - pin description 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 8 9 10 11 23 24 25 26 27 28 29 30 31 1 2 32 33 34 35 36 37 38 39 40 41 42 43 44 txdi txdo fsx bclkx eyey dgnd2 eyex rxclk rxhsclk rxsync agndt v cm rxa2 rxa1 agndr rxoclk (test3) eocmode (test1) nlpr (nreset) rxdi rxdo fsr bclkr dgnd1 ssim bfrs txoclk (test2) txa1 txa2 dv dd2 dv dd1 av dd v refp v refn txsync txhsclk dgnd3 txsclk xtal2 xtal10 xtal11 rxrclk txrclk txclk dv dd3 7545-01.eps tqfp44 i.1 - pin connections (top view) STLC7545 5/53
i - pin description (continued) i.2 - pin list pqfp plcc name description 39 1 dgnd1 digital ground (0v) 40 2 dv dd1 positive digital power supply (3.15v to 5.25v) 41 3 bclkr receive bit clock output 42 4 fsr receive frame synchronization output 43 5 rxdo receive serial data output 44 6 rxdi receive serial data input 1 7 txdi transmit serial data input 2 8 txdo transmit serial data output 3 9 fsx transmit frame synchronization output 4 10 bclkx transmit bit clock output 5 11 eyey 8 bit y d/ac output for eye pattern display 6 12 dgnd2 digital ground (0v) 713 dv dd2 positive digital power supply (3.15v to 5.25v) 8 14 eyex 8bit x d/ac output for eye pattern display 9 15 rxclk receive bit rate clock output 10 16 rxhsclk receive highest clock output 11 17 rxsync receive synchronization pulse output 12 18 rxrclk receive baud rate clock output 13 19 txrclk transmit baud rate clock output 14 20 txsync transmit synchronous pulse output 15 21 txhsclk transmit highest clock output 16 22 txclk transmit bit rate clock output 17 23 dgnd3 digital ground (0v) 18 24 dv dd3 positive digital power supply (3.15v to 5.25v) 19 25 txsclk transmit synchronization clock input 20 26 xtal2 crystal output 21 27 xtal10 external clock/crystal input 1 22 28 xtal11 external clock/crystal input 2 23 29 nlpr low power reset input 24 30 eocmode (test1) external oversampling clock mode input. must be tied to dgnd in either the STLC7545 normal mode or the 7544 mode. 25 31 rxoclk (test3) receive oversampling clock input. output high-impedance in normal mode. 26 32 v refn 16 bit d/ac and a/dc negative reference voltage 27 33 v refp 16 bit d/ac and a/dc positive reference voltage 28 34 agndr analog ground (0v) 29 35 rxa1 receive positive analog input 30 36 rxa2 receive negative analog input 31 37 av dd positive analog power supply (+5v 5%) 32 38 v cm common mode voltage output (2.5v 10%) 33 39 agndt analog ground (0v) 34 40 txa1 smoothing filter positive output 35 41 txa2 smoothing filter negative output 36 42 txoclk (test2) transmit oversampling clock input. output high-impedance in normal mode. 37 43 bfrs bit frame rate select input 38 44 ssim serial synchronous interface mode input note : the pin names in brackets are the corresponding names for the st7544. STLC7545 6/53
i - pin description (continued) i.3 - pin function i.3.1 - power supply (9 pins) analog v dd supply (av dd ) this pin is the positive analog power supply (+5v 5%) for the transmit and the receive sec- tions. it is not internally connected to digital v dd supply (dv dd1-3 ). digital v dd supply (dv dd1 ,dv dd2 ,dv dd3 ) these pins are the positive digital power supply (3.5v to 5.25v) for transmit and receive digital internal circuitry. analog ground (agndt,agndr) these pins are the analog ground return of the analog transmit (receive) section. digital ground (dgnd1,dgnd2,dgnd3) these pins are the ground connections for trans- mit and receive internal digital circuitry. note 1 : to obtain published performance, the analog v dd and digital v dd should be decoupled with respect to agnd and dgnd, respectively. the decoupling is intended to isolate digital noise from the analog section; decoupling capacitors should be as close as possible to the respective analog and digital supply pins. note 2 : all the ground pins must be tied together. in the following section, the ground and supply pins are refered to as gnd and v dd , respectively. i.3.2 - clock and control signals (16 pins) externalclock/crystalinputs (xtal10,xtal11) xtal10 and xtal11 inputs must be tied to exter- nal crystal(s) or external clock(s). these inputs are selected from the txctrl register. the maximum clock rate is 38mhz. xtal10 is the default external clock/crystal input. it is mandatory to shortcircuit xtal10 and xtal11 whena singleexternalcrystal or clock generator is used. the nominal master clock frequency is 36.864mhz (this frequency and the frequency 25.8048mhz are well suited for the v.34 application) but the onchip amplifier is de- signed for a parrallel crystal oscillator with a fre- quency equal to 18.432mhz. the other master clocks frequencies (18.432mhz, 25.8048mhzand 29.4912mhz) are well suited for the well known ccitt recommendations (v.21 through v.32bis). crystal outputs (xtal2) this output is to be tied to one or two external crystals (see figure 1). if an external clock is used, xtal2 should be left open circuit. low power and reset input (nlpr) this pin , when low, synchronizes the STLC7545 clock system and puts it in low power mode. nlpr pin must be tied to v dd during normal operation. access to the chip is disabled during power-on reset until the clock oscillator starts. the reset time duration can be increased by connecting the nlpr input to an externalrc network (see figure 9). the low-power reset mode is activated when this pin is tied to gnd (operation of all clocks and the analog section is stopped). transmit synchronization clock input (txsclk) this pin can be connected to an external terminal clock to phase-lock the internal transmit clocks. it can be disabled under software control to allow the tx dpll to free run or phase lock on the rx clock system. to phase lock the txdpll there must be transition on txsclk input within fcomp period when programming txcr2 register. transmit bit rate clock output (txclk) this pin outputs the synchronous transmit bit clock selected for the modem. transmit baud rate clock output (txrclk) this pin, when the bit d4 within receive register rxcr3 is set to 0, outputs the synchronous trans- mit baud rate clock (initial state). when bit d4 is set to 1 this pin outputs the frequency comparison signal fcomp (used by the txdpll in both 7544 mode and v.fast synchronization) when bit 0 of rxcr1 is set to 0 this output is disabled. transmit synchronization pulse output (txsync) this pin outputs the synchronization transmit reset pulse when a softresetis appliedto the STLC7545. combined with txhsclk clock it can be used to externally provide any synchronous transmit clock. transmit highest clock output (txhsclk) this pin outputs the highest synchronous transmit clock to provide any external or multiplexing clock when bit 0 of rxcr1 is set to 0 this output is disabled. transmit oversampling clock input (txoclk) this input can be connected to an external clock to provide the chip with the over-sampling clock, de- pending on the external over sampling mode input (eocmode). in normal mode this pin should be static (tied to gnd or v dd ). receive bit rate clock output (rxclk) this pin outputs the synchronous receive bit clock selected for the modem. receive baud rate clock output (rxrclk) this pin outputs the synchronous receive baud rate clock when bit 0 of rxcr1is set to 0 this output is disabled. STLC7545 7/53
i - pin description (continued) receive synchronization pulse output (rxsync) this pin outputs the synchronization receive reset pulse when a soft reset is applied to the STLC7545. combined with rxhsclk clock it can be used to externally provide any synchronous receive clock. receive highest clock output (rxhsclk) this pin outputs the highest synchronous receive clock to give any external or multiplexing clock when bit 0 of rxcr1 is set to 0 this output is disabled. receive oversampling clock input (rxoclk) this input can be connected to an external clock to provide the chip with the oversampling clock, de- pending on the external over sampling mode input pin (eocmode). in normal mode this pin should be static (tied to gnd or v dd ). external oversampling clock mode (eocmode) this pin is used forselecting one of the twopossible oversampling modes. when eocmode is tied to gnd, all the clock are provided internally (mode compatible with the st7544). when eocmode is tied to v dd , the oversampling clocks must be input on txoclk and rxoclk pins. the txhsclk (rxhsclk) and txsync (rxsync) signals along with external fractional divider can be used to pro- vide the oversampling clocks to the STLC7545. i.3.3 - synchronous serial interfaces (ssia,ssib) (10 pins) serial synchronous interface mode input (ssim) this input activates one or both serial interfaces. when ssim is tied to v dd , both a and b ports are functional : port a (ssia) is dedicated to the trans- mit channel and port b (ssib) is dedicated to the receive channel. when ssim is tied to gnd only port a (ssia) is selected. in this case ssia carries both tx and rx signals and eye pattern. bit frame rate select input (bfrs) this input selects one of the two possible bit fre- quenciesfor the bclkx and bclkr clocks. when bfrs is tied to v dd the bclkx (bclkr) frequen- cies are equals to the oversampling ratio (divider v table 40) times the fsx (fsr) frequencies. when bfrs is tiedto gnd, bclkx (bclkr) frequencies are equal to v/2 times the fsx (fsr) frequencies. frame synchronization transmit output (fsx) this output clock is the transmit frame synchroni- zation pulse signal of the ssia port which has nominal frequency equal to the transmit sampling frequency.this pulse indicatesthe beginningof the 16-bit serial words on the serial data input/output port a. bit clock transmit output (bclkx) this output pin provides the serial bit clock for the ssi port a. the bclkx frequency equals v or v/2 times the transmit sampling frequency, depending on the bit frame select input (bfrs). serial data transmit input (txdi) this input receives word-oriented serial data. data is loadedfrom txdi into the transmit shift register (tsrin) on the falling edge of bclkx and trans- fered to the transmit bufferregister(tbrin) when a complete 16 bit word has been received. data is assumed to be received msb first. serial data transmit output (txdo) this output sends word-oriented serial data. the 16 bit data word loaded in the transmit buffer register (tbrout) is transfered to the transmit shift register (tsrout) and clocked out of tsrout on the rising edge of bclkx. serial words are transmitted msb first. receive frame synchronization output (fsr) this output clock is the receive frame synchroni- zation pulse signal of ssi port b which has fre- quency equal to the receive sampling frequency. this pulse is used to indicate the beginning of serial words on the serial data input/output port b. receive bit clock output (bclkr) this output pin provides the serial bit clock for the ssi port b. the bclkr frequency is v times or (v/2) times, selected by bfrs ) the receive sam- pling frequency. receive serial data input (rxdi) this input receives word-oriented serial data. data is clockedfrom rxdiinto the receive shift register (rsrin) on the falling edge of bclkr and trans- fered to the receive buffer register (rbrin) when a complete 16-bit word has been received. data is assumed to be received msb first. receive serial data output (rxdo) this output sends word-oriented serial data. the 16-bit data word loaded in the receive buffer register (rbrout) is transfered to the receive shift register (rsrout) and clocked out of rsrout on the rising edge of bclkr. serial words are transmitted msb first. STLC7545 8/53
i - pin description (continued) i.3.4 - analog interface (9 pins) d/ac and a/dc positive reference voltage out- put (v refp ) this pin provides the positive reference voltage used by the 16-bit converters. the reference volt- age, v ref , is the voltage difference between the v refp and v refn outputs, and its nominal value is 2.5v. v refp should be externally decoupled with respect to v cm (see figure 17). d/ac and a/dc negative reference voltage (v refn ) this pin provides the negative reference voltage used by the 16 bit converters, and should be exter- nally decoupled with respect to v cm . common mode voltage output (v cm ) this output pin is the common mode voltage (av dd -agnd)/2 internally generated. this output must be decoupled with respect to agnd. this output pin could be forced externally (compatible with st7544 application). smoothing filter positive output (txa1) this pin is the positive output of the fully differential analog smoothing filter. smoothing filter negative output (txa2) this pin is the negativeoutput of the fullydifferential analog smoothing single pole switch capacitor fil- ter. outputs txa1 and txa2 provide analog signals with maximum peak to peak amplitude 2 x v ref , and must be followed by an external continuous time two pole smoothing filter (see figure 16). the smoothing filter order depends of the acceptable transmit signal spectrum on the line. the cut-off frequency of the external filter must be greater than two times the transmit sampling frequency (fsx), so that the combined frequency response of both the internal and external filters is flat in the pass band. receive positive analog input (rxa1) this pin is the differential positive a/dc input. receive negative analog input (rxa2) this pin is the differential negative a/dc input. these analog inputs (rxa1,rxa2) are presented to the sigmadelta modulator,the analoginput peak to peak signal range must be less than 2 x v ref , and must be preceededby an external continuous- time single pole anti-aliasing filter (see figure 16). the cut-off frequency of the filter must be lower than one half the transmit over-sampling frequency (txosck). these filters should be set as close as possible to the rxa1 (rxa2) pins. d/ac output for eye pattern (eyex,eyey) these pins are the outputs of two 8-bit digital to analog converters used to monitor, on a crt, the x and y quadrature signals of the eye pattern of the demodulated signal. STLC7545 9/53
ii - block diagram reference voltage s witch capacitor lpf & attenuator tx filter & d/ac digital reconstruction filter digital inter face control registers 16 bits 8 8 d7:d0 d15:d8 rx filter & a/dc 16 bits 16 bits 16 bits 16 bits (12+1) bits coefficients d/ac d/ac av dd agndt txa1 txa2 v refp v cm v refn rxa1 rxa2 eyex eyey agndr dv dd1 dv dd2 dv dd3 fsx bclkx txdi txdo ssim bfrs (fsr) (bclkr) (rxdi) (rxdo) dgnd1 dgnd2 dgnd3 nlpr txclk txsync txrclk txhsclk txsclk rxclk rxsync rxrclk rxhsclk synchronous serial port a (ssia) synchronous serial port b (ssib) txoclk eocmode rxoclk tx & rx dpll clock generators xtal11 xtal10 xtal2 7545-03.eps figure 1 : general block diagram STLC7545 10/53
iii - functional description s erial/parallel conversion control logic ressig fir1 fir2 fir3 iir3 ram3 iir2 ram2 iir1 ram1 a/dc d/ac rxtx txs ig ana log input (rx signal + echo) analog output (tx signal) rxs ig selector rxsig fs rsync fs rs ync rxs2 rxs1 status 2bits txdo bclkx txdi ssia s erial/parallel conversion ssib rxdo bclkr rxdi 16-bit data bus s ynchronized to the tx clock s yste m reg fsx fsx fsx 4xfsx fsx 4xfsx fs x fsr txoclk 4xfsx fs x note : re gister with trista te ou tput fs r fs r or5xfsx or5xfsx or 6 x fsx or 5 x fsx or 6 x fsx txoclk txoclk rxoclk txoclk txoclk = 128 or 160 x fsx or 192 x fsx txoclk txoclk 16-bit da ta bus s ynchronized to the rx clock s ys tem d/ac eyex eyey 88 d7:d0 d15 :d8 d/ac multiplexer ssim 16-bit da ta bus tx 7545-04.eps figure 2 : signal transfer block diagram iii.1 - signal transfer block diagram the STLC7545 block diagram illustrates three paths as follows : the transmit d/a section, the receive a/d section and the receive reconstruction section. STLC7545 11/53
iii - functional description (continued) iii.2 - transmit d/a section the functions included in the tx d/a section are detailed hereafter. iii.2.1 - interpolation filters the oversampling is performed by two cascaded digital interpolating filters : iir1 and fir1. the iir1 and fir1 filters are sampled at 4 x fsx and 128 x fsx (5 x fsx and 160 x fsx) (6 fsx and 192 x fsx), respectively. iii.2.1.1 - programmable interpolation filter (iir1) iir1 is an infinite impulse response interpolating filter. the purpose of this digital filter is to interpolate 4-times (5 times, 6 times) the digital signal coming from the dsp. this filter is sampled at the basic sampling frequency, (e.g. 9600 x 4 hz), and must exhibit, as a minimum, a low-pass section which is mandatory to remove replicas above half the sam- pling frequency (e.g. 4800hz) (see figure 13). the digital samples are encoded in 16-bit two's complement format. the iir1 filter is a cascade of seven biquads (see figure a1). the filter coefficients are loaded into the associated ram (38 x 13). each coefficient is coded into 12bits and can be doubled by virtue of an extra bit. all 38 coefficients have to be loaded to implement an iir transfer function (see an- nexe a). this filter has been made programmable to offer each user the possibility to add filtering charac- teristics, e.g. high-pass section or equalization, matched to a particular application. iii.2.1.2 - fir filter (fir1) fir1 is a finite impulse responseinterpolatingfilter. its input sampling frequency is 4 x fsx (or 5 x fsx) (or 6 x fsx) and its interpolation ratio is 32. the z transfer function of this fir is : h ( z )= ? ? ? 1 - z - 32 32 ( 1 - z - 1 ) ? ? ? 3 with z = exp (j2 p f/txoclk) and txoclk = 128 (160, 192) x fsx iii.2.2 - d/a converter the 128-times (160 times, 192 times) oversampled d/a converter includes a second order digital noise shaper, a one bit d/a converter and a single pole analog low-pass filter. the gain of the last output stage can be programmed to 0db,-6db or infinite attenuation.the cut-off frequencyof the single pole switch-capacitor low-pass filter is : fc-3db=txoclk /(2 x p x 10) where txoclk = 128 (160, 192) x fsx continuous-time filtering of the analog differential output is necessary using an off-chip amplifier and a few external passive component s (see fig- ure 16). at least 86db signal to noise plus distortion ratio can be obtained in the frequency band 300- 3400hz, with a -6dbr output signal. iii.3 - receive a/d section the different functions included in the rx a/d section are detailed hereafter. the format used at the digital interfaces of the rx channel is two's complement encoded 16-bit. iii.3.1 - a/d converter the 128 (160, 192) oversampled a/d converter is based on a second order sigma-delta modulator. the signal to noise plus distortion ratio obtained for a signal spectrum limited to the 300-3400hz tele- phone band, is typically 86db with a -6dbr input signal. iii.3.2 - decimation filters the 128 (160, 192) decimation is performed by two interpolatingdigital filters: fir2 and iir2,which are sampled at 128 x fsx and 4 x fsx (160 x fsx and 5 x fsx) (192 x fsx and 6 x fsx), respectively . iii.3.2.1 - fir filter (fir2) fir2 is a finite impulse response decimating filter. its sampling frequency is 128 x fsx (or 160 x fsx or 192 x fsx) and its decimation ratio is 32. the z transfer function of this fir is : h ( z )= ? ? ? 1 - z - 32 32 ( 1 - z - 1 ) ? ? ? 3 with z = exp (j2 p f/txoclk) and txoclk = 128 (160, 192) x fsx STLC7545 12/53
iii - functional description (continued) iii.3.2.2- programmabledecimation filter (iir2) iir2 is an infinite impulse responsefilter. it provides the low-pass filtering needed to remove the noise remaining above half the sampling frequency (e.g. 4800hz) (see figure 14). the output of the iir2, rxtx, will be processed by the dsp. in oband splito mode (see table 21), rxtx becomes the input signal to iir3. the rxtx will always be avail- able on serial interface (ssia in figure 2). the iir2 filter is a cascade of seven biquads. the filter coefficients are loaded into the associated ram (38 x 13). the filter transfer function has been made pro- grammable in order to meet specific requirements. the sampling frequency is 4-times (5-times, 6- times) the down-sampling frequency selected for the tx section (e.g. 9600 x 4hz). to support echo cancelling applications the clocks used for the a/d converter and the decimation filters are synchronized on the tx system clock, i.e. on the tx rate. it must be pointed out that using a single clock system in a/d and d/a conversions is important for reducing induced noise. the 12+1 bit filter coefficients are loaded into the internal ram2 and must be loaded from the serial bus. all 38 coefficients have to be loaded to imple- ment an iir transfer function. iii.3.3 - eye-diagram display two 8-bit digital to analog converters are provided to monitor, on a crt, the x and y quadrature signals of the eye pattern related to the demodu- lated signal. the format of the data input is msb first, 8-bit two's complement, and most significant byte for eyey sample and least significant byte for the eyex sample. the reference voltage of these two converters is the power supply voltage v dd . the eye pattern can be monitored on one or two synchronous serial interface mode. iii.4 - receive reconstruction section as the rx channel sampling is synchronized to the tx system clock, it is necessary to reconstruct the rx signal in order to get samples synchronized to the rx symbol rate recovered in the demodulator. the function of the reconstruction filter (iir3 and fir3) is to oversample by 128 x fsx (160 x fsx, 192 x fsx) the receive signal (ressig) comming from the dsp after echo cancellation. the over- sampled signal is then down-sampled at fsr rate to make it available to the dsp as rxsig at ssib or rxs1/rxs2 at ssia (see section iv.1 and iv.2). the down sampling process does not introduce significant error. the transfer function of the first section of the reconstruction filter is programmable in the same way as the tx and rx iir filters previously de- scribed. iii.4.1 - programmable interpolation filter (iir3) iir3 is an infinite impulse response interpolating filter. the purpose of this digital filter is to interpolate 4-times (5-times, 6-times) the digitalsignal from the dsp. this filter is sampled at 4-times (5-times, 6-times) the basic sampling frequency, (e.g. 9600 x 4 hz). the digital samples are encoded in 16-bit two's complement format. the iir3 filter is a cascade of seven biquads. the filter coefficients are loaded into the associated ram (38 x 13). each coefficient is coded into 12 bits and can be doubled by virtue of an extra bit. all 38 coefficients have to be loaded to implement an iir transfer function. this filter has been made programmable to offer each user the possibility to add filtering charac- teristics, e.g. highpass section or equalization, matched to a particular application. for example, in a band-split modem application, the first section can be a wide channel band-pass filter (allowing the dsp to supervise boundary audio tones) and the second section can be dedi- cated to high band and low band splitting. iii.4.2 - fir filter (fir3) fir3 is a finiteimpulse response interpolatingfilter. its input sampling frequency is 4 x fsx (5 x fsx), (6x fsx) and the interpolation ratio is 32. the z transfer function of this fir is : h ( z )= ? ? ? 1 - z - 32 32 ( 1 - z - 1 ) ? ? ? 3 with z = exp (j2 p f/txoclk) and txoclk = 128 (160, 192) x fsx STLC7545 13/53
iii - functional description (continued) iii.5 - clock generation master clock is obtained from either a crystal tied between pins xtal10 (or xtal11) and xtal2 or from an external signal connected to the xtal10 (or xtal11) pin, in the latter case, the xtal2 pin should be left open circuit. two external crystals (or two external master clock signals), software selectable one at a time, can be used to cope with complex applications. it is man- datory to shortcircuit xtal10 and xtal11 when a single external crystal or clock generator is used. the crystal selection is done by bit d13 (qs) in txctrl word of the serial interface a. setting qs to 0 select the xtal11 input and txclk = fq / (n x r x s x t x cs) with cs = 8. setting qs to 1 select the xtal10 input and txclk = fq / (n x r x s x t x cs) with cs = 16. to insure the start-up of the STLC7545, the xtal10 input must always be tied to a crystal or an externalclock signal, as that pin is automatically selected when powering-on the device. the different transmit (tx) and receive (rx) clocks are obtained by master clock frequency division in several programmable counters. the tx and rx clocks can be synchronized on external signals by performing phase shifts in the frequency division process (equivalent to adding or suppressingmas- ter clock transitions at the counter inputs). two independant digital phase locked loops (dpll) are implemented using this principle , one for tx and one for rx. two clock modes are available, selected by the external oversampling clock mode input pin (eocmode). when the eocmode pin is tied to the gnd the internal clock mode is selected. in this mode all the clock are generated internally. when the eocmode pin is tied to v dd , the external oversampling clock mode is selected. in external oversampling clock mode, the user must provide the chip with the oversampling fre- quency knowing the interpolation and the decima- tion ratios selected in the txcr3 and rxcr3 register. it can be provided from the highest syn- chronous clock (txhsclk and rxhsclk) using an external divider. in any case, the user will have to comply with the relation : crystal frequency fq must be greater than 470 x 4 x fsx with an over- sampling ratio of 128 or than 470 x 5 x fsx with an oversamplingratio of 160 or than 470 x 6 x fsx with an oversampling ratio of 192. several values can be chosen for the master clock frequency. thefour frequenciesgiven in table 1 are of particular interest, as they are compatible with standard modem frequencies. note : in the remainder of the datasheet, unless otherwise indicated, 36.864mhz will be considered as the nominal master clock frequency. the maximum master clock frequency is 38mhz. table 1 : list of usual frequency available crystal frequency symbol rate frequency bit rate (bps) sampling (bps) fq (mhz) fbaud (baud) fsx, fsr (hz) (1) 18.432 (2) 600, 1200, 1600, 2400 all up to 19200 3,4,5,6,8,12 or 16 times fbaud 25.8048 600, 1200, 1600, 2400, 2800 all up to 28800 3,4,5,6,8,12 or 16 times fbaud 29.4912 (2) 600, 1200, 1600, 2400 all up to 19200 3,4,5,6,8,12 or 16 times fbaud 36.864 (3) 600, 1200, 1600, 2400, 2560, 2743, 2954, 3000, 3200, 3429, 3491 all up to 38400 3,4,5,6,8,12 or 16 times fbaud notes : 1. depending on the symbol rate frequency 2. 7544 like 3. this crystal frequency provides all the symbol rates satisfying the relation : symbol rate = (2400 x 16)/k with k = (16, 15, 14, 13, 12, 11) symbol rate = (2400 x 8)/k with k = (8, 7, 6) symbol rate = (2400 x 10)/k with k = (8, 7) STLC7545 14/53
iii - functional description (continued) iii.5.1 - transmit dpll frequency control of the tx clock system (fig- ure 10) is obtained by performing additional up or down counting steps in the three input dividers m, n and p. these elementary phase shifts of one master clock period are repeated at either the rate of the fsx clock, or half that rate, depending on the required captureand tracking ranges (see table 15 and 26). the average updated frequency then varies be- tween the following limits : fq - fshift faverage fq + fshift where fq is the master clock frequency and fshift equals fsx or fsx/2 (see table 26). the txdpll phase comparison which determines lead or lag decisions, is simply obtained by sam- plingthe synchronizationclock, txsclk or rxclk, on the falling edges of an internal clock taken from the division chain, fcomp (see table 25). fcomp frequency must be an integer submultiple of the synchronization clock. this frequency determines the tx jitter magnitude. in v.34 synchronization mode fcomp is equal to 2400hz, and in 7544 mode the synchronization clock fcomp can be chosento be equal to the baud ratefrequency.only phase shifts of the same sense (lead or lag) are performed during each fcomp period. the actual phase shifts during fcomp period are given by the ratio fshift/fcomp these phase shifts are performed at the inputs of the m,n, and p dividers to lock the dpll to the synchronisation signal (see table 22). if there is no transitionon txsclk pin, the tx dpll is free running. to phase lock the txdpll there must be transis- tion on txsclk input within fcomp period when programming txcr2 register. the tx clock system may also run freely without any phase shift. in this case, the txsclk input is no longer active. the dpll capture and tracking range equals fshift/fq. they have to be greater than 200ppm to comply with ccitt recommenda- tions. fshift = fsx/2 minimizesthe jitter.because of this, there is a trade-off between higher capture and tracking ranges and lower jitter. ex : fq = 36.864mhz and fshift = 9600hz. capture and tracking range = fshift/fq = 9600hz/36.864mhz= 260ppm iii.5.2. transmit clocks iii.5.2.1 - internal mode the internal clock mode is selected when the pin eocmode is tied to gnd. in this mode the STLC7545 provides three tx programmable syn- chronous modem clocks : - a transmit bit rate clock txclk - a transmit baud rate clock txrclk - a transmit highest synchronous clock txhsclk, associated with the txsync synchronization pulse, useful to generate additional clocks (e.g. extra divisors) if needed. the outputs of the txrclk and txhsclk clocks, can be disabled when not used, but in 7544 syn- chronisation mode a correct baud rate frequency must be programmed as the fcomp clock fre- quency depends on it. the tx clock system provides the sampling and oversampling clocks as well as the bit and synchro clocks (bclkx and fsx) used by the serial inter- face a (ssi-a) described in section iv. the countersof the tx clock system (figure 10) are automatically reset when powering-on the STLC7545 and when the nlpr input level is low. they can also be reset, under software control, during the following conditions : (1) on the next falling edge of thetxsclk terminal clock or of the rxclk receive bit rate clock (sst bit table 22). (2) on the next falling edge of the txrclk transmit baud rate clock (baud chain clock reset) and in the next falling edge of fcomp (bit chain clocks) when txcr0, txcr2 or txcr3 register is accessed. the case (1) gives the capability to speed-up the tx dpll synchronization; the case (2) is useful to fix the phase of the bit rate clock with respect to the baud rate clock, in particularafter each modification of the bit or baud rate value. the internally generated pulse resetting the tx counters is output at the txsync pin in order to synchronizeexternal functionsusing the txhsclk clock. iii.5.2.2 - external mode the external clock mode is selected when the pin eocmode is tied to the v dd . in this mode the user must provide the STLC7545with the transmit over- sampling clock. the internal dpll can be used if the external transmit oversampling clock is gener- ated by a divider synchronized by both the txhsclk and txsync signals. STLC7545 15/53
iii - functional description (continued) iii.5.3 - receive dpll the synchronization of the rx counters delivering the rx clocks (figure 11) is performed by addition or suppression of master clock periods under dsp control.in thiscase, the phasecomparison function of the rxdpll is implemented in the associated dsp recovering the received symbols. two types of phase shift control are provided in the STLC7545 : - a coarse phase lag of programmable magnitude, obtained from the suppression of 64 to 4096 successive master clock transitions. this control is to be used to reduce the rxdpll locking time. - a fine phase lead or lag of programmable magni- tude (i.e. 8 to 32 master clock periods or one tx oversampling clock period) continuously used to implementthe phasecontrol loop. (see table 38). each elementaryphaseshift, correspondingto an addition or a subtraction of one master clock transition, is synchronized on an internal clock with frequency equal to the rxoclk (128, 160 or 192 times the rx sampling frequency fsr). a phase shift is ,therefore,alwayscompletedin less than one fsr period. iii.5.4 - receive clocks iii.5.4.1- internal mode the internal clock mode is selected when the pin eocmode is tied to gnd. in this mode the STLC7545 provides three rx synchronous pro- grammable modem clocks : - receive bit rate clock rxclk - receive baud-rate clock rxrclk - receive highest synchronous clock, rxhsclk associated with the rxsync synchronization pulse useful to generate additional clocks the rxrclk and rxhsclk outputs can be dis- abled when not used. the bit rate clock frequency of the rx modemcan be chosento be differentfrom its tx counterpart, provided rx to tx loopback is not required. the rx clock system also provides the rx sampling clockas well as the bit and synchro clocks (bclkr and fsr) used by the serial inter- face b (ssi-b) described in section iv. the digital reconstructionfilter implemented in the STLC7545 makes possible the choice of a receive nominal sampling frequency different from the transmit nominal sampling frequency. the counters of the rx clock system (figure 11) are reset when pow- ering on the STLC7545 and when the nlpr input level is low. they can also be reset, under software control, on the next falling edge of the rxrclk receive baud rate clock when the rxcr0, rxcr1 or rxcr3 register are accessed : this feature is used to fix the phase of the bit rate clock with respect to the baud rate clock, e.g. after each modification of the bit or baud rate value. the internally generated pulse resetting the rx count- ers is output at the rxsync pin in order to be used with the rxhsclk clock. iii.5.4.2 - external mode the external clock mode is selected when the pin eocmode is tied the v dd . in this mode the user must provide the STLC7545 with the receive over- sampling clock. the internal dpll can be used if the external receive oversampling clock is gener- ated by a divider synchronized by both the rxhsclk and rxsync signals. iii.6 - serial input/output synchronous interfaces the STLC7545 has two synchronous serial inter- faces ports, ssia and ssib. they allow inde- pendent transmit and receive paths. through the two serial ports, the STLC7545 can talk to various digital signal processors. the various serial inter- face signals and internalregisters are given below : ssi port a (ssia) - transmit frame synchronization output (fsx) - transmit bit clock output (bclkx) - transmit serial data input (txdi) - transmit input shift register (tsrin) - transmit input buffer register (tbrin) - transmit output shift register (tsrout) - transmit serial data output (txdo) ssi port b (ssib) - receive frame synchronization output (fsr) - receive bit clock output (bclkr) - receive serial data input (rxdi) - receive input shift register (rsrin) - receive input buffer register (rbrin) - receive output shift register (rsrout) - receive serial data output (rxdo) input modes - synchronous serial interface mode (ssim) - bit frame rate select (bfrs) with ssim input, the user can choose either single interface mode or dual interface mode. in single interface mode (section iv.2), only port ssia is operational.where as in dual interface mode (sec- tion iv.1), both ssia and ssib ports are opera- tional. these two ports carry data inside a synchron ous frame consisting of four/five or eight/ten sixteen bit time slots (only the four first time slots are used for transporting information. ssia port is synchronous to the tx system clock and ssib port is synchronous to rx system clock. the format of the signal samples carried on these port is two's complement with msb sent or received first. as explained hereafterit is alsopossible touse the port a only to transfer the data between the STLC7545 and the associated dsp. STLC7545 16/53
(12+1+3) bit coeff ram txctrl ressig txcr0 txsig coeff ram + status rxs1 rxs2 rxrc0 rxtx 16 bits 16 bits 16 bits (12+1) bit 16 bits 16 bits 16 bits 16 bits ssim 16 bit data bus (synchronized to the tx clock system) clock generator tsrin tbrin tsr out 16 bits 16 bits txdi wclkx bclkx bclkx wclkx ssim bfrs 16 bits txdo bclkx wclkx fsx txoclk rxctrl eye pattern 7545-05.eps figure 3 : tx clocks related registers ressig rxctrl rxrc0 16 bits 16 bits ssim 16 bit data bus (synchronized to the tx clock system) clock generator 16 bits 16 bits ssim bfrs 16 bits eyex eyey 16 bits 8 bits 8 bits rbrin rsrin rsrout rxdi rxdo rxoclk fsr bclkr wclkr wclkr bclkr bclkr wclkr 7545-06.eps figure 4 : rx clocks related registers iii - functional description (continued) iii.6.1 - tx clock related registers iii.6.2 - rx clock related registers STLC7545 17/53
(d0) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 (d0) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d15 hz bclkx (bclkr) txdi (rxdi) txdo (rxdo) fsx (fsr) 7545-07.eps figure 5 : serial channel timing iv - serial interface operation serial data transmission (reception) is initiated by a frame synchro signal fsx (fsr). the data is clocked from txdi (rxdi) into tsrin (rsrin) on the falling edge of bclkx (bclkr) and transfered to the tbrin (rbrin) registerwhen a complete 16 bit word has been received. data is assumed to be received msb first. serial data transmission (reception) output is initi- ated by a frame synchro signal fsx (fsr). the 16-bit data word is loaded into tsrout (rsrout) and serially clocked out of tsrout (rsrout) to txdo (rxdo) on the rising edge of bclkx (bclkr). bclkx (bclkr) frequency can be programmed to be either 64 or 128 (80 or 160) (90 or 192) times fsx (fsr) using the bit frame select (bfrs) input pin. this mean that the frame contains four, five, six, eight, ten or twelve time slots of 16 bits. the time slots used for circuit operation are indicated in the next paragraph. iv.1 - dual serial interface mode (ssia, ssib) when ssim is tied to v dd , both a and b ports are functional : port a (ssia) is dedicated to the tx channel and port b (ssib) to the rx channel. the timing diagram showing the data format is given in figures 5 and 6. the time-slot txo1 is dedicatedto ramcoefficient reading. the ram coefficient is selected by the address bits ra0 to ra1 in the txctrl word (see table 4). reading is initiated by the rising edge of start bit stb (bit d14 in table 3) in the txctrl word. note : rxsig is also available in two time slot rxs1 and rxs2 on the time slot txo2 and txo3 on ssia (see section iv.2) STLC7545 18/53
bclkx txdi txdo hz (tx04) (tx03) (tx02) (tx01) (tx00) (txi0) (txi1) (txi2) (txi3) (txi4) unused itr3 ressig txsig rxtx itr2 txctrl ssia hz ssib rxctrl bclkr rxdi rxdo (tri0) (tr00) rxsig itr1 reserved (tr01) (tri1) eyey-eyex itr2 reserved itr3 reserved itr1 reserved reserved (tri2) (tr02) (tri3) (tr03) (tri4) (tr04) add 5 data 8 mode 3 ram 13 add 8 data 8 fsx fsr unused unused unused 7545-08.eps figure 6 : serial channel timing. dual port mode iv - serial interface operation (continued) iv.2 - single serial interface mode when ssim is tied to gnd, only port a (ssia) is selected. in this case, port a carries both tx and rx signal samples and control words at tx sam- pling rate (fsx). the rxdi input should be tied to v dd . since port b is not functional in this mode, the rxsig (synchro- nized to fsr) will be available in the two time slots, rxs1 and rxs2, synchronized to fsx. the reason for the two time slots is that the fsr could be different in magnitude and phase from the fsx. the status bit st0 and st1 are used to indicate which of the rxs1 and rxs2 are valid. please see the table following. for example, if fsx = 9600hz and fsr = 14400hz both rxs1 and rxs2 could carry valid data. figure7 showsthe timing diagram. the time-slot txo1 is dedicatedto ramcoefficient reading. the ram coefficient is selected by ad- dress bits (ra0 to ra1) in the txctrl word (see table 4). reading is initiated by the rising edge of a startbit stb (bit d14 in table 3) in the txctrl word. the time-slot txi3 is dedicated to the rxctrl word or the eye-pattern, selected in the txctrl (see table 5). table 2 status word in txo1 time slot d1 d0 valid data st1 st0 0 0 none 0 1 none 1 0 rxs2 1 1 rxs1 and rxs2 (1) note 1 : the rxs1 sample precedes the rxs2 sample. STLC7545 19/53
bclkx txdi txdo hz (tx03) (tx02) (tx01) (tx00) (txi0) (txi1) (txi2) (txi3) rxs2 rxs1 ressig txsig rxtx txctrl ssia add 5 data 8 mode 3 st 2 1 ram 13 rxctrl or eye-pattern add 8 data 8 fsx eyex eyey (txi4) (tx04) 7545-09.eps figure 7 : serial channel timing. single port mode bclkx txdi (txi0) (txi1) (txi2) (txi3) txctrl ssia add 5 data 8 mode 3 bclkx txdi (txi0) (txi1) (txi2) (txi3) txctrl add 5 data 8 mode 3 unused coeff 1 (a). 1st frame coeff 2 coeff 38 (b). 13th frame coeff 36 1st frame 13th frame fsx fsx coeff 37 (txi4) (txi4) 7545-10.eps figure 8 : coefficient loading mode iv - serial interface operation (continued) iv.3 - coefficient loading mode the coefficient loading mode is selected by the mode select bit (ms) in the txctrl word (table 3). when the ms bit is a logic o1o the loading mode is selected. the iir rams (ram1 to ram3) are selected in the txctrl word by two address bits (ra0 to ra1). each coefficient ram stores 38 coefficients of 13 bits. therefore the size of the coefficient ram is 38 x 16 bits. the first frame transfers2 coefficientsand the 12 following frames each transfer 3 coefficients into the selected ram, as shown in figure 8. the transfer is initiated by the rising edge of the start bit coefficient stb which is loaded into the txctrl word. when the coefficient loading mode is selected all data path are fixed to zero. notes : 1. coefficient loading is the same for both dual and single interface modes. 2. in coefficient loading mode , the eye-pattern (time slot txi3) (and the rxctrl in a single serial interface) cannot be accessed STLC7545 20/53
iv - serial interface operation (continued) iv.4 - coefficient reading coefficient reading is selected in data mode only, i.e. when the mode select bit (ms) in the txctrl word is tied to logical 0. the iir rams (ram1 to ram3) are selected in the txctrl word by two address bits (ra0 to ra1). the 38 coefficients of 13 bits are available, one per frame, in the timeslot txo1 on the output tx port a (see figures 6, 7). the reading is available on the rising edge of the start bit stb loaded into the txctrl word. the first coefficient is output with one frame of delay on txo1. iv.5 - crystal selection (xtal10, xtal11) for application needing different or higher symbol rates, the user can software select different master clock frequencies for the STLC7545. two xtal inputs are provided for this purpose. the active xtal input is selected in the time slot txi1 with the quartz select bit (qs). it is mandatory to shortcir- cuit the xtal10 and xtal11 inputs when a single external crystal or clock generator is used. iv.6 - frame frequency programming when using the nominal master clock frequency, the frame frequency can be from 7200hz to 16000hz (see tables 15 and 32). whenever the frame frequency fsx (fsr) is modified, the data to the STLC7545 during that frame should be high in the time slots txi1 (rxi1), txi2 (rxi2) and txi3 (rxi3). this is because the bclkx(bclkr) during that frame may not be correct. therefore, when- ever the fsx (fsr) is changed the user has to send informationto the STLC7545 after one frame delay. iv.7 - initialization and low-power reset mode internal power-on circuitry automaticallyresets the dpll, the clock generator counters, and initializes the internal control registers. the clocks affected are the symbol clock, the bit clock and the sampling clock. the initial status of these registers is given in the programmable functions section. the transmit attenuator is initialized to an infinite attenuation mode (see table 24) to avoid the trans- mission of undesirable signals on the phone line. during hardware low power reset (nlpr pin is tied to gnd), the input of the inverter (across the crys- tal) will be high (dv dd ), the dplls and the clock generator counters are initialized, all the analog circuitry is placed in low-power mode and the xtal oscillator is stopped. access to the circuit is disabled during reset until the clock oscillator starts. the duration of the reset time can be increased by connecting the nlpr input to an external rc timeconstant as indicated in figure 9. in normal operation the nlpr input is used to control the lowpower mode. when nlpr is not used, it must be tied to v dd . STLC7545 21/53
xtal2 xtal10 - xtal11 dv dd tx and rx dpll & clo ck generators general reset software controlled reset (*) ana log functions low-power control registers r clk dq s 0 power-on internal reset pulse generator dd v nlpr c r (*) the software controlled reset is synchronized on the next falling edge of the baud rate clocks. 7545-11.eps figure 9 : power-on initialization circuitry iv - serial interface operation (continued) STLC7545 22/53
v - circuit programming this section defines the control and status words required to program the STLC7545. the circuit configuration is managed by the control words txctrl and rxctrl and the ssim, bfrs inputs. the control words contain three fields : - mode field 3 bits (d15-d13) mode control bit - address field 5 bits (d12-d8) 2 bits for coeff ram address 3 bits for control registers address - data field 8 bits (d7-d0) control registers content v.1 - mode field table 3 : mode field txctrl word d15 d14 d13 select mode ms stb qs 0 - - data mode and control register access mode 1 - - coefficient loading mode and filter data memory reset (ini) - - start bit for coefficient loading or reading. the loading is initiated by a rising edge, i.e. a logical one programmed after a logical zero. - - 1 xtal10 selected (ini) (cs equals 16 in bit chain clock) - - 0 xtal11 selected (cs equals 8 in bit chain clock) ini : initial value v.2 - address field v.2.1 - ram address field table 4 : ram address field txctrl word d15 d14 d13 d12 d11 d10 d9 d8 ram address ms stb qs ra0 ra1 ad2 ad1 ad0 - - 0 0 - - - ram 1 (ini) - - 0 1 - - - ram 2 - - 1 0 - - - ram 3 - - - 1 1 - - - not ram access ini : initial value v.2.2 - transmit control register address field table 5 : transmit control register address field register name txctrl word (2) d15 d14 d13 d12 d11 d10 d9 d8 ms stb qs ra0 ra1 ad2 ad1 ad0 txcr0 (1) -----000 txcr1 (1) -----001 txcr2 -----010 txcr3 (1) -----011 none - 1 1 1 eye pattern on txi3 1 1 0 (3) notes : 1. a reset is generated when programming these registers (see iii.5.2.1). 2. no register access for the non-specified code 3. in single interface mode only STLC7545 23/53
v - circuit programming (continued) v.2.3 - receive control register address field table 6 : receive control register address field register name rxctrl word (2, 3) d15 d14 d13 d12 d11 d10 d9 d8 -----ad2ad1ad0 rxcr0 (note 1) -----000 rxcr1 (note 1) -----001 rxcr2 -----010 rxcr3 (note 1) -----011 none -----111 notes : 1. a reset is generated when programming the rxcr0, rxcr1 and rxcr3 registers, this reset is synchronous with the falling edge of the rx symbol clock. 2. in single interface mode, the rxctrl registers cannot be programmed during the coefficient loading mode (see figures 7 and 8). 3. no register access for the non-specified code v.3 - control register data field v.3.1 - transmit control register programming table 7 : transmit control register programming register data programmed function d7 d6 d5 d4 d3 d2 d1 d0 txcr0 n0 r1 r0 s1 s0 t2 t1 t0 tx bit rate clock generator txcr1 m0 q1 q0 u2 u1 u0 p0 bs tx sampling, baud and hs clock generators; band split configuration. txcr2 at1 at0 ltx lc sst r3 vf r2 tx attenuator, txclock synchronization, v.fast synchronization mode, divider by 12/11 bit clock txcr3 v2 v1 v0 w hq1 hq0 ts0 dl tx sampling (used with txcr1), fcomp and fshift frequency programming half-integer q divider (used with txcr1), test configuration v.3.2 - receive control register programming table 8 : receive control register programming register data programmed function d7 d6 d5 d4 d3 d2 d1 d0 rxcr0 n0 r1 r0 s1 s0 t2 t1 t0 rx bit rate clock generator rxcr1 m0 q1 q0 u2 u1 u0 p0 eck rx sampling, baud and hs clock generators, baud and hs clock enable rxcr2 ll ps3 ps2 ps1 ps0 ap2 ap1 ap0 rx fine and coarse phase, shift control rxcr3 v2 v1 v0 emx r2 r3 hq1 hq0 rx sampling (used with rxcr1), fcomp or txrclk output enable half-integer q divider (used with rxcr1), divider by 12/11 and 15/13 bit clock, test configuration STLC7545 24/53
v - circuit programming (continued) v.3.3 - control bit function summary v.3.3.1 - txctrl word table 9 : txctrl word, programmed function table bit programmed function 11,12,13,14 n0 n divisor rank : 3, 4 o r3,r2,r1,r0 r divisor rank : 15/13, 12/11, 10/9, 8/7, 6/5, 4/3, 1 (1) o s1,s0 s divisor rank : 1, 3, 5, 7 o t2,t1,t0 t divisor rank : 4, 8, 16, 32, 64, 128, 256, 512 14,15,16,17,18 m0 m divisor rank : 3, 4 o q1,q0 q divisor rank : 5, 6, 7, 8 19 u2,u1,u0 u divisor rank : 3, 4, 5, 6 ,7, 8, 12, 16 20 p0 p divisor rank : 3, 4 21 bs band split or echo cancelling mode. (in band split mode the iir2 filter output is internally tied to iir3 filter input) 22 ltx synchronization signal : txsclk or rxclk 22 lc synchronization enabling : lock or free dpll. 22 sst txdpll reset on the next falling edge of the synchronization signal. sst is automatically reset after its action is completed. 23 vf 7544 and v.34 synchronization mode 23 r2, r3 r divisor rank 24 at1,at0 tx attenuation : 0db, 6db or infinite 25 v2,v1,v0 v divisor rank : 128 , 160, 192 25 f f divisor rank 24 w fshift frequency : fsx or fsx / 2 (related to frequency capture range of the txdpll as fq-fshift < faverage < fq + fshift) 27 ts0,hq1, hq0 half-integer q divider (used with txcr1 q bit). test functions. must be set to logical 0 for normal operation 27 dl test loop note 1 : the r2 and r3 bits are found in the txcr2 register table 23 v.3.3.2 - rxctrl word table 10 : rxctrl word, programmed function table bit programmed function 28,29,30,31 n0 n divisor rank : 3, 4 o r3,r2, r1,r0 r divisor rank : 15/13, 12/11, 10/9, 8/7, 6/5, 4/3, 1 (1) o s1,s0 s divisor rank : 1, 3, 5, 7 o t2,t1,t0 t divisor rank : 4, 8, 16, 32, 64, 128, 256, 512 32,33,34,35 m0 m divisor rank : 3, 4 o q1,q0 q divisor rank : 5, 6, 7, 8 36 u2,u1,u0 u divisor rank : 3, 4, 5, 6 ,7, 8, 12, 16 37 p0 p divisor rank : 3, 4 37 eck tx/rxrclk and tx/rxhsclk output enabling 38 ll rx dpll lead/lag control 38 ps1,ps0 rx dpll phase shift magnitude : 0, 8, 12, 16, 20, 24, 28, ps2 38 ps3 rx dpll phase shift magnitude : one 128*fsx period. this bit is reset after phase shift completion. 39 ap2,ap1 rx dpll coarse phase lag : 0, 64, 128, 256 512, 1024, ap0 40 v2,v1,v0 v divisor rank 41 emx fcomp or txrclk output enable (used in v.fast synchronization mode to multiplex the transmit bit frame) 41 hq0,hq1 half-integer q divider (used with rxcr1 q bit) 41 r3, r2 r divisor rank note 1 : the r2 and r3 bits are found in the rxcr3 register table 41 STLC7545 25/53
mux 2 to 1 phase shift %u %w %2 %y n-1 %n n+1 %f m- 1 %m m+ 1 %q osmode txoclk fsx fshift (inte rna l) txpclk (inte rnal) phase shift p-1 %p p+1 phase shift v.fast fcomp (inte rna l) r r r txs ync txclk = fq/(n x r x s x t x c s) txrclk = fs x/u emx osmode fq up to 38mhz txsc lk te rminal clock fcomp txhsclk txoclk txsync txrc lk eoc mode dv dd mux 2 to 1 %v (128 or 160) or 192 % r xs xtxcs txs ync r %x txs ync r 2400hz 7545-12.eps figure 10 : transmit clock generator vi - programmable functions vi.1 - transmit section the different transmit (tx) clocks are obtained by frequency division in several counters (see fig- ure 10). note 1 : txpclk is an internal processing clock used by the three iir filters note 2 : the phase of internal clock fcomp will be compared to the synchronization signal (ta- ble 22) in order to control txdpll (see tables 22, 25 and 26). in v.34 synchronizationmode fcomp is automatically set to 2400/f hz if the crystal frequency is equal to 36.864mhz (with qs = 1) or 25.8048mhz (with qs = 0) and if the bit rate clock is multiple of 2400hz chosen from the table. in 7544 mode v divisor must be chosen such that the fcomp frequencyis an integral sub-multiple of the synchronization frequency. in the 7544 mode the most typical frequency for fcomp is the baud rate frequency. during each period of fcomp the average input frequency of the transmit clock generator can be : fq , fq + fshift or fq - fshift with fshift = fsx or fsx/2 note 3 : in 7544 mode the bit rate frequency must always be an integer multiple of the baud rate frequency for the transmit dpll to lock onto the synchronization signal. note 4 : the x divisor is programed automatically with respect to qs bit. STLC7545 26/53
vi - programmable functions (continued) vi.1.1 - transmit bit rate clock frequency programming with master clock frequency fq=36.864mhz table11 : transmit bit rate clock frequency programming with master clock frequency fq=36.864mhz txcro register bit rate clock frequency(hz) txcr2 d2 txcr2 d0 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank (fq = 36.864mhz) txclk = fq/(n*r*s*t*cs) (1) r3 r2 n0 r1 r0 s1 s0 t2 t1 t0 0 0 0 1 1 1 0 0 0 0 960 38400 0 0 1 1 1 0 0 0 1 0 1024 36000 0 0 0 0 0 1 0 0 0 0 960x8/7 33600 0 0 0 1 1 0 1 0 0 1 1152 32000 1 1 1 0 0 0 0 0 1 0 1024x15/13 31200 0 0 1 1 1 1 0 0 0 0 1280 28800 0 1 1 0 0 1 0 0 0 0 1280x12/11 26400 0 0 1 1 1 0 1 0 0 1 1536 24000 0 0 1 1 0 1 0 0 0 0 1280x4/3 21600 0 0 0 1 1 1 0 0 0 1 1920 19200 (ini) 0 0 0 0 0 1 0 0 0 1 1920x8/7 16800 0 0 0 1 1 0 1 0 1 0 2304 16000 0 0 1 1 1 1 0 0 0 1 2560 14400 0 0 1 1 1 0 1 0 1 0 3072 12000 0 0 0 1 1 1 0 0 1 0 3840 9600 0 0 0 1 1 0 1 0 1 1 4608 8000 0 0 1 1 1 1 0 0 1 0 5120 7200 0 0 0 1 1 1 0 0 1 1 7680 4800 0 0 0 1 1 1 0 1 0 0 15360 2400 0 0 0 1 1 1 0 1 0 1 30720 1200 0 0 0 1 1 1 0 1 1 0 61440 600 0 0 0 1 1 1 0 1 1 1 122880 300 note : 1. the qs bit in txctrl word (bit d3) must be set to 1 to have cs = 16. vi.1.2 - transmit bit rate clock frequency programming with master clock frequency fq=25.8048mhz table12 : transmitbit rateclock frequencyprogrammingwith master clock frequencyfq=25.8048mhz txcro register bit rate clock frequency (hz) txcr2 d0 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank (fq = 25.8048mhz) txclk = fq/(n*r*s*t*cs) (2) r2 n0 r1 r0 s1 s0 t2 t1 t0 0 1 1 1 1 1 0 0 0 896 28800 1 1 0 0 1 1 0 0 0 896x12/11 26400 0 1 0 1 1 1 0 0 0 896x6/5 24000 0 1 1 0 1 1 0 0 0 896x4/3 21600 0 0 1 1 1 1 0 0 1 1344 19200 0 0 0 0 1 1 0 0 1 1344x8/7 16800 0 0 0 1 1 1 0 0 1 1344x6/5 16000 0 1 1 1 1 1 0 0 1 1792 14400 0 1 0 1 1 1 0 0 1 1792x6/5 12000 0 0 1 1 1 1 0 1 0 2688 9600 0 0 0 1 1 1 0 1 0 2688x6/5 8000 0 1 1 1 1 1 0 1 0 3584 7200 0 0 1 1 1 1 0 1 1 5376 4800 0 0 1 1 1 1 1 0 0 10752 2400 0 0 1 1 1 1 1 0 1 21504 1200 0 0 1 1 1 1 1 1 0 43008 600 0 0 1 1 1 1 1 1 1 86016 300 note : 2. the qs bit in txctrl word (bit d3) must be set to 0 to have cs = 8. STLC7545 27/53
vi - programmable functions (continued) vi.1.3 - transmit bit rate clock frequency programming with master clock frequency fq=18.432mhz table13 : transmit bit rate clock frequency programmingwith master clock frequencyfq=18.432mhz txcro register bit rate clock frequency (hz) d7 d6 d5 d4 d3 d2 d1 d0 divisor rank txclk= fq/(n*r*s*t*cs) (1) n0 r1 r0 s1 s0 t2 t1 t0 01101000 576 32000 11101000 768 24000 01110000 960 19200 00010000 960x8/7 16800 01101001 1152 16000 11110000 1280 14400 11101001 1536 12000 01110001 1920 9600 (ini) 01101010 2304 8000 11110001 2560 7200 01110010 3840 4800 01110011 7680 2400 01110100 15360 1200 01110101 30720 600 01110110 61440 300 ini : initial value notes : 1. the bit r2 and r3 in the txcr2 register (bit d0 and d2) must be set to 0. the qs bit in txctrl word must be set to 1 to have cs = 16. STLC7545 28/53
vi - programmable functions (continued) vi.1.4 - transmit bit clock frequency programming. divisor rank table 14 : transmit bit clock frequency programming. divisor rank txcr0 register bit rate clock frequency(hz) txclk = fq/(n*r*s*t*cs) (1) txcr2 d2 txcr2 d0 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank r3 r2 n0 r1 r0 s1 s0 t2 t1 t0 n r s t - - 0 - - - - - - - 3(ini) - - 1------- 4 0 0 -00----- 8/7 0 0 -01----- 6/5 0 0 -10----- 4/3 0 0 - 1 1 - - - - - 1 (ini) 0 1 - 0 0 - - - - - 12/11 0 1 - 0 1 - - - - - 10/9 0 1 -10----- 8/7 0 1 -11----- 1 - - ---00--- 1 - - ---01--- 3 - - - - - 1 0 - - - 5 (ini) - - ---11--- 7 - - -----000 4 - - -----001 8 (ini) - - -----010 16 - - -----011 32 - - -----100 64 - - -----101 128 - - -----110 256 - - -----111 512 1 0 - 0 0 - - - - - 11/9 1 0 -01----- 9/7 1 0 -10----- 7/5 1 0 -11----- 1 1 1 - 0 0 - - - - - 15/13 1 1 - 0 1 - - - - - 13/11 1 1 - 1 0 - - - - - 11/9 1 1 - 1 1 - - - - - 1 (ini) ini : initial value note 1 : the cs divisor is set by qs bit in txctrl word (qs = 1 cs = 16, qs = 0 cs = 8) STLC7545 29/53
vi - programmable functions (continued) vi.1.5 - transmit sampling clock frequency programming with master clock frequency fq=36.864mhz table 15 : transmitsampling clock frequencyprogramming with masterclock frequency fq=36.864mhz symbol rate (baud) u m x (y or q) ratio sampling frequency(hz) v over-sampling ratio w capture range 600 12 4 x 8 7200 160 1 1.95e-4 600 16 4 x 6 9600 160 1 2.60e-4 1200 6 4 x 8 7200 160 1 1.95e-4 1200 8 4 x 6 9600 160 1 2.60e-4 1600 5 4 x 6 8000 192 1 2.17e-4 1600 6 4 x 6 9600 160 1 2.60e-4 2400 3 4 x 8 7200 160 1 1.95e-4 2400 4 4 x 6 9600 160 1 2.60e-4 2400 6 4 x 5 14400 (ini) 128 2 1.95e-4 2560 3 4 x 7.5 7680 160 1 2.08e-4 2560 4 3 x 7.5 10240.00 160 1 2.77e-4 2560 6 3 x 5 15360.00 160 2 2.98e-4 2742.86 3 4 x 7 8228.57 160 1 2.40e-4 2742.86 4 3 x 7 10971.43 160 1 2.98e-4 2953.85 3 4 x 6.5 8861.54 160 1 2.40e-4 2953.85 4 3 x 6.5 11815.38 160 1 3.21e-4 3000 3 4 x 8 9000 128 1 2.44e-4 3000 4 3 x 8 12000 128 1 3.26e-4 3200 3 4 x 6 9600 160 1 2.60e-4 3200 4 3 x 6 12800 160 1 3.48e-4 3200 5 3 x 6 16000 128 1 4.34e-4 3428.57 3 4 x 7 10285.71 128 1 2.79e-4 3428.57 4 3 x 7 13714.28 128 2 1.86e-4 3490.91 3 4 x 5.5 10472.73 160 1 2.84e-4 3490.91 4 3 x 5.5 13963.64 160 1 3.79e-4 ini : initial value vi.1.6- transmit sampling clock frequency programming with master clock frequency fq=25.8048mhz table16 : transmit sampling clock frequency programming with master clock frequencyfq=25.8048mhz symbol rate (baud) u m x qratio sampling frequency(hz) v over-sampling ratio w capture range 2800 3 4 x 6 8400 128 1 3.26e-4 2800 4 3 x 6 11200 128 2 2.17e-4 2400 3 4 x 7 7200 128 1 2.79e-4 2400 4 3 x 7 9600 128 2 1.86e-4 vi.1.7 - transmit sampling clock frequency programming with master clock frequency fq=18.432mhz table 17 : transmit sampling clock frequency programming with master clock frequency fq=18.432mhz symbol rate (baud) u m x q ratio sampling frequency (hz) v over-sampling ratio w capture range 1600 5 3 x 6 8000 128 2 2.17e-4 1600 6 3 x 5 9600 128 2 2.60e-4 (ini) 2400 (ini) 3 4 x 5 7200 128 2 1.95e-4 2400 4 3 x 5 9600 128 2 2.60e-4 ini : initial value STLC7545 30/53
vi - programmable functions (continued) vi.1.8. transmit sampling clock frequency programming. divisor rank table 18 : transmit sampling clock frequency programming. divisor rank txcr1 register sampling clock frequency fsx = fq/(mxqxv) (1) d7 d6 d5 d4 d3 d2 d1 d0 divisor rank m0 q1 q0 u2 u1 u0 p0 bs m q (2) 0------- 3 1------- 4 (ini) -00----- 5 (ini) (4.5) -01----- 6 (5.5) -10----- 7 (6.5) -11----- 8 (7.5) ini : initial value notes : 1. the v divider is programmed in the txcr3 register. 2. to use the fractional q divider bits hq1 and hq0 in table 27 must be set to o1o (otherwise they are set to o0o). vi.1.9. transmit baud rate frequency programming. divisor rank table 19 : transmit baud rate frequency programming. divisor rank txcr1 register baud rate frequency txrclk = fsx / u d7 d6 d5 d4 d3 d2 d1 d0 divisor rank m0 q1 q0 u2 u1 u0 p0 bs u - - - 0 0 0 - - 3 (ini) ---001- 4 ---010-- 5 ---011-- 6 ---100-- 8 ---101-- 12 ---110-- 16 ---111-- 16 ini : initial value vi.1.10. highest synchronous transmit frequency programming. divisor rank table 20 : highest synchronous transmit frequency programming. divisor rank txcr1 register highest synchronous transmit frequency txhsclk=fq/p d7 d6 d5 d4 d3 d2 d1 d0 divisor rank m0 q1 q0 u2 u1 u0 p0 bs p - - - - - - 0 - 3 (ini) ------1 4 ini : initial value vi.1.11. band split mode table 21 : band split mode txcr1 register band split mode d7 d6 d5 d4 d3 d2 d1 d0 m0 q1 q0 u2 u1 u0 p0 bs -------0 (ini) inactive (ini) -------1 active : rx filter output connected to reconstruction filter input (see figure 1). ini : initial value STLC7545 31/53
vi - programmable functions (continued) vi.1.12 - transmit synchronization signal programming table 22 : transmit synchronization signal programming txcr2 register tx dpll clock d7 d6 d5 d4 d3 d2 d1 d0 synchronization at1 at0 ltx lc sst r3 vf r2 --01---- t xsclk (1) --11---- rxclk (1) - - - 1 1 - - - reset on the next falling edge of the synchronization signal (1) (2) ---0---- no synchronization (ini) ini : initial value notes : 1. if d4 = 1, the txdpll will be locked to the synchronization signal if present when programming is done. otherwise, the tx dpll will be free-running. 2. the sst bit is automatically reset after its action is completed. vi.1.13 - clock mode programming & r2 & r3 divisor table 23 : clock mode programming & r2 & r3 divisor txcr2 register mode programming & r2 & r3 divisor d7 d6 d5 d4 d3 d2 d1 d0 at1 at0 ltx lc sst r3 vf r2 - - - - - - 0 - 7544 synchronization mode (ini) - - - - - - 1 - v.34 synchronization mode -------r2 see table 14 - r2 = 0 (ini) - - - - - r3 - - see table 14 - r3 = 0 (ini) ini : initial value vi.1.14 - transmit attenuator programming table 24 : transmit attenuator programming txcr2 register transmit attenuator d7 d6 d5 d4 d3 d2 d1 d0 attenuation (db) at1 at0 ltx lc sst r3 vf r2 00------ infinite (ini) 10------ -6 11------ 0 ini : initial value vi.1.15 - phase comparator frequency and decimation & interpolation ratio table 25 : phase comparator frequency and decimation & interpolation ratio txcr3 register tx phase comparator frequency fcomp = txrclk / f or 2400 / f (2) and v divisor rank d7 d6 d5 d4 d3 d2 d1 d0 fcomp oversampling ratio v2 v1 v0 w hq1 hq0 ts0 dl f v 000----- 1 128 001----- 2 128 010----- 1 160 011----- 2 160 100----- 4 128 (ini) 101----- 1 192 110----- 4 160 111----- 1 256(1) ini : initial value notes : 1. the performance is not guaranteed with this oversampling ratio. 2. fcomp is depending of the synchronization mode (normal or v.34). STLC7545 32/53
vi - programmable functions (continued) vi.1.16 - phase shift frequency table 26 : phase shift frequency txcr3 register phase shift frequency (1) fshift = fsx / w d7 d6 d5 d4 d3 d2 d1 d0 (average updated master clock frequency) v2 v1 v0 w hq1 hq0 ts0 dl w ---0---- (ini) fsx/2 (ini) (fq fsx/2 ) ---1---- fsx(fq fsx) ini : initial value note 1 : the w bit selects the phase shift frequency of the txdpll, and hence the capture range vi.1.17 - transmit test programming table 27 : transmit test programming txcr3 register test modes d7 d6 d5 d4 d3 d2 d1 d0 v2 v1 v0 w hq1 hq0 ts0 dl 0000 n ormal mode (ini) -------1 digital loop test (1) - - - - - - 1 - test 0 (internal use only) - - - - 0 1 - - test 1 (internal use only) - - - - 1 0 - - test 2 (internal use only) - - - - 1 1 - - half-integer q divider (see table 18) (2) ini : initial value notes : 1. to perform the digital loop test, the single serial interface and band split modes should be selected, the signal at txd0 pin should be connected to the rxdi pin, and the fsx should be equal to the fsr. under these conditions, the a/dc input will appear at the output on the d/ac. this test is useful to verify the performance of the adc, dac and iir filters. 2. test pin eocmode must be set to o0o in this configuration. STLC7545 33/53
phase shift %u %y %q osmode rxoclk fsr phase shift phase shift r r r rxs ync rxclk = fq/(n x r x s x t x cs) rxrclk = fs r/u fq up to 38mhz rxhsclk rxoclk rxsync rxsync r rxrclk coa rse phase shift m- 1 %m m+ 1 n-1 %n n+1 p-1 %p p+1 %v (128 or 160) or 192 %rxsxtxcs 7545-13.eps figure 11 : receive clock generator vi - programmable functions (continued) vi.2 - receive section the different receive (rx) clocks are derived from the master clock (fq) using the dividers shown in figure 11. the counters of the rx clock system (without the rxhsclk) are reset when powering on the STLC7545 and when the nlpr input level is low. they can also be reset, under software control, on the next falling edge of the rxrclk receive baud rate clock when the rxcr0, rxcr1 or rxcr3 register are accessed : this feature is used to fix the phase of the bit rate clock with respect to the baud rate clock, e.g. after each modification of the bit or baud rate value. STLC7545 34/53
vi - programmable functions (continued) vi.2.1 - receive bit rate clock frequency programming with master clock frequency fq=36.864mhz table 28 : receive bit rate clock frequency programming with master clock frequency fq=36.864mhz rxcro register bit rate clock frequency(hz) rxcr3 d2 rxcr3 d3 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank (fq = 36.864mhz) rxclk = fq/(n*r*s*t*cs) (1) r3 r2 n0 r1 r0 s1 s0 t2 t1 t0 0 0 0 1 1 1 0 0 0 0 960 38400 0 0 1 1 1 0 0 0 1 0 1024 3600 0 0 0 0 0 1 0 0 0 0 960x8/7 33600 0 0 0 1 1 0 1 0 0 1 1152 32000 1 1 1 0 0 0 0 0 1 0 1024x15/13 31200 0 0 1 1 1 1 0 0 0 0 1280 28800 0 1 1 0 0 1 0 0 0 0 1280x12/11 26400 0 0 1 1 1 0 1 0 0 1 1536 24000 0 0 1 1 0 1 0 0 0 0 1280x4/3 21600 0 0 0 1 1 1 0 0 0 1 1920 19200 (ini) 0 0 0 0 0 1 0 0 0 1 1920x8/7 16800 0 0 0 1 1 0 1 0 1 0 2304 16000 0 0 1 1 1 1 0 0 0 1 2560 14400 0 0 1 1 1 0 1 0 1 0 3072 12000 0 0 0 1 1 1 0 0 1 0 3840 9600 0 0 0 1 1 0 1 0 1 1 4608 8000 0 0 1 1 1 1 0 0 1 0 5120 7200 0 0 0 1 1 1 0 0 1 1 7680 4800 0 0 0 1 1 1 0 1 0 0 15360 2400 0 0 0 1 1 1 0 1 0 1 30720 1200 0 0 0 1 1 1 0 1 1 0 61440 600 0 0 0 1 1 1 0 1 1 1 122880 300 ini : initial value note 1 : the qs bit (d13) in txctrl word must be set 1 to have cs = 16. vi.2.2 - receive bit rate clock frequency programming with master clock frequency fq=25.8048mhz table 29 : receivebit rate clock frequencyprogramming with master clock frequencyfq=25.8048mhz rxcro register bit rate clock frequency (hz) rxcr3 d3 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank (fq = 25.8048mhz) rxclk = fq/(n*r*s*t*cs) (1) r2 n0 r1 r0 s1 s0 t2 t1 t0 0 1 1 1 1 1 0 0 0 896 28800 1 1 0 0 1 1 0 0 0 896x12/11 26400 0 1 0 1 1 1 0 0 0 896x6/5 24000 0 1 1 0 1 1 0 0 0 896x4/3 21600 0 0 1 1 1 1 0 0 1 1344 19200 0 0 0 0 1 1 0 0 1 1344x8/7 16800 0 0 0 1 1 1 0 0 1 1344x6/5 16000 0 1 1 1 1 1 0 0 1 1792 14400 0 1 0 1 1 1 0 0 1 1792x6/5 12000 0 0 1 1 1 1 0 1 0 2688 9600 0 0 0 1 1 1 0 1 0 2688x6/5 8000 0 1 1 1 1 1 0 1 0 3584 7200 0 0 1 1 1 1 0 1 1 5376 4800 0 0 1 1 1 1 1 0 0 10752 2400 0 0 1 1 1 1 1 0 1 21504 1200 0 0 1 1 1 1 1 1 0 43008 600 0 0 1 1 1 1 1 1 1 86016 300 note : 1. the qs bit (d13) in txctrl word must be set 0 to have cs = 8. STLC7545 35/53
vi - programmable functions (continued) vi.2.3 - receive bit rate clock frequency programming with master clock frequency fq=18.432mhz table 30 : receive bit rate clock frequency programming with master clock frequency fq=18.432mhz rxcro register bit rate clock frequency (hz) d7 d6 d5 d4 d3 d2 d1 d0 divisor rank (fq = 18.432mhz) rxclk = fq/(n*r*s*t*cs) (1) n0 r1 r0 s1 s0 t2 t1 t0 01101000 576 32000 11101000 768 24000 01110000 960 19200 00010000 960*8/7 16800 01101001 1152 16000 11110000 1280 14400 11101001 1536 12000 01110001 1920 9600 (ini) 01101010 2304 8000 11110001 2560 7200 01110010 3840 4800 01110011 7680 2400 01110100 15360 1200 01110101 30720 600 01110110 61440 300 ini : initial value notes : 1. the qs bit (d13) in txctrl word must be set 1 to have cs = 8. the bit r2 in the txcr2 register (bit d0) must be set to 0. STLC7545 36/53
vi - programmable functions (continued) vi.2.4 - receive bit rate clock frequency programming. divisor rank table 31 : receive bit rate clock frequency programming. divisor rank rxcr0 register bit rate clock frequency(hz) rxclk = fq/(n*r*s*t*cs) (1) rxcr3 d2 rxcr3 d0 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank r3 r2 n0 r1 r0 s1 s0 t2 t1 t0 n r s t - - 0 - - - - - - - 3(ini) - - 1------- 4 0 0 -00----- 8/7 0 0 -01----- 6/5 0 0 -10----- 4/3 0 0 - 1 1 - - - - - 1 (ini) 0 1 - 0 0 - - - - - 12/11 0 1 - 0 1 - - - - - 10/9 0 1 -10----- 8/7 0 1 -11----- 1 -----00--- 1 -----01--- 3 - - - - - 1 0 - - - 5 (ini) -----11--- 7 - - -----000 4 - - - - - - - 0 0 1 8 (ini) - - -----010 16 - - -----011 32 - - -----100 64 - - -----101 128 - - -----110 256 - - -----111 512 1 0 - 0 0 - - - - - 11/9 1 0 -01----- 9/7 1 0 -10----- 7/5 1 0 -11----- 1 1 1 - 0 0 - - - - - 15/13 1 1 - 0 1 - - - - - 13/11 1 1 - 1 0 - - - - - 11/9 1 1 - 1 1 - - - - - 1 (ini) ini : initial value note 1 : the cs divisor is set by qsbit (d13) in txctrl word (qs = 1 cs = 16, qs = 0 cs = 8) STLC7545 37/53
vi - programmable functions (continued) vi.2.5 - receivesampling clock frequency programming with master clock frequency fq=36.864mhz table 32 : receivesampling clock frequency programming with masterclock frequencyfq=36.864mhz symbol rate (baud) u m x y or m x q ratio sampling frequency (hz) v oversampling ratio 600 12 4 x 8 7200 160 600 16 4 x 6 9600 160 1200 6 4 x 8 7200 160 1200 8 4 x 6 9600 160 1600 5 4 x 6 8000 160 1600 6 4 x 6 9600 192 2400 3 4 x 8 7200 160 2400 4 4 x 6 9600 160 2400 6 4 x 5 (ini) 14400 (ini) 128 2560 3 (29) 4 x 7.5 7680 160 2560 4 (29) 3 x 7.5 10240.00 160 2560 6 3 x 5 15360.00 160 2742.86 3 4 x 7 8228.57 160 2742.86 4 3 x 7 10971.43 160 2953.85 3 (29) 4 x 6.5 8861.54 160 2953.85 4 (29) 3 x 6.5 11815.38 160 3000 3 4 x 8 9000 128 3000 4 3 x 8 12000 128 3200 3 4 x 6 9600 160 3200 4 3 x 6 12800 160 3200 5 3 x 6 16000 128 3428.57 3 4 x 7 10285.71 128 3428.57 4 3 x 7 13714.28 128 3490.91 3 (30) 4 x 5.5 10472.73 160 3490.91 4 (30) 3 x 5.5 13963.64 160 ini : initial value vi.2.6 - receivesampling clock frequency programming with master clock frequency fq=25.8048mhz table33 : receivesamplingclock frequencyprogramming with master clock frequencyfq=25.8048mhz symbol rate (baud) u mx(y or q) sampling ratio v oversampling frequency (hz) 2800 3 4 x 6 8400 128 2800 4 3 x 6 11200 128 2400 3 4 x 7 7200 128 2400 4 3 x 7 9600 128 vi.2.7 - receivesampling clock frequency programming with master clock frequency fq=18.432mhz table 34 : receivesampling clock frequency programming with masterclock frequencyfq=18.432mhz symbol rate (baud) u m x q sampling ratio v oversampling frequency (hz) 1600 5 3 x 6 8000 128 1600 6 3 x 5 9600 128 2400 (ini) 3 4 x 5 7200 128 2400 4 3 x 5 9600 128 ini : initial value STLC7545 38/53
vi - programmable functions (continued) vi.2.8 - receive sampling clock frequency programming. divisor rank table 35 : receive sampling clock frequency programming. divisor rank rxcr1 register sampling clock frequency fsr=fq/(m x q x v) (1) d7 d6 d5 d4 d3 d2 d1 d0 divisor rank m0 q1 q0 u2 u1 u0 p0 eck m q (2) 0------- 3 1------- 4 (ini) -00----- 5 (ini) (4.5) -01----- 6 (5.5) -10----- 7 (6.5) -11----- 8 (7.5) ini : initial value notes : 1. the v divider is programmed in the rxcr3 register 2. to use the fractional divider bits hq1 and hq0 in table 41 must be set to o1o (otherwise they are set to o0o). vi.2.9 - receive baud rate frequency programming. divisor rank table 36 : receive baud rate frequency programming. divisor rank rxcr1 register baud rate frequency rxrclk = fsr / u d7 d6 d5 d4 d3 d2 d1 d0 divisor rank u m0 q1 q0 u2 u1 u0 p0 eck (1) - - - 0 0 0 - - 3 (ini) ---001- - 4 ---010- - 5 ---011- - 6 ---100- - 8 ---101- - 12 ---110- - 16 ---111- - 16 ini : initial value note : 1. eck bit is used to enable the rxrclk and rxhsclk outputs (as well as txrclk and txhsclkclock outputs) when set at logical 1. the baud rate clock must be programmed to its correct value even though the corresponding output pin is disabled (eck = 0). vi.2.10 - highest synchronous transmit bit frequency programming. divisor rank table 37 : highest synchronous transmit bit frequency programming. divisor rank rxcr1 register highest synchronous receive frequency rxhsclk=fq/p0 d7 d6 d5 d4 d3 d2 d1 d0 divisor rank p m0 q1 q0 u2 u1 u0 p0 eck - - - - - - 0 - 3 (ini) ------1- 4 - - - - - - - 0 disable rxrclk, rxhsclk, txrclk and txhsclk output - - - - - - - 1 enable rxrclk, rxhsclk, txrclk and txhsclk output (ini) ini : initial value STLC7545 39/53
vi - programmable functions (continued) vi.2.11 - receive fine phase shift programming table 38 : receive fine phase shift programming rxcr2 register receive fine phase shift programming d7 d6 d5 d4 d3 d2 d1 d0 action on rxdpll number of master clock pulses suppressed ll ps3 ps2 ps1 ps0 ap2 ap1 ap0 00000000 no phase shift (ini) 00001000 8 00010000 12 00011000 16 00100000 20 00101000 24 00110000 28 00111000 32 01000000one txoclk oversampling period (1) 1-------as above but lead instead of lag (i.e. addition of master-clock pulses) ini : initial value note 1 : available only with an internal q divider. to shift one oversampling period, the chip must know the q divider value currently used. vi.2.12 - receive coarse phase shift programming table 39 : receive coarse phase shift programming rxcr2 register receive coarse phase shift amplitude programming d7 d6 d5 d4 d3 d2 d1 d0 number of master clock pulses suppressed ll ps3 ps2 ps1 ps0 ap2 ap1 ap0 0 0 0 0 0 0 0 0 no phase shift (ini) 00000001 64 00000010 128 00000011 256 00000100 512 0 0 0 0 0 1 0 1 1024 0 0 0 0 0 1 1 0 2048 0 0 0 0 0 1 1 1 4096 ini : initial value STLC7545 40/53
vi - programmable functions (continued) vi.2.13 - interpolation ratio table 40 : interpolation ratio rxcr3 register interpolation ratio divisor value d7 d6 d5 d4 d3 d2 d1 d0 v v2 v1 v0 emx r2 r3 hq1 hq0 000----- 128 001----- 128 010----- 160 011----- 160 100----- 128 (ini) 101----- 192 110----- 160 111----- 256(1) ini : initial value note 1 : the performances are not garanted with this oversampling ratio. vi.2.14 - receive test programming & r2 & r3 divisor table 41 : receive test programming and r2 and r3 divisor rxcr3 register test mode & r2 & r3 divisor d7 d6 d5 d4 d3 d2 d1 d0 v2 v1 v0 emx r2 r3 hq1 hq0 -----000 n ormal mode (ini) ----r2--- see table 31 (rxcr0) r2 = 0 (ini) -----r3-- see table 31 (rxcr0) r3 = 0 (ini) ---0---- tx rclk output on txrclk pin (ini) ---1----f comp output on txrclk pin (see figure 10) ------11 half-integer q divider (see table 35) ini : initial value STLC7545 41/53
vii - electrical specifications unless otherwise noted, electrical characteristics are specified over the operating range. typical values are given for v dd = +5v , t amb =25 c and for nominal crystal frequency fq = 36.864mhz. vii.1 - absolute maximum ratings (referenced to gnd) table 42 : absolute maximum ratings symbol parameter value unit v dd dc supply voltage -0.3 to 7.0 v v i ,v in digital or analog input voltage - 0.3, v dd +0.3 v i i ,i in digital or analog input current 1ma i o digital output current 20 ma i out analog output current 10 ma t oper operating temperature 0, +70 o c t stg storage temperature (plastic) - 40, + 125 o c p dmax maximum power dissipation 500 mw esd electrostatic discharge pins rxa1, rxa2, txa1, txa2, av dd ,v cm all other pins 1500 2000 v v vii.2 - dc characteristics (v dd =5.0v 5%, gnd = 0v, t a = 0 to +70 o c, unless otherwise specified) vii.2.1 - power supply and common mode voltage table 43 : power supply and common mode voltage symbol parameter min. typ. max. unit single power supply (dv dd =av dd ) v dd supply voltage 4.75 5 5.25 v i dda analog supply current 8 ma i ddd digital supply current 32 ma i dd -lp supply current in low power mode 600 m a v cm output common mode voltage v cm output voltage load current (see note 1) v dd /2-5% v dd /2 v dd /2+5% v double power supply (dv dd #av dd ) dv dd digital supply voltage 3.15 3.3 3.45 v av dd analog supply voltage 4.75 5 5,25 v i dda analog supply current 8 ma i ddd digital supply current 20 ma v cm output common mode voltage (see note 1) v dd /2-5% v dd /2 v dd /2+5% v note 1 : device is very sensitive to noise on v cm pin. v cm output voltage load current must be dc (<10 m a). in order to drive dynamic load, v cm must be buffered. ac variation in v cm current magnitude decrease a/d and d/a performance. vii.2.2 - digital interface (all digital pins except xtal pins) table 44 : digital interface symbol parameter min. typ. max. unit (t a =25 c, dv dd = +3.3v) v il low level input voltage 0.8 v v ih high level input voltage dv dd -0.5 v i i input current v i =v dd or v i = gnd -10 110 m a v oh high level output voltage (i load = -1ma) dv dd -0.5 v v ol low level output voltage (i load = 1ma) 0.4 v c in input capacitance 5 pf (t a =25 c, dv dd = +3.3v) v il low level input voltage -0.3 0.5 v v ih high level input voltage dv dd -0.5 v i i input current v i =v dd or v i = gnd -10 110 m a v oh high level output voltage (i load = -600 m a) dv dd -0.5 v v ol low level output voltage (i load = 800 m a) 0.3 v STLC7545 42/53
vii - electrical specifications (continued) vii.2.3 - crystal oscillator interface (xtal10,xtal11) crystal mode only available at dv dd = 5v otherwise external clock oscillator mandatory. table 45 : crystal oscillator interface symbol parameter min. typ. max. unit v il low level input voltage 1.5 v v ih high level input voltage 3.5 v i l low level input current (gnd v i v il max) -15 m a i h high level input current (v ih min v i v dd ) - 15 m a vii.2.4 - analog interface table 46 : analog interface symbol parameter min typ max unit v ref differential reference voltage output = v refp -v refn =v ref (with av dd = 5v) 2.40 2.50 2.60 v tempco (v ref )v ref temperature coefficient 200 ppm/ c v cmo in input common mode offset voltage = rxa1 + rxa2 2 - v cm -300 300 mv v dif in differential input voltage : rxa1-rxa2 <= 2*v ref 2*v ref vpp v off in differential input dc offset voltage : rxa1 = rxa2 = v cm (1) -100 100 mv v cmo out output common mode voltage offset = txa1 + txa2 2 - v cm 200 200 mv v dif out differential output voltage : txa1-txa2 <= 2*v ref 2*v ref vpp v off out differential output dc offset voltage : (txa1 - txa2) -100 100 mv v out output voltage eyex,eyey gnd vdd v r in input resistance rxa1, rxa2 100 k w r out output resistance txa1,txa2 eyex, eyey 20 50 w w r l load resistance txa1,txa2 eyex, eyey 10 1 k w m w c l load capacitance txa1,txa2 eyex, eyey 20 30 pf pf note 1 : input dc offset can be cancelled by high-pass filtering in iir2 filter STLC7545 43/53
10 89 11 243 5 1 7 6 bclkx (bclkr) txdi (rxdi) txdo (rxdo) n=64 hz fsx (fsr) n=1 n=1 n=64 7545-14.eps figure 12 : serial channel timming vii - electrical specifications (continued) vii.3 - ac electrical specifications (v dd = 5.0 v 5%, t a = 0 to +70 o c) output load = 50 pf, reference levels : v il = 0.8 v, v ih = 2.2 v, v ol = 0.4 v, v oh = 2.4 v vii.3.1 - serial channel timing table 47 : serial channel timing number parameter min. typ. max. unit 1 bclkx, bclkr period 300 ns 2 bclkx, bclkr width low 135 ns 3 bclkx, bclkr width high 135 ns 4 bclkx, bclkr rise time 30 ns 5 bclkx, bclkr fall time 30 ns 6 fsx, fsr to bclkx, bclkr setup 100 ns 7 fsx, fsr to bclkx, bclkr hold 100 ns 8 txdi, rxdi to bclkx, bclkr setup 20 ns 9 txdi, rxdi to bclkx, bclkr hold 0 ns 10 bclkx, bclkr high to txdo, rxdo valid 50 50 ns 11 bclkx, bclkr to txdo, rxdo hiz 50 50 ns STLC7545 44/53
7545-15.tif figure 13 : filter transfer function (sampling frequency = 48000hz, fsx = 9600hz, sample of group delay = 1/5 x fsx) viii - transmit characteristics viii.1 - test conditions the tx characteristics depend on the transfer function of the transmit filter. the indicated performance is measured when iir1 filter implements the 8th order low-pass transfer function (including sinx/x correction) shown in figure 13. this is achieved by loading the coefficients given in table 48. the frequency response in figure 13 includes the gain of 72.25db in front of the biquad 1 (see figure a1) table 48 : interpolator filter coefficients word 7200,9600 word 7200,9600 word 7200,9600 word 7200,9600 word 7200,9600 1 0000,0000 9 0000,ca08 17 4c98,5070 25 a000,a000 33 0750,0858 2 0000,0000 10 0000,a000 18 2438,3508 26 adb8,ac18 34 6aa8,4098 3 a000,a000 11 b368,b570 19 d7a8,cfa0 27 5e70,6118 35 a000,a000 4 0000,0000 12 4400,48a0 20 a000,a000 28 0748,07a0 36 0000,0000 5 0000,0000 13 0200,2838 21 af18,aed8 29 a280,3368 37 0000,0000 6 0000,b7d8 14 d330,cb68 22 5690,59d0 30 a000,a000 38 0008,0008 7 0000,42b0 15 a000,a000 23 2118,2898 31 a910,adf0 - - 8 a000,0118 16 b118,b268 24 4f80,dd90 32 5120,5338 - - filter coefficients (hex format) for fsx equal to 7200 and 9600hz respectively viii.2 - performance of the tx chain (from iir1 filter input to (txa1-txa2) output) typical values are given for v dd = +5v , t amb =25 o c and for nominal crystal frequency fq = 36.864mhz. measurement band = 300hz to 3.4khz - tx dpll free running. table 49 : performance of the tx chain symbol parameter min typ max unit gabs absolute gain at 1khz -0.5 0 0.5 db thd total harmonic distortion (differential tx signal : v out = 1.6v pp , f = 1khz, oversampling ratio 160) fsx = 7200hz fsx = 9600hz -89 -89 db db dr dynamic range (1) (f = 1khz, oversampling ratio 160) fsx = 7200hz fsx = 9600hz 91 92 db db psrr power supply rejection ratio (f = 1khz, v ac = 200mv pp )50db ctxrx crosstalk (transmit channel to receive channel) 95 db note 1 : measured over the full 0 to fsx/2 with a -10dbr input and extrapolated to fullscale viii.3 - smoothing filter transfer characteristics the cut-off frequency of the single pole switch-capacitor low-pass filter following the dac (figure 1) is : fc-3db= 128*fsx/(2* p *10) or fc-3db= 160*fsx/(2* p *10) STLC7545 45/53
ix - receive characteristics ix.1 - test conditions the rx characteristics depend on the transfer function of the receive filter. the indicated performance is measured when iir2 filter implements the 6th order band-pass transfer function shown in figure 14. this is achieved by loading the coefficients given in table 50. 7545-16.tif figure 14 : filter transfer function (sampling frequency = 48000hz, fsx = 9600hz, sample of group delay = 1/5 x fsx) table 50 : decimator filter coefficients word 7200,9600 word 7200,9600 word 7200,9600 word 7200,9600 word 7200,9600 1 0000,0000 9 0000,e000 17 4d90,4250 25 a000,a000 33 0d38,0618 2 0000,0000 10 e000,0000 18 25b8,2890 26 ab60,b5b0 34 0000,1a38 3 a000,a000 11 b2c0,bf38 19 d1b0,ca18 27 5a40,4e88 35 a000,a000 4 0000,0000 12 5998,4188 20 a000,a000 28 09b8,23c8 36 0000,0000 5 0000,0000 13 12c8,0188 21 b1f8,b748 29 2c30,d620 37 0000,0000 6 0000,0000 14 4c80,e000 22 4668,47a8 30 a000,a000 38 0008,0008 7 0000,0000 15 a000,0000 23 1408,1b98 31 a088,b470 - - 8 20f8,3208 16 a5e0,b8e0 24 de78,cc80 32 6a30,5468 - - filter coefficients (hex format) for fsx equal to 7200 and 9600hz respectively ix.2 - performance of the rx chain (from (rxa1-rxa2) input to iir2 filter output) typical values are given for v dd = +5v , t amb =25 o c and for nominal crystal frequency fq=36.864mhz. measurement band = 300hz to 3.4khz - tx dpll free running. table 51: performance of the rx chain symbol parameter min typ max unit gabs absolute gain at 1 khz -0.5 0 0.5 db thd total harmonic distortion (differential rx signal : v in = 1.6 v pp , f = 1khz, oversampling ratio 160) fsx = 7200 hz fsx = 9600 hz -89 -89 db db dr dynamic range (1) f = 1khz, oversampling ratio 160 fsx = 7200 hz fsx = 9600 hz 91 92 db db psrr power supply rejection ratio (f = 1khz, v ac = 200mv pp )50db ctxrx crosstalk (receive channel to transmit channel) 95 db note 1 : measured over the full 0 to fsx/2 with a -10dbr input and extrapolated to fullscale STLC7545 46/53
x - typical applications s erial interface s tx rx s tlc7545 afe system bus mcu txa rxa ana log s ignals modem clocks modem data to terminal ds p v.24 interface 7545-17.eps figure 15 : multistandard modem with echo cancelling capability 100pf 100pf 680pf c 2r 22k w 13 .2k w 13 .2k w 22k w 22k w 22k w txa1 txa2 c 2r z0/2 z0/2 p hone line r r 1.2k w 1.2k w c' 2.2nf rxa1 rxa2 v cm v cm c : improve the low frequency response . its value depends on the transformer inductance. c': reduce s the dc offse t gain. z0 : nominal line impedance. r' r r' 2.2nf 7545-18.eps figure 16 : differential duplexer x.1 - multi-standard modem with echo cancelling x.2 - line interface STLC7545 47/53
x - typical applications (continued) x.3 - common mode voltage generation and decoupling v cm 10 m f 47nf 10 m f 47nf 10 m f 47nf 100nf 47 m f 5.0v av dd v refp v refn agndt agndr 2.5v 7545-19.eps figure 17 : voltage decoupling x.4 - crystal oscillator xtal11 xtal10 xtal2 crystal STLC7545 7545-20.eps figure 18 : external components for crystal oscillator STLC7545 48/53
xi - annexe a xi.1 - iir filter operation each iir filtering section included in the st7544 can perform up to seven biquadratic transfer func- tions in cascade, operating at four times the sam- pling frequency (see figure a1). each biquad is defined by five coefficients,a, b, c, d and e (see figure a2). an additional coefficient ,f, scales the iir filter output. unused biquads are made transparent by pro- gramming a to one and the four remaining coeffi- cients to zero. such biquads should preferably be located in the first sections of the iir filter in order to reduce the calculation noise. xi.1.1 - coefficient rounding initially, coefficients of the filter to be implemented must be exclusively between +2 and -2. to derive the actual usable 12+1bit coefficients,the rounding processdescribed in figurea3 must be performed. each 13 bit coefficient k is split into its doubling factor k2, and its 12 bit basic value k1, as the iir architecture works with 12 bit coefficients and uses an extra accumulation when coefficient doubling is needed. k2 [0,1] and -2 12 to programme one iir filter it is necessaryto send five words per biquad followed by two additional words set to zero and the f coefficient word : b(1), c(1), a(1), d(1), e(1), b(2),..., e(7), 0000 h , 0000 h ,f the total number of words sent is therefore 38. xi.1.2 - detailed operation the architecture of the device supporting the iir filter is based on 28 bit data path. thebasicfunction is as follows: one coefficient k(n) is multipled by one sample x(n) followed by one accumulation with value clampling. it can be precisely described as follows : function pac k(n), x(n), s local p p= trunc (k1(n) x x(n)/2 12 ) s=s+p if abs (s) > 2 27 then if sign (s) > 0 then clamp s to 2 27 -1 else clamp s to 2 27 if k2(n) = 1 then s=s+p if abs (s) > 227 then if sign (s) > 0 then clamp s to 2 27 -1 else clamp s to 2 27 end of function the trunc function is a two's complement trun- cature. as previously mentionned, the second accumula- tion is controlled by the doubling factor k2(n). the complete process of computing 16 bit output samples (v out ) from 16 bit input samples (v in ) appears in figure a4. biquad#1 in v (1) v (1) out 2 12 f in v in out in out biquad#2 v (2) v (2) out v biquad#7 v (7) v (7) coefficients : a(1), b(1),..., e(1) a(2), b(2),..., e(2) a(7), b(7),..., e(7) 7545-21.eps figure a1 : iir filter diagram STLC7545 49/53
delay delay a(n) b(n) d(n) c(n) e(n) in v(n) out v(n) v (n) 0 v (n) 1 2 v (n) 7545-22.eps v 0 (n) = b(n) x v 1 (n) + c(n) x v 2 (n) + a(n) x v in (n) v out (n) = v 0 (n) + d(n) x v 1 (n) + e(n) x v 2 (n) v 2 (n) = v 1 (n) v 1 (n) = v 0 (n) hn ( z )= a 1 + dz - 1 + ez - 2 1 - bz - 1 - cz - 2 equation set : next step with : n = biquad number (1:7) figure a2 : biquad structure k2(n) = 0 k1(n) = round (204 8*k(n)) starting coefficient k(n) (-2 < k(n) < +2) -1 < k(n) < +1 k2(n) = 1 k1(n) = round (1024*k(n)) no yes k2 = 0 or 1 k1 = 12-bit word k = a, b, c, d, e or f 7545-23.eps figure a3 : iir coefficients rounding xi - annexe a (continued) STLC7545 50/53
new input sa mple in v ( 16-bit) n=1 s= 0 t=s t=s n=n+1 n< 7 no yes first biquad accumulator reset in v storage in 28-bit format recursive coefficients v0(n) stored into t direct coefficients state variables up-dating for the next computation next biquad output scaling coeffiecient iir output sample stored into t out v (n) stored into t out iir output sample loaded into v after 16-bit saturation (new output sample) s=0 pac f, t, s t=s 1 2 v (n) = v (n) 1 v (n) = temp v (n), s 1 2 v(n),s pac d(n), pac e(n), pac b(n), v (n), s 1 2 pac c (n), v (n), s pac a(n), t, s in h t = 800 x v v=t out if greater than 16-bit then clamped to 7fff or 8000 h h 7545-24.eps figure a4 : iir operating sequence xi - annexe a (continued) STLC7545 51/53
pmlpcc44.eps xii - package mechanical data 44 pins - plastic leaded chip carrier (plcc) dimensions millimeters inches min. typ. max. min. typ. max. a 17.4 17.65 0.685 0.695 b 16.51 16.65 0.650 0.656 c 3.65 3.7 0.144 0.146 d 4.2 4.57 0.165 0.180 d1 2.59 2.74 0.102 0.108 d2 0.68 0.027 e 14.99 16 0.590 0.630 e 1.27 0.050 e3 12.7 0.500 f 0.46 0.018 f1 0.71 0.028 g 0.101 0.004 m 1.16 0.046 m1 1.14 0.045 plcc44.tbl STLC7545 52/53
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1998 stmicroelectronics - all rights reserved purchase of i 2 c components of stmicroelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com 44 34 d3 e 12 22 1 11 c b a1 a2 a d1 d 23 33 e3 e1 e l k l1 0,25 mm .010 inch gage plane 0,10 mm .004 inch seating plane pmtqfp44.eps package mechanical data (continued) 44 pins - plastic quad flat pack (thin) (tqfp) dimensions millimeters inches min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.40 0.012 0.015 0.016 c 0.09 0.20 0.004 0.008 d 12.00 0.472 d1 10.00 0.394 d3 8.00 0.315 e 0.80 0.031 e 12.00 0.472 e1 10.00 0.394 e3 8.00 0.315 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k0 o (min.), 7 o (max.) 4y.tbl STLC7545 53/53

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