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19-6465; rev 0; 9/12 for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max5318.related . general description the max5318 is a high-accuracy, 18-bit, serial spi input, buffered voltage output digital-to-analog converter (dac) in a 4.4mm x 7.8mm, 24-lead tssop package. the device features q 2 lsb inl (max) accuracy and a q 1 lsb dnl (max) accuracy over the full temperature range of -40 n c to +105 n c. the dac voltage output is buffered resulting in a fast settling time of 3 f s and a low offset and gain drift of q 0.5ppm/ n c of fsr (typ). the force-sense output (out) maintains accuracy while driving loads with long lead lengths. additionally, a separate avss supply, allows the output amplifier to go to 0v (gnd) while maintaining full linearity performance. the max5318 includes user-programmable digital gain and offset correction to enable easy system calibration. at power-up, the device resets its outputs to zero or mid - scale. the wide 2.7v to 5.5v supply voltage range and integrated low-drift, low-noise reference buffer amplifier make for ease of use. the max5318 features a 50mhz 3-wire spi interface. the max5318 is available in a 24-lead tssop package and operates over the -40 n c to +105 n c temperature range. applications benefits and features s ideal for ate and high-precision instruments ? inl accuracy guaranteed with 2 lsb (max) over temperature s fast settling time (3s) with 10k i || 100pf load s safe power-up-reset to zero or midscale dac output (pin-selectable) ? predetermined output device state in power-up and reset in system design s negative supply (avss) option allows full inl and dnl performance to 0v s spi interface compatible with 1.8v to 5.5v logic s high integration reduces development time and pcb area ? buffered voltage output directly drives 2k i load rail-to-rail ? integrated reference buffer ? no external amplifiers required s small 4.4mm x 7.8mm, 24-pin tssop package test and measurement equipment automatic test equipment gain and offset adjustment data-acquisition systems process control and servo loops programmable voltage and current sources automatic tuning and calibration communication systems medical imaging ordering information and typical operating circuit appear at end of data sheet. functional diagram 18-bit dac input/ dac register ref control logic shutdown power-on reset spi interface buffer output buffer v ddio dgnd bypass agnd_s agnd_f avss avdd1 avdd2 refo rfb out 7.8ki 7.8ki 7.8ki 7.8ki ldac 5 9 8 7 6 2 4 1 3 10 11 23 22 13 19 20 12 15 16 17 21 14 18 24 ready busy rst m/ z tc/ sb pd sclk din dout cs agnd max5318 digital offset digital gain din spi max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maximintegrated.com.
2 agnd to dgnd ................................................... -0.3v to +0.3v agnd_f, agnd_s to agnd ............................... -0.3v to +0.3v agnd_f, agnd_s to dgnd ............................... -0.3v to +0.3v avdd to agnd ....................................................... -0.3v to +6v avdd to ref ........................................................... -0.3v to +6v avss to agnd ........................................................ -2v to +0.3v v ddio to dgnd ....................................................... -0.3v to +6v bypass to dgnd ....................................... -0.3v to the lower of (v avdd_ or v ddio + 0.3v) and +4.5v out, refo, rfb to agnd ......................... -0.3v to the lower of (v avdd + 0.3v) and +6v ref to agnd ................... -0.3v to the lower of v avdd and +6v sclk, din, cs , busy , ldac , ready , m/ z , tc/ sb , rst , pd, dout to dgnd ....... -0.3v to the lower of (v ddio + 0.3v) and +6v continuous power dissipation (t a = +70 n c) tssop (derate 13.9mw/ n c above +70 n c) ............. 1111.1mw operating temperature range ........................ -40 n c to +105 n c maximum junction temperature ..................................... +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tssop junction-to-case thermal resistance ( q ja ) ............... 13c/w junction-to-ambient thermal resistance ( q ja ) .......... 72c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics (v avdd = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) parameter symbol conditions min typ max units static performance resolution n 18 bits integral nonlinearity (note 3) inl din = 0x00000 to 0x3ffff (binary mode), din = 0x20000 to 0x1ffff (twos complement mode) -2 q 0.5 +2 lsb din = 0x01900 to 0x3ffff (binary mode), din = 0x21900 to 0x1ffff (twos complement mode), v avss = 0v differential nonlinearity (note 3) dnl -1 q 0.275 +1 lsb zero code error oe din = 0, t a = +25 n c -48 q 4 +48 lsb din = 0, t a = -40 n c to +105 n c q 14 zero code error drift (note 4) din = 0 -1.6 q 0.10 +1.6 ppm/ n c gain error ge t a = +25 n c -16 q 1 +16 lsb t a = -40 n c to +105 n c q 27 gain error temperature coefficient (note 4) tcge -2.5 q 0.10 +2.5 ppm/ n c of fsr output voltage range no load 0 v avdd - 0.1 v maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
3 electrical characteristics (continued) (v avdd = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) parameter symbol conditions min typ max units reset voltage output v out-reset rst = pulse low m/ z = dgnd 75 f v m/ z = v ddio 2.048 v rst = pulse low, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 2.048 v rst = dgnd m/ z = dgnd -68 mv m/ z = v ddio 2.036 v rst = dgnd, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 2.036 v dc output impedance (normal mode) r out closed-loop connection (rfb connected to out) 4 m i output resistance (power-down mode) pd = v ddio 2 k i output current i out source/sink within 100mv of the supply rails q 4 ma source/sink within 800mv of the supply rails q 25 load capacitance to gnd c l 200 pf load resistance to gnd r l for specified performance 2 k i short-circuit current i sc out shorted to agnd or avdd q 60 ma refo shorted to agnd or avdd q 65 bypass shorted to agnd or avdd q 48 short-circuit duration t sc short to agnd or avdd indefinite s dc power-supply rejection dc psrr v out at full scale, v avdd = 4.5v to 5.5v -2.5 q 0.20 +2.5 lsb/v v avss = -1.5v to -0.5v -2.5 q 0.012 +2.5 static performancevoltage reference input section reference high input range v ref 2.4 v avdd - 0.1 v reference input capacitance c ref 10 pf reference input resistance r ref 10 m i reference input current i b q 0.15 f a static performancevoltage reference output section reference high output range 2.4 v avdd - 0.1 v reference high output load regulation 500 ppm/ ma reference output capacitor r esr < 5 i 0.1 nf maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
4 electrical characteristics (continued) (v avdd = v ddio = 4.5v to 5.5v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 4.096v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) parameter symbol conditions min typ max units static performancev bypass out section output voltage v bypass 2.3 2.4 2.5 v load capacitance to gnd c l required for stability, r esr = 0.1 i (typ) 1 8 f f power-supply requirements positive analog power-supply range v avdd 4.5 5.5 v digital interface power-supply range v ddio 1.8 v avdd v negative analog power-supply range v avss -1.5 -1.25 0 v positive analog power-supply current i avdd no load, external reference, output at zero scale 5.2 6.5 ma negative analog power-supply current i avss no load, external reference, output at zero scale -1.5 -1.0 ma interface power-supply current i vddio digital inputs at v ddio or dgnd 0.2 5.0 f a positive analog power-supply power-down current pd = v ddio , power-down mode 20 50 f a negative analog power-supply power-down current pd = v ddio , power-down mode -5 -3 f a dynamic performance voltage output slew rate sr from 10% to 90% full scale, positive and negative transitions 4.9 v/ f s voltage output settling time t s from falling edge of ldac to within 0.003% fs, r l = 10k i , din = 04000h (6.25% fs) to 3c000h (93.75% fs) 3 f s busy time t busy (note 5) 1.9 f s dac glitch impulse major code transition (1ffffh to 20000h), r l = 10k i , c l = 50pf 4 nvs digital feed through csb = v ddio , f sclk = 1khz, all digital inputs from 0v to v ddio 1 nvs output voltage-noise spectral density at f = 1khz to 10khz, without reference, code = 20000h 26 nv/ hz output voltage noise at f = 0.1hz to 10hz, without reference, code = 20000h 1.55 f v p-p wake-up time from power-down mode 75 f s power-up time from power-off 2 ms maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
5 electrical characteristics (v avdd = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, gain = 0x3ffff, offset = 0x00000, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) parameter symbol conditions min typ max units static performance resolution n 18 bits integral nonlinearity (note 3) inl din = 0x00000 to 0x3ffff (binary mode), din = 0x20000 to 0x1ffff (twos complement mode) -2.0 q 0.75 +2.0 lsb din = 0x01900 to 0x3ffff (binary mode), din = 0x21900 to 0x1ffff (twos complement mode), v avss = 0v differential nonlinearity ( note 3) dnl -1.0 q 0.3 +1.0 lsb zero code error oe din = 0, t a = +25 n c -50 q 6 +50 lsb din = 0, t a = -40 n c to +105 n c q 25 zero code error drift (note 4) din = 0 -2.7 q 1.4 +2.7 ppm/ n c gain error ge t a = +25 n c -16 q 1.5 +16 lsb t a = -40 n c to +105 n c q 35 gain error temperature coefficient (note 4) tcge -3.2 +3.2 ppm/ n c of fsr output voltage range no load 0 v avdd - 0.1 v reset voltage output v out-reset rst = pulse low m/ z = dgnd 75 f v m/ z = v ddio 1.25 v rst = pulse low, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 1.25 v rst = dgnd m/ z = dgnd -40 mv m/ z = v ddio 1.25 v rst = dgnd, v avss = 0v m/ z = dgnd 10 mv m/ z = v ddio 1.24 v dc output impedance r out closed-loop connection, rfb connected to out 4 m i output current i out source/sink within 100mv of the supply rails q 4 ma source/sink within 800mv of the supply rails q 25 load capacitance to gnd c l 200 pf load resistance to gnd r l for specified performance 2 k i short-circuit current i sc out shorted to agnd or avdd q 60 ma refo shorted to agnd or avdd q 65 bypass shorted to agnd or avdd q 48 short-circuit duration t sc short to agnd or avdd indefinite s maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
6 electrical characteristics (continued) (v avdd = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, gain = 0x3ffff, offset = 0x00000, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) parameter symbol conditions min typ max units dc power-supply rejection dcpsrr v out at full scale, v avdd = 2.7v to 3.3v -2.5 q 0.4 +2.5 lsb/v v avss = -1.5v to -0.5v -2.5 q 0.04 +2.5 static performancevoltage reference input section reference high input range v ref 2.4 v avdd - 0.1 v reference input capacitance c ref 10 pf reference input resistance r ref 10 m i reference input current ib q 0.15 f a static performancevoltage reference output section reference high output range 2.4 v avdd - 0.1 v reference high output load regulation 500 ppm/ma reference output capacitor r esr < 5 i 0.1 nf static performancev bypass out section output voltage v bypass 2.3 2.4 2.5 v load capacitance to gnd c l required for stability, r esr = 0.1 i (typ) 1 8 f f power-supply requirements positive analog power-supply range v avdd 2.7 3.3 v interface power-supply range v ddio 1.8 5.5 v negative analog power-supply range v avss -1.5 -1.25 0 v positive analog power-supply current i avdd no load, external reference, output at zero scale 5.0 6.5 ma negative analog power-supply current i avss no load, external reference, output at zero scale -1.5 -0.8 ma interface power-supply current i vddio digital inputs at v ddio or dgnd 0.2 5.0 f a positive analog power-supply power-down current pd = v ddio , power-down mode 20 50 f a negative analog power-supply power-down current pd = v ddio , power-down mode -5 -2 f a dynamic performance voltage output slew rate sr from 10% to 90% full scale, positive and negative transitions 4.9 v/ f s voltage output settling time t s from falling edge of ldac to within 0.003% fs, r l = 10k i , din = 04000h (6.25% fs) to 3c000h (93.75% fs) 3 f s maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
7 electrical characteristics (continued) (v avdd = v ddio = 2.7v to 3.3v , v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v, v ref = 2.5v, tc/ sb = pd = ldac = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, gain = 0x3ffff, offset = 0x00000, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.) (gain = 0x3ffff and offset = 0x00000.)(note 2) digital interface electrical characteristics (v avdd = 5v, v ddio = 2.7v to 5.5v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z = dgnd, c refo = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.)(gain = 0x3ffff and offset = 0x00000.) (note 2) parameter symbol conditions min typ max units busy time t busy (note 5) 1.9 f s dac glitch impulse major code transition (1ffffh to 20000h), r l = 10k i , c l = 50pf 2.5 nvs digital feedthrough csb = v ddio , f sclk = 1khz, all digital inputs from 0v to v ddio 1 nvs output voltage-noise spectral density at f = 1khz to 10khz, without reference, code = 20000h 26 nv/ hz output voltage noise at f = 0.1hz to 10hz, without reference, code = 20000h 1.55 f v p-p wake-up time from power-down mode 75 f s power-up time from power-off 2 ms parameter symbol conditions min typ max units digital inputs (sclk, din, cs , ldac , m/ z , rst ) input high voltage v ih 0.7 x v ddio v input low voltage v il 0.3 x v ddio v input hysteresis (note 4) v ihyst 200 300 mv input leakage current i in q 0.1 q 1 f a input capacitance c in 10 pf digital output characteristics (dout, ready , busy ) output low voltage v ol i source = 5.0ma 0.25 v output high voltage v oh i sink = 5.0ma, except for busy v ddio - 0.25 v output three-state leakage i oz dout only q 0.1 q 1 f a output three-state capacitance c oz dout only 15 pf output short-circuit current i oss v ddio = 5.25v q 150 ma maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
8 digital interface electrical characteristics (continued) (v avdd = 5v, v ddio = 2.7v to 5.5v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z = dgnd, c refo = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.)(gain = 0x3ffff and offset = 0x00000.) (note 2) parameter symbol conditions min typ max units timing characteristics serial clock frequency f sclk stand-alone, write mode 50 mhz stand-alone, read mode and daisy- chained read and write modes (note 5) 12.5 sclk period t cp stand-alone, write mode 20 ns stand-alone, read mode and daisy- chained read and write modes 80 sclk pulse width high t ch 40% duty cycle 8 ns sclk pulse width low t cl 40% duty cycle 8 ns cs fall to sclk fall setup time t csso first sclk falling edge stand-alone, write mode 8 ns stand-alone, read mode and daisy-chained read and write modes 38 cs fall to sclk fall hold time t csh0 inactive falling edge preceding first falling edge 0 ns sclk fall to cs rise hold time t csh1 24th falling edge 2 ns din to sclk fall setup time t ds 5 ns din to sclk fall hold time t dh 4.5 ns sclk rise to dout settle time t dot c l = 20pf (note 6) 32 ns sclk rise to dout hold time t doh c l = 0pf (note 6) 2 ns sclk fall to dout disable time t doz 24th active edge deassertion 2 30 ns cs fall to dout enable t doe asynchronous assertion 2 30 ns cs rise to dout disable t csdoz stand-alone, aborted sequence 35 ns daisy-chained, aborted sequence 70 sclk fall to ready fall t crf 24th falling-edge assertion, c l = 20pf 30 ns sclk fall to ready hold t crh 24th falling-edge assertion, c l = 0pf 2 ns sclk fall to busy fall t cbf busy assertion 5 ns cs rise to ready rise t csr c l = 20pf 35 ns cs rise to sclk fall t csa 24th falling edge, aborted sequence 20 ns cs pulse width high t cspw stand alone 20 ns sclk fall to cs fall t csf 24th falling edge 100 ns ldac pulse width t ldpw 20 ns ldac fall to sclk fall hold t ldh last active falling edge 20 ns rst pulse width t rstpw 20 ns maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
9 digital interface electrical characteristics (v avdd = 5v, v ddio = 1.8v to 2.7v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z = dgnd, c refo = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.)(gain = 0x3ffff and offset = 0x00000.) (note 2) parameter symbol conditions min typ max units digital inputs (sclk, din, cs , ldac, m/ z , rst ) input high voltage v ih 0.8 x v ddio v input low voltage v il 0.2 x v ddio v input hysteresis (note 4) v ihyst 200 300 mv input leakage current i in input = 0v at v ddio q 0.1 q 1 f a input capacitance c in 10 pf digital outputs characteristics (dout, ready , busy ) output low voltage v ol i source = 1.0ma 0.2 v output high voltage v oh i sink = 1.0ma, except for busy v ddio - 0.2 v output three-state leakage i oz dout only q 0.1 q 1 f a output three-state capacitance c oz dout only 15 pf output short-circuit current i oss v ddio = 2.7v q 150 ma timing characteristics serial clock frequency f sclk stand-alone write mode 50 mhz stand-alone read mode and daisy- chained read and write modes (note 6) 8 sclk period t cp stand-alone write mode 20 ns stand-alone read mode and daisy- chained read and write modes 125 sclk pulse-width high t ch 40% duty cycle 9 ns sclk pulse-width low t cl 40% duty cycle 9 ns cs fall to sclk fall setup time t csso first sclk falling edge stand-alone write mode 12 ns stand-alone read mode and daisy-chained read and write modes 72 cs fall to sclk fall hold time t csh0 inactive falling edge preceding first falling edge 0 ns sclk fall to cs rise hold time t csh1 24th falling edge 4 ns din to sclk fall setup time t ds 8 ns din to sclk fall hold time t dh 8 ns sclk rise to dout settle time t dot c l = 20pf (note 7) 40 ns sclk rise to dout hold time t doh c l = 0pf (note 7) 2 ns maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
10 digital interface electrical characteristics (continued) (v avdd = 5v, v ddio = 1.8v to 2.7v , v avss = -1.25v, v ref = 4.096v, r l = 10k, tc/ sb = m/ z = dgnd, c refo = 100pf, c bypass = 1f, t a = -40 c to +105 c, unless otherwise noted. typical values are at t a = +25 c.)(gain = 0x3ffff and offset = 0x00000.) (note 2) figure 1. serial interface timing diagram, stand-alone operation note 2: all devices are 100% tested at t a = +25 c and t a = + 105 c . limits at t a = -40 c are guaranteed by design. note 3: linearity is tested from v ref to agnd. note 4: guaranteed by design. note 5: the total analog throughput time from din to v out is the sum of t s and t busy (4.9s, typ). note 6: daisy-chain speed is relaxed to accommodate (t crf + t css0 ). note 7: dout speed limits overall spi speed.. r3 12 t csso 34 56 78 21 22 23 24 25 din sclk t csh0 r2 r1 r0 d17 d16 d15 d14 d1 d0 x ?? 0r 3 r2 r1 r0 d17 d16 d15 d2 d1 d0 0 z dout cs z t csh1 t csa t ds t dh t cp t cl t ch t doh t dot t doe t cspw t doz t crh t csf t crf t csr ready parameter symbol conditions min typ max units sclk fall to dout disable time t doz 24th active edge deassertion 2 40 ns cs fall to dout enable t doe asynchronous assertion 2 50 ns cs rise to dout disable t csdoz stand-alone, aborted sequence 70 ns daisy-chained, aborted sequence 130 sclk fall to ready fall t crf 24th falling edge assertion, c l = 20pf 60 ns sclk fall to ready hold t crh 24th falling edge assertion, c l = 0pf 2 ns sclk fall to busy fall t cbf busy assertion 5 ns cs rise to ready rise t csr c l = 20pf 60 ns cs rise to sclk fall t csa 24th falling edge, aborted sequence 20 ns cs pulse width high t cspw stand alone 20 ns sclk fall to cs fall t csf 24th falling edge 100 ns ldac pulse width t ldpw 20 ns ldac fall to sclk fall hold t ldh last active falling edge 20 ns rst pulse width t rstpw 20 ns maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
11 typical operating characteristics (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) max5318 toc01 integral nonlinearity vs. digital input code code inl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 5v v avdd = 5.25v -2.0 0 262144 max5318 toc02 integral nonlinearity vs. digital input code code inl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 4.096v v avdd = 5v -2.0 0 262144 max5318 toc03 integral nonlinearity vs. digital input code code inl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 2.5v v avdd = 3v -2.0 0 262144 max5318 toc04 differential nonlinearity vs. digital input code code dnl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 5v v avdd = 5.25v -2.0 0 262144 max5318 toc05 differential nonlinearity vs. digital input code code dnl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 4.096v v avdd = 5v -2.0 0 262144 max5318 toc06 differential nonlinearity vs. digital input code code dnl (lsb) 196608 131072 65536 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 v ref = 2.5v v avdd = 3v -2.0 0 262144 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
12 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) dnl distribution vs. temperature max5318 toc09a lsb count (no. of units) 0.50 0.45 0.35 0.40 0.20 0.25 0.30 0.15 20 40 60 80 100 120 140 160 180 0 0.10 -40c +25c +105c integral nonlinearity vs. temperature max5318 toc10 temperature (c) inl (lsb) 110 95 65 35 50 80 52 0 -25 -10 0 -40 -3.2 -2.4 -1.6 -0.8 0.8 1.6 2.4 3.2 4.0 -4.0 min inl max inl v ref = 4.096v inl distribution vs. temperature max5318 toc10a lsb count (no. of units) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 10 20 30 40 50 60 70 0 0.2 -40c +10c +25c differential nonlinearity vs. temperature max5318 toc07 temperature (c) dnl (lsb) 110 95 65 35 50 80 52 0 -25 -10 0 -40 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min dnl max dnl v ref = 2.5v integral nonlinearity vs. temperature max5318 toc08 temperature (c) inl (lsb) 110 95 65 35 50 80 52 0 -25 -10 0 -40 -3.2 -2.4 -1.6 -0.8 0.8 1.6 2.4 3.2 4.0 -4.0 min inl max inl v ref = 2.5v differential nonlinearity vs. temperature max5318 toc09 temperature (c) dnl (lsb) 110 95 65 35 50 80 52 0 -25 -10 0 -40 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min dnl max dnl v ref = 4.096v maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
13 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) inl distribution vs. temperature max5318 toc10b lsb count (no. of units) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 10 20 30 40 50 60 70 0 0.2 +25c +40c +105c 5.1 4.7 3.9 4.3 3.5 3.1 differential nonlinearity vs. supply voltage max5318 toc11 v avdd (v) dnl (lsb) 5.5 0 2.7 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min dnl max dnl v ref = 2.5v 5.1 4.7 3.9 4.3 3.5 3.1 integral nonlinearity vs. supply voltage max5318 toc12 v avdd (v) inl (lsb) 5.5 0 2.7 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min inl max inl v ref = 2.5v 4.8 4.4 3.6 4.0 3.2 2.8 differential nonlinearity vs. reference voltage max5318 toc13 reference voltage (v) dnl (lsb) 5.2 0 2.4 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min dnl max dnl v avdd = 5.25v 4.8 4.4 3.6 4.0 3.2 2.8 integral nonlinearity vs. reference voltage max5318 toc14 reference voltage (v) inl (lsb) 5.2 0 2.4 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 min inl max inl v avdd = 5.25v 5.1 4.7 3.9 4.3 3.5 3.1 zero-scale output error vs. supply voltage max5318 toc15 v avdd (v) output error (lsb) 5.5 0 2.7 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 v ref = 2.5v code = 0x00000 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
14 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 5.1 4.7 3.9 4.3 3.5 3.1 full-scale output error vs. supply voltage max5318 toc16 v avdd (v) output error (lsb) 5.5 0 2.7 -1.6 -1.2 -0.8 -0.4 0.4 0.8 1.2 1.6 2.0 -2.0 v ref = 2.5v code = 0x3ffff zero-scale output error vs. output current max5318 toc17 output current (ma) output error (lsb) 27 24 3 6 9 15 18 12 21 -3 -2 -1 0 1 2 3 4 -4 03 0 sourcing sinking code = 0x00000 v avss = -1.25v v ref = 4.096v zero code error distribution vs. temperature max5318 toc17a lsb count (no. of units) 50 40 -40 -30 -20 0 10 20 -10 30 10 20 30 40 50 60 70 80 0 -50 -40c +10c +25c zero code error distribution vs. temperature max5318 toc17b lsb count (no. of units) 50 40 -40 -30 -20 0 10 20 -10 30 10 20 30 40 50 60 70 80 0 -50 +25c +40c +105c zero code error drift max5318 toc17c drift (ppm/c) count (units) 10 20 30 40 50 60 70 80 0 +10c -40c 1.4 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0 zero code error drift max5318 toc17d drift (ppm/c) count (units) 10 20 30 40 50 60 70 0 +40c +105c 1.4 1.6 1.2 1.0 0.8 0.6 0.4 0.2 0 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
15 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) full-scale output error vs. output current max5318 toc18 output current (ma) output error (lsb) 27 24 3 6 9 15 18 12 21 -3 -2 -1 0 1 2 3 4 -4 03 0 sourcing sinking code = 0x3ffff v ref = 4.096v gain error temperature coefficien t max5318 toc18a drift (ppm/c) count (units) 10 20 30 40 50 60 70 0 +40c +105c 0 -0.4 -0.6 -0.2 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 gain error temperature coefficien t max5318 toc18b drift (ppm/c) count (units) 10 20 30 40 50 60 70 0 +10c -40c 0 -0.4 -0.6 -0.2 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 output drive capability max5318 toc19 output current (ma) output error (lsb) 7 6 4 5 2 3 1 -8 -6 -4 -2 0 2 4 6 8 10 -10 08 code = 0x01900 v avss = 0v v ref = 4.096v sinking current t a = +25c 45 40 30 35 10 15 20 25 5 output drive capability max5318 toc20 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0x00000 v avss = -1.25v v ref = 4.096v sinking current t a = +25c output drive capability max5318 toc21 output current (ma) output error (lsb) 7 6 4 5 2 3 1 -8 -6 -4 -2 0 2 4 6 8 10 -10 08 code = 0x3ffff v avdd = 4.2v v ref = 4.096v sourcing current t a = +25c maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
16 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 45 40 30 35 10 15 20 25 5 output drive capability max5318 toc22 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0x3ffff v avdd = 5v v ref = 4.096v sourcing current t a = +25c 45 40 30 35 10 15 20 25 5 output drive capability max5318 toc23 output current (ma) output error (lsb) -8 -6 -4 -2 0 2 4 6 8 10 -10 05 0 code = 0x00000 v avss = -1.25v v ref = 2.5v sinking current t a = +25c 45 40 30 35 10 15 20 25 5 output drive capability max5318 toc24 output current (ma) output error (lsb) -7 -4 -1 2 5 8 11 14 17 27 -10 06 0 50 55 code = 0x3ffff v avdd = 5v v ref = 2.5v sourcing current t a = +25c supply current vs. supply voltage max5318 toc25 v avdd (v) i avdd (ma) 5.25 5.00 4.75 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 5.0 4.50 5.50 t a = +105c t a = +25c t a = -40c power-down supply current vs. supply voltage max5318 toc26 v avdd (v) i avdd (a) 5.25 5.00 4.75 40 10 4.50 5.50 t a = +105c 15 20 25 30 35 v pd = 5v t a = +25c t a = -40c maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
17 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) 0.1hz to 10hz output noise max5318 toc27 1s / div v out 1v/div 10k 1k 100 10 100k output noise density max5318 toc28 frequency (hz) voltage noise (nv/rt-hz) 10 20 30 40 50 60 70 80 90 100 0 code = 0x20000 100 200 300 400 500 ground current vs. code max5318 toc29 code current (a) 196608 131072 65536 600 current through agnd_f and agnd_s v ref = 4.096v 0 0 262144 digital clock feedthrough max5318 toc30 2s / div v out 1mv/div v sclk 5v/div maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
18 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) major carry glitch (1 lsb positive step) max5318 toc31 400ns / div v out 10mv/div v ldac 5v/div major carry glitch (1 lsb negative step) max5318 toc32 400ns / div v out 10mv/div v ldac 5v/div settling time (code = 0x3c000 to 0x04000) max5318 toc33 1s / div v out 2v/div v out 200v/div v ldac 5v/div settling time (code = 0x04000 to 0x3c000) max5318 toc34 1s / div v out 2v/div v out 200v/div v ldac 5v/div maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
19 typical operating characteristics (continued) (v avdd = v ddio = 5v, v avss = -1.25v, v agnd = v dgnd = v agnd_f = v agnd_s = 0v; v ref = 4.096v, tc/ sb = pd = m/ z = dgnd, rst = v ddio , c refo = 100pf, c l = 100pf, r l = 10k, c bypass = 1f, t a = +25 c, unless otherwise noted.) entering power-down response max5318 toc35 10s / div v out 2v/div v pd 1v/div r l = open exiting power-down response max5318 toc36 10s / div v out 2v/div v pd 1v/div slow power-up response (rstsel = low) max5318 toc37 4ms /d iv v out 2v/div v avss 2v/div v bypass 2v/div v refo 2v/div v avdd 5v/div slow power-up response (rstsel = high) max5318 toc38 4ms /d iv v out 2v/div v avss 2v/div v bypass 2v/div v refo 2v/div v avdd 5v/div maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
20 pin description pin configuration m/ z dout din sclk cs avdd2 agnd_f agnd_s ref refo rst v ddio dgnd bypass rfb out tc/sb pd avss agnd avdd1 busy ldac ready 24 23 22 21 20 19 18 1 2 3 4 5 6 7 top view max5318 17 8 16 9 15 10 14 11 13 12 tssop + pin name function 1 rst active-low reset input. drive rst low to dgnd to put the device into a reset state. a reset state sets all spi input registers to their default power-on reset states as defined by the state of inputs m/ z and tc/ sb . set rst high to vddio, the dac output remains at the state defined by m/ z until ldac is taken low. 2 ready spi active-low ready output. ready asserts low when the device successfully completes processing an spi data frame. ready asserts high at the next rising edge of cs . in daisy-chain applications, the ready output typically drives the cs input of the next device in the chain or a gpio of a microcontroller. 3 m/ z reset select input. m/ z selects the default state of the analog output (out) after power-on or a hardware or software reset. connect m/ z to v ddio to set the default output voltage to midscale or to dgnd to set the default output voltage to zero scale. 4 busy digital input/open-drain output. connect a 2k i pullup resistor from busy to v ddio . busy goes low during the internal calculations of the dac register data. during this time, the user can continue writing new data to the din, offset, and gain registers, but no further updates to the dac register and dac output can take place. if ldac is asserted low while busy is low, this event is stored. busy is bidirectional, and can be asserted low externally to delay ldac action. busy also goes low during power-on reset, when rst is low, or when software reset is activated. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
21 pin description (continued) pin name function 5 ldac active-low load dac logic input. if ldac is taken low while busy is inactive (high), the contents of the input registers are transferred to the dac register and the dac output is updated. if ldac is taken low while busy is asserted low, the ldac event is stored and the dac register update is delayed until busy deasserts. any event on ldac during power-on reset or when rst is low is ignored. 6 dout spi bus serial data output. see the serial interface section for details. 7 din spi bus serial data input. see the serial interface section for details. 8 sclk spi bus serial clock input. see the serial interface section for details. 9 cs spi bus active-low chip-select input. see the serial interface section for details. 10 tc/ sb din format select input. connect tc/ sb to dgnd to set the data input format to straight binary or to v ddio to set it to twos complement. 11 pd active-high power-down input. connect pd to dgnd for normal operation. connect pd to v ddio to place the device in power-down. in power-down, out (analog voltage output) is connected to agnd through a 2k resistor, but the contents of the input registers and the dac latch do not change. the spi interface remains active in power-down. 12 avss negative analog power-supply input. connect to agnd or a negative supply voltage. when connected to the negative supply voltage, bypass avss with a 0.1f capacitor to agnd. 13 agnd analog ground. connect to the analog ground plane. 14 avdd1 positive analog power-supply input. bypass each avdd_ locally with a 0.1f and 10f capacitor to agnd (analog ground plane). connect avdd1 and avdd2 together. 15 out buffered analog voltage output. connect out to rfb externally to close the output buffer feedback loop. the buffered output is capable of directly driving a 10k load. the state of m/ z sets the power- on reset state of out (zero or midscale). in power-down, out is connected to agnd through a 2k pulldown resistor. 16 rfb feedback resistor input. rfb is connected through the internal feedback resistor to the inverting input of the analog output buffer. externally connect rfb to out to close the output buffer feedback loop. 17 refo voltage reference buffered output. bypass with a 100pf capacitor to agnd. 18 ref high-impedance 10m voltage reference input 19 agnd_s dac analog ground sense 20 agnd_f dac analog ground force. connect to the analog ground plane. 21 avdd2 positive analog power-supply input. avdd2 supplies power to the internal digital linear regulator. bypass avdd2 locally to agnd with 0.1f and 10f capacitors. connect avdd2 and avdd1 together. 22 bypass internal bypass connection. connect bypass to dgnd with 0.01f and 1f capacitors. 23 dgnd digital ground 24 v ddio digital interface power-supply input. connect to a 1.8v to 5.5v logic-level supply. bypass v ddio with a 0.1f capacitor to dgnd. the supply voltage at v ddio sets the logic-level for the digital interface. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
22 detailed description the max5318 is a high-accuracy, 18-bit, serial spi input, buffered voltage output digital-to-analog converter (dac) in a 4.4mm x 7.8mm, 24-lead tssop package. the device fea - tures q 2 lsb inl (max) accuracy and a q 1 lsb dnl (max) accuracy over the full temperature range of -40 n c to +105 n c. the dac voltage output is buffered resulting in a fast settling time of 3 f s and a low offset and gain drift of q 0.5ppm/ n c of fsr (typ). the force-sense output (out) maintains accuracy while driving loads with long lead lengths. additionally, a separate avss supply allows the output amplifier to go to 0v (gnd) while maintaining full linearity performance. the max5318 includes user-programmable digital gain and offset correction capability to enable easy system calibration. at power-up, the device resets its outputs to zero or mid - scale, providing additional safety for applications, which drive valves or other transducers that need to be off on power-up. this is selected by the state of the m/ z input on power-up. the wide 2.7v to 5.5v supply voltage range and integrated low-drift, low-noise reference buffer amplifier makes for ease of use. since the reference buffer input has a high input resistance, an external buffer is not required. the device accepts an external reference between 2.4v and v avdd - 0.1v for maximum flexibility and rail-to-rail operation. the max5318 features a 50mhz, 3-wire spi, qspi, microwire, and dsp-compatible serial interface. the sep - arate digital interface supply voltage input (v ddio ) is com - patible with a wide range of digital logic levels from 1.8v to 5.5v, eliminating the need for separate voltage translators. dac reference buffer the external reference input has a high input (ref) imped - ance of 10m i ||10pf and accepts an input voltage from +2.4v to v avdd - 0.1v. connect an external reference supply between ref and agnd. bypass the reference buffer output refo to agnd with a 100pf capacitor. connect the anode of an external schottky diode to ref and the cathode to avdd1 to prevent internal esd diode conduction in the event that the reference voltage comes up before avdd at power up. follow the recommenda - tions described in the power-supply sequencing section. visit www.maximintegrated.com/products/references for a list of available external voltage-reference devices. output amplifier (out) the max5318 includes an internal buffer for the dac output. the internal buffer provides improved load regulation for the dac output. the output buffer slews at 5v/ f s and drives up to 2k i in parallel with 200pf. the buffer has a rail-to-rail output capable of swinging to within 100mv of avdd_ and avss. the positive analog supply voltage (avdd_) determines the maximum output voltage of the device as avdd_ powers the output buffer. the output is diode clamped to ground, preventing nega - tive voltage excursions beyond approximately -0.6v. negative supply voltage (avss) the negative supply voltage (avss) determines the mini - mum output voltage. if avss is connected to ground, the output voltage can be set to as low as 100mv without degrading linearity. for operation down to 0v, connect avss to a negative supply voltage between -0.1v and -1.5v. the max1735 is recommended for generating -1.25v from a -5v supply. force/sense the max5318 uses force/sense techniques to ensure that the load is regulated to the desired output volt - age despite line drops due to long lead lengths. since agnd_f and agnd_s have code dependent ground currents, a ground impedance less than 13m ensures that the inl will not degrade by more than 0.1 lsb. form a star ground connection ( figure 2a ) near the device with agnd_f, agnd_s, and agnd tied together. always refer remote dac loads to this system ground for best performance. figure 2b shows how to configure the device and an external op amp for proper force/sense operation. the amplifier provides as much drive as needed to force the sensed voltage (measured between rfb and agnd_s) to equal the desired voltage. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
23 18-bit ideal transfer function the max5318 features 18-bit gain and 18-bit offset adjustment as shown in figure 3 . the incoming din code is multiplied and offset compen - sated by the generic equation shown in equation 1. the resulting value is then applied to the dac. equation 1) generic gain and offset adjustment dac din gain offset =+ the gain code is always an 18-bit straight binary word. the offset code is always twos complement. it is therefore simply added to the output of the multiplier. to guarantee that a gain of exactly 1 is possible, the actual gain coefficient applied to din is as defined in equation 2. equation 2) calculation of gain ( ) 18 gain 1 g 2 + = when din is straight binary, the ideal transfer function is given by: equation 3) straight binary ideal transfer function out din offset v gv v =+ when din is twos complement, the ideal transfer func - tion is given by: equation 4) twos complement ideal transfer function ref out din offset v v gv v 2 = + + v din and v offset are the voltages to which the din and offset codes are converted and v out is the voltage at the dac output buffer. see the conversion formulas for din, gain, and offset section for equations needed to convert the din and offset codes into v din and v offset . figure 2a. star ground connection figure 2b. force/sense connection figure 3. gain and offset adjustment out rfb agnd_f agnd_s agnd max5318 out rfb agnd agnd_f agnd_s max5318 spi interface offset gain din dac register ldac maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
24 the data din can be either straight binary or twos com - plement. in straight binary, zero code results in a zero- scale output. in twos complement, zero code results in a midscale output. to better understand how gain and offset affect the output voltage, see figure 4 and figure 5 . consider the generation of a ramp. for now assume offset is set to 0x00000. in straight binary mode, with gain set to 0x3ffff (g = 1), din starts from 0x00000 and increases to 0x3ffff. the output voltage will start at 0v and increase to (v ref - 1 lsb). if gain is reduced, the ramp will still start at 0v but the maximum level reached is reduced. with din set to twos complement mode, to generate the same ramp, din would start at 0x20000 and increase until it wraps around to 0x00000. at this point the dac output would be midscale. din then increases to 0x1ffff where the output would be full-scale -1 lsb. as gain is reduced, the start of the ramp becomes larger and the end of the ramp becomes smaller. the ramp is therefore centered at midscale. in both cases, a nonzero value for offset results in the output moving up or down. should the output of the gain and offset adjust block overflow full-scale or underflow zero-scale, the data is clipped so the dac output will be clipped rather than overflow or underflow. the effect of gain and offset adjustment is shown in figure 4 for straight binary mode and figure 5 for twos complement mode. if any of the din, gain, or offset registers is changed, the device takes 1.9s (t busy ) to compute the new val - ues to present to the dac. while the device is computing the new dac value, the busy output is set low. see the section on the busy output and ldac input for details. figure 4. gain and offset adjustment in straight binary mode figure 5. gain and offset adjustment in twos complement mode positive offset full-scale v out v ref 0v 00000 h2 0000 h midscale gain < 0x3ffff (g < 1) zero-scale din ideal characteristic negative offset 3ffffh positive offset full-scale v out v ref 0v 20000 h0 0000 h midscale gain < 0x3ffff (g < 1) zero-scale din ideal characteristic negative offset 1ffffh maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
25 conversion formulas for din, gain, and offset tables 1a and 1b show how to convert the din code to v din in straight binary and twos complement modes. table 2 shows how to convert the gain code to the gain factor g, which is multiplied with v din . table 3 shows how to convert the offset code to v offset , which is summed with the product g?v din . input, gain, and offset ranges the ranges of din, gain, and offset are summarized in table 4 to table 6 . also shown are the range values for the 18-bit max5318 with a 4.096v reference. note that v ref is the reference voltage applied to ref and 1 lsb is equal to v ref /2 18 . table 1a. converting din to v din (straight binary mode) table 2. converting gain to g table 3. converting offset to v offset table 1b. converting din to v din (twos complement mode) din equation for v din range 0x00000 to 0x3ffff din ref 18 din vv 2 = 0v to (v ref - 1 lsb) offset equation range 0x20000 to 0x3ffff -v ref /2 to -1 lsb 0x00000 to 0x1ffff 0v to (v ref /2 - 1 lsb) din equation for v din and v offset range 0x20000 to 0x3ffff v ref /2 to -1 lsb 0x00000 to 0x1ffff 0v to (v ref /2 - 1 lsb) ref din ref 18 v din - 0x20000 vv - 2 2 ?? = ?? ?? din ref 18 code vv 2 = gain equation range 0x00000 to 0x3ffff 1/2 18 to 1 18 gain 1 g 2 + = ref offset ref 18 v offset 0x20000 vv 2 2 ?? ? = ? ?? ?? offset ref 18 offset vv 2 = maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
26 table 6. offset range table 7. straight binary din examples table 4a. din range (straight binary mode) table 4b. din range (twos complement mode) table 5. gain range range offset v offset (v) value (v) minimum 0x20000 -v ref /2 -2.048 maximum 0x1ffff (v ref /2 - 1 lsb) 2.047992188 din v din (v) gain g offset v offset (v) calculation comment 0x20000 2.048 0x2ffff 0.75 0x10000 1.024 v out = 0.75 x 2.048 + 1.024 = 2.56v ? for v out , use equation 3 ? for v din , use table 1a ? for g, use table 2 ? for v offset , use table 3 second formula 0x30000 3.072 0x0ffff 0.25 0x30000 -1.024 v out = 0.25 x 3.072 - 1.024 = 0.512v ? for v out , use equation 3 ? for v din , use table 1a ? for g, use table 2 ? for v offset , use table 3 first formula range din v din (v) value (v) minimum 0x00000 0 0 maximum 0x3ffff (v ref - 1 lsb) 4.095984375 range din v din (v) value (v) minimum 0x20000 0 0 maximum 0x1ffff (v ref - 1 lsb) 4.095984375 range gain g value (v) minimum 0x00000 1/2 18 0.0000038147 maximum 0x3ffff 1 1 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
27 numerical examples several numerical examples for the max5318, as shown in table 7 and table 8 , illustrate how the gain and off - set control changes the output voltage. the examples assume a reference voltage of 4.096v. note that if the result of the calculation results in an under- or over-range output voltage, v out is set to its zero or full-scale value, respectively. an under-range output is less than 0v and an over-range output is greater than v ref - 1 lsb. reset the device is reset upon power-on, hardware reset using rst , or software reset using register 0x4, bit 15, com - mand rstsw . after reset, the value of the input register, the dac latch and the output voltage are set to the values defined by the m /z input. if a hardware reset occurs dur - ing a spi programming frame, anything before and after the reset for the frame will be ignored. a software reset initiated through the spi interface takes effect after the end of the valid frame. output state upon reset the output voltage can be set to either zero or mid - scale upon power-up, or a hardware or software reset, depending on the state of the m/ z input. after power-up, if the device detects that this input is low, the output volt - age is set to zero scale. if m/ z is high, the output voltage is set to midscale. note that during reset, when rst is low or rstsw is set to 0, the output voltage is set slightly lower than the value after coming out of reset. during reset, the output voltage is set to the values shown for the v out-reset specifica - tion in the electrical characteristics . power-down the device can be powered down by either hardware (pulling pd high) or software (setting the pd_sw bit in either the 0x4 or 0xc registers). note that the hardware and software inputs are ored. asserting either is enough to place the device in power-down mode. in order to restore normal operation to the device, satisfy both of these conditions: 1) pull pd low. 2) set the bits pd_sws (in both 0x4 and 0xc registers) to 0. in power-down, the output is internally connected to agnd through a 2k i resistor. the spi interface remains active and the dac register content remains unchanged. data format selection (straight binary vs. twos complement) the max5318 interprets the data code input (din) as either straight binary or twos complement. to choose the straight binary format, set the tc/ sb input low. for twos complement, set the input high. table 8. twos complement din examples din v din (v) gain g offset v offset (v) calculation comment 0x30000 -1.024 0x2ffff 0.75 0x08000 0.512 v out = 4.096/2 + 0.75 x (-1.024) + 0.512 = 1.792v ? for v out , use equation 4 ? for v din , use table 1b first formula ? for g, use table 2 ? for v offset , use table 3 second formula 0x10000 1.024 0x0ffff 0.25 0x38000 -0.512 v out = 4.096/2 + 0.25 x 1.024 - 0.512 = 1.792v ? for v out , use equation 4 ? for v din , use table 1b first formula ? for g, use table 2 ? for v offset , use table 3 first formula maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
28 ldac and busy interaction the busy line is open drain and is normally pulled up by an external resistor. it is software-configurable bidi - rectional and can be pulled down externally. if any of the din, gain, and offset registers is changed, the device must calculate the value to be presented to the dac reg - ister. to indicate to the host processor that the device is busy, the device pulls the busy output low. once com - putation is complete, the device releases busy and the host processor can load the dac by toggling the ldac input. if ldac is set low while busy is low, the ldac event is latched and implemented when the computation is complete and busy rises. there are four ways in which the ldac and busy out - puts can be used. this is shown graphically in figure 6 . 1) the host sends a new command. the device sets busy low. the host monitors busy to determine when it goes high. the device then pulses ldac low to update the dac. 2) the host sends a new command. the device sets busy low. the host toggles ldac low then high before busy goes high. the device latches the ldac event but does not implement it until processing is complete. then, busy goes high and the device updates the dac. 3) ldac is held low. the host sends a new command and the device sets busy low. the device updates the dac when the processing is complete and busy goes high. 4) busy is pulled down externally to delay dac update. the busy pin is bidirectional. to use busy as an input, set the no_busy bit to 1 using the 0x4 or 0xc command. when configured as an input, pulling busy low at least 50ns before the device releases the line delays dac update. dac update occurs only after busy is released and goes high. if used as an input, drive busy with an open-drain output with a pullup to v ddio . the processing required for calculating the final dac code is controlled by an internally generated clock. the clock frequency is not related to any exter - nal signals and the frequency is not precisely defined. therefore, if the dac must be updated at a precise time with the least amount of jitter, use option 1. figure 6. busy and ldac timing din sclk busy busy ldac ldac ldac ldac v out v out v out v out option 1 input register loaded option 2 option 3 option 4 (used as input) x1 2x 21 22 23 x t busy t s t cbf t ldh 50ns t ldpw busy pulled low externally maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
29 serial interface overview the spi interface supports speeds up to 50mhz. when cs is high, the remaining interface inputs are disabled to reduce transient currents. the interface supports daisy chaining to enable multiple devices to be controlled on the same spi bus. the device has a double-buffered interface consisting of two register banks: the input register and the dac register. the input register for din/gain/offset is con - nected directly to the 24-bit spi input shift register. the dac latch contains the dac code after digital process - ing and is loaded as defined in the ldac and busy interaction section above. a valid spi frame is 24-bit wide with 4-bit command r3 to r0, 18-bit data d17 to d0, and 2 unused lsbs. a full 24-bit spi command sequence is required for all spi command operations, regardless of the number of data bits actually used for the command. any commands terminating with less than a full 24-bit sequence will be aborted without impacting the operation of the part (sub - ject to t csa timing requirements). data is not written into the spi input register or dac and it continues to hold the preceding valid data. if a command sequence with more than 24 bits is provided, the command will be executed on the 24th sclk falling edge and the remainder of the command will be ignored. all spi commands result in the device assuming con - trol of the dout line from the first sclk edge through the 24th sclk edge. after relinquishing the dout line, the max5318 returns to a high-impedance mode. an optional bus hold circuit can be engaged to hold dout at its last bit value while not interfering with other devices on the bus. dout is disabled at power-up and must be enabled through the spi interface. when enabled, dout echoes the 4-bit command plus 18-bit data, which is being programmed. during readback, dout echoes the 4-bit command followed by the true readback data depending upon the type of read command. table 9 shows the bit positions for dout and din within the 24-bit spi frame. the device is designed such that sclk idles low, and din and dout change on the rising clock edge and get latched on the falling clock edge. the spi host controller should be set accordingly. daisy-chain spi operation using ready output the ready pulse appears 24 clock cycles after the neg - ative edge of cs as shown in figure 7 and can therefore be used as the cs line for the next device in the daisy chain. since the device looks at the first 24 bits of the transmission following the falling edge of cs , it is pos - sible to daisy-chain the device with different command word lengths. ready goes high after cs is driven high. to perform a daisy-chain write operation, drive cs low and output the data serially to din. the propagation of the ready signal then controls how the data is read by the device. as the data propagates through the daisy chain, each individual command in the chain is executed on the 24th falling clock edge following the falling edge of the respective cs input. to update just one device in a daisy chain, send the no-op command to the other device in the chain. to update the first device in the chain, raise the cs input after writing to that device. because daisy-chain operation requires parallel - ing the douts of all the max5318 in the chain, the no_holden bit in register 0x4 or 0xc should be set to 1 for all devices. doing so ensures that dout goes into high-impedance after the spi frame is complete (i.e. after the 24th clock cycle) as shown in figure 8 . stand-alone operation the diagram in figure 9 shows a stand-alone connec - tion of the max5318 in a typical spi application. if more than one peripheral device shares the dout bus, the no_holden bit in register 0x4 or 0xc should be set to 1 for the max5318. doing so ensures that dout goes into high-impedance after the spi frame is complete (i.e. after the 24th clock cycle). note that x is dont care. table 9. spi command and data mapping with clock falling edges clock edge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 din r3 r2 r1 r0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x dout 0 r3 r2 r1 r0 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
30 figure 7. daisy-chain spi connection terminating with a standard spi device. figure 8. daisy-chain spi connection timing c slave 1 sclk din dout mosi miso i/ o sck slave 3 sclk din dout slave 2 sclk din dout cs ready cs ready cs ready cs din dout1 sclk 12 32 4 22 21 20 4 3 21 23 24 22 21 5 4 3 21 23 24 22 21 5 4 3 2 slave 1 data slave 2 data slave 3 data ready 1 ready 3 ready 2 dout2 hi-z hi-z hi-z hi-z dout3 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
31 command and register map all command and data registers have read and write functionality. the register selected depends on the com - mand select bits r[3:0]. each write to the device consists of 4 command select bits (r[3:0]), 18 data bits (which are detailed in table 11 to table 19 ), and 2 dont care lsbs. a summary of the commands is shown in table 10 . applications information power-on reset (por) upon power-on, the output is set to either zero-scale (if m/ z is low) and midscale (if m/ z is high). the entire register map is set to their default values as shown in table 11 to table 19 . figure 9. stand-alone operation table 10. register map summary csm cs1 cs cs sclk c dwrite dread sclk din dout max5318 to other devices/ chains hex r3 r2 r1 r0 function 0 0 0 0 0 no-op. used mainly in daisy-chain communications. 1 0 0 0 1 din register write 2 0 0 1 0 offset register write 3 0 0 1 1 gain register write 4 0 1 0 0 configuration register write 5C8 reserved 9 1 0 0 1 din register read a 1 0 1 0 offset register read b 1 0 1 1 gain register read c 1 1 0 0 configuration and status register read. dCf reserved maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
32 register details table 11. no-op command (0x0) table 12a. straight binary din write register (tc/ sb ) = 0) (0x1) table 12b. twos complement din write register (tc/ sb ) = 1) (0x1) bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name x x x x x x x x x x x x x x x x x x default x x x x x x x x x x x x x x x x x x bit name description 17:0 dont care no action on spi shift register and dac input registers. use for daisy-chain purposes when r[3:0] = 0000. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x00000 when m/ z = dgnd (zero scale) 0x20000 when m/ z = v ddio (midscale) bit name description 17:0 b[17:0] 18-bit dac input code in straight binary format. for clarity, a few examples are shown below: 00 0000 0000 0000 0000 0x00000 zero scale 01 0000 0000 0000 0000 0x10000 quarter scale 10 0000 0000 0000 0000 0x20000 midscale 11 0000 0000 0000 0000 0x30000 three-quarter scale 11 1111 1111 1111 1111 0x3ffff full scale - 1 lsb bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x20000 when m/ z = dgnd (zero scale) 0x00000 when m/ z = v ddio (midscale) bit name description 17:0 b[17:0] 18-bit dac input code in twos complement format. for clarity, a few examples are shown below: 10 0000 0000 0000 0000 0x20000 zero scale 11 0000 0000 0000 0000 0x30000 quarter scale 11 1111 1111 1111 1111 0x3ffff midscale - 1 lsb 00 0000 0000 0000 0000 0x00000 midscale 00 0000 0000 0000 0001 0x00001 midscale + 1 lsb 01 0000 0000 0000 0000 0x10000 three-quarter scale 01 1111 1111 1111 1111 0x1ffff full scale - 1 lsb maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
33 table 13. offset register write in twos complement (0x2) table 14. gain write register (0x3) bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x00000zero offset bit name description 17:0 b[17:0] 18-bit offset code in twos complement format. for clarity, a few examples are shown below: 10 0000 0000 0000 0000 0x20000 offset of -2 17 11 1111 1111 1111 1111 0x3ffff offset of -1 00 0000 0000 0000 0000 0x00000 offset of 0 00 0000 0000 0000 0001 0x00001 offset of +1 01 1111 1111 1111 1111 0x1ffff offset of 2 17 C 1 bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0x3ffffgain of 1 bit name description 17:0 b[17:0] 18-bit gain code. for clarity, a few examples are shown below: 11 1111 1111 1111 1111 3ffff\h gain of 1. (2 18 C 1 + 1)/2 18 11 1111 1111 1111 1110 3fffe\h gain of 0.999996. (2 18 C 2 + 1)/2 18 01 1111 1111 1111 1111 1ffff\h gain of 0.5. (2 17 C 1 + 1)/2 18 01 1111 1111 1111 1110 1fffe\h gain of 0.499996. (2 17 C 2 + 1)/2 18 00 0000 0000 0000 0000 00000\h gain of 0.0000076. 1/2 18 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
34 table 15. general configuration write register (0x4) bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pd_sw no_holden rst_sw no_busy dout_on x x x x x x x x x x x x x default 0 0 1 0 0 x x x x x x x x x x x x x bit name description 17 pd_sw software pd (power-down). equivalent to the pd input. 0: normal mode 1: power-down mode. out is internally connected to agnd using a 2k i resistor. 16 no_holden spi bus hold enable. 0: bus hold enabled for spi dout output. dout stays at its last value after the spi cs input rises at the end of the spi frame (i.e. after the 24th clock cycle). 1: bus hold disabled for spi dout output. dout goes high impedance after the spi cs input rises at the end of the spi frame (i.e. after the 24th clock cycle). 15 rst_sw software reset. equivalent to the rst input. 0: place device in reset 1: normal operation set the active low rst _sw bit low to initiate a software reset (equivalent to pulling rst low) 14 no_busy busy input disable. 0: busy input is active. 1: busy input is disabled. note that this does not affect the busy bit in the general configuration and status register. the busy pin is bidirectional. when enabled, it can be pulled down externally to delay dac updates. 13 dout_on spi dout output disable. dout is disabled by default. 0: dout output disabled. when dout is disabled, the output is pulled low for the duration of the spi frame. 1: dout output enabled. 12:0 dont care. these bits are reserved for the corresponding read command. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
35 table 16. din read register (0x9) table 17. offset read register (0xa) table 18. gain read register (0xb) bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name description 17:0 b[17:0] 18-bit din readback value. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit name description 17:0 b[17:0] 18-bit offset readback value in twos complement. bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit name description 17:0 b[17:0] 18-bit gain readback value. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
36 table 19. general configuration and status read register (0xc) bit 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name pd_sw no_ holden rst_sw no_busy dout_on busy x x x x x x rev_id[3:0] x x default 0 0 1 0 0 0 0 0 0 0 0 0 0001 0 0 bit name description 17 pd_sw software pd (power-down). equivalent to the pd input. 0: normal mode. 1: power-down mode. out is internally connected to agnd using a 2k i resistor. 16 no_holden spi bus hold enable. 0: bus hold enabled for spi dout output. dout stays at its final value after the spi cs input rises at the end of the spi frame. 1: bus hold disabled for spi dout output. dout goes high impedance after the spi cs input rises at the end of the spi frame. 15 rst_sw software reset. equivalent to the rst input. 0: place device in reset. 1: normal operation. set the active low rst _sw bit low to initiate a software reset (equivalent to pulling rst low). 14 no_busy busy input disable. 0: busy input is active. 1: busy input is disabled. note that this does not affect the busy bit in the general configuration and status register. the busy pin is bidirectional. when enabled, it can be pulled down externally to delay dac updates. 13 dout_on spi dout output disable. dout is disabled by default. 0: dout output disabled. when dout is disabled, the output is pulled low for the duration of the spi frame. 1: dout output enabled. 12 busy global busy status readback. 0: device is busy calculating output voltage. 1: device is not busy. 11:6 reserved. will read back 0. 5:2 rev_id[3:0] device revision 1:0 reserved. will read back 0. maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
37 power supplies and bypassing considerations for best performance, use a separate supply for the max5318. bypass v ddio , avdd_, and avss with high- quality ceramic capacitors to a low-impedance ground as close as possible to the device. a typical high-quality x5r 10 f f capacitor can become self resonant at 2mhz. therefore, it is actually an inductor above 2mhz and is useless for decoupling signals above 2mhz. it is there - fore recommended that several capacitors of different values are connected in parallel. figure 10 shows the magnitude of impedance of typical 1 f f, 100nf, and 10nf x5r capacitors. as the capacitance reduces, the self-resonant frequency increases. in addition, the paral - lel combination of all three is shown and exhibits a sig - nificant improvement over a single capacitor. these plots do not include any pcb trace inductance. minimize lead lengths to reduce lead inductance. adding just 2nh trace inductance to each of the typical capaci - tors above produces the effects shown in figure 11 . this shows significant reduction in the self-resonant frequen - cies of the capacitors. internal linear regulator (bypass) bypass is the output of an internal linear regulator and is used to power digital circuitry. connect bypass to dgnd with a ceramic capacitor in the range of 1 f f to 10 f f with esr in the range of 100m i to 20m i to ensure stability. the typical voltage on this pin is 2.4v. use a low-leakage capacitor to ensure low power-down current. power-supply sequencing during power-up, ensure that avdd_ comes up before the reference does. if this is not possible, connect a schottky diode between the ref and avdd_ such as the mbr0530t1g. if ref does come up before avdd_, the diode conducts and clamps ref to avdd_. once avdd_ has come up, the diode no longer conducts. ref should always be below avdd_ as specified in the electrical characteristics . avdd_ and avdd_ should be connected together and powered from the same supply. v ddio and avss can be sequenced in any order. always perform a reset operation after all the supplies are brought up to place the device in a known operating state. layout considerations digital and ac transient signals on agnd inputs can create noise at the outputs. connect both agnd inputs to form the star ground for the dac system. refer remote dac loads to this system ground for the best possible performance (see the force/sense section). use proper grounding techniques, such as a multilayer board with a low-inductance ground plane, or star con - nect all ground return paths back to agnd. do not use wire-wrapped boards and sockets. use ground plane shielding to improve noise immunity. do not run analog and digital signals parallel to one another (especially clock signals) and avoid routing digital lines underneath the device package. for a recommended layout, consult the max5318 evaluation kit datasheet. figure 10. typical x5r capacitor impedance figure 11. typical x5r capacitor impedance with additional 2nh pcb trace inductance 3k 1k 100 10 1 100m 10m 100k 1m 10m 100m 4m impedance (i) frequency (hz) 10nf 1f 100nf 3k 1k 100 10 1 100m 10m 100k 1m 10m 100m 4m impedance (i) frequency (hz) 10nf 1f 100nf 10nf 1f 100nf maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
38 voltage reference selection and layout the voltage reference should be placed close to the dac. the same power-supply decoupling and grounding rules as the dac should be implemented. many voltage refer - ences require an output capacitor for stability or noise reduction. provided the trace between the reference device and the dac is kept short and well shielded, a sin - gle capacitor may be used and placed close to the dac. however, for improved noise immunity, additional capaci - tors may be used but be careful not to exceed the recom - mended capacitance range for the voltage reference. refer to maxim applications note an4300: calculating the error budget in precision digital-to-analog converter (dac) applications for detailed description of voltage reference parameters and trading off the error budget. the max6126 is recommended for use with this device. optimizing data throughput rate the ldac and busy interaction section details the tim - ing of data written to the device and how the dac is updated. data throughput speed can be increased by overlapping the data load time with the calibration and settling time as shown below in figure 12 . following the 24th sclk falling edge, the device starts its calibration period. providing that the ldac falling edge arrives before the 24th sclk falling edge, and assuming the spi clock frequency is high enough, the throughput period is therefore limited by the internal calculation and settling times only. a slight further increase in throughput time can be gained by either toggling ldac during the cal - culation time or by pulling it low permanently. however, the exact point at which the dac update occurs is then determined internally as indicated by the busy line rising edge. this is not an exact time. busy line pullup resistor selection the busy pin is an open-drain output. it therefore requires a pullup resistor. 2k i value is recommended as a compromise between power and speed. stray capaci - tance on this line can easily slow the rise time to an unacceptable level. the busy pin can sink up to 5ma. therefore a resistor as low as v ddio /0.005 may be used if faster rise times are required. producing unipolar high-voltage and bipolar outputs figure 11 and figure 12 show how external op amps can be used to produce a unipolar high-voltage output and a bipolar output definitions integral nonlinearity (inl) inl is the deviation of the measured transfer function from a straight line drawn between two codes. this line is drawn between the zero and full-scale codes of the transfer func - tion, once offset and gain errors have been nullified. differential nonlinearity (dnl) dnl is the difference between an actual step height and the ideal value of 1 lsb. if the magnitude of the dnl is less than or equal to 1 lsb, the dac guarantees no miss - ing codes and is monotonic. figure 12. optimum throughput with stable update period 24th sclk din out busy t busy ldac 24th sclk ldac falling edge before 24th sclk falling edge maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
39 offset error offset error indicates how well the actual transfer func - tion matches the ideal transfer function at a single point. typically, the point at which the offset error is specified is at or near the zero-scale point of the transfer function. gain error gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. settling time the settling time is the amount of time required from the start of a ldac high-to-low transition or busy low-to-high transition (whichever occurs last), until the dac output settles to within 0.003% of the final value. digital feedthrough digital feedthrough is the amount of noise that appears on the dac output when the dac digital control lines are toggled. digital-to-analog glitch impulse the glitch impulse occurs at the major carry transitions along the segmented bit boundaries. it is specified as the net area of the glitch impulse which appears at the output when the digital input code changes by 1 lsb. the glitch impulse is specified in nanovolts-seconds (nv-s). digital-to-analog power-up glitch impulse the digital-to-analog power-up glitch is the net area of the glitch impulse which appears at the output when the device exits power-down mode. figure 13. unipolar high-voltage output figure 14. bipolar output ou t 0v to kv ref k = 1 + r2 /r 1 r2 r1 max5318 max44250 ou t refo -v re f to v re f r2 r1 = r2 r1 max5318 max9632 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
40 typical operating circuit chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. + denotes a lead(pb)-free/rohs-compliant package. ordering information 2.4v to (v avdd - 0.1v) mbr0530t1g v ddio 2.0ki 24 ref 0.1f 0.01f 18 c gpio?s spi interface 0.1f 1f 10f 2.7v to 5v 1.8v to 5v avdd2 21 avdd1 14 17 refo 15 out 16 rfb bypass 22 linear regulator max5318 23 dgnd 13 agnd 19 agnd_s 20 agnd_f 12 avss buffer output buffer 0 to -1.25v 4 busy 3 m/z 10 ts/s b 11 pd 1 rst 5 ldac 2 ready 9 cs 8 sclk 7 din 6 dout 0.1f 0.1f 10f 100pf r l interface and control dac register digital gain and offset 18-bit dac input register part temp range pin-package max5318gug+ -40 n c to +105 n c 24 tssop package type package code outline no. land pattern no. 24 tssop u24+1 21-0066 90-0118 maxim integrated max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 41 ? 2012 maxim integrated the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 9/12 initial release max5318 18-bit, high-accuracy voltage output dac with digital gain, offset control, and spi interface

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