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june 2007 ? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller features ? fastvcore? nonlinear control for fast transient and to minimizes the number of output caps required ? selectable 2- or 3-phase operation at up to 1mhz per phase ? 7.7mv worst-case differential sensing error over temperature ? active current balanci ng between output phases ? power good and crowbar blanking supports on-the-fly vid code changes ? 0.5v to 1.6v output ? usable for intel ? vr10 and vr11 designs ? selectable vr10 extended (7-bit) and vr11 (8-bit) vid tables ? programmable soft-start ramp ? programmable short-circuit protection and latch-off delay applications ? desktop pc/server processor power supplies for existing and next-generation intel ? processors ? vrm modules related applications notes ? an-6052 ? instructions for the multi-phase vr11 mathcad ? design tool description the FAN50FC3 device is a multi-phase buck switching regulator controller optimiz ed to convert a 12v input supply to the processor core voltage required by high- performance intel ? processors. it has an internal, 8-bit dac that converts a digita l voltage identification (vid) code sent from the processo r, to set the output voltage between 0.5v and 1.6v in 6.25mv steps. it outputs pwm signals to external mosf et drivers that drive the switching power mosfets. the switching frequency of the design is programmable by a single resistor value and the number of phases can be programmed to support 2- or 3-phase applications. the FAN50FC3 also includes programmable no-load offset and droop functions to adjust the output voltage as a function of the load cu rrent, as required by the intel ? specifications. the FAN50FC3 also provides an accurate and reliable short-circuit protection function with an adjustable over-current set point. fastvcore? technology great ly improves the fast transient response required by today?s high-performance processors. this allows fewer output capacitors to be used in the application. the FAN50FC3 is specified over the commercial temperature range of 0c to +85c and is available in a 32-lead mlp package. ordering information part number pb-free operating temperature range package packing method FAN50FC3mpx yes 0 to 85c 32-lead, molded leadless package (mlp) tape and reel
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 2 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller block diagram + gnd en vidsel vid7 ss z cscomp sw1 pwm1 rampadj rt vcc pwm2 pwm3 sw2 sw3 vosadj csref cssum vid5 vid6 vid4 vid3 vid2 vid1 vid0 fbrtn comp delay ilimit pwrgd uvlo shut down &bias oscillator reset en set reset reset delay 2/3 phase logic crowbar curr ent lim it current limit circuit start up control dac buff vid dac precision reference boot control dac - uvp dac + ovp csref current balance circuit fb threshold od + + - - figure 1. block diagram
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 3 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller pin assignments 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 vosadj od# gnd cscomp cssum csref rampadj rt pwm1 pwm2 pwm3 sw1 sw2 sw3 vcc vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vidsel en pwrgd fbrtn fb comp ss delay FAN50FC3 ilimit exposed paddle on bottom of package figure 2. pin assignments pin definitions pin # name description 1 en power supply enable input . analog comparator input wi th hysteresis. if the input voltage is higher than the internal threshold, the controller is enabl ed; if lower, the controller is disabled. 2 pwrgd power good output . open-drain output that pulls to gnd when the output voltage is outside the proper operating range. 3 fbrtn feedback return . vid dac and error amplifier refe rence for remote sensing output voltage. 4 fb feedback input . error amplifier input for remote sensing output vo ltage. a positive internal current source is connected to this pin to allow the output voltage to be offset lower than the dac voltage. 5 comp error amplifier output . for loop compensation. 6 ss soft-start input . an external capacitor connected between this pin and gnd sets the soft-start ramp-up time. 7 delay delay timer input . an external capacitor connect ed between this pin and gnd sets the over-current latch-off delay time, boot voltage hold time, en delay time, and pwrgd delay time. 8 ilimit current limit set . an external resistor from this pin to gnd sets the current limit threshold of the converter. 9 rt frequency set input . an external resistor connect ed between this pin and gnd sets the oscillator frequency of the device. 10 rampadj pwm ramp set input . an external resistor c onnected between this pin and the converter input voltage sets the internal pwm ramp. 11 csref current-sense amplifier positive input . the voltage on this pin is used as the reference for the current-sense amplifier. the power good and crowbar functions are internally connected to this pin. 12 cssum current-sense amplifier negative input . 13 cscomp current-sense amplifier compensation output .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 4 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller pin definitions (continued) 14 gnd ground . biasing and logic output signals of the device are referenced to this ground. 15 od# output disable . this pin is actively pulled low when the en input is low or when v cc is below the uvlo threshold, to di sable the external mosfet drivers. 16 vosadj fastvcore? v os adjustment input. this signal is used as a control input for the fastvcore? circuit. 17 to 19 sw3 to sw1 switching node current balance inputs . sense the switching side of the inductor and used to measure the current level in each phase. the sw pins of unused phases should be left open. 20 to 22 pwm3 to pwm1 pwm outputs . each output is connected to the i nput of an external mosfet driver, such as the fan5109. connecting the pwm3 output to v cc disables that phase, allowing the FAN50FC3 to oper ate as a 2-phase controller. 23 vcc supply voltage . 24 to 31 vid7 to vid0 voltage identification code inputs . these digital inputs are connected to the internal dac and used to program the out put voltage. these pins hav e 1a internal pull-down; if they are left open, the input state is decoded as logic low. 32 vidsel vid table select input . a logic low selects the ex tended vr10 dac table and a logic high selects the vr11 dac table. this pin has a 1a internal pull-down; if left open, the input state is decoded as logic low. exposed paddle internally connected to die ground . may be connected to ground or left floating. connect to ground for lowest package thermal resistance.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 5 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit supply voltage, vcc -0.3 +15 v fbrtn -0.3 +0.3 v rampadj, pwm3 -0.3 v cc +0.3 v sw1 ? sw3 -10 +25 v all other inputs and outputs -0.3 +5.5 v t j operating juncti on temperature 0 +125 c t stg storage temperature -65 +150 c t ls lead soldering temperature (10 seconds) 300 c t li lead infrared temperature (15 seconds) 260 c ja thermal resistance, junction-to-ambient (1) 45 c/w note: 1. junction-to-ambient thermal resistance, ja , is a strong function of pcb material, board thickness, thickness and number of copper planes, number of via used, diameter of via used, avail able copper surface, and attached heat sink characteristics. recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designi ng to absolute maximum ratings. symbol parameter conditions min. typ. max. unit v cc supply voltage vcc to gnd 9.6 12.0 14.4 v t a ambient temperature 0 +85 c
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 6 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller electrical characteristics v cc = 12v, fbrtn = gnd, and t a = +25 c. the ? denotes specifications whic h apply over the full operating temperature range. symbol parameter conditions min. typ. max. unit error amplifier v comp output voltage range ? 0.5 4.0 v v fb accuracy relative to nominal dac output, referenced to fbrtn. (see figure 3) ? -7.7 +7.7 mv v fb(boot) accuracy vrm11 vid range: 1.00625v to 1.60000v during start-up ? 1.092 1.1001.108 v load line droop accuracy csref-cscomp= 80mv (see figure 5) ? -78 -80 -82 mv differential non-linearity ? -1 +1 lsb v fb line regulation v cc =10v to 14v 0.05 % i fb input bias current ? 13.5 15 16.5 a i fbrtn fbrtn current ? 70 95 a i o(err) output current fb forced to v out -3% 500 a gbw (err) gain bandwidth product comp = fb (3) 20 mhz slew rate comp = fb (3) 25 v/s v cscomp cscomp voltage range relative to csref ? -250 +250 mv t boot boot voltage hold time c delay = 10nf 2 ms vid inputs and vidsel v il(vid) input low voltage vidx, vidsel ? 0.4 v v ih(vid) input high voltage vidx, vidsel ? 0.8 3.3 v v il(vid) select vr10 table vidsel logic low 0.4 v v ih(vid) select vr11 table vidsel logic high 0.8 3.3 v i in(vid) input current, vid low -1 a t dly(vid) vid transition delay time vid code change to fb change (3) ? 200 ns t dly(cpu) no cpu detection turn-off delay time vid code change to off state to pwm going low (3) ? 200 ns oscillator f osc frequency ? 0.25 4.50 mhz f phase frequency variation t a = 25c, r t = 200k, 3-phase -20% 400 20% khz v rt output voltage r t =100k to gnd ? 1.9 2.0 2.1 v v rampadj rampadj output voltage v rampadj = v dac + 2k * (v cc ? v dac ) / (r rampadj + 2k ) ? -50 +50 mv i rampadj rampadj input current range 1 50 a current-sense amplifier v os(csa) offset voltage cssum ? csref (see figure 4) ? -1.0 +1.0 mv i bias(cssum) input bias current (for cssum) ? -50 +50 na i bias(csref) input current (for csref) current drawn by csref pin ? -3 +3 a gbw (csa) gain bandwidth product cssum = cscomp (3) 10 mhz slew rate c cscomp = 10pf (3) 10 v/s v csacm input common-mode range cssum and csref ? 0 3.2 v
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 7 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller electrical characteristics (continued) v cc = 12v, fbrtn = gnd, and t a = +25 c. the ? denotes specifications whic h apply over the full operating temperature range. symbol parameter conditions min. typ. max. unit current-sense amplifier (continued) output voltage range ? 0.05 3.20 v i cscomp output current 1 ma current balance circuit v sw(x)cm common mode range (3) ? -600 +200 mv r sw(x) input resistance sw(x) = 0v ? 35 50 65 k i sw(x) input current sw(x) = 0v ? 1.6 3.3 5.0 a i sw(x) input current matching sw(x) = 0v ? -5 +5 % current limit comparator v ilimit output voltage r ilimt = 143k ? 1.6 1.7 1.8 v i ilimit output current r ilimt = 143k 12 a maximum output current ? 60 a v cl current limit threshold voltage v csref ? v cscomp , r ilimt = 143k ? 100 120 140 mv current limit setting ratio v cl / i ilimt 10 mv/a delay timer i delay normal mode output current ? 12 15 18 a i delay(cl) output current in current limit ? 3.00 3.75 4.50 a v delay(th) threshold voltage ? 1.6 1.7 1.8 v soft-start i (ss) output current during start-up ? 12 15 18 a enable input v th(en) threshold voltage ? 800 850 900 mv v hys(en) threshold hysteresis ? 80 100 130 mv i in(en) enable input current 1 a t delay(en) turn-on delay start-up sequence, en>950mv, c delay = 10nf 2 ms #od output v ol(odb) output voltage low i pwm(sink) = 400 a ? 160 400 mv v oh(odb) output voltage high i pwm(source) = 400 a ? 4 5 v power-good comparator v pwrgd(uv) under-voltage threshold relative to nominal dac output ? -300 -250 -200 mv v pwrgd(ov) over-voltage threshold relative to nominal dac output ? 100 150 200 mv v ol(pwrgd) output low voltage i pwrgd(sink) = -4ma ? 200 300 mv t1 pg(dly) power good delay time 1 start-up sequence; c delay = 10nf; power good blanking time ? 2 ms t2 pg(dly) power good delay time 2 vid code changing; c delay = 10nf; power good blanking time ? 100 250 s t3 pg(dly) power good delay time 3 (3) vid code static; c delay = 10nf; power good blanking time ? 100 200 ns
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 8 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller electrical characteristics (continued) v cc = 12v, fbrtn = gnd, and t a = +25 c. the ? denotes specifications whic h apply over the full operating temperature range. symbol parameter conditions min. typ. max. unit power-good comparator (continued) v crowbar crowbar trip point relative to nominal dac output ? 100 150 200 mv v cr_rst crowbar reset point relative to fbrtn ? 250 300 350 mv t1 crowbar crowbar delay time 1 vid code change over-voltage to pwm going low crowbar blanking time ? 100 250 s t2 crowbar crowbar delay time 2 vid code static over-voltage to pwm going low crowbar blanking time ? 400 ns pwm outputs v ol(vrtm) output voltage low i pwm(sink) = 400a ? 160 400 mv v oh(vrtm) output voltage high i pwm(source) = 400a ? 4 5 v v dis phase disable voltage applicable to pwm3 pins only. connect this pin to vcc to disable the phase. (4) ? v cc -.1 v input supply i dc dc supply current en = logic high ? 8 12 ma v uvlo uvlo threshold v cc rising ? 6.5 6.9 7.3 v v uvlo_hys uvlo hysteresis ? 0.7 0.9 1.1 v notes: 2. limits at operating temperat ure extremes are guaranteed by design, characterization, an d statistical quality control. 3. ac specifications are guaranteed by design and characteri zation; not production tested. 4. to operate the FAN50FC3 with fewer t han three phases, pwm3 should be connected to v cc to disable this phase. see the theory of operat ion section for details.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 9 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller test diagrams 8 8 bit code 12 v 1.25 v 20k 100nf 1k 250k 10nf 10nf sw1 sw2 sw3 vid0 vid1 vid2 vid7 vid6 vid5 vid4 vid3 vcc en vidsel cscomp cssum ss csref fb comp delay ilimit gnd fbrtn v cscomp csref cssum vcc gnd csa 12 v 39k 100nf 1k 1 v + - + - 23 13 12 11 14 figure 3. closed-loop output voltage accuracy figure 4. current-sense amplifier v os comp cscomp fb vcc csref 12 v 10k 23 5 4 13 11 v + - gnd v + - 14 v dv rt as a function of oscillator frequency 6 2 8 4 1 4 3 0 8 2 4 3 2 0 1 1 7 0 1 4 7 1 2 9 1 1 5 1 0 4 9 4 8 6 7 9 7 2 6 7 6 2 5 8 5 4 5 1 4 8 4 5 4 3 4 0 3 8 10 100 1000 0 1000 2000 3000 4000 5000 oscillator frequency (khz) rt (k ? ) figure 5. droop voltage accuracy figure 6. r t required to set o scillator frequency
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 10 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller table 1. output voltage programming codes (ext ended vr10); 0 = logic low; 1 = logic high. vid4 vid3 vid2 vid1 vid0 vid5 vid6 v out (v) 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 off 1 1 1 1 1 0 0 off 1 1 1 1 1 0 1 off 1 1 1 1 0 1 0 1.09375 1 1 1 1 0 1 1 1.10000 1 1 1 1 0 0 0 1.10625 1 1 1 1 0 0 1 1.11250 1 1 1 0 1 1 0 1.11875 1 1 1 0 1 1 1 1.12500 1 1 1 0 1 0 0 1.13125 1 1 1 0 1 0 1 1.13750 1 1 1 0 0 1 0 1.14375 1 1 1 0 0 1 1 1.15000 1 1 1 0 0 0 0 1.15625 1 1 1 0 0 0 1 1.16250 1 1 0 1 1 1 0 1.16875 1 1 0 1 1 1 1 1.17500 1 1 0 1 1 0 0 1.18125 1 1 0 1 1 0 1 1.18750 1 1 0 1 0 1 0 1.19375 1 1 0 1 0 1 1 1.20000 1 1 0 1 0 0 0 1.20625 1 1 0 1 0 0 1 1.21250 1 1 0 0 1 1 0 1.21875 1 1 0 0 1 1 1 1.22500 1 1 0 0 1 0 0 1.23125 1 1 0 0 1 0 1 1.23750 1 1 0 0 0 1 0 1.24375 1 1 0 0 0 1 1 1.25000 1 1 0 0 0 0 0 1.25625 1 1 0 0 0 0 1 1.26250 1 0 1 1 1 1 0 1.26875 1 0 1 1 1 1 1 1.27500 1 0 1 1 1 0 0 1.28125 1 0 1 1 1 0 1 1.28750 1 0 1 1 0 1 0 1.29375 1 0 1 1 0 1 1 1.30000 1 0 1 1 0 0 0 1.30625 1 0 1 1 0 0 1 1.31250 1 0 1 0 1 1 0 1.31875 1 0 1 0 1 1 1 1.32500 1 0 1 0 1 0 0 1.33125 1 0 1 0 1 0 1 1.33750 1 0 1 0 0 1 0 1.34375 1 0 1 0 0 1 1 1.35000 1 0 1 0 0 0 0 1.35625 1 0 1 0 0 0 1 1.36250 1 0 0 1 1 1 0 1.36875 1 0 0 1 1 1 1 1.37500 1 0 0 1 1 0 0 1.38125 1 0 0 1 1 0 1 1.38750 1 0 0 1 0 1 0 1.39375 1 0 0 1 0 1 1 1.40000 1 0 0 1 0 0 0 1.40625 1 0 0 1 0 0 1 1.41250 1 0 0 0 1 1 0 1.41875 1 0 0 0 1 1 1 1.42500 1 0 0 0 1 0 0 1.43125 1 0 0 0 1 0 1 1.43750 1 0 0 0 0 1 0 1.44375 1 0 0 0 0 1 1 1.45000 1 0 0 0 0 0 0 1.45625 1 0 0 0 0 0 1 1.46250 0 1 1 1 1 1 0 1.46875 0 1 1 1 1 1 1 1.47500
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 11 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller vid4 vid3 vid2 vid1 vid0 vid5 vid6 v out (v) 0 1 1 1 1 0 0 1.48125 0 1 1 1 1 0 1 1.48750 0 1 1 1 0 1 0 1.49375 0 1 1 1 0 1 1 1.50000 0 1 1 1 0 0 0 1.50625 0 1 1 1 0 0 1 1.51250 0 1 1 0 1 1 0 1.51875 0 1 1 0 1 1 1 1.52500 0 1 1 0 1 0 0 1.53125 0 1 1 0 1 0 1 1.53750 0 1 1 0 0 1 0 1.54375 0 1 1 0 0 1 1 1.55000 0 1 1 0 0 0 0 1.55625 0 1 1 0 0 0 1 1.56250 0 1 0 1 1 1 0 1.56875 0 1 0 1 1 1 1 1.57500 0 1 0 1 1 0 0 1.58125 0 1 0 1 1 0 1 1.58750 0 1 0 1 0 1 0 1.59375 0 1 0 1 0 1 1 1.60000 0 1 0 1 0 0 0 0.83125 0 1 0 1 0 0 1 0.83750 0 1 0 0 1 1 0 0.84375 0 1 0 0 1 1 1 0.85000 0 1 0 0 1 0 0 0.85625 0 1 0 0 1 0 1 0.86250 0 1 0 0 0 1 0 0.86875 0 1 0 0 0 1 1 0.87500 0 1 0 0 0 0 0 0.88125 0 1 0 0 0 0 1 0.88750 0 0 1 1 1 1 0 0.89375 0 0 1 1 1 1 1 0.90000 0 0 1 1 1 0 0 0.90625 0 0 1 1 1 0 1 0.91250 0 0 1 1 0 1 0 0.91875 0 0 1 1 0 1 1 0.92500 0 0 1 1 0 0 0 0.93125 0 0 1 1 0 0 1 0.93750 0 0 1 0 1 1 0 0.94375 0 0 1 0 1 1 1 0.95000 0 0 1 0 1 0 0 0.95625 0 0 1 0 1 0 1 0.96250 0 0 1 0 0 1 0 0.96875 0 0 1 0 0 1 1 0.97500 0 0 1 0 0 0 0 0.98125 0 0 1 0 0 0 1 0.98750 0 0 0 1 1 1 0 0.99375 0 0 0 1 1 1 1 1.00000 0 0 0 1 1 0 0 1.00625 0 0 0 1 1 0 1 1.01250 0 0 0 1 0 1 0 1.01875 0 0 0 1 0 1 1 1.02500 0 0 0 1 0 0 0 1.03125 0 0 0 1 0 0 1 1.03750 0 0 0 0 1 1 0 1.04375 0 0 0 0 1 1 1 1.05000 0 0 0 0 1 0 0 1.05625 0 0 0 0 1 0 1 1.06250 0 0 0 0 0 1 0 1.06875 0 0 0 0 0 1 1 1.07500 0 0 0 0 0 0 0 1.08125 0 0 0 0 0 0 1 1.08750
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 12 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller table 2. output voltage programming codes (8 bit) 0 = logic low; 1 = logic high. (msb: vid7, lsb: vid0; 11110001b = f1h) hex voltage tolerance hex voltage tolerance hex voltage tolerance hex voltage tolerance 0 0 off 4 0 1.21250 +-15mv ll (0 - 110a) 8 0 0.81250 monotonic c 0 0.4125 dont care 0 1 off 4 1 1.20625 +-15mv ll (0 - 110a) 8 1 0.80625 monotonic c 1 0.40625 dont care 0 2 1.60000 +-15mv ll (0 - 4 2 1.20000 +-15mv ll (0 - 110a) 8 2 0.8 monotonic c 2 0.40000 dont care 0 3 1.59375 +-15mv ll (0 - 4 3 1.19375 +-15mv ll (0 - 110a) 8 3 0.79375 monotonic c 3 0.39375 dont care 0 4 1.58750 +-15mv ll (0 - 4 4 1.18750 +-15mv ll (0 - 110a) 8 4 0.7875 monotonic c 4 0.38750 dont care 0 5 1.58125 +-15mv ll (0 - 4 5 1.18125 +-15mv ll (0 - 110a) 8 5 0.78125 monotonic c 5 0.38125 dont care 0 6 1.57500 +-15mv ll (0 - 4 6 1.17500 +-15mv ll (0 - 110a) 8 6 0.775 monotonic c 6 0.37500 dont care 0 7 1.56875 +-15mv ll (0 - 4 7 1.16875 +-15mv ll (0 - 110a) 8 7 0.76875 monotonic c 7 0.36875 dont care 0 8 1.56250 +-15mv ll (0 - 4 8 1.16250 +-15mv ll (0 - 110a) 8 8 0.7625 monotonic c 8 0.36250 dont care 0 9 1.55625 +-15mv ll (0 - 4 9 1.15625 +-15mv ll (0 - 110a) 8 9 0.75625 monotonic c 9 0.35625 dont care 0 a 1.55000 +-15mv ll (0 - 4 a 1.15000 +-15mv ll (0 - 110a) 8 a 0.75 monotonic c a 0.35000 dont care 0 b 1.54375 +-15mv ll (0 - 4 b 1.14375 +-15mv ll (0 - 110a) 8 b 0.74375 monotonic c b 0.34375 dont care 0 c 1.53750 +-15mv ll (0 - 4 c 1.13750 +-15mv ll (0 - 110a) 8 c 0.7375 monotonic c c 0.33750 dont care 0 d 1.53125 +-15mv ll (0 - 4 d 1.13125 +-15mv ll (0 - 110a) 8 d 0.73125 monotonic c d 0.33125 dont care 0 e 1.52500 +-15mv ll (0 - 4 e 1.12500 +-15mv ll (0 - 110a) 8 e 0.725 monotonic c e 0.32500 dont care 0 f 1.51875 +-15mv ll (0 - 4 f 1.11875 +-15mv ll (0 - 110a) 8 f 0.71875 monotonic c f 0.31875 dont care 1 0 1.51250 +-15mv ll (0 - 5 0 1.11250 +-15mv ll (0 - 110a) 9 0 0.7125 monotonic d 0 0.31250 dont care 1 1 1.50625 +-15mv ll (0 - 5 1 1.10625 +-15mv ll (0 - 110a) 9 1 0.70625 monotonic d 1 0.30625 dont care 1 2 1.50000 +-15mv ll (0 - 5 2 1.10000 +-15mv ll (0 - 110a) 9 2 0.7 monotonic d 2 0.30000 dont care 1 3 1.49375 +-15mv ll (0 - 5 3 1.09375 +-15mv ll (0 - 110a) 9 3 0.69375 monotonic d 3 0.29375 dont care 1 4 1.48750 +-15mv ll (0 - 5 4 1.08750 +-15mv ll (0 - 110a) 9 4 0.6875 monotonic d 4 0.28750 dont care 1 5 1.48125 +-15mv ll (0 - 5 5 1.08125 +-15mv ll (0 - 110a) 9 5 0.68125 monotonic d 5 0.28125 dont care 1 6 1.47500 +-15mv ll (0 - 5 6 1.07500 +-15mv ll (0 - 110a) 9 6 0.675 monotonic d 6 0.27500 dont care 1 7 1.46875 +-15mv ll (0 - 5 7 1.06875 +-15mv ll (0 - 110a) 9 7 0.66875 monotonic d 7 0.26875 dont care 1 8 1.46250 +-15mv ll (0 - 5 8 1.06250 +-15mv ll (0 - 110a) 9 8 0.6625 monotonic d 8 0.26250 dont care 1 9 1.45625 +-15mv ll (0 - 5 9 1.05625 +-15mv ll (0 - 110a) 9 9 0.65625 monotonic d 9 0.25625 dont care 1 a 1.45000 +-15mv ll (0 - 5 a 1.05000 +-15mv ll (0 - 110a) 9 a 0.65 monotonic d a 0.25000 dont care 1 b 1.44375 +-15mv ll (0 - 5 b 1.04375 +-15mv ll (0 - 110a) 9 b 0.64375 monotonic d b 0.24375 dont care 1 c 1.43750 +-15mv ll (0 - 5 c 1.03750 +-15mv ll (0 - 110a) 9 c 0.6375 monotonic d c 0.23750 dont care 1 d 1.43125 +-15mv ll (0 - 5 d 1.03125 +-15mv ll (0 - 110a) 9 d 0.63125 monotonic d d 0.23125 dont care 1 e 1.42500 +-15mv ll (0 - 5 e 1.02500 +-15mv ll (0 - 110a) 9 e 0.625 monotonic d e 0.22500 dont care 1 f 1.41875 +-15mv ll (0 - 5 f 1.01875 +-15mv ll (0 - 110a) 9 f 0.61875 monotonic d f 0.21875 dont care 2 0 1.41250 +-15mv ll (0 - 6 0 1.01250 +-15mv ll (0 - 110a) a 0 0.6125 monotonic e 0 0.21250 dont care 2 1 1.40625 +-15mv ll (0 - 6 1 1.00625 +-15mv ll (0 - 110a) a 1 0.60625 monotonic e 1 0.20625 dont care 2 2 1.40000 +-15mv ll (0 - 6 2 1.00000 monotonic dac (6.25 mv) a 2 0.6 monotonic e 2 0.20000 dont care 2 3 1.39375 +-15mv ll (0 - 6 3 0.99375 monotonic dac (6.25 mv) a 3 0.59375 monotonic e 3 0.19375 dont care 2 4 1.38750 +-15mv ll (0 - 6 4 0.98750 monotonic dac (6.25 mv) a 4 0.5875 monotonic e 4 0.18750 dont care 2 5 1.38125 +-15mv ll (0 - 6 5 0.98125 monotonic dac (6.25 mv) a 5 0.58125 monotonic e 5 0.18125 dont care 2 6 1.37500 +-15mv ll (0 - 6 6 0.97500 monotonic dac (6.25 mv) a 6 0.575 monotonic e 6 0.17500 dont care 2 7 1.36875 +-15mv ll (0 - 6 7 0.96875 monotonic dac (6.25 mv) a 7 0.56875 monotonic e 7 0.16875 dont care 2 8 1.36250 +-15mv ll (0 - 6 8 0.96250 monotonic dac (6.25 mv) a 8 0.5625 monotonic e 8 0.16250 dont care 2 9 1.35625 +-15mv ll (0 - 6 9 0.95625 monotonic dac (6.25 mv) a 9 0.55625 monotonic e 9 0.15625 dont care 2 a 1.35000 +-15mv ll (0 - 6 a 0.95000 monotonic dac (6.25 mv) a a 0.55 monotonic e a 0.15000 dont care 2 b 1.34375 +-15mv ll (0 - 6 b 0.94375 monotonic dac (6.25 mv) a b 0.54375 monotonic e b 0.14375 dont care 2 c 1.33750 +-15mv ll (0 - 6 c 0.93750 monotonic dac (6.25 mv) a c 0.5375 monotonic e c 0.13750 dont care 2 d 1.33125 +-15mv ll (0 - 6 d 0.93125 monotonic dac (6.25 mv) a d 0.53125 monotonic e d 0.13125 dont care 2 e 1.32500 +-15mv ll (0 - 6 e 0.92500 monotonic dac (6.25 mv) a e 0.525 monotonic e e 0.12500 dont care 2 f 1.31875 +-15mv ll (0 - 6 f 0.91875 monotonic dac (6.25 mv) a f 0.51875 monotonic e f 0.11875 dont care 3 0 1.31250 +-15mv ll (0 - 7 0 0.91250 monotonic dac (6.25 mv) b 0 0.5125 monotonic f 0 0.11250 dont care 3 1 1.30625 +-15mv ll (0 - 7 1 0.90625 monotonic dac (6.25 mv) b 1 0.50625 monotonic f 1 0.10625 dont care 3 2 1.30000 +-15mv ll (0 - 7 2 0.90000 monotonic dac (6.25 mv) b 2 0.5 monotonic f 2 0.10000 dont care 3 3 1.29375 +-15mv ll (0 - 7 3 0.89375 monotonic dac (6.25 mv) b 3 0.49375 dont care f 3 0.09375 dont care 3 4 1.28750 +-15mv ll (0 - 7 4 0.88750 monotonic dac (6.25 mv) b 4 0.4875 dont care f 4 0.08750 dont care 3 5 1.28125 +-15mv ll (0 - 7 5 0.88125 monotonic dac (6.25 mv) b 5 0.48125 dont care f 5 0.08125 dont care 3 6 1.27500 +-15mv ll (0 - 7 6 0.87500 monotonic dac (6.25 mv) b 6 0.475 dont care f 6 0.07500 dont care 3 7 1.26875 +-15mv ll (0 - 7 7 0.86875 monotonic dac (6.25 mv) b 7 0.46875 dont care f 7 0.06875 dont care 3 8 1.26250 +-15mv ll (0 - 7 8 0.86250 monotonic dac (6.25 mv) b 8 0.4625 dont care f 8 0.06250 dont care 3 9 1.25625 +-15mv ll (0 - 7 9 0.85625 monotonic dac (6.25 mv) b 9 0.45625 dont care f 9 0.05625 dont care 3 a 1.25000 +-15mv ll (0 - 7 a 0.85000 monotonic dac (6.25 mv) b a 0.45 dont care f a 0.05000 dont care 3 b 1.24375 +-15mv ll (0 - 7 b 0.84375 monotonic dac (6.25 mv) b b 0.44375 dont care f b 0.04375 dont care 3 c 1.23750 +-15mv ll (0 - 7 c 0.83750 monotonic dac (6.25 mv) b c 0.4375 dont care f c 0.03750 dont care 3 d 1.23125 +-15mv ll (0 - 7 d 0.83125 monotonic dac (6.25 mv) b d 0.43125 dont care f d 0.03125 dont care 3 e 1.22500 +-15mv ll (0 - 7 e 0.82500 monotonic dac (6.25 mv) b e 0.425 dont care f e off 3 f 1.21875 +-15mv ll (0 - 7 f 0.81875 monotonic dac (6.25 mv) b f 0.41875 dont care f f off
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 13 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller typical applications d5 mmsd4148 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 s1 dip20 c23 0.1uf c20 4.7uf r20 0 r24 680 r25 680 r9 10k r10 2.2 d1 mmsz4678 q1 bcw33 vin vtta sod-123 vid0 c27 1nf c25 0.1uf r22 1k r21 680 en_b r15 3k d7 green vin en c26 18nf c24 18nf ss delay comp r7 0 r8 0 gnd agnd notes : 1. optional parts are not populated unless otherwise specified. r19 30.1k r12 1.21k r11 0 r3 0 r13 optional r2 0 r5 optional r1 10 r6 optional r4 10 c21 470pf c22 33pf c19 optional vsns_b fbrtn vcore r39 182k r38 110k r40 200k r44 0 r49 10 r48 10 r47 10 r50 102k r55 102k r57 102k r53 60.4k r46 53.6k r43 0 rt 2 100k r45 0 c35 1500pf c33 1800pf c29 6.8nf ilimit vcc thermis tor 5% cscom p r52 optional r59 op tion al r56 10 c37 1uf/16v r27 680 r28 680 r30 680 r32 680 r34 680 r35 680 vid1 vid2 vid3 vid4 vid5 vid6 vid7 vcc vr odb1 csref pwrgd vin sw2 sw1 sw3 odb1 pwm 1 pwm 2 pwm 3 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vr_vssdie vr_vssse vr_vccse vr_vccdie vcore csrefa vr_ vssee vr_vccee r1a optional r2a optional r20 a optional vtt pwm1 pwm2 pwm3 c174 330nf r153 0 en 1 pwrgd 2 fbrtn 3 fb 4 comp 5 ss 6 delay 7 vcore 8 vrhot 9 ttsense 10 ilimit 11 rt 12 rampadj 13 llset 14 csref 15 cssum 16 cscom p 17 gnd 18 iout 19 odb1 20 vosadj 21 odb2 22 sw4 23 sw3 24 sw2 25 sw1 26 pwm4 27 pwm3 28 pwm2 29 pwm1 30 vcc 31 vid7 32 vid6 33 vid5 34 vid4 35 vid3 36 vid2 37 vid1 38 vid0 39 psi# 40 u10 fan50fc4 c175 1nf(x7r) psi# c145 18nf r138 0 rt 4 optional thermis tor 5 % ttsns vin r128 3k d16 red vrhot r154 0 r184 op tiona l iout imon r169 optional r173 0 odb2 odb2 pwm 4 pwm4 r51 10 sw4 r58 102k r68 optional r69 op tion al r137 optional r129 op tion al figure 7. typical three-phase design, controller note: contact a fairchild representative for the latest vr11 reference designs.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 14 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller typical applications (continued) vcore l1 0.6uf/27a d3 sod123 c2 4.7uf/16v c4 0.1uf c100 22uf/16v c101 22uf/16v c6 1000pf + c65 560uf + c67 560uf r29 2.2 r17 2.2 r36 10 pwm1 odb1 od 3 pgnd 6 pwm 2 vcc 4 boot 1 ldrv 5 sw 7 hdrv 8 9 u2 fan5109 csrefa sw1 c102 0.1uf tp_l1 vin vcore l2 300nh/30a d4 sod123 c13 4.7uf c14 0.1uf c15 1000pf + c75 560uf + c76 560uf r63 2.2 r54 2.2 r67 10 pwm2 odb2 od 3 pgnd 6 pwm 2 vcc 4 boot 1 ldrv 5 sw 7 hdrv 8 9 u3 fan5109 csrefa sw2 tp_l2 vcore l3 0.6uh/27a d2 sod123 c1 4.7uf/16v c3 0.1uf c5 1000pf + c64 560uf + c66 560uf r26 2.2 r16 2.2 r33 10 pwm3 odb2 od 3 pgnd 6 pwm 2 vcc 4 boot 1 ldrv 5 sw 7 hdrv 8 9 u4 fan5109 csrefa sw3 tp_l3 + c69 560uf + c77 560uf + c68 560uf + c70 560uf + c72 1200uf/16v + c73 1200uf/16v + c74 1200uf/16v +12v gnd q5 fdd8780 q3 fdd8796 q7 fdd8796 q9 fdd8780 q8 fdd8796 q10 fdd8796 q4 fdd8780 q2 fdd8796 q6 fdd8796 vin vin sw2 sw1 sw3 vin c103 22uf/16v c104 22uf/16v c105 0.1uf c16 22uf/16v c17 22uf/16v c18 0.1uf bottom side socket outside socket inside socket q5b fdd8780 q4b fdd8780 q9b fdd8780 com 1 com 2 com 3 com 4 +12v 8 +12v 7 +12v 6 +12v 5 j3 molex_8b 1 p3 vcore 1 p4 gnd vcore r70 10k r71 10k r72 10k r73 10k r74 10k r75 10k optional mmsd4148 mmsd4148 mmsd4148 optional c30 22uf/6.3v c31 22uf/6.3v c32 22uf/6.3v c34 22uf/6.3v c36 22uf/6.3v c39 22uf/6.3v c40 22uf/6.3v c41 22uf/6.3v c42 22uf/6.3v c43 22uf/6.3v c44 22uf/6.3v c45 22uf/6.3v c46 22uf/6.3v c47 22uf/6.3v c48 22uf/6.3v c49 22uf/6.3v c50 22uf/6.3v c51 22uf/6.3v c58 22uf/6.3v c59 22uf/6.3v c60 22uf/6.3v c61 22uf/6.3v c62 22uf/6.3v c63 22uf/6.3v c52 22uf/6.3v c53 22uf/6.3v c54 22uf/6.3v c56 22uf/6.3v c57 22uf/6.3v c38 22uf/6.3v c81 22uf/6.3v c82 22uf/6.3v c83 22uf/6.3v c84 22uf/6.3v c85 22uf/6.3v c86 22uf/6.3v vcore l4 0.6uf/27a d6 sod123 c7 4.7uf/16v c8 0.1uf c106 22uf/16v c107 22uf/16v c9 1000pf r42 2.2 r18 2.2 r37 10 pwm4 odb2 od 3 pgnd 6 pwm 2 vcc 4 boot 1 ldrv 5 sw 7 hdrv 8 9 u5 fan5109 csrefa sw4 c108 0.1uf tp_l4 q11 fdd8780 q12 fdd8796 q13 fdd8796 vin sw4 q11b fdd8780 r76 10k r77 10k mmsd4148 c87 22uf/6.3v c88 22uf/6.3v c89 22uf/6.3v c90 22uf/6.3v c91 22uf/6.3v c92 22uf/6.3v c93 22uf/6.3v c94 22uf/6.3v c95 22uf/6.3v c96 22uf/6.3v figure 8. typical three-phase design, drivers note: contact a fairchild representative for the latest vr11 reference designs.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 15 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller theory of operation note : the values shown in this section are for reference only. see the parametric tables for actual values. the FAN50FC3 is a fixed-frequency pwm control with multi-phase logic outputs fo r use in 2- and 3-phase synchronous buck cpu power supplies. it has an internal vid dac designed to interface directly with 8-bit vrd/vrm 11 and 7-bit vrd/ vrm 10.x compatible cpus. multiphase operation is required for the high currents and low voltages of today?s microprocessors that can require up to 150a of current. the integrated feat ures of the FAN50FC3 ensure a stable, high-performance topology for: ? balanced currents and thermals between phases ? high-speed response at the lowest possible switching frequency and output decoupling capacitors ? tight load line regulation and accuracy ? high current output by allowing up to 3-phase designs ? reduced output ripple due to multiphase operation ? good pc board layout noise immunity ? easily settable and adjus table design parameters with simple component selection ? 2- to 3-phase operation a llows optimizing designs for cost/performance and support a wide range of applications. start-up sequence the start-up sequence is show n in figure 9. once the en and uvlo conditions are met, the delay pin goes through one cycle (td1), after which, the internal oscillator starts. the first two clock cycles are used for phase detection. the soft-st art ramp is then enabled (td2), raising the output voltage up to the boot voltage of 1.1v. the boot hold time (td3) allows the processor vid pins to settle to the programmed vid code. after td3 timing is finished, the out put soft starts, either up or down, to the final vid volt age (during td4). td5 is the time between the output r eaching the vid voltage and the pwrgd being present ed to the system. phase-detection sequence during start-up, the number of operational phases and their phase relationship is determined by the internal circuitry that monitors t he pwm outputs. normally, the FAN50FC3 operates as a 3-phase pwm controller. for 2-phase operation, connect the pwm3 pin to v cc . the pwm logic, which is driv en by the master oscillator, directs the phase sequencer and channel detectors. channel detection is carried out during the first two clock cycles after the chip is enabled. during the detection period, pwm3 is connected to a 100a sinking current source and two internal vo ltage comparators check the pin voltage of pwm3 versus a threshold of 3v typical. if the pin is tied to v in , the pin voltage is above 3v and that phase is disabled and put in a tri-state mode. otherwise, the internal 100a current source pulls pwm pin below the 3v threshold. after channel detection, the current source is removed. shorting pwm3 to v cc configures the system into 2- phase operation. v ready 12v v in uvlo threshold v cc (core) td1 td3 td2 td4 td5 v core =v boot v core =vid vids invalid valid 50s v tt 0.85v 1.0v v boot =1.1v ss delay delay threshold figure 9. start-up sequence timing after detection time is complete, the pwm outputs not sensed as ?pulled high? function as normal pwm outputs. pwm outputs sensed as ?pulled high? are put into a high-impedance state. the pwm signals are logic-level outputs intended for driving external gate drivers, such as the fan5109. since each phase is monitored independently; operation approaching 100% duty cycle is possible. more than one output can be on at the same ti me to allow phase overlap. master clock frequency the clock frequency is set with an external resistor connected from the rt pin to ground. the frequency-to- resistor relationship is show n in the graph in figure 6. to determine the frequency per phase, divide the clock by the number of enabled phases. output current sensing the FAN50FC3 provides a dedicated current-sense amplifier (csa) to monitor t he output current for proper voltage positioning and for current limit detection (see figure 1) . it differentially senses the voltage drop across the dcr of the inductors to gi ve the total average current being delivered to the load. this method is inherently more accurate than peak current detection or sampling the voltage across the low-side mosfets. the csa implementation can be configured for the objectives of the system. it can use output inductor dcr sensing without a thermistor for lowest cost or output inductor dcr sensing with a thermistor for improved accuracy with tracking of inductor temperature.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 16 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller to measure the differentia l voltage across the output inductors, the positive input of the csa (csref pin) is connected, using equal value re sistors, to the output capacitor side of the inducto rs. the negative input of the csa (cssum pin) is connected, using equal value resistors, to the mosfet side of the inductors. the csa?s output (cscomp) is a voltage equal to the voltage dropped across the inductors, times the gain of the csa, and is inversely proportional to the output current. the gain of the csa is set by connecting an external feedback resistor between the csa?s cscomp and cssum pins. a capacitor, connected across the resistor, is used to create a low-pass filter to remove high frequency switching effects and create a rc pole to cancel the zero created by the l/dcr of the inductor. the end result is that t he voltage between the cscomp and csref pins is inversel y proportional to the output current (cscomp goes negative relative to csref as current increases) and the csa gain sets the ratio of the csa output voltage change as a function of output current change. this differenc e in voltage is used by the current limit comparator and by the droop amplifier to create the output load line. the csa is designed to have a low offset input voltage. the sensing gain is determined by external resistors, so it can be made extremely accurate. load line impedance control the FAN50FC3 has an internal ?droop amp? that effectively subtracts t he voltage applied between the cscomp and csref pins from the fb pin voltage of the error amplifier, allo wing the output voltage to be varied independent of the da c setting. a positive voltage on cscomp (relative to csref) increases the output voltage and a negative voltage decreases it. since the voltage between the csa?s cscomp and csref pins is inversely proportional to the output, current causes the output voltage to decrease an amount directly proportional to the increase in output current creating a droop or l oad line. the ratio of output voltage decrease to output current increase is the effective r o of the power supply and is set by the dc gain of the csa. current control mode & thermal balance the FAN50FC3 has individual sw inputs for each phase. they are used to measure the voltage drop across the bottom fets to determine the current in each phase. this information is combined with an internal ramp to create a current balancing feedback system. this gives good current balance accuracy that takes into account, not only the current, but also the thermal balance between the bottom fets in each phase. external resistors r sw1 through r sw3 can be placed in series with individual sw inputs to create an intentional current imbalance, such as in cases where one phase may have better cooling and can support higher currents. it is best to hav e the ability to add these resistors in the initial desi gn, to ensure that placeholders are provided in the layout. to increase the current in a phase, increase r sw for that phase. adding a resistor of a few hundred ohms can make a noticeable increase in current, so use small steps. the amplitude of the internal ramp is set by a resistor connected between the input voltage and the rampadj pin. this method also implements the voltage feedforward function. output voltage differential sensing the FAN50FC3 uses differential sensing in conjunction with a high-accuracy dac and a low-offset error amplifier to maintain a wo rst-case specification of 7.7mv differential sensing a ccuracy over its specified operating range. a high gain-bandwidth error amplifier is used for the voltage control loop. the voltage on the fb pin is compared to the dac volt age to control the output voltage. the fb voltage is also effectively offset by the csa output voltage for accura tely positioning the output voltage as a function of curr ent. the output of the error amplifier is the comp pin, which is compared to the internal pwm ramps to create the pwm pulse widths. the negative input (fb) is tied to the output sense location with a resistor r b and is used for sensing and controlling the output voltage at this point. additionally a current source is connected in ternally to the fb pin, which causes a fixed dc current to flow through r b . this current creates a fixed vo ltage drop (offset voltage) across r b . the offset voltage adds to the sensed output voltage, which causes the erro r amplifier to regulate the actual output voltage lowe r than the programmed vid voltage by this amount. the main loop compensation is incorporated into the feedba ck by an external network connected between fb and comp. delay timer the delay times for the start-up timing sequence are set with a capacitor from t he delay pin to ground, as stated in the start-up sequenc e section. in uvlo or when en is logic low, the delay pin is held at ground. once the uvlo and en are asserted, a 15a current flows out of the delay pin to charge c dly . a comparator, with a threshold of 1.7v, monitors the delay pin voltage. the delay time is therefore set by the 15a charging the delay c apacitor from 0v to 1.7v. this delay pin is used for multiple delay timings (td1, td3, and td5) during start-up. delay is also used for timing the current-limit latc h-off, as explained in the current limit section. soft-start the soft-start times for the output voltage are set with a capacitor from the ss pin to ground. after td1 and the phase-detection cycle are complete, the ss time (td2 in figure 9) starts. the ss pi n is disconnected from gnd and the capacitor is charged up to the 1.1v boot voltage by the ss amplifier, which has a limited output current of 15a. the voltage at the fb pin follows the ramping voltage on the ss pin, limiting the inrush current during start-up. the soft-start time depends on the value of the boot voltage and c ss .
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 17 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller once the ss voltage is wi thin 100mv of the boot voltage, the boot voltage delay time (td3) is started. the end of the boot voltage delay time signals the beginning of the second soft-start time (td4). the ss voltage changes from t he boot voltage to the programmed vid dac voltage (either higher or lower) using the ss amplifier with the limited output current of 15a. the voltage of the fb pin follows the ramping voltage of the ss pin, limiti ng the inrush current during the transition from the boot voltage to the final dac voltage. the second soft-st art time depends on the boot voltage, the programmed vid dac voltage, and c ss . if either en is taken low or v cc drops below uvlo, delay and ss are reset to ground to be ready for another soft-start cycle. figur e 10 shows typical start-up waveforms for the FAN50FC3. figure 10. start-up waveforms current-limit, short-circuit, and latch-off protections the FAN50FC3 compares a programmable current-limit set point to the voltage from the output of the current sense amplifier. the current- limit level is set with the resistor from the ilimit pi n to ground. during operation, the voltage on ilimit is 1. 7v. the current through the external resistor is internally scaled to give a current limit threshold of 10mv/a. if the voltage between csref and cscomp rises above the cu rrent-limit threshold, the internal current-limit amp lifier controls the internal comp voltage to maintain t he average output current at the limit. after td5 has completed, an over-current (oc) event starts a latch-off delay timer. the delay timer uses the delay pin timing capacitor. during current limit, the delay pin current is reduced to 3.75a. when the voltage on the delay pin reac hes 1.7v, the controller shuts down and latches off. the current limit latch-off delay time is therefore se t by the current of 3.75a charging the delay capacitor 1.7v. this delay is four times longer than the delay time during the start-up sequence. if there is a current limit during start-up, the FAN50FC3 goes through td1 to td5 in current limit, then starts the latch-off ti mer. because the controller continues to operate during t he latch-off delay time, if the oc is removed before the 1.7v threshold is reached, the controller returns to normal operation and the delay capacitor is reset to gnd. the latch-off function can be reset by cycling the supply voltage to the FAN50FC3 or by toggling the en pin low for a short time. to disable the short-circuit latch- off function, an external resi stor can be placed in parallel with c dly to prevent the delay capacitor from charging up to the 1.7v threshold. t he addition of this resistor causes a slight increase in the delay times. during start-up, when the output voltage is below 200mv, a secondary current limit is active. this secondary current limit clam ps the internal comp voltage at the pwm comparator s to 1.5v. typical over- current latch-off waveforms are shown in figure 11. figure 11. over-current latch-off waveforms fastvcore? operation fastvcore? improves the tr ansient response for a load step-up change. normally a contro ller has to wait till the next clock cycle if a load step-up happens during between pwm signals. with fastvcore?, the controller is able to immediately re spond to the load step change, so that the inductor current increases to the new load current in a shorter period of time. fastvcore? is adjusted by connecting a resistor (r setos ) between pin 16 (vosadj) and agnd to set the threshold where fastvc ore? is initiated. r setos = (v os +lltob) ? r t ? 10 eq. 1 where: r t = the frequency set resistor v os = the target fastvcore? detection threshold that is the voltage differ ence between the output voltage starting point and the voltage when the fastvcore? starts to respond to a load step- up change lltob= the socket load line tolerance band fastvcore? design example: if: r t = 267kohm v os = 35mv lltob = +/-19mv then: r setos = (v os +lltob) ? r t ? 10 = (35mv+19mv) ? 267kohm ? 10 = 144.2kohm v phase1 v od# v dela y vcore vcore v en v vrread y v dela y
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 18 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller dynamic vid the FAN50FC3 has the ab ility to dynamically change the vid inputs while the contro ller is running. this allows the output voltage to change wh ile the supply is running and supplying current to the load. this is commonly referred to as vid on-the-fly (otf). a vid otf can occur under light or heavy load conditions. the processor signals the cont roller by changing the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. when a vid input changes state, the FAN50FC3 detects the change and ignores the dac inputs for a minimum of 200ns. this time prevents a false code due to logic skew while the ei ght vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 100s to prevent a false pwrgd or crowbar event. each vid change resets the internal timer. power good monitoring the power good comparator m onitors the output voltage via the csref pin. the pwrgd pin is an open-drain output whose high level (w hen connected to a pull-up resistor) indicates that the output voltage is within the nominal limits specifi ed based on the vid voltage setting. pwrgd goes low if the output voltage is outside of this specified range, if the vid dac inputs are in no cpu mode, or whenever the en pin is pulled low. pwrgd is blanked during a vid otf event for a period of ~200s to prevent false signals during the time the output is changing. the pwrgd circuitry also inco rporates an initial turn-on delay time (td5) based on the delay timer. prior to the ss voltage reaching the progr ammed vid dac voltage, 100mv, the pwrgd pin is held low. once the ss pin is within 100mv of the progr ammed dac voltage, the capacitor on the delay pi n begins to charge up. a comparator monitors t he delay voltage and enables pwrgd when the voltage r eaches 1.7v. the pwrgd delay time is therefore set by a current of 15a charging a capacitor from 0v to 1.7v. output crowbar as part of the protecti on for the load and output components of the supply, the pwm outputs are driven low (turning on the low-side mosfets) when the output voltage exceeds the upper cr owbar threshold. this crowbar action stops once t he output voltage falls below the release threshold of approximately 300mv. turning on the low-side mosf ets pulls down the output as the reverse current builds up in the inductors. if the output over-voltage is due to a short in the high-side mosfet, this action current -limits the input supply, protecting the microprocessor. output enable and uvlo for the FAN50FC3 to begin sw itching, the input supply (v cc ) to the controller must be higher than the uvlo threshold and the en pin mu st be higher than its 0.85v threshold. this initiates a system start-up sequence. if either uvlo or en is less than their respective thresholds, the FAN50FC3 is disabled; which holds the pwm outputs low, discharges the delay and ss capacitors, and forces pwrgd and od# signals low. in the application circuit, the od# pin should be connected to the od# i nputs of the fan5009 or fan5109 drivers. pulling od# low disables the drivers such that both drvh and drv l are driven low. this turns off the bottom mosfets to prevent them from discharging the output capac itors through the output inductors. if the bottom mosfets were left on, the output capacitors could ring with the output inductors and produce a negative output vo ltage to the processor. ntc resistance versus temperature normalized to 25c 0.0 0.2 0.4 0.6 0.8 1.0 25 50 75 100 125 temperature (c) resistance (25c = 1) figure 12. typical ntc resistance vs. temperature applications and component selection please consult fairchild application note: an-6052 ? instructions for the multi-phase vr11 mathcad ? design tool
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 19 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. general recommendations for good results, a pcb with at least four layers is recommended. this should allow the needed versatility for control circuitry interconnections with optimal placement, power planes fo r ground, input and output power, and wide interconnection traces in the remainder of the power delivery current paths. keep in mind that each square unit of one-ounc e copper trace has a resistance of ~0.53m ? at room temperature. whenever high currents mu st be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by t hese current paths is minimized and the via current rating is not exceeded. if critical signal lines (inc luding the output voltage sense lines of the FAN50FC3) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. this serves as a shield to minimize noise injection into the si gnals at the expense of making signal ground a bit noisier. an analog ground plane should be around and under the FAN50FC3 as a reference for the components associated with the controlle r. this plane should be tied to the nearest output dec oupling capacitor ground and should not be tied to any other power circuitry to prevent power currents from flowing in it. the components around the FAN50FC3 should be located close to the controller with short traces. the most important traces to keep short and away from other traces are the fb and cssum pins. the output capacitors should be connected as close as possible to the load (or connector); for example, a microprocessor core that receives the power . if the load is distributed, the capacitors should be di stributed and generally be in proportion to where the load tends to be more dynamic. avoid crossing any signal lines over the switching power path loop described in the following section. power circuitry recommendations the switching power path should be routed on the pcb to encompass the shortest possible length to minimize radiated switching noise energy (i.e., emi) and conduction losses in the board. failure to take proper precautions can result in em i problems for the entire pc system as well as noise-rela ted operational problems in the power converter control circuitry. the switching power path is the loop fo rmed by the current path through the input capacitor s and the power mosfets, including all interconnecting pcb traces and planes. using short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it acco mmodates the high-current demand with minimal voltage loss. whenever a power dissipating component, for example, a power mosfet, is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are improved current rating through the vias and impr oved thermal performance from vias extended to the opposite side of the pcb, where a plane can more readily transfer the heat to t he air. make a mirror image of any pad being used to heatsink the mosfets on t he opposite side of the pcb to achieve the best thermal dissipation to the air around the board. to further improv e thermal performance, use the largest possible pad area. the output power path s hould also be routed to encompass a short distance. the output power path is formed by the current path through the inductor, the output capacitors, and the load. for best emi containment, a solid power ground plane should be used as one of t he inner layers, extending fully under all the power components. signal circuitry recommendations the output voltage is sens ed and regulated between the fb pin and the fbrtn pin, which connect to the signal ground at the load. to avoi d differential mode noise pickup in the sensed signal, the loop area should be small. thus, the fb and fb rtn traces should be routed adjacent to each other on t op of the power ground plane back to the controller. the feedback traces from the switch nodes should be connected as close as possi ble to the inductor. the csref signal should be c onnected to the output voltage at the nearest inducto r to the controller.
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 20 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller physical dimensions dimensions are in millimeters (i nches) unless otherwise noted. figure 13. 32-pin, molded leadless p ackage (mlp), jedec mo-220, 5mm square
? 2007 fairchild semiconductor corporation www.fairchildsemi.com FAN50FC3 rev. 1.0.0 21 of 21 FAN50FC3 ? 8-bit programmable, 2- to 3-phase fastvcore? buck controller

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