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document. no. e1922e11 (ver. 1.1) date published september 2012 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2012 preliminary data sheet cover specifications ? density: 4g bits ? organization ? 128m words 4 bits 8 banks (edj4204efbg) ? 64m words 8 bits 8 banks (edj4208efbg) ? 32m words 16 bits 8 banks (edj4216efbg) ? package ? 78-ball fbga (edj4204efbg, edj4208efbg) ? 96-ball fbga (edj4216efbg) ? lead-free (rohs compliant) and halogen-free ? power supply: 1.35v (typ) ? vdd = 1.283v to 1.45v ? backward compatib le for vdd, vddq = 1.5v 0.075v ? data rate ? 1600mbps/1333mbps (max) ? 1kb page size ? row address: a0 to a15 ? column address: a0 to a9, a11 (edj4204efbg) a0 to a9 (edj4208efbg) ? 2kb page size (edj4216efbg) ? row address: a0 to a14 ? column address: a0 to a9 ? eight internal banks for concurrent operation ? burst length (bl): 8 and 4 with burst chop (bc) ? burst type (bt): ? sequential (8, 4 with bc) ? interleave (8, 4 with bc) ? /cas latency (cl): 5, 6, 7, 8, 9, 10, 11 ? /cas write latency (cwl): 5, 6, 7, 8 ? precharge: auto precharge option for each burst access ? driver strength: rzq/7, rzq/6 (rzq = 240 ? ) ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc +85 c 3.9 s at +85 c < tc +95 c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architec ture: two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned wit h data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for pre-defined pattern read out ? zq calibration for dq drive and odt ? programmable partial array self-refresh (pasr) ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? programmable output driver impedance control 4g bits ddr3l sdram edj4204efbg (1024m words 4 bits) edj4208efbg (512m words 8 bits) edj4216efbg (256m words 16 bits)
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 2 ordering information note: 1. please refer to the edj4204bfbg, edj4208bfbg, edj 4216bfbg datasheet (e1923e) when using this device at 1.5v operation, unless stated otherwise. part number detailed information for detailed electrical specification and further information, please refer to the ddr3l sdram general functionality and electrical condition data sheet (e1927e). part number die revision organization (words bits) internal banks jedec speed bin (cl-trcd-trp) package edj4204efbg-gn-f edj4204efbg-dj-f f 1024m 48 ddr3l-1600k (11-11-11) ddr3l-1333h (9-9-9) 78-ball fbga edj4208efbg-gn-f edj4208efbg-dj-f f 512m 88 ddr3l-1600k (11-11-11) ddr3l-1333h (9-9-9) 78-ball fbga EDJ4216EFBG-GN-F edj4216efbg-dj-f f 256m 16 8 ddr3l-1600k (11-11-11) ddr3l-1333h (9-9-9) 96-ball fbga elpida memory density / bank 42: 4gb / 8-bank organization 04: x4 08: x8 16: x16 power supply e: 1.35v revision package bg: fbga speed gn: ddr3l-1600k (11-11-11) dj: ddr3l-1333h (9-9-9) product family j: ddr3 type d: packaged device e d j 42 04 e f bg - gn - f environment code f: lead free (rohs compliant) and halogen free
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 3 pin configurations pin configurations ( 4/ 8 configuration) /xxx indicates active low signal. notes: 1. not internally connected with die. 2. don't connect. internally connected. 3. input only pins (address, command, cke, odt and /reset) do not supply termination. pin name function pin name function a0 to a15* 3 address inputs a10(ap): auto precharge a12(/bc): burst chop /reset* 3 active low asynchronous reset ba0 to ba2* 3 bank select vdd supply voltage for internal circuit dq0 to dq7 data input/output vss ground for internal circuit dqs, /dqs differential data strobe vddq supply voltage for dq circuit tdqs, /tdqs termination data strobe vssq ground for dq circuit /cs* 3 chip select vrefdq reference voltage for dq /ras, /cas, /we* 3 command input vrefca reference voltage for ca cke* 3 clock enable zq reference pin for zq calibration ck, /ck differential clock input nc* 1 no connection dm write data mask nu* 2 not usable odt* 3 odt control vss vdd 1 vddq vss vss 2 vssq dq0 vss dq2 nc vssq vddq vrefdq vss vdd /cs ba0 a7 /reset nc a15 vdd 3 nc dqs /dqs nc /ras /cas /we ba2 a9 a13 7 nc dm dq1 vdd nc ck /ck a10(ap) nc a11 a14 8 vss vssq vddq vssq dq3 vss nc vss vdd zq vrefca a6 a8 cke vss vss 9 vdd vssq vddq nc vdd (top view) 78-ball fbga (4 configuration) odt nc a b c d e f g h j a3 vdd a0 a12(/bc) ba1 vdd a5 vss a2 a1 a4 vss k l m n vss vdd 1 vddq vss vss 2 vssq dq0 vss dq2 dq6 vssq vddq vrefdq vss vdd /cs ba0 a7 /reset nc a15 vdd 3 nc dqs /dqs dq4 /ras /cas /we ba2 a9 a13 7 nu/(/tdqs) dm/tdqs dq1 vdd dq7 ck /ck a10(ap) nc a11 a14 8 vss vssq vddq vssq dq3 vss dq5 vss vdd zq vrefca a6 a8 cke vss vss 9 vdd vssq vddq nc vdd (top view) 78-ball fbga (8 configuration) odt nc a b c d e f g h j a3 vdd a0 a12(/bc) ba1 vdd a5 vss a2 a1 a4 vss k l m n
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 4 pin configurations ( 16 configuration) /xxx indicates active low signal. notes: 1. not internally connected with die. 2. input only pins (address, command, cke, odt and /reset) do not supply termination. pin name function pin name function a0 to a14* 2 address inputs a10(ap): auto precharge a12(/bc): burst chop /reset* 2 active low asynchronous reset ba0 to ba2* 2 bank select vdd supply voltage for internal circuit dqu0 to dqu7 dql0 to dql7 data input/output vss ground for internal circuit dqsu, /dqsu dqsl, /dqsl differential data strobe vddq supply voltage for dq circuit /cs* 2 chip select vssq ground for dq circuit /ras, /cas, /we* 2 command input vrefdq reference voltage for dq cke* 2 clock enable vrefca reference voltage for ca ck, /ck differential clock input zq re ference pin for zq calibration dmu, dml write data mask nc* 1 no connection odt* 2 odt control a b c d e f g h j k l vddq 1 vddq vss nc 2 vdd vss vssq dqu3 vddq vssq vssq vss 3 dqu7 dqu5 dqu1 dmu dql0 vdd /cas /ras 7 dqu4 /dqsu dqsu dqu0 dml /ck 8 vddq dqu6 vssq dqu2 vssq vdd vssq vdd m n p t vss /reset a13 a14 nc a8 9 vss vddq vddq dql2 dql6 vssq vddq vrefdq dqsl /dqsl dql4 dql1 vdd dql3 vss vssq dql7 dql5 vddq vssq vddq ck vss nc vdd ba0 a3 a5 ba2 a0 a2 a12(/bc) a1 vrefca ba1 a4 vss vss (top view) 96-ball fbga /cs /we odt vss vss r a7 a9 a11 a6 vdd vdd a10(ap) vss vdd nc zq nc cke
edj4204efbg, edj42 08efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 5 contents specifications ................................................................................................................ ........................ 1 features ...................................................................................................................... .......................... 1 ordering information .......................................................................................................... ................... 2 part number ................................................................................................................... ....................... 2 detailed information .......................................................................................................... .................... 2 pin configurations ............................................................................................................ ..................... 3 1. electrical conditions ................................. ...................................................................... ............... 6 1.1 absolute maximum ratings ................................................................................................... ...........6 1.2 operating temperature condition ............................................................................................ ........6 1.3 recommended dc operating conditions ............... .............. .............. ........... ............ ........... ........... 7 1.4 idd and iddq measurement conditions ........................................................................................ ..8 2. electrical specifications ................................................................................................... ............ 19 2.1 dc characteristics ......................................................................................................... ................. 19 2.2 pin capacitance ............................................................................................................ .................. 20 2.3 standard speed bins .............. .............. .............. .............. .............. .............. ........... ......... .............. 21 3. package drawing .................. ........................................................................................... ............ 25 3.1 78-ball fbga ............................................................................................................... ................... 25 3.2 96-ball fbga ............................................................................................................... ................... 26 4. recommended soldering conditions .......................................................................................... 27
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 6 1. electrical conditions ? all voltages are referenced to vss (gnd) ? execute power-up and initialization sequence before proper device operation is achieved. 1.1 absolute maximum ratings notes: 1. stresses greater than those listed under absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any ot her conditions above those indicated in the operational sections of this specificat ion is not implied. exposure to absol ute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. 3. vdd and vddq must be within 300mv of each other at all times; and vref must be no greater than 0.6 vddq, when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. caution: exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this sp ecification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 1.2 operating temperature condition notes: 1. operating temperature is the case surfac e temperature on the center/top side of the dram. 2. the normal temperature range specifies the temperatures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 c to +85 c under all operating conditions. 3. some applications require operation of the dram in the extended temperature range between +85 c and +95 c case temperature. full specifications ar e guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, theref ore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for some devices.) b) if self-refresh operation is required in the extended temper ature range, then it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 bit [a6, a7] = [0, 1]) or enable the optional auto self-refresh mode (mr2 bit [a6, a7] = [1, 0]). table 1: absolute maximum ratings parameter symbol rating unit notes power supply voltage vdd ? 0.4 to +1.975 v 1, 3 power supply voltage for output vddq ? 0.4 to +1.975 v 1, 3 input voltage vin ? 0.4 to +1.975 v 1 output voltage vout ? 0.4 to +1.975 v 1 reference voltage vrefca ? 0.4 to 0.6 vdd v 3 reference voltage for dq vrefdq ? 0.4 to 0.6 vddq v 3 storage temperature tstg ? 55 to +100 c1, 2 power dissipation pd 1.0 w 1 short circuit output current iout 50 ma 1 table 2: operating temperature condition parameter symbol rating unit notes operating case temperature tc 0 to +95 c 1, 2, 3
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 7 1.3 recommended dc operating conditions notes: 1. maximum dc value may not be greater than 1.425v. the dc value is the linear average of vdd/vddq(t) over a very long period of time (e.g. 1 sec). 2. if maximum limit is exceeded, input levels shall be governed by ddr3 specifications. 3. under these supply voltages, the devic e operates to this ddr3l specifcation. 4. once initialized for ddr3l operation, ddr3 operation may only be used if the device is in reset while 5. vdd and vddq are changed for ddr3 operation shown as following timing wave form. notes: 1. if minimum limit is exceeded, input leve ls shall be governed by ddr3l specifications. 2. under 1.5v operation, this ddr3l device operates to th e ddr3 specifcations under the same speedtimings as defined for this device. 3. once initialized for ddr3 operation, ddr3l operation may only be used if the device is in reset while vdd and vddq are changed for ddr3l operation shown as below. table 3: recommended dc operating conditions (tc = 0 c to +85 c), ddr3l operation parameter symbol min. typ. max. unit notes supply voltage vdd 1.283 1.35 1.45 v 1, 2, 3, 4 supply voltage for dq vddq 1.283 1.35 1.45 v 1, 2, 3, 4 table 4: recommended dc operating conditions (tc = 0 c to +85 c), ddr3 operation parameter symbol min typ max unit notes supply voltage vdd 1.425 1.5 1.575 v 1, 2, 3 supply voltage for dq vddq 1.425 1.5 1.575 v 1, 2, 3 figure 1: vdd/vddq vo ltage switch between ddr3l and ddr3 t(min) = 10ns t(min) = 200 s t(min) = 10ns t = 500 s tis note: 1. from time point td until tk, nop or des commands must be applied between mrs and zqcl commands. : vih or vil ck, /ck vdd, vddq (ddr3) vdd, vddq (ddr3l) /reset cke command ba odt rtt txpr tmrd tmrd tmrd tmod tcksrx tis tis tis ta tb tc td te tf tg th ti tj tk t(min) = 10ns tdllk tzqinit *1 *1 valid valid valid valid mrs static low in case rtt_nore is enabled at time tg, otherwise static high or low mrs mrs mrs zqcl mr2 mr3 mr1 mr0
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 8 1.4 idd and iddq measurement conditions in this chapter, idd and iddq me asurement conditions such as te st load and patterns are defined. the figure measurement setup and test load for idd and iddq measurements shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt, i dd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) are measured as time-averaged currents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are meas ured as time-averaged currents with all vddq balls of the ddr3 sdram under test tied together. any i dd current is not included in iddq currents. note:iddq values cannot be directly us ed to calculate i/o power of the ddr3 sdram. they can be used to support correlation of simulated i/o power to actual i/o power as outlined in correlation from simulated channel i/o power to actual channel i/o power supported by iddq measurement. for idd and iddq measurements, the following definitions apply: ? l and 0: vin vil(ac)max ? h and 1: vin vih(ac)min ? mid-level: defined as inpu ts are vref = vddq / 2 ? floating: don't care or floating around vref. ? timings used for idd and iddq measurement-loop patt erns are provided in timings used for idd and iddq measurement-loop patterns table. ? basic idd and iddq measurement conditions are descr ibed in basic idd and iddq measurement conditions table. note:the idd and iddq measurement-loop pat terns need to be executed at least one time before actual idd or iddq measurement is started. ? detailed idd and iddq measurement-loop patterns are described in idd0 meas urement-loop pattern table through idd7 measurement-loop pattern table. ? idd measurements are done after properly initializing the ddr3 sdram. this includes but is not limited to setting. ron = rzq/7 (34 ? in mr1); qoff = 0b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ? in mr1); rtt_wr = rzq/2 (120 ? in mr2); tdqs feature disabled in mr1 ? define d = {/cs, /ras, /cas, /we} : = {h, l, l, l} ? define /d = {/cs, /ras, /cas, /we} : = {h, h, h, h}
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 9 figure 2: measurement setup and test load for idd and iddq measurements figure 3: correlation from simulated channe l i/o power to actual channel i/o power supported by iddq measurement idd iddq vddq/2 ddr3 sdram vdd vddq vss vssq cke /cs /ras, /cas, /we address, ba odt zq rtt = 25 ? /reset ck, /ck dqs, /dqs, dq, dm, tdqs, /tdqs application specific memory channel environment channel i/o power simulation channel i/o power number correction correlation iddq measurement iddq simulation iddq test load
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 10 1.4.1 timings used for idd and iddq measurement-loop patterns table 5: timings used for idd and iddq measurement-loop patterns ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 parameter 6-6-6 7-7-7 9-9-9 11-11-11 unit cl 67911nck tck(min) 2.5 1.875 1.5 1.25 ns nrcd(min) 67911nck nrc(min) 21 27 33 39 nck nras(min) 15 20 24 28 nck nrp(min)67911nck nfaw (1kb) 16 20 20 24 nck nfaw (2kb, 4kb) 20 27 30 32 nck nrrd (1kb) 4445nck nrrd (2kb, 4kb) 4656nck nrfc (1gb)44597488nck nrfc (2gb) 64 86 107 128 nck nrfc (4gb) 104 139 174 208 nck
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 11 1.4.2 basic idd and iddq measurement conditions table 6: basic idd and iddq measurement conditions parameter symbol description operating one bank active precharge current idd0 cke: h; external clock: on; tck, nrc, nras, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: h between act and pre; command, address, bank address inputs: partially toggling according to table 7 ; data i/o: mid-level; dm: stable at 0; bank activity: cycling wi th one bank active at a time: 0,0,1,1,2,2,... (see table 7 ); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 7 operating one bank active-read-precharge current idd1 cke: h; external clock: on; tck, nrc, nras, nrcd, cl: see table 5 ; bl: 8* 1 , * 6 ; al: 0; /cs: h between act, rd and pre; command, address, bank address inputs, data i/o: partially toggling according to table 8 ; dm: stable at 0; bank activity: cycling wi th one bank active at a time: 0,0,1,1,2,2,... (see table 8 ); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 8 precharge standby current idd2n cke: h; external clock: on; tck, cl: see table 5 bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to table 9 ; data i/o: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers* 2 ; odt signal: stable at 0; pattern details: see table 9 precharge standby odt current idd2nt cke: h; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to table 10 ; data i/o: mid-level; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mr* 2 ; odt signal: toggling according to table 10 ; pattern details: see table 10 precharge standby odt iddq current iddq2nt same definition like for idd2nt, however measuring iddq current instead of idd current precharge power-down current slow exit idd2p0 cke: l; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: st able at 0; data i/o: mid-level; dm: stable at 0; bank activity: all bank s closed; output buffer and rtt: emr* 2 ; odt signal: stable at 0; precharge power down mode: slow exit* 3 precharge power-down current fast exit idd2p1 cke: l; external clock: on; tck, cl: see table 6 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: mid-level; dm:stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; precharge power down mode: fast exit* 3 precharge quiet standby current idd2q cke: h; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: mid-level; dm: stable at 0;bank activity: all banks cl osed; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0 active standby current idd3n cke: h; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to table 9 ; data i/o: mid-level; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 9 active power-down current idd3p cke: l; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: mid-level; dm:stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0 operating burst read current idd4r cke: h; external clock: on; tck, cl: see table 5 ; bl: 8* 1 , * 6 ; al: 0; /cs: h between rd; command, address, bank address inputs: partially toggling according to table 11 ; data i/o: seamless read data burst with different data between one burst and the next one according to table 11 ; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... (see table 11 ); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 11 operating burst read iddq current iddq4r same definition like for idd4r, however measuring iddq current instead of idd current
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 12 notes: 1. burst length: bl8 fixed by mrs: mr0 bits [1,0] = [0,0]. 2. mr: mode register output buffer enable: set mr1 bit a12 = 1 and mr1 bits [5, 1] = [0,1]; rtt_nom enable: set mr1 bits [9, 6, 2] = [0, 1, 1]; rtt_wr enable: set mr2 bits [10, 9] = [1,0]. 3. precharge power down mode: set mr0 bit a12= 0 for slow exit or mr0 bit a12 = 1 for fast exit. 4. auto self-refresh (asr): set mr2 bit a6 = 0 to disable or 1 to enable feature. 5. self-refresh temperature range (srt): set mr0 bit a7= 0 for normal or 1 for extended temperature range. 6. read burst type: nibble sequential, set mr0 bit a3 = 0 operating burst write current idd4w cke: h; external clock: on; tck, cl: see table 5 ; bl: 8* 1 ; al: 0; /cs: h between wr; command, address, bank address inputs: partially toggling according to table 12 ; data i/o: seamless write data burst with different data between one burst and the next one according to idd4w measurement-loop pattern table; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,.. (see table 12 ); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at h; pattern details: see table 12 burst refresh current idd5b cke: h; external clock: on; tck, cl, nrfc: see table 5 ; bl: 8* 1 ; al: 0; /cs: h between ref; command, address, bank address inputs: partially toggling according to table 13 ; data i/o: mid-level; dm: stable at 0; bank activity: ref command every nrfc ( table 13 ); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 13 self-refresh current: normal temperature range idd6 tc: 0 to 85 c; asr: disabled* 4 ; srt: normal* 5 ; cke: l; external clock: off; ck and /ck: l; cl: see table 5 ; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: mid-level; dm: stable at 0; bank activity: self-refresh opera tion; output buffer and rtt: enabled in mr* 2 ; odt signal: mid-level self-refresh current: extended temperature range idd6et tc: 0 to 95 c; asr: disabled* 4 ; srt: extended* 5 ; cke: l; external clock: off; ck and /ck: l; cl: table 5 ; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: mid-level; dm: stable at 0; bank activity: extended te mperature self-refresh operation; output buffer and rtt: enabled in mr* 2 ; odt signal: mid-level auto self-refresh current (optional) idd6tc tc: 0 to 95 c; asr: enabled* 4 ; srt: normal* 5 ; cke: l; external clock: off; ck and /ck: l; cl: table 5 ; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: mid-level; dm: stable at 0; bank activity: auto self-refresh operation; output buffer and rtt: enabled in mr* 2 ; odt signal: mid-level operating bank interleave read current idd7 cke: h; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 5 ; bl: 8* 1 , * 6 ; al: cl-1; /cs: h between act and rda; command, address, bank address inputs: partially toggling according to table 14 ; data i/o: read data bursts with different data between one burst and the next one according to table 14 ; dm: stable at 0; bank activity: two times inte rleaved cycling through banks (0, 1, ?7) with different addressing, see table 14 ; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see table 14 reset low current idd8 /reset: low; external clock: off; ck and /ck: low; cke: floating; /cs, command, address, bank address, data io: floating; odt signal: floating reset low current reading is valid on ce power is stable and /reset has been low for at least 1ms. table 6: basic idd and iddq measurement conditions (cont?d) parameter symbol description
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 13 notes: 1. dm must be driven low all the time. dqs, /dqs are mid-level. 2. dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 7: idd0 measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 act00110000000 1, 2 d, d10000000000 3, 4 /d, /d11110000000 ? repeat pattern 1?4 until nras ? 1, truncate if necessary nraspre00100000000 ? repeat pattern 1...4 until nrc ? 1, truncate if necessary 1 nrc + 0 act001100000f0 1 nrc +1, 2 d, d100000000f0 1 nrc + 3, 4 /d, /d111100000f0 ? repeat pattern nrc + 1,...,4 until 1 nrc + nras ? 1, truncate if necessary 1 nrc + nras pre001000000f0 ? repeat nrc + 1,...,4 until 2 nrc ? 1, truncate if necessary 12 nrc repeat sub-loop 0, use ba= 1 instead 24 nrc repeat sub-loop 0, use ba= 2 instead 36 nrc repeat sub-loop 0, use ba= 3 instead 48 nrc repeat sub-loop 0, use ba= 4 instead 5 10 nrc repeat sub-loop 0, use ba= 5 instead 6 12 nrc repeat sub-loop 0, use ba= 6 instead 7 14 nrc repeat sub-loop 0, use ba= 7 instead
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 14 notes: 1. dm must be driven low all the time. dqs, /dqs are used according to read commands, otherwise mid-level. 2. burst sequence driven on each dq signal by read command. outside burst ope ration, dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 8: idd1 measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 act00110000000 ? 1, 2 d, d10000000000 ? 3, 4 /d, /d11110000000 ? ? repeat pattern 1...4 until nrcd ? 1, truncate if necessary nrcdrd01010000000 00000000 ? repeat pattern 1...4 until nras ? 1, truncate if necessary nraspre00100000000 ? ? repeat pattern 1...4 until nrc ? 1, truncate if necessary 1 nrc + 0 act001100000f0 ? 1 nrc + 1, 2 d, d100000000f0 ? 1 nrc + 3, 4 /d, /d111100000f0 ? ? repeat pattern nrc + 1,..., 4 until nrc + nrcd ? 1, truncate if necessary 1 nrc + nrcd rd010100000f0 00110011 ? repeat pattern nrc + 1,..., 4 until nrc +nras ? 1, truncate if necessary 1 nrc + nras pre001000000f0 ? ? repeat pattern nrc + 1,..., 4 until 2 nrc ? 1, truncate if necessary 12 nrc repeat sub-loop 0, use ba= 1 instead 24 nrc repeat sub-loop 0, use ba= 2 instead 36 nrc repeat sub-loop 0, use ba= 3 instead 48 nrc repeat sub-loop 0, use ba= 4 instead 5 10 nrc repeat sub-loop 0, use ba= 5 instead 6 12 nrc repeat sub-loop 0, use ba= 6 instead 7 14 nrc repeat sub-loop 0, use ba= 7 instead
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 15 notes: 1. dm must be driven low all the time. dqs, /dqs are mid-level. 2. dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. notes: 1. dm must be driven low all the time. dqs, /dqs are mid-level. 2. dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 9: idd2n and idd3n measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 d 10000000000 1 d 10000000000 2 /d111100000f0 3 /d111100000f0 1 4 to 7 repeat sub-loop 0, use ba= 1 instead 2 8 to 11 repeat sub-loop 0, use ba= 2 instead 3 12 to 15 repeat sub-loop 0, use ba= 3 instead 4 16 to 19 repeat sub-loop 0, use ba= 4 instead 5 20 to 23 repeat sub-loop 0, use ba= 5 instead 6 24 to 27 repeat sub-loop 0, use ba= 6 instead 7 28 to 31 repeat sub-loop 0, use ba= 7 instead table 10: idd2nt and iddq2nt measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 d 10000000000 1 d 10000000000 2 /d111100000f0 3 /d111100000f0 1 4 to 7 repeat sub-loop 0, but odt = 0 and ba= 1 2 8 to 11 repeat sub-loop 0, but odt = 1 and ba= 2 3 12 to 15 repeat sub-loop 0, but odt = 1 and ba= 3 4 16 to 19 repeat sub-loop 0, but odt = 0 and ba= 4 5 20 to 23 repeat sub-loop 0, but odt = 0 and ba= 5 6 24 to 27 repeat sub-loop 0, but odt = 1 and ba= 6 7 28 to 31 repeat sub-loop 0, but odt = 1 and ba= 7
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 16 notes: 1. dm must be driven low all the time. dqs, /dqs are used according to read commands, otherwise mid-level. 2. burst sequence driven on each dq signal by read command. outside burst ope ration, dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 11: idd4r and iddq4r measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 rd01010000000 00000000 1 d 10000000000 ? 2,3 /d, /d11110000000 ? 4 rd010100000f0 00110011 5 d 100000000f0 ? 6,7 /d, /d111100000f0 ? 1 8 to 15 repeat sub-loop 0, but ba= 1 2 16 to 23 repeat sub-loop 0, but ba= 2 3 24 to 31 repeat sub-loop 0, but ba= 3 4 32 to 39 repeat sub-loop 0, but ba= 4 5 40 to 47 repeat sub-loop 0, but ba= 5 6 48 to 55 repeat sub-loop 0, but ba= 6 7 56 to 63 repeat sub-loop 0, but ba= 7
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 17 notes: 1. dm must be driven low all the time. dqs, /dqs are used according to write commands, otherwise mid-level. 2. burst sequence driven on each dq signal by write command. outside burst operation, dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. notes: 1. dm must be driven low all the time. dqs, /dqs are mid-level. 2. dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 12: idd4w measu rement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 wr01001000000 00000000 1 d 10001000000 ? 2,3 /d, /d11111000000 ? 4 wr010010000f0 00110011 5 d 100010000f0 ? 6,7 /d, /d111110000f0 ? 1 8 to 15 repeat sub-loop 0, but ba= 1 2 16 to 23 repeat sub-loop 0, but ba= 2 3 24 to 31 repeat sub-loop 0, but ba= 3 4 32 to 39 repeat sub-loop 0, but ba= 4 5 40 to 47 repeat sub-loop 0, but ba= 5 6 48 to 55 repeat sub-loop 0, but ba= 6 7 56 to 63 repeat sub-loop 0, but ba= 7 table 13: idd5b measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 ref00010000000 ? 1, 2 d 10000000000 ? 3,4 /d, /d111100000f0 ? 1 5 to 8 repeat cycles 1...4, but ba= 1 9 to 12 repeat cycles 1...4, but ba= 2 13 to 16 repeat cycles 1...4, but ba= 3 17 to 20 repeat cycles 1...4, but ba= 4 21 to 24 repeat cycles 1...4, but ba= 5 25 to 28 repeat cycles 1...4, but ba= 6 29 to 32 repeat cycles 1...4, but ba= 7 2 33 to nrfc ? 1 repeat sub-loop 1, until nrfc ? 1. truncate, if necessary.
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 18 notes: 1. dm must be driven low all the time. dqs, /dqs are used according to read commands, otherwise mid-level. 2. burst sequence driven on each dq signal by read command. outside burst ope ration, dq signals are mid-level. 3. ba: ba0 to ba2. 4. am: m means most significant bit (msb) of row address. table 14: idd7 measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -am a10 a7 -a9 a3 -a6 a0 -a2 data* 2 toggling static h 0 0 act00110000000 ? 1 rda 0 1 0 1 0 0 0 1 0 0 0 00000000 2 d 10000000000 ? ? repeat above d command until nrrd ? 1 1 nrrd act 0 0 1 1 0 1 0 0 0 f 0 ? nrrd + 1 rda 0 1 0 1 0 1 0 1 0 f 0 00110011 nrrd + 2d 100001000f0 ? ? repeat above d command until 2 nrrd ? 1 22 nrrd repeat sub-loop 0, but ba= 2 33 nrrd repeat sub-loop 1, but ba= 3 44 nrrd d100003000f0 ? assert and repeat above d command until nfaw ? 1, if necessary 5 nfaw repeat sub-loop 0, but ba= 4 6 nfaw + nrrd repeat sub-loop 1, but ba= 5 7 nfaw + 2 nrrd repeat sub-loop 0, but ba= 6 8 nfaw + 3 nrrd repeat sub-loop 1, but ba= 7 9 nfaw + 4 nrrd d100007000f0 ? assert and repeat above d command until 2 nfaw ? 1, if necessary 10 2 nfaw + 0 act 0 0 1 1 0 0 0 0 0 f 0 ? 2 nfaw + 1 rda 0 1 0 1 0 0 0 1 0 f 0 00110011 2 nfaw + 2 d100000000f0 ? repeat above d command until 2 nfaw + nrrd ? 1 11 2 nfaw + nrrd act 0 0 1 1 0 1 0 0 0 0 0 ? 2 nfaw + nrrd + 1 rda 0 1 0 1 0 1 0 1 0 0 0 00000000 2 nfaw + nrrd + 2 d10000100000 ? repeat above d command until 2 nfaw + 2 nrrd ? 1 12 2 nfaw +2 nrrd repeat sub-loop 10, but ba= 2 13 2 nfaw + 3 nrrd repeat sub-loop 11, but ba= 3 14 2 nfaw + 4 nrrd d10000300000 ? assert and repeat above d command until 3 nfaw ? 1, if necessary 15 3 nfaw repeat sub-loop 10, but ba= 4 16 3 nfaw +nrrd repeat sub-loop 11, but ba= 5 17 3 nfaw + 2 nrrd repeat sub-loop 10, but ba= 6 18 3 nfaw + 3 nrrd repeat sub-loop 11, but ba= 7 19 3 nfaw + 4 nrrd d10000700000 ? assert and repeat above d command until 4 nfaw ? 1, if necessary
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 19 2. electrical specifications 2.1 dc characteristics table 15: dc characteristics 1 (tc = 0 c to +85 c, vdd, vddq = 1.283v to 1.45v) data rate 4 8 16 parameter symbol (mbps) max max max unit notes operating current (act-pre) idd0 1333 1600 40 45 40 45 50 55 ma operating current (act-rd-pre) idd1 1333 1600 55 60 55 60 70 75 ma precharge power-down standby current idd2p1 1333 1600 17 18 17 18 17 18 ma fast pd exit idd2p0 1333 1600 12 12 12 12 12 12 ma slow pd exit precharge standby current idd2n 1333 1600 25 25 25 25 25 25 ma precharge standby odt current idd2nt 1333 1600 30 30 30 30 30 30 ma precharge quiet standby current idd2q 1333 1600 25 25 25 25 25 25 ma active power-down current (always fast exit) idd3p 1333 1600 20 20 20 20 22 22 ma active standby current idd3n 1333 1600 30 30 30 30 30 32 ma operating current (burst read operating) idd4r 1333 1600 80 90 90 100 120 135 ma operating current (burst write operating) idd4w 1333 1600 85 95 95 105 135 150 ma burst refresh current idd5b 1333 1600 160 160 160 160 160 160 ma all bank interleave read current idd7 1333 1600 145 150 145 150 175 195 ma reset low current idd8 12 12 12 ma table 16: self-refresh current (tc = 0 c to +85 c, vdd, vddq = 1.283v to 1.45v) parameter symbol max unit notes self-refresh current normal temperature range idd6 12 ma self-refresh current extended temperature range idd6et 17 ma auto self-refresh current (optional) idd6tc ? ma
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 20 2.2 pin capacitance notes: 1. although the dm, tdqs and /tdqs pins have di fferent functions, the loading matches dq and dqs. 2. vdd, vddq, vss, vssq applied and all other pins float ing (except the pin under test, cke, /reset and odt as necessary). vdd = vddq = 1.35v, vbias=vdd/2 and ondie termination off. 3. absolute value of cck-c/ck. 4. absolute value of cio(dqs)-cio(/dqs). 5. ci applies to odt, /cs, cke, a0-a15, ba0-ba2, /ras, /cas and /we. 6. cdi_ctrl applies to odt, /cs and cke. 7. cdi_ctrl = ci(ctrl) ? 0.5 (ci(ck)+ci(/ck)). 8. cdi_add_cmd applies to a0-a15, ba0-ba2, /ras, /cas and /we. 9. cdi_add_cmd = ci(add_cmd) ? 0.5 (ci(ck)+ci(/ck)). 10. cdio=cio(dq,dm) ? 0.5 (cio(dqs)+cio(/dqs)). 11. maximum external load c apacitance on zq pin: 5pf. table 17: pin capacitance [ ddr3-800 to 1600] (tc = 25 c, vdd, vddq = 1.283v to 1.45v) ddr3l-800 ddr3l-1066 ddr3l-1333 ddr3l-1600 parameter symbol min max min max min max min max units notes input/output capacitance cio 1.4 2.5 1.4 2.5 1.4 2.3 1.4 2.2 pf 1, 2 input capacitance, ck and /ck cck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2 input capacitance delta, ck and /ck cdck 0 0.15 0 0.15 0 0.15 0 0.15 pf 2, 3 input/output capacitance delta, dqs and /dqs cddqs 0 0.2 0 0.2 0 0.15 0 0.15 pf 2, 4 input capacitance, (control, address, command, input-only pins) ci 0.75 1.3 0.75 1.3 0.75 1.3 0.75 1.2 pf 2, 5 input capacitance delta, (all control input-only pins) cdi_ctrl ? 0.5 0.3 ? 0.5 0.3 ? 0.4 0.2 ? 0.4 0.2 pf 2, 6, 7 input capacitance delta, (all addres/command input-only pins) cdi_add_ cmd ? 0.5 0.5 ? 0.5 0.5 ? 0.4 0.4 ? 0.4 0.4 pf 2, 8, 9 input/output capacitance delta, dq,dm, dqs, /dqs, tdqs, /tdqs cdio ? 0.5 0.3 ? 0.5 0.3 ? 0.5 0.3 ? 0.5 0.3 pf 2, 10 input/output capacitance of zq pin czq ? 3 ? 3 ? 3 ? 3pf2, 11
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 21 2.3 standard speed bins table 18: ddr3-800 speed bins speed bin ddr3-800e cl-trcd-trp 6-6-6 symbol /cas write latency min max unit notes taa 15 20 ns 9 trcd 15 ? ns 9 trp 15 ? ns 9 trc 52.5 ? ns 9 tras 37.5 9 trefi ns 8 tck(avg) @cl=5 cwl = 5 3.0 3.3 ns 1, 2, 3, 10 tck(avg) @cl=6 cwl = 5 2.5 3.3 ns 1, 2, 3, 10 supported cl settings 5, 6 nck supported cwl settings 5 nck table 19: ddr3-1066 speed bins speed bin ddr3-1066f cl-trcd-trp 7-7-7 symbol /cas write latency min max unit notes taa 13.125 20 ns 9 trcd 13.125 ? ns 9 trp 13.125 ? ns 9 trc 50.625 ? ns 9 tras 37.5 9 trefi ns 8 tck(avg) @cl=5 cwl = 5 3.0 3.3 ns 1, 2, 3, 4, 5, 10 cwl = 6 reserved reserved ns 4 tck(avg) @cl=6 cwl = 5 2.5 3.3 ns 1, 2, 3, 5 cwl = 6 reserved reserved ns 4 tck(avg) @cl=7 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 4 tck(avg) @cl=8 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3 supported cl settings 5, 6, 7, 8 nck supported cwl settings 5, 6 nck
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 22 table 20: ddr3-1333 speed bins speed bin ddr3-1333h cl-trcd-trp 9-9-9 symbol /cas write latency min max unit notes taa 13.5 (13.125) 20 ns 9 trcd 13.5 (13.125) ? ns 9 trp 13.5 (13.125) ? ns 9 trc 49.5 (49.125) ? ns 9 tras 36 9 trefi ns 8 tck(avg) @cl=5 cwl = 5 3.0 3.3 ns 1, 2, 3, 4, 6, 10 cwl = 6, 7 reserved reserved ns 4 tck(avg) @cl=6 cwl = 5 2.5 3.3 ns 1, 2, 3, 6 cwl = 6 reserved reserved ns 4 cwl = 7 reserved reserved ns 4 tck(avg) @cl=7 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 4, 6 cwl = 7 reserved reserved ns 4 tck(avg) @cl=8 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 6 cwl = 7 reserved reserved ns 4 tck(avg) @cl=9 cwl = 5, 6 reserved reserved ns 4 cwl= 7 1.5 < 1.875 ns 1, 2, 3, 4 tck(avg) @cl=10 cwl = 5, 6 reserved reserved ns 4 cwl= 7 1.5 < 1.875 ns 1, 2, 3 supported cl settings 5, 6, 7, 8, 9, 10 nck supported cwl settings 5, 6, 7 nck
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 23 table 21: ddr3-1600 speed bins speed bin ddr3-1600k cl-trcd-trp 11-11-11 symbol /cas write latency min max unit notes taa 13.75 (13.125) 20 ns 9 trcd 13.75 (13.125) ? ns 9 trp 13.75 (13.125) ? ns 9 trc 48.75 (48.125) ? ns 9 tras 35 9 trefi ns 8 tck(avg) @cl=5 cwl = 5 3.0 3.3 ns 1, 2, 3, 4, 7, 10 cwl = 6, 7, 8 reserved reserved ns 4 tck(avg) @cl=6 cwl = 5 2.5 3.3 ns 1, 2, 3, 7 cwl = 6 reserved reserved ns 4 cwl = 7, 8 reserved reserved ns 4 tck(avg) @cl=7 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 4, 7 cwl = 7 reserved reserved ns 4 cwl = 8 reserved reserved ns 4 tck(avg) @cl=8 cwl = 5 reserved reserved ns 4 cwl = 6 1.875 < 2.5 ns 1, 2, 3, 7 cwl = 7 reserved reserved ns 4 cwl = 8 reserved reserved ns 4 tck(avg) @cl=9 cwl = 5, 6 reserved reserved ns 4 cwl= 7 1.5 < 1.875 ns 1, 2, 3, 4, 7 cwl= 8 reserved reserved ns 4 tck(avg) @cl=10 cwl = 5, 6 reserved reserved ns 4 cwl= 7 1.5 < 1.875 ns 1, 2, 3, 7 cwl= 8 reserved reserved ns 4 tck(avg) @cl=11 cwl = 5, 6, 7 reserved reserved ns 4 cwl= 8 1.25 < 1.5 ns 1, 2, 3 supported cl settings 5, 6, 7, 8, 9, 10, 11 nck supported cwl settings 5, 6, 7, 8 nck
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 24 notes: 1. the cl setting and cwl setting result in tck(avg)mi n and tck(avg)max requirements. when making a selection of tck(avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg)min limits: since /cas latenc y is not purely analog - data and strobe out put are synchronized by the dll - all possible intermediate frequencies may not be guaranteed. an application should use the ne xt smaller jedec standard tck(avg) value (3.0, 2.5, 1.875, 1.5, or 1.25ns) when ca lculating cl(nck) = taa(ns) / tck(avg)(ns), rounding up to the next ?supported cl?. 3. tck(avg)max limits: calculate tck(avg) + taa(max)/cl selected and round the resulting tck(avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). th is result is tck(avg)max corresponding to cl selected. 4. reserved? settings are not allowed. user must program a different value. 5. any ddr3-1066 speed bin also supports functional operation at lower frequencie s as shown in the table ddr3-1066 speed bins which are not subject to production tests but verified by design/characterization. 6. any ddr3-1333 speed bin also supports functional operation at lower frequencie s as shown in the table ddr3-1333 speed bins which is not subject to production te sts but verified by design/characterization. 7. any ddr3-1600 speed bin also supports functional operation at lower frequencie s as shown in the table ddr3-1600 speed bins which is not subject to production te sts but verified by design/characterization. 8. trefi depends on operating case temperature (tc). 9. for devices supporting optional down binni ng to cl = 7 and cl = 9, taa/trcd/trp(min) must be 13.125 ns or lower. spd settings must be programmed to match. 10. ddr3-800 ac timing apply if dram operates at lower than 800 mt/s data rate.
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 25 3. package drawing 3.1 78-ball fbga solder ball: lead free (sn-ag-cu) 9.0 0.1 index mark 10.6 0.1 b a index mark 0.8 9.6 1.6 6.4 unit: mm 0.20 s b 78- 0.45 0.05 0.15 m sa b eca-ts2-0421-01 0.20 s a 0.10 s 0.20 s 1.20 max. 0.35 0.05 s 0.8
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 26 3.2 96-ball fbga solder ball: lead free (sn-ag-cu) 9.0 0.1 index mark 13.5 0.1 b a 12.0 1.6 6.4 unit: mm 0.4 0.8 0.20 s b 96- 0.45 0.05 0.15 m sa b eca-ts2-0422-01 0.20 s a 0.8 index mark 0.10 s 0.20 s 1.20 max. 0.35 0.05 s
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 27 4. recommended soldering conditions please consult with our sales offices for sol dering conditions of the 4g bits ddr3 sdram. type of surface mount device edj4204efbg, edj4208efbg: 78-ball fbga < lead free (sn-ag-cu) > edj4216efbg: 96-ball fbga < lead free (sn-ag-cu) >
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 28 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edj4204efbg, ed j4208efbg, edj4216efbg preliminary data sheet e1922e11 (ver. 1.1) 29 m01e1007 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, this product is not intended for use in the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. customers are instructed to contact elpida memory's sales office before using this product for such applications. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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