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ordering number : enn7253 n2002rm (ot) no. 7253-1/15 overview the LC723481W, 723482w, and 723483w are low- voltage electronic tuning radio microcontrollers that include a pll that operates up to 250 mhz and a 1/4 duty 1/2 bias lcd driver on chip. these ics include an on-chip dc-dc converter, making it is easy to create the supply voltages required for tuning and allowing cost reductions in end products. these ics are optimal for use in low-voltage portable audio equipment that includes a radio receiver. function ? program memory (rom): 2048 16 bits (4k bytes) LC723481W 3072 16 bits (6k bytes) lc723482w 4096 16 bits (8k bytes) lc723483w ? data memory (ram): 128 4 bits LC723481W 192 4 bits lc723482w 256 4 bits lc723483w ? cycle time: 40 s (all 1-word instructions) at 75khz crystal oscillation ? stack: 4 levels (8 levels) LC723481W(lc723482w/3w) ? lcd driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) ? interrupts: one external interrupt timer interrupts (1, 5, 10, and 50 ms) ? a/d converter: three input channels (5-bit successive approximation conversion) ? input ports: 7 ports (of which 3 can be switched for use as a/d converter inputs) ? output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are open- drain ports) continued on next page. package dimensions unit: mm 3190a-sqfp64 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 (0.5) (1.25) 116 17 32 33 48 49 64 sanyo: sqfp64 [LC723481W/2w/3w] LC723481W,723482w,723483w sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan low-voltage etr-controller cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
no. 7253- 2 /15 LC723481W/2w/3w continued from preceding page. i/o ports: 16 pins (of these 8 can be switched over to function as lcd ports as a mask options.) ? pll: dead band control is supported. (four types) reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 khz ? input frequencies: fm band: 10 to 250 mhz am band: 0.5 to 40 mhz ? input sensitivity: fm band: 35 mvrms (50 mvrms at 130 mhz or higher frequency) am band: 35 mvrms ? if counting: using the hctr input pin for 0.4 to 12 mhz signals ? external reset input: during cpu and pll operations, instruction execution is started from location 0. ? built-in power-on reset circuit: the cpu starts execution from location 0 when power is first applied. ? halt mode: the controller-operating clock is stopped. ? backup mode: the crystal oscillator is stopped. ? static power-on function: backup state is cleared with the pf port ? beep tone: 1.5625 and 3.125 khz ? built-in low-pass filter amplifier: this circuit obviates the need for an external amplifier for the pll circuit and contributes to reduced end product costs. ? built-in dc/dc converter: cost reduced in tuner-use power supply circuit ? memory retention voltage: 0.9 v at least ? v dd voltage pll: 1.8 to 3.6 v cpu: 1.4 to 3.6 v adc: 1.6 to 3.6 v ? optional function switches: ph0 to ph3/s13 to s16 pg0 to pg3/s17 to s20 pg0 to pg3 (open-drain output/general-purpose output) ph0 to ph3 (open-drain output/general-purpose output) fm dc/dc clock (75 khz or 1/256 times the local fm oscillator frequency) am dc/dc clock (1/2, 1/4, 1/8, or 1/16 times the am local oscillator frequency) ? package: sqfp-64 (0.5-mm pitch) pin assignment xout test2 pa3 pb3 pc3 pd3 pd2 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 com4 com3 com2 com1 pc2 pc1 pc0 pb2 pb1 pb0 pa2 pa1 pa0 pd2 pe1 beep/pe0 adi3/pf2 adi1/pf1 adi0/pf0 s20/pg3 s16/ph3 s15/ph2 s14/ph1 s13/ph0 s19/pg2 s18/pg1 s17/pg0 v ss int/pd0 63 64 61 62 58 59 60 56 57 54 55 52 53 49 50 1 48 2 47 51 46 45 44 43 42 41 40 39 38 37 36 35 34 33 31 32 3 4 5 6 7 8 9 10 11 12 13 14 15 16 28 29 30 26 27 24 25 22 23 17 18 19 20 21 dbr4 tu dbr3 dbr2 dbr1 bres hctr v dd v ss fmin amin eo ain xin general-purpose inputs general-purpose unbalanced outputs open drain outputs general-purpose i/o open drain outputs general-purpose inputs/ a/d converter inputs general-purpose i/o, open drain outputs, segment outputs general-purpose i/o, open drain outputs, segment outputs general- purpose i/o test1 aout
no. 7253- 3 /15 LC723481W/2w/3w parameter symbol conditions ratings unit maximum supply voltage v dd max C0.3 to +4.0 v input voltage v in all input pins C0.3 to v dd +0.3 v output voltage v out (1) aout, pe, tu C0.3 to +15 v v out (2) all output pins except v out (1) C0.3 to v dd + 0.3 v i out (1) pc, pd, pg, ph, eo 0 to 3 ma i out (2) pb 0 to 1 ma output current i out (3) aout, pe, tu 0 to 2 ma i out (4) s1 to s20 300 a i out (5) com1 to com4 3 ma allowable power dissipation pdmax ta = C20 to +70 c 300 mw operating temperature topr C20 to +70 c storage temperature tstg C45 to +125 c specifications absolute maximum ratings at ta = 25 c, v ss = 0 v parameter symbol conditions ratings unit min typ max v dd (1) pll operating voltage 1.8 3.0 3.6 supply voltage v dd (2) memory retention voltage 1.0 v v dd (3) cpu operating voltage 1.4 3.0 3.6 v dd (4) a/d converter operating voltage 1.6 3.0 3.6 v ih (1) input ports other than v ih (2), v ih (3), amin, 0.7 v dd v dd v input high-level voltage fmin, hctr, and xin v ih (2) bres port 0.8 v dd v dd v v ih (3) port pf 0.6 v dd v dd v v il (1) input ports other than v il (2), v il (3), amin, 0 0.3 v dd v input low-level voltage fmin, hctr, and xin v il (2) bres port 0 0.2 v dd v v il (3) port pf 0 0.2 v dd v v in (1) xin 0.5 0.6 vrms input amplitude v in (2) fmin, amin 0.035 0.35 vrms v in (3) fmin 0.05 0.35 vrms v in (4) hctr 0.035 0.35 vrms input voltage range v in (5) adio, adi1, adi3 0 v dd v f in (1) xin: ci 35 k 70 75 80 khz f in (2) fmin: v in (2), v dd (1) 10 130 mhz input frequency f in (3) fmin: v in (3), v dd (1) 130 250 mhz f in (4) amin(h): v in (2), v dd (1) 2 40 mhz f in (5) amin(l): v in (2), v dd (1) 0.5 10 mhz f in (6) hctr: v in (4), v dd (1) 0.4 12 mhz allowable operating ranges at ta = C20 to +70 c, v dd = 1.8 to 3.6 v
no. 7253- 4 /15 LC723481W/2w/3w parameter symbol conditions ratings unit min typ max i ih (1) xin: v i = v dd = 3.0 v 3 a input high-level current i ih (2) fmin, amin, hctr: v i = v dd = 3.0 v 3 8 20 a pa/pf (without pull-down resistors), the pc, i ih (3) pd, pg, ph, ports, 3 a and bres: v i = v dd = 3.0 v i il (1) xin: v dd = v ss C3 a input low-level current i il (2) fmin, amin, hctr: v i = v dd = v ss C3 C8 C20 a pa/pf (without pull-down resistors), the pc, i il (3) pd, pg, ph, ports, C3 a and bres: v i = v dd = v ss input floating voltage v if pa/pf (with pull-down resistors) 0.05 v dd v pull-down resistor values r pd (1) pa/pf (with pull-down resistors), v dd = 3.0 v 75 100 200 k r pd (2) test1, test2 10 k hysteresis v h bres 0.1 v dd 0.2 v dd v voltage doubler reference voltage dbr4 referenced to v dd , c(3) = 0.47 f, 1.3 1.5 1.7 v ta = 25 c * 1 voltage doubler step-up voltage dbr1, 2, 3 c(1) = 0.47 f 2.7 3.0 3.3 v c(2) = 0.47 f, without loading, ta = 25 c * 1 v oh (1) pb: i o = C1 ma v dd C v dd C v 0.7 v dd 0.3 v dd v oh (2) pc, pd, pg, ph, : i o = C1 ma v dd C v 0.3 v dd v oh (3) eo: i o = C500 a v dd C v output high-level voltage 0.3 v dd v oh (4) xout: i o = 200 a v dd C v 0.3 v dd v oh (5) s1 to s20: i o = C20 a * 1 2.0 v v oh (6) com1, com2, com3, com4: 2.0 v i o = C100 a * 1 v ol (1) pb: i o = C50 a 0.3 v dd 0.7 v dd v v ol (2) pc, pd, pg, ph, pe: i o = C1 ma 0.3 v dd v v ol (3) eo: i o = C500 a 0.3 v dd v v ol (4) xout: i o = C200 a 0.3 v dd v output low-level voltage v ol (5) s1 to s20: i o = C20 a * 1 1.0 v v ol (6) com1, com2, com3, com4: 1.0 v i o = C100 a * 1 v ol (7) pe: i o = 2 ma 1.0 v v ol (8) aout (ain = 1.3 v), tu: i o = 1 ma, v dd = 3 v 0.5 v output off leakage current i off (1) ports pb, pc, pd, pg, ph and eo C3 +3 a i off (2) aout, pe and port tu C100 +100 na a/d converter error adi0, adi1, adi3, v dd (4) C1/2 +1/2 lsb i dd (1) v dd (1): f in (2) 130 mhz, ta = 25 c 5 ma i dd (2) v dd (2): in halt mode, ta = 25 c * 2 0.1 ma current drain i dd (3) v dd = 3.6 v, with the oscillator stopped, 1 a ta = 25 c * 3 i dd (4) v dd = 1.8 v, with the oscillator stopped, 0.5 a ta = 25 c * 3 electrical characteristics within the allowable operating ranges note: the halt mode current is due to the cpu executing 20 instruction steps every 125 ms.
note: * c(1), c(2), and c(3) must be connected even if an lcd is not used. no. 7253- 5 /15 LC723481W/2w/3w dbr1 dbr2 dbr3 0.1 to 1 f 0.1 to 1 f 0.1 to 1 f c(c1) c(c2) dbr4 c(c3) notes: *1. the capacitors c(1), c(2), and c(3) must be connected to the dbr pins. a a 7 pf 7 pf fmin xin amin test1, 2 hctr xout vdd dbr2 dbr1 dbr1 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f dbr3 dbr4 bres bres vss pa, pf ain fmin xin amin test1, 2 hctr xout vdd vss ain 7pf 75 khz 75 khz 7pf dbr2 dbr3 dbr4 *2. halt mode current measurement circuit *3. backup mode current measurement circuit with all ports other than those specified above left open. with output mode selected for pc and pd. with segments s13 to s20 selected. with all ports other than those specified above left open. with output mode selected for pc and pd. with segments s13 to s20 selected.
block diagram no. 7253- 6 /15 LC723481W/2w/3w phase detector reference divider divider system clock generator programmble divider divider 1/16, 1/17 seg la p-on reset 1/2 time base control universal counter (20bits) bank count end address decoder data bus timer 0 judge alu cf skip bank latch a stack 4 14 14 address counter address decoder rom 2k 16bits (lc723481) 3k 16bits (lc723482) 4k 16bits (lc723483) ram 128 4bits (lc723481) 256 4bits (lc723483) 192 4bits (lc723482) bus control jmp cal return interrupt reset instruction decoder pll data latch pll control fm local 1/256 am local 1/2, 1/4, 1/8, 1/16 data latch bus driver data latch bus driver bus driver xin xout fmin pc2 pc1 pc0 pc3 pa3 pa2 pa1 pa0 test2 test1 bres * amin s16/ph0 s15/ph1 s13/ph3 s14/ph2 lcd port driver lcpa/b lcda/b eo s12 s1 1/2 hctr vss vdd pb2 pb1 pb0 pb3 * data latch bus driver pd2 pd1 int/pd0 pd3 latch b pe0/beep com1 com2 com3 com4 dbr4 dbr3 dbr2 dbr1 data latch / bus driver data latch / bus driver mpx (5bits) mpx mpx beep tone common driver doubler circuit data latch bus driver data latch / / bus driver 7 80 pf1/adi1 pf0/adi0 pe1 pf2/adi3 tu 75khz 1/8 s20/pg0 s19/pg1 s17/pg3 s18/pg2 / / / ain aout
no. 7253- 7 /15 LC723481W/2w/3w pin functions pin no. pin i/o function i/o circuit 75 khz oscillator connections 64 1 xin xout i o ic testing. these pins must be connected to ground during normal operation. 63 2 test1 test2 i i special-purpose key return signal input ports designed with a low threshold voltage. when used in conjunction with port pb to form a key matrix, up to 3 simultaneous key presses can be detected. the four pull-down resistors are selected together in a single operation using the ios instruction (pwn = 2, b1); they cannot be specified individually. input is disabled in backup mode, and the pull-down resistors are disabled after a reset. 6 5 4 3 pa0 pa1 pa2 pa3 i general-purpose cmos and n-channel open-drain output shared-function ports. the ios instruction (pwn = 2) is used for function switching. (b0: pb0, b2: pb1, b3: pb2, pb3) (0: general-purpose cmos, 1: n-channel open- drain) special-purpose key source signal output ports. since unbalanced cmos output transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. these ports go to the output high-impedance state in backup mode. these ports go to the output high-impedance state after a reset and remain in that state until an output instruction (out, spb, or rpb) is executed. * : verify the output impedance conditions carefully if these pins are used for functions other than key source outputs. 10 9 8 7 pb0 pb1 pb2 pb3 o general-purpose i/o ports. pd0 can be used as an external interrupt port. input or output mode can be set individually using the ios instruction (pwn = 4, 5) by the bit . a value of 0 specifies input, and 1 specifies output. these ports go to the input disabled high-impedance state in backup mode. they are set to function as general-purpose input ports after a reset. 14 13 12 11 18 17 16 15 pc0 pc1 pc2 pc3 int0/pd0 pd1 pd2 pd3 * 2 i/o general-purpose output and beep output (pe0 shared function ports). the beep instruction is used to switch the beep/pe0 port between the general- purpose output port and the beep output functions. a beep instruction with b2 = 0 will set the beep/pe0 port to function as a general- purpose output port. if b2 is set to 1, the instruction will select the beep output function. bits b0 and b1 switch the frequency of the beep output. this ic supports two beep frequencies. * : when the pe0 port is set to function as the beep output, executing an output instruction for pe0 will only change the value of the internal output latch; it will have no effect on the output. only the pe0 pin can be switched between the general- purpose output port and beep output functions; the pe1 pin is a dedicated general- purpose output port. in backup mode, these ports go to the high-impedance state. these ports will remain in that state until either an output instruction or a beep instruction is executed. since these ports are open drain ports, a resistor must be inserted between each port and vdd. at reset, they are set to the general-purpose output port function. 20 19 beep/pe0 pe1 input with built-in pull-down resistor unbalanced cmos push-pull n-channel open-drain cmos push-pull continued on next page. o
no. 7253- 8 /15 LC723481W/2w/3w continued from preceding page. pin no. pin i/o function i/o circuit general-purpose input and a/d converter input shared function ports. the ios instruction (pwn = fh) is used to switch between the general-purpose input and a/d converter port functions. the general-purpose input and a/d converter port functions can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying the a/d converter input function. to select the a/d converter function, set up the a/d converter pin with an ios instruction with pwn set to 1. the a/d converter is started with the ucc instruction (b3 = 1, b2 = 1). the adce flag is set when the conversion completes. the inr instruction is used to read in the data. * : if an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since cmos input is disabled. in backup mode these pins go to the input disabled high-impedance state. these ports are set to their general-purpose input port function after a reset. the a/d converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. note that the full-scale a/d converter voltage (1fh) is (62 / 96) v dd . 23 22 21 pf0/adi0 pf1/adi1 pf2/adi3 i cmos input/analog input shared function ports that function either as lcd driver segment outputs or general- purpose i/o ports. the ios instruction is used to switch between the segment output and the general- purpose i/o port functions. when used as segment output ports the ios (pwn=8) instruction is used to set the general-purpose i/o port . b0 to 3 = s17 to s20/pg0 to pg3 (0: segment output, 1: pg0 to pg3) the ios (pwn=9) instruction is used to set the general-purpose i/o port . b0 to 3 = s13 to s16/ph0 to ph3 (0: segment output, 1: ph0 to ph3) when used as general-purpose i/o ports the ios instruction (pwn=6, 7) is used to switch the i/o direction. the directions of these pins can be set individually in 1-bit units. b0 = pg0 b0 = ph0 b1 = pg1 0: input b1 = ph1 0: input b2 = pg2 1: output b2 = ph2 1: output b3 = pg3 b3 = ph3 in backup mode, if used as general-purpose i/o ports, they will be in the input disabled high-impedance state. if used as segment outputs, they will be held fixed at the low level. although the general-purpose port/lcd port setting is a mask option, the setup with the ios instruction described above is also necessary. 25 26 27 28 29 30 31 32 pg3/s20 pg2/s19 pg1/s18 pg0/s17 ph3/s16 ph2/s15 ph1/s14 ph0/s13 * 2 o cmos push-pull continued on next page. lcd driver segment output pins. a 1/4-duty 1/2-bias drive technique is used. the frame frequency is 75 hz. in backup mode, the outputs are fixed at the low level. after a reset, the outputs are fixed at the low level. 33 to 44 s12 to s1 o lcd driver common output pins. a 1/4-duty 1/2-bias drive technique is used. the frame frequency is 75 hz. in backup mode, the outputs are fixed at the low level. after a reset, the outputs are fixed at the low level. 45 46 47 48 com4 com3 com2 com1 o lcd power supply step-up voltage inputs. 50 51 52 53 dbr4 dbr3 dbr2 dbr1 i cmos push-pull
no. 7253- 9 /15 LC723481W/2w/3w continued from preceding page. pin no. pin i/o function i/o circuit continued on next page. system reset input. in cpu operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the pc set to location 0. this pin is connected in parallel with the internal power on reset circuit. 54 bres i tuning voltage generation circuit outputs. these pins include a n-ch transistor, and a tuning voltage can be generated by connecting external coil, diode, and capacitor components. 49 tu o n-channel open-drain fm vco (local oscillator) input. this pin is selected with the pll instruction cw1. 57 fmin i cmos amplifier input am vco (local oscillator) input. this pin and the bandwidth are selected with the pll instruction cw1. the input must be capacitor coupled. input is disabled in backup mode, in halt mode, after a reset, and in pll stop mode. 58 amin i cmos amplifier input cw1 b1, b0 bandwidth 1 0 2 to 40 mhz (sw) 1 1 0.5 to 10 mhz (mw, lw) special-purpose universal counter input port to measure a frequency, set up hctr frequency measurement mode and the measurement time with a ucs instruction (b3 = 0, b2 = 0) and start the count with a ucc instruction. 55 hctr i cmos amplifier input ucs b3 b2 input pin measurement mode 0 0 hctr frequency measurement 0 1 1 0 the cntend flag is set when the count completes. since the input circuit functions as an ac amplifier in this mode, the input must be capacitance coupled. this pin goes to the input disabled state in backup mode, halt mode, pll stop mode, and after a reset. ucs b1 b0 measurement time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 32 ms the input must be capacitor coupled. input is disabled in backup mode, in halt mode, after a reset, and in pll stop mode. cw1 b1, b0 bandwidth 0 0 10 to 250 mhz
no. 7253- 10 /15 LC723481W/2w/3w continued from preceding page. pin no. pin i/o function i/o circuit connections for the built-in transistor used to form a low-pass filter. 61 62 ain aout o main charge pump output. when the local oscillator frequency divided by n is higher than the reference frequency a high level is output, when lower, a low level is output. the pin is set to the high-impedance state when the frequencies match. output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in pll stop mode. 60 eo o power supply pin. this pin must be connected to ground. this pin must be connected to ground. this pin must be connected to v dd . 24 59 56 v ss v ss v dd cmos push-pull note 2: when a pin in an i/o switching port is used as an output, applications must first set up the data with an out, spb, or rpb inst ruction and then set up output mode with an ios instruction.
no. 7253- 11 /15 LC723481W/2w/3w xi n xo u t v dd fm i n a mi n ra di o o n mask option a m t fm t 75k 64 h z 1/ 256 1/ 2 to 1/ 16 1 56 57 49 58 1 100 1000 10000 0 2 4 6 8 10 12 lc723481 dc-dc converter load = 100 kw (when vdd = 1.8 v) clock frequency during fm reception (when 75 khz is selected) clock frequency range during am reception 220 h 180 h 150 h 100 h vt voltage - v clock frequency - khz a ou t a in eo tu varactor + b 60 63 62 sample application for tuning voltage generation circuit sample application for low-pass filter amplifier
LC723481W, 723482w and 723483w series instruction set terminology addr : program memory address b : borrow c : carry dh : data memory address high (row address) [2 bits] dl : data memory address low (column address) [4 bits] i : immediate data [4 bits] m : data memory address n : bit position [4 bits] rn : resister number [4 bits] pn : port number [4 bits] pw : port control word number [4 bits] r : general register (one of the addresses from 00h to 0fh of bank0) ( ), [ ] : contents of register or memory m (dh, dl) : data memory specified by dh, dl no. 7253- 12 /15 LC723481W/2w/3w mnemonic operand function operations function instruction format 1st 2nd ad r m add m to r r ? (r) + (m) ads r m add m to r, then skip if carry r ? (r) + (m), skip if carry ac r m add m to r with carry r ? (r) + (m) + c acs r m add m to r with carry, r ? (r) + (m) + c then skip if carry skip if carry ai m i add i to m m ? (m) + i ais m i add i to m, then skip if carry m ? (m) + i, skip if carry aic m i add i to m with carry m ? (m) + i + c aics m i add i to m with carry, m ? (m) + i + c, then skip if carry skip if carry su r m subtract m from r r ? (r) C (m) sus r m subtract m from r, r ? (r) C (m), then skip if borrow skip if borrow sb r m subtract m from r with borrow r ? (r) C (m) C b sbs r m subtract m from r with borrow, r ? (r) C (m) C b, then skip if borrow skip if borrow si m i subtract i from m m ? (m) C i sis m i subtract i from m, m ? (m) C i, then skip if borrow skip if borrow sib m i subtract i from m with borrow m ? (m) C i C b sibs m i subtract i from m with borrow, m ? (m) C i C b, then skip if borrow skip if borrow f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 dh dl r 0 1 0 0 0 1 dh dl r 0 1 0 0 1 0 dh dl r 0 1 0 0 1 1 dh dl r 0 1 0 1 0 0 dh dl i 0 1 0 1 0 1 dh dl i 0 1 0 1 1 0 dh dl i 0 1 0 1 1 1 dh dl i 0 1 1 0 0 0 dh dl r 0 1 1 0 0 1 dh dl r 0 1 1 0 1 0 dh dl r 0 1 1 0 1 1 dh dl r 0 1 1 1 0 0 dh dl i 0 1 1 1 0 1 dh dl i 0 1 1 1 1 0 dh dl i 0 1 1 1 1 1 dh dl i instruc- tions continued on next page. addition instructions subtraction instructions
no. 7253- 13 /15 LC723481W/2w/3w continued from preceding page. mnemonic operand function operations function instruction format 1st 2nd seq r m skip if r equal to m (r) C (m), skip if zero seqi m i skip if m equal to i (m) C i, skip if zero snei m i skip if m not equal to i (m) C i, skip if not zero sge r m skip if r is greater than or (r) C (m), equal to m skip if not borrow sgei m i skip if m is greater than (m) C i, skip if not borrow equal to i slei m i skip if m is less than i (m) C i, skip if borrow and r m and m with r r ? (r) and (m) andi m i and i with m m ? (m) and i or r m or m with r r ? (r) or (m) ori m i or i with m m ? (m) or i exl r m exclusive or m with r r ? (r) xor (m) exli m i exclusive or m with m m ? (m) xor i shr r shift r right with carry ld r m load m to r r ? (m) st m r store r to m m ? (r) mvrd r m move m to destination m [dh, rn] ? (m) referring to r in the same row mvrs m r move source m referring to r m ? [dh, rn] to m in the same row mvsr m1 m2 move m to m in the same row [dh, dl1] ? [dh, dl2] mvi m i move i to m m ? i tmt m n test m bits, then skip if all bits if m (n) = all 1s, then skip specified are true tmf m n test m bits, then skip if all bits if m (n) = all 0s, then skip specified are false jmp addr jump to the address pc ? addr cal addr call subroutine pc ? addr stack ? (pc) + 1 rt return from subroutine pc ? stack pc ? stack, rti return from interrupt bank ? stack, carry ? stack f e d c b a 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 dh dl r 0 0 0 1 1 0 dh dl i 0 0 0 0 0 1 dh dl i 0 0 0 1 1 0 dh dl r 0 0 0 1 1 1 dh dl i 0 0 0 0 1 1 dh dl i 0 0 1 0 0 0 dh dl r 0 0 1 0 0 1 dh dl i 0 0 1 0 1 0 dh dl r 0 0 1 0 1 1 dh dl i 0 0 1 1 0 0 dh dl r 0 0 1 1 1 0 dh dl i 0 0 0 0 0 0 0 0 1 1 1 0 r 1 1 0 1 0 0 dh dl r 1 1 0 1 0 1 dh dl r 1 1 0 1 1 0 dh dl r 1 1 0 1 1 1 dh dl r 1 1 1 0 0 0 dh dl1 dl2 1 1 1 0 0 1 dh dl i 1 1 1 1 0 0 dh dl n 1 1 1 1 0 1 dh dl n 1 0 0 addr (13 bits) 1 0 1 addr (13 bits) 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 bit test instructions jump and subroutine call instructions carry (r) comparison instructions logic instructions transfer instructions continued on next page. instruc- tions
no. 7253- 14 /15 LC723481W/2w/3w continued from preceding page. mnemonic operand function operations function instruction format 1st 2nd ss swr n set status register (status w-reg) n ? 1 rs swr n reset status register (status w-reg) n ? 0 tst srr n test status register true if (status r-reg) n = all tsf srr n test status register false if (status r-reg) n = all tul n test unlock f/f if unlock f/f (n) = all 0s, then skip pll m load m to pll register pll reg ? pll data ucs i set i to uccw1 uccw1 ? i ucc i set i to uccw2 uccw2 ? i beep i beep control beep reg ? i dzc i dead zone control dzc reg ? i tms i set timer register timer reg ? i ios pwn n set port control word ios reg pwn ? n in m pn input port data to m m ? (pn) out m pn output contents of m to port p1n ? m inr m pn input port data to m m ? (pn) spb p1n n set port1 bits (pn)n ? 1 rpb p1n n reset port1 bits (pn)n ? 0 tpt p1n n test port1 bits, then skip if all bits if (pn)n = all 1s, then skip specified are true tpf p1n n test port1 bits, then skip if all bits if (pn)n = all 0s, then skip specified are false bank i select bank bank ? i lcda m i output segment pattern to lcd lcd (digit) ? m lcdb m i digit direct lcpa m i output segment pattern to lcd lcd (digit) ? la ? m lcpb m i digit through la halt i halt mode control halt reg ? i, then cpu clock stop ckstp clock stop stop xtal osc nop no operation no operation f e d c b a 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 0 0 swr n 1 1 1 1 1 1 1 1 0 1 swr n 1 1 1 1 1 0 0 0 0 srr n 1 1 1 1 1 0 0 0 1 srr n 0 0 0 0 0 0 0 0 1 1 0 1 n 1 1 1 1 1 0 dh dl r 0 0 0 0 0 0 0 0 0 0 0 1 i 0 0 0 0 0 0 0 0 0 0 1 0 i 0 0 0 0 0 0 0 0 0 1 1 0 i 0 0 0 0 0 0 0 0 1 0 1 1 i 0 0 0 0 0 0 0 0 1 1 0 0 i 1 1 1 1 1 1 1 0 pwn n 1 1 1 0 1 0 dh dl pn 1 1 1 0 1 1 dh dl pn 0 0 1 1 1 0 dh dl pn 0 0 0 0 0 0 1 0 pn n 0 0 0 0 0 0 1 1 pn n 1 1 1 1 1 1 0 0 pn n 1 1 1 1 1 1 0 1 pn n 0 0 0 0 0 0 0 0 0 1 1 1 i 1 1 0 0 0 0 dh dl digit 1 1 0 0 0 1 dh dl digit 1 1 0 0 1 0 dh dl digit 1 1 0 0 1 1 dh dl digit 0 0 0 0 0 0 0 0 0 1 0 0 i 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 bank switching instructions status register instructions hardware control instructions lcd instructions other instructions i/o instructions instruc- tions
ps no. 7253- 15 /15 LC723481W/2w/3w this catalog provides information as of november, 2002. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.

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