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JMF612 sataii to flash controller datasheet document no.: 61x-00002 / revision: 1.04 / issue da te: 09-12-2009 jmicron technology corporation 1f, no. 13, innovation road 1, science-based industr ial park, hsinchu, taiwan 300, r.o.c. tel: 886-3-5797389 fax: 886-3-5799566 website: http://www.jmicron.com certificate no.: fm 84262 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 i document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. copyright ? 2009, jmicron technology corp. all righ ts reserved. printed in taiwan 2009 jmicron and the jmicron logo are trademarks of jmic ron technology corporation in taiwan and/or other c ountries. other company, product and service names may be tra demarks or service marks of others. all information contained in this document is subje ct to change without notice. the products describe d in this document are not intended for use implantation or o ther life supports application where malfunction ma y result in injury or death to persons. the information contai ned in this document does not affect or change jmic rons product specification or warranties. nothing in this docum ent shall operate as an express or implied license or environments, and is presented as an illustration. the results o btained in other operating environments may vary. the information contained in this document is provi ded on an as is basis. in no event will jmicron be liable for damages arising directly or i ndirectly from any use of the information contained in this document. for more information on jmicron products, please vi sit the jmicron web site at http://www.jmicron.com or send e-mail to sales@jmicron.com . for product application support, please send e-ma il to fae@jmicron.com . jmicron technology corporation 1f, no.13, innovation road 1, science-based industr ial park, hsinchu, taiwan 300, r.o.c. tel: 886-3-5797389 fax: 886-3-5799566 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 ii document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. revision history description of revision revision effect date reference description of the change author 1.01 06-26-2009 draft release. m 1.02 06-29-2009 electrical characteristics modified. m 1.03 08-31-2009 10.4\10.5 modify. m 1.04 09-12-2009 delete flash 2k page. this document is valid until the date dd-mm-yyyy the next revision has been effective. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 iii document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. table of contents revision history................................... ................................................... ................................................... ..................ii table of contents .................................. ................................................... ................................................... ................iii figure list........................................ ................................................... ................................................... .......................v table list......................................... ................................................... ................................................... ........................v 1 general description ................................ ................................................... ................................................... .........1 2 features ........................................... ................................................... ................................................... .................1 2.1 compliance..................................... ................................................... ................................................... .............. 1 2.2 satai\ii....................................... ................................................... ................................................... .................. 1 2.3 cpu............................................ ................................................... ................................................... .................. 1 2.4 flash.......................................... ................................................... ................................................... ................... 1 2.5 sdram .......................................... ................................................... ................................................... .............. 2 2.6 system......................................... ................................................... ................................................... .............. 2 2.7 firmware ....................................... ................................................... ................................................... ............... 2 3 block diagram ...................................... ................................................... ................................................... ............3 4 total capacity ..................................... ................................................... ................................................... ..............3 5 package pin out (tfbga 281 ball) ................... ................................................... .................................................4 6 package outline drawing (tfbga 281 ball)........... ................................................... ...........................................5 7 pin descriptions ................................... ................................................... ................................................... ............8 7.1 pin type definition................................ ................................................... ................................................... ....... 8 7.2 pin definition ..................................... ................................................... ................................................... ......... 8 8 ecc descriptions ................................... ................................................... ................................................... ........15 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 iv document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 9 sata interface ..................................... ................................................... ................................................... ...........16 9.1 out of bank signaling .............................. ................................................... ................................................... . 16 9.2 comreset........................................... ................................................... ................................................... .. 17 9.3 comini ............................................. ................................................... ................................................... ....... 19 9.4 power on sequence timing diagram ................... ................................................... ......................................... 21 9.5 ata command register ............................... ................................................... ................................................. 23 10 electrical characteristics......................... ................................................... ................................................... ......33 10.1 absolute maximum rating ............................ ................................................... .............................................. 33 10.2 recommended power supply operation conditions and t emperature......................................... ................ 33 10.3 recommended external clock source conditions ....... ................................................... .............................. 34 10.4 power supply dc characteristics (sata idle mode and power saving mode disable)........................ .......... 34 10.5 power supply dc characteristics (sata active mode). ................................................... ............................. 34 10.6 i/o dc characteristics ............................. ................................................... ................................................... 34 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 v document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. figure list figure 1 block diagram of JMF612 ................................................... ................................................... ..............3 figure 2 package ball assignment of JMF612 ................................................... .............................................4 figure 3 outline drawing_ top view ................................................... ................................................... ...........5 figure 4 outline drawing_ bottom view ................................................... ................................................... .....6 figure 5 outline drawing_ side view ................................................... ................................................... ..........7 figure 6 outline drawing_ symbol ................................................... ................................................... ..............7 figure 7 allocation for ecc algorithm bch in nand flash ................................................... ..................16 figure 8 oob signals ................................................... ................................................... ....................................17 figure 9 comreset sequence ................................................... ................................................... ......................18 figure 10 cominit sequence ................................................... ................................................... .......................20 figure 11 power on sequence ................................................... ................................................... ....................21 table list table 1 total capacity table ................................................... ................................................... ...........................3 table 2 pin type definition table ................................................... ................................................... ...................8 table 3 pin definition table ................................................... ................................................... ............................8 table 4 oob signal times ................................................... ................................................... .............................17 table 5 command table ................................................... ................................................... ................................23 table 6 identify device information default value ................................................... .....................................24 table 7 identify device information default value ( continued ) ................................................... ..............25 table 8 features register value and settable opera ting mode ................................................... ..............32 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 1 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 1 general description JMF612 is a single chip, supports external sdram, s ata ii to nand flash interface. it is native design to provide higher bandwidth for flash memory access. JMF612 can support the maximum read and write speed to drive the limit of flash memory. JMF612 has the best supporting to the latest nand flash me mory, including samsung, toshiba, hynix, micron and im flash. it also provides the embedded hardware er ror correction code (ecc), wear leveling, and bad block management technology in this chip. in order to resolve compatibility issue, JMF612 provides the on line firmware upgrade ability. JMF612 provides embedded processor, internal masked rom, data sram, sata link/transport layer, sata phy. data swap between different interfaces ca n be done very efficiency by dma without cpu involvement. based on the efficient architecture, t he JMF612 can provide the best performance. 2 features 2.1 compliance compliant with universal serial bus specification revision 2.0. compliant with usb mass storage class specificatio n version 1.0. compliant with serial ata international organizati on: serial ata revision 2.6. 2.2 satai\ii supports 1-port 1.5/3.0gbps sata i/ii interface. 2.3 cpu embedded data buffer. 32bits embedded processor. 32 kbytes embedded masked program rom. 128 kbytes embedded system ram. 2.4 flash support maximum 16ces flash per channel. support 5x/4x/3x nm flash. enhanced endurance by dynamic/static wear-leveling . www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 2 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. supports 4k/8k bytes page size. supports dynamic power management. smart (self-monitoring, analysis and reporting tec hnology). data integrity under power-cycling. supports online sata/usb firmware update. supports 8 bits flash interface. supports bch 16/24 bits ecc. 2.5 sdram supports ddr/ddr2 support 128mbits to 2gbits 2.6 system integrated 1-usb2.0 port, 1-sata ii port and 8-cha nnels flash controller. led indicator for usb2.0 and sata read/write acces s. led indicator for usb2.0 and sata phy link up. provides 14 gpio pins for customer. provides uart and jtag for s/w debugging. built-in power-up self-test (bist). manual and automatic self-diagnostics. provides voltage low detect interrupt. 281-ball tfbga package 2.7 firmware support ncq on this controller. support lba24 & lba48 on this controller. support 1 to 8 banks selected free. support 2 to 8 channels selected free . www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 3 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 3 block diagram figure 1 block diagram of JMF612 4 total capacity table 1 total capacity table density/per flash support ce pins/per flash maximum flash number total capacity 1g x 8 bits (8gb) 1 ce pin 32 32g bytes 2g x 8 bits (16gb) 1 ce/ 2 ce pin 32 64g bytes 4g x 8 bits (32gb) 1 ce/ 2 ce pin 32 128g bytes 8g x 8 bits (64gb) 2 ce pin 32 256g bytes 16g x 8 bits (128gb) 4 ce pin 32 512g bytes www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 4 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 5 package pin out (tfbga 281 ball) figure 2 package ball assignment of JMF612 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 5 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 6 package outline drawing (tfbga 281 ball) figure 3 outline drawing_ top view www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 6 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. figure 4 outline drawing_ bottom view www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 7 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. figure 5 outline drawing_ side view figure 6 outline drawing_ symbol www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 8 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 7 pin descriptions 7.1 pin type definition table 2 pin type definition table pin type definition a analog d digital i input o output io bi-directional il internal week pull-low (typical 75k w ) ih internal week pull-high (typical 75k w ) 7.2 pin definition table 3 pin definition table signal name ball no. type description f0_[d0~d7] u3,p1,r1,t 1,t2,u4n2, t4 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f1_[d0~d7] u10,t10,r1 0,p10,r11, t11,p11,n1 1 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f2_[d0~d7] l2,l3,m1,l 1,k1,j1h1, g1 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f3_[d0~d7] u13,p14,m 13,r13,t13 ,p13,t14,m 14 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f4_[d0~d7] r7,t6,u6,r 6,p7,p6,n7, n6 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f5_[d0~d7] u7,u8,t7,r 8,p9,u9,t9, n9 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 9 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description f6_[d0~d7] f1,d4,e4,e 2,d1,d3f2, e1 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. f7_[d0~d7] a3,b3,b4,c 4,a4,c5b5, b2 io flash data input/output the i/o pins are used to output command, address, d ata and to input data during read operations. [f0~f7]_wen r2,u11,h2, p15,t5,n8, f3,c3 o write enable the wen output controls writes to the i/o port. com mands, address and data are latched on the rising edge of the wen pulse [f0~f7]_ale t3,n10,g2, t15,r5,t8, d2,b1 o address latch enable the ale output controls the activating path for add ress to the internal address registers. addresses are latched o n the rising edge of wen with ale high. [f0~f7]_cle r3,m11,k2, n13,u5,p8, f4,c1 o command latch enable the cle output controls the activating path for com mands sent to the command registers. when active high, commands a re latched into the command register through the i/o ports on the edge of the wen signal. [f0~f7]_ren p2,n12,h3, n14,p5,r9, e3,c2 o read enable the ren output is the serial data-out control, and when active drives the data onto the i/o bus. data is valid tre a after the falling edge of ren which also increments the internal colu mn address counter by one. bk_[0n~15n] p4,r4,p3,n 1,p12,r12, t12,u12,j3 ,k3,j2,g3, r15,u14,u 15,r14 o bank selector the bkn output is the device selection control. whe n the device is in the busy state, bkn high is ignored, and the dev ice does not return to standby mode in program or erase operatio n. gpio0 t16 dio general purpose i/o, for normal function can be configured by customer. gpio1 g15 dio general purpose i/o, for normal function can be configured by customer. gpio2/uai g14 dio general purpose i/o, rs232 debug port. gpio3/uao b14 dio general purpose i/o, rs232 debug port. gpio4 a15 dio general purpose i/o,(f/w setting) 0: run sata 1.5gbps. 1: run sata 3.0gbps. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 10 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description gpio5 p16 dio general purpose i/o, 0: load firmware code from flash to program memory. 1: load firmware code from host to program memory. gpio6 b15 dio general purpose i/o, can be configured by customer firmware. gpio7 c15 dio general purpose i/o, can be configured by customer firmware. gpio8 a14 dio general purpose i/o, can be configured by customer firmware. gpio9 d15 dio general purpose i/o, can be configured by customer firmware. gpio10 d14 dio general purpose i/o, can be configured by customer firmware. gpio12 g13 dio general purpose i/o, can be configured by customer firmware. gpio14 n15 dio general purpose i/o, can be configured by customer firmware. gpio15 f14 dio general purpose i/o, can be configured by customer firmware. dm p17 aio usb bus d- signal. dp n17 aio usb bus d+ signal. vbus m15 i usb cable power detector. the 51k and 100k resistances should be connected to divide the 5v cable power into 3.3v. agnd_usb l16 ai usb analog ground. agndp m17 ai usb analog ground. avddh_usb m16 ai usb analog 3.3v power supply. tmen f15 dih test mode enable, (internal pull-h) this pin is reserved for ic mass production testing . always keep this pin to logic 1 in normal operati on. mode[3:0] n16,r17,t1 7,r16 il chip operation mode selection.(internal 0000) ball b4 a3 b5 a4 0 0 0 0 rstn e15 dih system global reset input. active-low to reset the entire chip. an external 10msec rc should be connected to this p in. hdda c14 do sata hard disk active.(gpio21) can be configured by customer firmware. phyrdy e14 do phyrdy of sata/usb output. xtali l17 ai crystal input pad it is connected to a 30mhz crystal. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 11 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description xtalo k17 ao crystal output pad it is connected to a crystal. asv33 h16,j17 ai sata analog 3.3v power supply. asg33 g16 ai sata analog ground. asrext0 j16 ai external reference resistance. a 12k w 1% external resistor should be connected to this pi n. asrxp0 h17 ai serial ata rx+ signal. a 10nf cap. should be connected between this pin an d sata connector. asrxn0 g17 ai serial ata rx- signal. a 10nf cap. should be connected between this pin an d sata connector. asv12 f17 ai sata analog 1.2v power supply. this power could be sourced from internal 1.2v volt age regulator through avreg pin. asg12 e16 ai sata analog ground. astxn0 e17 ao serial ata tx- signal. a 10nf cap. should be connected between this pin an d sata connector. astxp0 d17 ao serial ata tx+ signal. a 10nf cap. should be connected between this pin an d sata connector. lx b17 ao switching regulator output. gndsr c17 ai switching regulator ground pv33(reg) h15 ai switching regulator 3.3v power supply ddr_ppout d16 ao ddr regulator output agndr f16 ai ddr regulator ground pv33(avddhr) c16 ai ddr regulator 3.3v power supply a0 e8 a1 a7 a2 c7 a3 e7 a4 f7 a5 d7 a6 b7 a7 f8 a8 d8 a9 b8 a10 c8 a11 d9 a12 b6 a13 a5 o address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one locati on out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. ba0 e9 ba1 f9 o bank address inputs: ba[2:0] define to which bank a n active, read, write, or precharge command is being www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 12 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description ba2 a6 applied. ba[2:0] define which mode register, includ ing mr, emr, emr(2), and emr(3), is loaded during the l oad mode command. ck a8 o ck# a9 clock: ck and ck# are differential clock inputs. al l address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck# . output data (dq and dqs/dqs#) is referenced to the crossings of ck and ck#. cke b9 o clock enable: cke (registered high) activates and c ke (registered low) deactivates clocking circuitry on the ddr2 sdram. the specific circuitry that is enabled/ disabled is dependent on the ddr2 sdram configuration and operating mode. cke low provides precharge powerdown and self refresh operation (all banks idle), or activate power-down (row active in any bank). cke i s synchronous for power-down entry, power-down exit, output disable, and for self refresh entry. cke is asynchr onous for self refresh exit. input buffers (excluding ck, ck#, cke, and odt) are disabled during power-down. input buffers (excluding cke) are disabled during self re fresh. cke is an sstl_18 input but will detect a lvcmos low level once vdd is applied during first power-up . after vref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self refr esh operation, vref must be maintained. cs# c9 o chip select: cs# enables (registered low) and disab les (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provide s for external bank selection on systems with multiple ra nks. cs# is considered part of the command code. ldm b10 udm c10 o input data mask: dm is an input mask signal for wri te data. input data is masked when dm is concurrently sampled high during a write access. dm is sampled on both edges of dqs. although dm balls are input-only, the dm loading is designed to match that of dq and dqs bal ls. ldm is dm for lower byte dq0Cdq7 and udm is dm for upper byte dq8Cdq15. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 13 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description odt f13 on-die termination: odt (registered high) enables termination resistance internal to the ddr2 sdram. when enabled, odt is only applied to each of the followi ng balls: dq0Cdq15, ldm, udm, ldqs, ldqs#, udqs, and udqs# for the x16; dq0Cdq7, dqs, dqs#, rdqs, rdqs#, and dm for the x8; dq0Cdq3, dqs, dqs#, and dm for the x4. the odt input will be ignored if disabled v ia the load mode command. ras# f10 cas# e10 we# d10 o command inputs: ras#, cas#, and we# (along with cs#) define the command being entered. dq0 a13 data input/output: bidirectional data bus for x16. dq1 c13 data input/output: bidirectional data bus for x16. dq2 e13 data input/output: bidirectional data bus for x16. dq3 b12 data input/output: bidirectional data bus for x16. dq4 d12 data input/output: bidirectional data bus for x16. dq5 f12 data input/output: bidirectional data bus for x16. dq6 b11 data input/output: bidirectional data bus for x16. dq7 d11 data input/output: bidirectional data bus for x16. dq8 e11 data input/output: bidirectional data bus for x16. dq9 c11 data input/output: bidirectional data bus for x16. dq10 a11 data input/output: bidirectional data bus for x16. dq11 e12 data input/output: bidirectional data bus for x16. dq12 c12 data input/output: bidirectional data bus for x16. dq13 a12 data input/output: bidirectional data bus for x16. dq14 d13 data input/output: bidirectional data bus for x16. dq15 b13 io data input/output: bidirectional data bus for x16. ldqs f11 io data strobe for lower byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with wr ite data. ldqs# is only used when differential data str obe mode is enabled via the load mode command. udqs a10 io data strobe for upper byte: output with read data, input with write data for source synchronous operation. edge-aligned with read data, center-aligned with wr ite data. udqs# is only used when differential data str obe mode is enabled via the load mode command. pv33 g4 di i/o pad 3.3v power supply. pv33 h4 di i/o pad 3.3v power supply. pv33 h14 di i/o pad 3.3v power supply. pv33 j4 di i/o pad 3.3v power supply. pv33 j15 di i/o pad 3.3v power supply. pv33 k4 di i/o pad 3.3v power supply. pv33 k15 di i/o pad 3.3v power supply. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 14 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description pv33 l4 di i/o pad 3.3v power supply. pv33 l15 di i/o pad 3.3v power supply. pv33 m4 di i/o pad 3.3v power supply. pv33 m5 di i/o pad 3.3v power supply. pv33 m6 di i/o pad 3.3v power supply. pv33 m7 di i/o pad 3.3v power supply. pv33 m8 di i/o pad 3.3v power supply. pv33 m9 di i/o pad 3.3v power supply. pv33 m10 di i/o pad 3.3v power supply. pv33 m12 di i/o pad 3.3v power supply. pv33 n5 di i/o pad 3.3v power supply. gnd j6 di ground. gnd j7 di ground. gnd j8 di ground. gnd j9 di ground. gnd j10 di ground. gnd j11 di ground. gnd j12 di ground. gnd j13 di ground. gnd k6 di ground. gnd k7 di ground. gnd k8 di ground. gnd k9 di ground. gnd k10 di ground. gnd k11 di ground. gnd k12 di ground. gnd k13 di ground. gnd k16 di ground. dv12 f5 di 1.2v power supply. dv12 g5 di 1.2v power supply. dv12 h5 di 1.2v power supply. dv12 j5 di 1.2v power supply. dv12 j14 di 1.2v power supply. dv12 k5 di 1.2v power supply. dv12 k14 di 1.2v power supply. dv12 l5 di 1.2v power supply. dv12 l6 di 1.2v power supply. dv12 l7 di 1.2v power supply. dv12 l8 di 1.2v power supply. dv12 l9 di 1.2v power supply. dv12 l10 di 1.2v power supply. dv12 l11 di 1.2v power supply. dv12 l12 di 1.2v power supply. dv12 l13 di 1.2v power supply. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 15 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. signal name ball no. type description dv12 l14 di 1.2v power supply. dv12 m2 di 1.2v power supply. dv12 m3 di 1.2v power supply. dv12 n3 di 1.2v power supply. dv12 n4 di 1.2v power supply. dv12 b16 di 1.2v power supply. ddr_pp c6 di ddr pad 1.8v power supply ddr_pp d5 di ddr pad 1.8v power supply ddr_pp d6 di ddr pad 1.8v power supply ddr_pp e5 di ddr pad 1.8v power supply ddr_pp e6 di ddr pad 1.8v power supply ddr_pp f6 di ddr pad 1.8v power supply ddr_pp g6 di ddr pad 1.8v power supply ddr_pp g7 di ddr pad 1.8v power supply ddr_pp g8 di ddr pad 1.8v power supply ddr_pp g9 di ddr pad 1.8v power supply ddr_pp g10 di ddr pad 1.8v power supply ddr_pp g11 di ddr pad 1.8v power supply ddr_vref g12 di ddr pad 0.9v reference voltage ddr_gnd h6 di ground for ddr pad ddr_gnd h7 di ground for ddr pad ddr_gnd h8 di ground for ddr pad ddr_gnd h9 di ground for ddr pad ddr_gnd h10 di ground for ddr pad ddr_gnd h11 di ground for ddr pad ddr_gnd h12 di ground for ddr pad ddr_gnd h13 di ground for ddr pad 8 ecc descriptions please refer to fig. 4 that is a diagram illustrati ng an allocating method of a spare area in each pag e of a nand flash memory, where in the specific ecc a lgorithm utilizes a bose, chaudhuri and hocquengham (bch) ecc algorithm. when a bch 16 ecc algorithm encodes the data in the nand flash memory, the parity code generated in the encoding p rocess may occupy 28 bytes of the spare area in eac h page. when a bch 24 ecc algorithm encodes the data in the nand flash memory, the parity code generated in the encoding process may occupy 42 byt es of the spare area in each page. when a bch 16 algorithm decodes the data in the nan d flash memory, the data can be decoded correctly if the error bit happened in two sector ( 1024bytes) is 16. when a bch 24 algorithm decodes t he www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 16 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. data in the nand flash memory, the data can be deco ded correctly if the error bit happened in two sect or is 24. figure 7 allocation for ecc algorithm bch in nand flash 9 sata interface 9.1 out of bank signaling there shall be three out of band (oob) signals used /detected by the phy: comreset, cominit, and comwake. cominit, comreset and comwake oob sign aling shall be achieved by transmission of either a burst of four gen1 align p primitives or a burst composed of four gen1 dwords with each dword composed of four d24.3 characters, each burst having duration of 160 ui oob . each burst is followed by idle periods (at common-mode levels) , having durations as depicted in figure 5 and tabl e 2. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 17 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. figure 8 oob signals table 4 oob signal times 9.2 comreset comreset always originates from the host controller , and forces a hardware reset in the device. it is indicated by transmitting bursts of data separat ed by an idle bus condition. the oob comreset signa l shall consist of no less than six data bursts, incl uding inter-burst temporal spacing. the comreset signal shall be: 1) sustained/continued uninterrupted as long as the system hard reset is asserted, or 2) started durin g the system hardware reset and ended some time after the negation of system hardware reset, or 3) transmitted immediately following the negation of t he system hardware reset signal. the host controller shall ignore any signal receive d from the device from the assertion of the hardware reset signal until the comreset signal is transmitted. each burst shall be 160 gen1 uis long (106.7 ns) and each inter-burst idle state shall be 480 gen1 uis long (320 ns). a comreset detector looksfor four consecutive bursts with 320 ns spacin g (nominal). any spacing less than 175 ns or greate r www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 18 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. than 525 ns shall invalidate the comreset detector output. the comreset interface signal to the phy layer shall initiate the reset sequence shown in fi gure 6 below. the interface shall be held inactive for at least 525 ns after the last burst to ensure far-end detector detects the negation properly. figure 9 comreset sequence description: 1. host/device are powered and operating normally w ith some form of active communication. 2. some condition in the host causes the host to is sue comreset 3. host releases comreset. once the condition causi ng the comreset is released, the host releases the comreset signal and puts the bus in a quiescent condition. 4. device issues cominit C when the device detects the release of comreset, it responds with a cominit. this is also the entry point if the device is late starting. the device may initiate communications at any time by issuing a cominit. 5. host calibrates and issues a comwake. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 19 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 6. device responds C the device detects the comwake sequence on its rx pair and calibrates its transmitter (optional). following calibration the d evice sends a six burst comwake sequence and then sends a continuous stream of the align sequenc e starting at the device's highest supported speed. after alignp dwords have been sent for 54.6u s (2048 nominal gen1 dword times) without a response from the host as determined by detection o f alignp primitives received from the host, the device assumes that the host cannot communicate at that speed. if additional speeds are available the device tries the next lower supported speed by sending alignp dwords at that rate for 54.6 us (2048 nominal gen1 dword times.) this step is repea ted for as many slower speeds as are supported. once the lowest speed has been reached without resp onse from the host, the device enters an error state. 7. host locks C after detecting the comwake, the ho st starts transmitting d10.2 characters (see 7.6) a t its lowest supported rate. meanwhile, the host rece iver locks to the align sequence and, when ready, returns the align sequence to the device at the sam e speed as received. a host shall be designed such that it acquires lock in 54.6us (2048 nominal gen1 dword times) at any given speed. the host should allow for at least 873.8 us (32768 nominal g en1 dword times) after detecting the release of comwake to receive the first alignp. this ensures i nteroperability with multi-generational and synchronous designs. if no alignp is received withi n 873.8 us (32768 nominal gen1 dword times) the host restarts the power-on sequence C repeating indefinitely until told to stop by the application layer. 8. device locks C the device locks to the align seq uence and, when ready, sends syncp indicating it is ready to start normal operation. 9. upon receipt of three back-to-back non-alignp pr imitives, the communication link is established and normal operation may begin. 9.3 comini cominit always originates from the drive and reques ts a communication initialization. it is electrically identical to the comreset signal excep t that it originates from the device and is sent to the host. it is used by the device to request a reset f rom the host in accordance to the sequence shown in figure 7, below: www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 20 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. figure 10 cominit sequence description: 1. host/device are powered and operating normally w ith some form of active communication. 2. some condition in the device causes the device t o issues a cominit 3. host calibrates and issues a comwake. 4. device responds C the device detects the comwake sequence on its rx pair and calibrates its transmitter (optional). following calibration the d evice sends a six burst comwake sequence and then sends a continuous stream of the align sequenc e starting at the device's highest supported speed. after align p dwords have been sent for 54.6 us (2048 nominal gen 1 dword times) without a response from the host as determined by detection o f align p primitives received from the host, the device assumes that the host cannot communicate at that speed. if additional speeds are available the device tries the next lower supported speed by sending align p dwords at that rate for 54.6 us (2048 nominal gen1 dword times.) this step is repea ted for as many slower speeds as are supported. once the lowest speed has been reached without resp onse from the host, the device enters an error state. 5. host locks C after detecting the comwake, the ho st starts transmitting d10.2 characters (see www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 21 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. section 7.6) at its lowest supported rate. meanwhil e, the host receiver locks to the align sequence and, when ready, returns the align sequence to the device at the same speed as received. a host shall be designed such that it acquires lock in 54. 6 us (2048 nominal gen1 dword times) at any given speed. the host should allow for at least 873.8 us (32768 nominal gen1 dword times) after detecting the release of comwake to receive the first align p . this ensures interoperability with multi-generational and synchronous designs. if no a lign p is received within 873.8 us (32768 nominal gen1 dword times) the host restarts the power-on se quence C repeating indefinitely until told to stop by the application layer. 6. device locks C the device locks to the align seq uence and, when ready, sends sync p indicating it is ready to start normal operation. 7. upon receipt of three back-to-back non-align p primitives, the communication link is established a nd normal operation may begin. 9.4 power on sequence timing diagram the following timing diagrams and descriptions are provided for clarity and are informative. the state diagrams provided in section 8.4 comprise the norma tive behavior specification and is the ultimate reference figure 11 power on sequence description: www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 22 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 1. host/device power-off - host and device power-of f. 2. power is applied - host side signal conditioning pulls tx and rx pairs to neutral state (common mod e voltage). 3. host issues comreset 4. host releases comreset. once the power-on reset is released, the host releases the comreset signal and puts the bus in a quiescent condition. 5. device issues cominit C when the device detects the release of comreset, it responds with a cominit. this is also the entry point if the device is late starting. the device may initiate communications at any time by issuing a cominit. 6. host calibrates and issues a comwake. 7. device responds C the device detects the comwake sequence on its rx pair and calibrates its transmitter (optional). following calibration the d evice sends a six burst comwake sequence and then sends a continuous stream of the align sequenc e starting at the device's highest supported speed. after align p primitives have been sent for 54.6 us (2048 nominal gen1 dword times) without a response from the host as determined by detection of align p primitives received from the host, the device assumes that the host cannot communicate at that speed. if additional speeds are available the device tries the next lower supported speed by sending align p primitives at that rate for 54.6 us (2048 nominal gen1 dword times.) this step is repea ted for as many slower speeds as are supported. once the lowest speed has been reached without resp onse from the host, the device shall enter an error state. 8. host locks C after detecting the comwake, the ho st starts transmitting d10.2 characters (see 7.6) a t its lowest supported rate. meanwhile, the host rece iver locks to the align sequence and, when ready, returns the align sequence to the device at the sam e speed as received. a host shall be designed such that it acquires lock in 54.6 us (2048 nominal gen1 dword times) at any given speed. the host should allow for at least 873.8 us (32768 nominal g en1 dword times) after detecting the release of comwake to receive the first align p . this insures interoperability with multi-generati onal and synchronous designs. if no align p is received within 873.8 us (32768 nominal gen1 dwo rd times) the host restarts the power-on sequence C repeating indefinitely until told to stop by the application layer. 9. device locks C the device locks to the align seq uence and, when ready, sends the sync p primitive indicating it is ready to start normal operation. 10.upon receipt of three back-to-back non-align p primitives, the communication link is established a nd normal operation may begin. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 23 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. 9.5 ata command register this table with the following paragraphs summarizes the ata command set. table 5 command table parameters used command name code sc sn cy dr hd ft check power mode e5h x x x o x x execute diagnostics 90h x x x o x x flush cache e7h x x x o o x identify device ech x x x o x x idle e3h o x x o x x idle immediate e1h x x x o x x initialize device parameters 91h o x x o o x read dma c8h or c9h o o o o o x read multiple c4h o o o o o x read sector(s) 20h or 21h o o o o o x read verify sector(s) 40h or 41h o o o o o x recalibrate 10h x x x o x x security disable password f6h x x x o x x security erase prepare f3h x x x o x x security erase unit f4h x x x o x x security freeze lock f5h x x x o x x security set password f1h x x x o x x security unlock f2h x x x o x x seek 7xh x x o o o x set features efh o x x o x o set multiple mode c6h o x x o x x sleep e6h x x x o x x smart b0h x x o o x o standby e2h x x x o x x standby immediate e0h x x x o x x write dma cah or cbh o o o o o x www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 24 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. write multiple c5h o o o o o x write sector(s) 30h or 31h o o o o o x note: o = valid, x = don't care sc = sector count register sn = sector number register cy = cylinder low/high register dr = device select bit (device/head register bit 4) hd = head select bit (device/head register bit 3-0) ft = features register ata command specifications check power mode (e5h) the host can use this command to determine the curr ent power management mode. execute diagnositics (90h) this command performs the internal diagnostic tests implemented by the drive. see error register for dianostic codes. flush cache (e7h) this command is used by the host to request the dev ice to flush the write cache. if there is data in the write cache, that data shall be written to the media. the bsy bit shall remain set to one until al l data has been successfully written or an error occurs. identify device (ech) this commands read out 512bytes of drive parameter information. parameter information consists of the arrangement and value as shown in the follow ing table. this command enables the host to receive the identify drive information from the dev ice. table 6 identify device information default value word value f/v description 0 0040h f x f x general configuration bit-significant information: 15 0 = ata device 14-8 retired 7 1 = removable media device 6 obsolete www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 25 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. x f x f 5-3 retired 2 reserved 1 retired 0 reserved 1 xxxxh x number of logical cylinders table 7 identify device information default value ( continued ) word value f/v description 2 c837h v specific configuration 3 00xxh x number of logical heads 4-5 xxxxh x retired 6 xxxxh x number of logical sector per logical track 7-8 xxxxh v reserved for assignment by the compactflash_ asso ciation 9 000eh x retired 10-19 xxxxh f serial number (20 ascii characters) 20-21 xxxxh x retired 22 003fh x obsolete 23-26 xxxxh f firmware revision (8 ascii characters) 27-46 xxxxh f model number (40 ascii characters) 47 8000h f f f 15-8 80h 7-0 00h = reserved 01h = maximum number of 1 sectors on read/write mul tiple commands 48 4000h f reserved 49 2f00h f f f f f f f x capabilities 15-14 reserved for the identify packet device com mand. 13 1 = standby timer values as specified in th is standard are supported 0 = standby timer values shall be managed by the de vice 12 reserved for the identify packet device com mand. 11 1 = iordy supported 0 = iordy may be supported 10 1 = iordy may be disabled 9 1 = lba supported 8 1 = dma supported. 7-0 retired 50 4000h f f f x capabilities 15 shall be cleared to zero. 14 shall be set to one. 13-2 reserved. 1 obsolete www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 26 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. f 0 shall be set to one to indicate a device specific standby timer value minimum. 51 0280h x 15-8 pio data transfer cycle timing mode 7-0 reserved 52 0000h x obsolete 53 0007h f f f x 15-3 reserved 2 1 = the fields reported in word 88 are val id 0 = the fields reported in word 88 are not valid 1 1 = the fields reported in words 70:64 are valid 0 = the fields reported in words 70:64 are not vali d 0 1 = the fields reported in words 58:54 are valid 0 = the fields reported in words 58:54 are not vali d 54 xxxxh x number of current cylinders 55 00xxh x number of current heads 56 xxxxh x number of current sector per track 57-58 xxxxh x current capacity in sectors 59 0000h f v v 15-9 reserved 8 1 = multiple sector setting is valid 7-0 xxh = setting for number of sectors that sh all be transferred per interrupt on r/w multiple command 60-61 xxxxh f total number of user addressable sectors 62 0000h x obsolete 63 0007h f v v v f f f f 15-11 reserved 10 1 = multiword dma mode 2 is selected 0 = multiword dma mode 2 is not selected 9 1 = multiword dma mode 1 is selected 0 = multiword dma mode 1 is not selected 8 1 = multiword dma mode 0 is selected 0 = multiword dma mode 0 is not selected 7-3 reserved 2 1 = multiword dma mode 2 and below are supp orted 1 1 = multiword dma mode 1 and below are supp orted 0 1 = multiword dma mode 0 is supported 64 0003h f f 15-8 reserved 7-0 advanced pio modes supported 65 0078h f minimum multiword dma transfer cycle time per wor d 66 0078h f manufacturers recommended multiword dma transfer cycle time 67 0078h f minimum pio transfer cycle time without flow cont rol 68 0078h f minimum pio transfer cycle time with iordy flow c ontrol 69-79 0000h f reserved (for future command overlap and queuing) 80 01feh f f major version number 0000h or ffffh = device does n ot report version 15 reserved 14 reserved for ata/atapi-14 www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 27 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. f f f f f f f f f f f x x f 13 reserved for ata/atapi-13 12 reserved for ata/atapi-12 11 reserved for ata/atapi-11 10 reserved for ata/atapi-10 9 reserved for ata/atapi-9 8 reserved for ata/atapi-8 7 1 = supports ata/atapi-7 6 1 = supports ata/atapi-6 5 1 = supports ata/atapi-5 4 1 = supports ata/atapi-4 3 obsolete 2 obsolete 1 obsolete 0 reserved 81 0021h f minor version number 82 0068h x f f f x f f f f f f f f f f f command set supported. 15 obsolete 14 1 = nop command supported 13 1 = read buffer command supported 12 1 = write buffer command supported 11 obsolete 10 1 = host protected area feature set support ed 9 1 = device reset command supported 8 1 = service interrupt supported 7 1 = release interrupt supported 6 1 = look-ahead supported 5 1 = write cache supported 4 shall be cleared to zero to indicate that t he packet command feature set is not supported. 3 1 = mandatory power management feature set supported 2 1 = removable media feature set supported 1 1 = security mode feature set supported 0 1 = smart feature set supported 83 5000h f f f f f f f f f f f f command sets supported. 15 shall be cleared to zero 14 shall be set to one 13-9 reserved 8 1 = set max security extension supported 7 reserved 6 1 = set features subcommand required to spi nup after power-up 5 1 = power-up in standby feature set support ed 4 1 = removable media status notification fea ture set supported 3 1 = advanced power management feature set s upported 2 1 = cfa feature set supported 1 1 = read/write dma queued supported 0 1 = download microcode command supported 84 4000h f command set/feature supported extension. 15 shall be cleared to zero www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 28 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. f f f f 14 shall be set to one 13-2 reserved 1 1 = smart self-test supported 0 1 = smart error logging supported 85 0008h x f f f x v f v v v v f f f v v command set/feature enabled. 15 obsolete 14 1 = nop command enabled 13 1 = read buffer command enabled 12 1 = write buffer command enabled 11 obsolete 10 1 = host protected area feature set enabled 9 1 = device reset command enabled 8 1 = service interrupt enabled 7 1 = release interrupt enabled 6 1 = look-ahead enabled 5 1 = write cache enabled 4 shall be cleared to zero to indicate that t he packet command feature set is not supported. 3 1 = power management feature set enabled 2 1 = removable media feature set enabled 1 1 = security mode feature set enabled 0 1 = smart feature set enabled 86 5000h f f f f v v v f command set/feature enabled. 15-9 reserved 8 1 = set max security extension enabled by s et max set password 7 see address offset reserved area boot, inci ts tr27:2001 6 1 = set features subcommand required to spi n-up after power-up 5 1 = power-up in standby feature set enabled 4 1 = removable media status notification fea ture set enabled 3-1 1 = advanced power management feature set e nabled 0 1 = download microcode command supported 87 4000h f f f f f command set/feature default. 15 shall be cleared to zero 14 shall be set to one 13-2 reserved 1 1 = smart self-test supported 0 1 = smart error logging supported 88 203fh v v v v v f 15-13 reserved 12 1 = ultra dma mode 4 is selected 0 = ultra dma mode 4 is not selected 11 1 = ultra dma mode 3 is selected 0 = ultra dma mode 3 is not selected 10 1 = ultra dma mode 2 is selected 0 = ultra dma mode 2 is not selected 9 1 = ultra dma mode 1 is selected 0 = ultra dma mode 1 is not selected 8 1 = ultra dma mode 0 is selected 0 = ultra dma mode 0 is not selected 7-5 reserved www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 29 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. f f f f f 4 1 = ultra dma mode 4 and below are supporte d 3 1 = ultra dma mode 3 and below are supporte d 2 1 = ultra dma mode 2 and below are supporte d 1 1 = ultra dma mode 1 and below are supporte d 0 1 = ultra dma mode 0 is supported 89 0000h f time required for security erase unit completion 90 0000h f time required for enhanced security erase complet ion 91 0000h v current advanced power management value 92 0000h v master password revision code 93 0000h x hardware reset result 94-126 0000h v reserved 127 0000h f f removable media status notification feature set sup port 15-2 reserved 1-0 00 = removable media status notification fe ature set not supported 01 = removable media status notification feature su pported 10 = reserved 11 = reserved 128 0001h f v f f v v v v f security status 15-9 reserved 8 security level 0 = high, 1 = maximum 7-6 reserved 5 1 = enhanced security erase supported 4 1 = security count expired 3 1 = security frozen 2 1 = security locked 1 1 = security enabled 0 1 = security supported 129-159 0000h x vendor specific 160-254 0000h x reserved 255 0000h x integrity word 15-8 checksum 7-0 signature key: f/v = fixed/variable content f = the content of the word is fixed and does not c hange. for removable media devices, these values ma y change when media is removed or changed. v = the contents of the word is variable and may ch ange depending on the state of the device or the co mmands executed by the device. x = the content of the word may be fixed or variabl e. idle (e3h) this command causes the device to set bsy, enter th e idle mode, clear bsy and generate an interrupt. if sector count is non-zero, the automat ic power down mode is enabled. if the sector count is www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 30 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. zero, the automatic power mode is disabled. idle immediate (e1h) this command causes the device to set bsy, enter th e idle(read) mode, clear bsy and generate an interrupt. initialize device parameters (91h) this command enables the host to set the number of sectors per track and the number of tracks per heads. read dma (c8h) reads data from sectors during ultra dma and multiw ord dma transfer. use the set features command to specify the mode value. a sector count o f zero requests 256 sectors. read multiple (c4h) this command performs similarly to the read sectors command. interrupts are not generated on each sector, but on the transfer of a block which c ontains the number of sectors defined by a set multiple command. read sector(s) (20h/21h) this command reads 1 to 256 sectors as specified in the sector count register from sectors which is set by sector number register. a sector count of the requests 256 sectors. the transfer beings specified in the sector number register. read verify sector(s) (40h/41h) this command verifies one or more sectors on the dr ive by transferring data from the flash media to the data buffer in the drive and verifying that the ecc is correct. this command is identical to the r ead sectors command, except that drq is never set and n o data is transferred to the host. recalibrate (10h) the current drive performs no processing if it rece ives this command. it is supported for backward compatibility with previous devices. security disable password (f6h) disables any previously set user password and cance ls the lock. the host transfers 512 bytes of data, as shown in the following table, to the drive . the transferred data contains a user or master password, which the drive compares with the saved p assword. if they match, the drive cancels the lock. the master password is still saved. it is re-enable d by issuing the security set password command to re-set a user password. security erase prepare (f3h) www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 31 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. this command shall be issued immediately before the security erase unit command to enable erasing and unlocking. this command prevents accide ntal loss of data on the drive. security erase unit (f4h) the host uses this command to transfer 512 bytes of data, as shown in the following table, to the drive. the transferred data contains a user or mast er password, which the drive compares with the saved password. if they match, the drive deletes us er data, disables the user password, and cancels the lock. the master password is still saved. it is re-enabled by issuing the security set password command to re-set a user password. security freeze lock (f5h) causes the drive to enter frozen mode. once this co mmand has been executed, the following commands to update a lock result in the aborted com mand error: ? security set password ? security unlock ? security disable password ? security erase prepare ? security erase unit the drive exits from frozen mode upon a power-off o r hard reset. if the security freeze lock command is issued when the drive is placed in froze n mode, the drive executes the command, staying in frozen mode. security set password (f1h) this command set user password or master password. the host outputs sector data with pio data-out protocol to indicate the information defin ed in the following table. security unlock (f2h) this command disabled locked mode of the device. th is command transfers 512 bytes of data from the host with pio data-out protocol. the follo wing table defines the content of this information. seek (7xh) this command is effectively a nop command to the de vice although it does perform a range check. set features (efh) this command set parameter to features register and set drives operation. for transfer mode, paramete r is set to sector count register. this command is us ed by the host to establish or select certain featu res. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 32 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. table 8 features register value and settable operating mode value function 02h enable write cache 03h set transfer mode based on value in sector coun t register. 55h disable read look-ahead feature 82h disable write cache aah enable read look-ahead feature set multiple mode (c6h) this command enables the device to perform read mul tiple and write multiple operations and establishes the block count for these commands. sleep (e6h) this command causes the device to set bsy, enter th e sleep mode, clear bsy and generate an interrupt. smart function set (b0h) performs different processing required for predicti ng device failures, according to the subcommand specified in the features register. if the features register contains an unsupported value, the aborte d command error is returned. if the smart function is disabled, any subcommand other than smart enable operations results in the aborted command er ror. standby (e2h) this command causes the device to set bsy, enter th e sleep mode (which corresponds to the atastandby mode), clear bsy and return the interr upt immediately. standby immediate (e0h) this command causes the drive to set bsy, enter the sleep mode (which corresponds to the ata standby mode), clear bsy and return the interrupt immediately. write dma (cah) write data to sectors during ultra dma and multiwor d dma transfer. use the set features command to specify the mode value. write multiple (c5h) this command is similar to the write sectors comman d. interrupts are not presented on each sector, but on the transfer of a block which contai ns the number of sectors defined by set multiple command. www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 33 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. write sector(s) (30h/31h) write data to a specified number of sectors (1 to 2 56, as specified with the sector count register) from the specified address. specify 00h to write 256 sectors. 10 electrical characteristics 10.1 absolute maximum rating parameter symbol condition min max unit analog power supply avddh -0.5 6 v digital i/o power supply dvdd -0.5 6 v digital i/o input voltage v i(d) -0.4 dvdd+0.4 v storage temperature t storage -55 140 o c 10.2 recommended power supply operation conditions and temperature parameter symbol condition min typical max unit pv33 3.0 3.3 3.6 v operation digital power supply d1v2 -5% 1.2 +5% v asv33 3.0 3.3 3.6 v asv12 -5% 1.2 +5% v operation analog power supply avddh 3.0 3.3 3.6 v operation ddr_pp power supply ddr_pp 1.7 1.8 1.9 v operation ddr_vref power supply ddr_vref vref=0.5x ddr_pp 0.85 vref 0.95 v ambient operation temperature t a for commercial spec. 0 70 o c ambient operation temperature t a for industry spec. -40 85 o c junction temperature t j 125 o c case operation temperature t c for commercial spec and base on t a 85 o c case operation temperature t c for industry spec and base on t a 100 o c www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 34 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. tfbga ?ball jc o c/w tfbga ?ball ja o c/w 10.3 recommended external clock source conditions parameter symbol condition min typical max unit external reference clock 30 mhz clock duty cycle 45 50 55 % 10.4 power supply dc characteristics (sata idle mo de and power saving mode disable) power supply: pcs sata 5v input. (max=peak) parameter symbol condition min typical max unit i pv33 3.3v 7 14 ma digital power supply i dv12 1.2v 272 373 ma usb analog power supply i avddh 3.3v 6 18 ma i asv33 3.3v 34 41 ma sata analog power supply sata analog power supply i asv12 1.2v 61 68 ma ddr pad and ddrii i ddr_pp 1.8v 143 162 ma 10.5 power supply dc characteristics (sata active mode) power supply: pcs sata 5v input. (max=peak) parameter symbol condition min typical max unit i pv33 3.3v 44 103 ma digital power supply i dv12 1.2v 320 442 ma usb analog power supply i avddh 3.3v 6 18 ma i asv33 3.3v 34 41 ma sata analog power supply sata analog power supply i asv12 1.2v 61 67 ma ddr pad and ddrii i ddr_pp 1.8v 135 302 ma 10.6 i/o dc characteristics parameter symbol condition min typical max unit input low voltage v il 0.8 v input high voltage v ih 2.4 v www.datasheet.co.kr datasheet pdf - http://www..net/
JMF612 sataii to flash controller revision1.04 35 document no.:61x-00002 the information contained in this document is the e xclusive property of jmicron technology corporation and shall not be used, collected, reproduced, distributed and/or disclosed in whole or in part without prior written permissi on of jmicron technology corporation. hard copies or electronic files downlo aded from jmicron document control system are for r eference only. please enter jmicron document control system to access updated d ocuments or download updated documents from the aut horized ftp site. parameter symbol condition min typical max unit output low voltage v ol 1.5 v output high voltage v oh 3.3 v www.datasheet.co.kr datasheet pdf - http://www..net/
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