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s3c7044/c7048/p7048 product overview 1 - 1 1 product overview the s3c7044/c7048 single-chip cmos microcontroller has been designed for very high - performance using samsung's newest 4 -b it cpu core, sam47 (samsung arrangeable microcontrollers). the S3P7048 is the microcontroller which has 8k-bytes one-time-programmable rom and the functions are same to s3c7044/c7048. with two 8-bit timer / counters, an 8-bit serial i/o interface, and eight software n-channel open-drain i/o pins, the s3c7044/c7048 offers an excellent design solut io n for a wide variety of general-purpose applicat ions . up to 36 pins of the 42-pin sdip or 44-pin qfp package can be dedicated to i/o . seven vectored interrupts provide fast response to internal and external events. in additio n, the s3c7044/c7048 's advanced cmos technology provides for low power consumpt io n and a wide operating voltage range.
product overview s3c7044/c7048/p7048 1 - 2 features summary memory 512 4-bit ram 4096 8-bit rom: s3c7044 8192 8-bit rom: s3c7048 36 i/o pins input only: 4 pins i/o: 24 pins n-channel open-drain i/o: 8 pins memory-mapped i/o structure data memory bank 15 8-bit basic timer 4 interval timer functions two 8-bit timer/counters programmable interval timer external event counter function timer/counters clock outputs to tclo0 and tclo1 pins watch timer time interval generation: 0.5 s, 3.9 ms at 4.19 mhz 4 frequency outputs to the buz pin 8-bit serial i/o interface 8-bit transmit/receive mode 8-bit receive mode lsb-first or msb-first transmission selectable bit sequential carrier supports 16-bit serial data transfer in arbitrary format interrupts 3 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts power-down modes idle: only cpu clock stops stop: system clock stops oscillation sources crystal or ceramic for system clock oscillation frequency : 0.4 ? 6.0mhz cpu clock divider circuit (by 4. 8, or 64) instruction execution times 0.95, 1.91, 15.3 m s at 4.19 mhz 0.67, 1.33, 10.7 m s at 6.0 mhz operating temperature - 40 c to 85 c operating voltage range 1.8 v to 5.5 v (main) 2.0 v to 5.5 v (otp) package types 42-pin sdip, 44-pin qfp
s3c7044/c7048/p7048 product overview 1 - 3 function overview sam47 cpu all s3c7-series microcontrollers have the advanced sam47 cpu core. the sam47 cpu can directly address up to 32k-byte of program memory. the arithmetic logic unit(alu) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operation in two cycles. cpu registers program counter a 12-bit program counter (pc) stores addresses for instruction fetches during program execution. usually, the pc is incremented by the number of bytes of the fetched instruction. the one instruction fetch that does not increment the pc is the 1-byte ref instruction which references instruction stored in a look-up table in the rom. whenever a reset operation or an interrupt occurs, bits pc12 though pc0 are set to the vector address. stack pointer an 8-bit stack pointer (sp) stores addresses for stack operation. the stack area is located in general-purpose data memory bank 0. the sp is 8-bit read/writeable and sp bit 0 must always be logic zero. during an interrupt or a subroutine call, the pc value and the psw are written to the stack area. when the service routine has completed, the values referenced by the stack pointer are restored. then, the next instruction is executed. the stack pointer can access the stack despite data memory access enable flag status. since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00h. this sets the first register of the stack area to data memory location 0ffh. program memory in its standard configuration, the 4096 x 8-bit (s3c7404), 8192 x 8-bit (s3c7408) rom is divided into four areas: ? 16-byte area for vector addresses ? 96-byte instruction reference area ? 16-byte general-purpose area (0010 ? 001fh) ? 3968-byte area for general-purpose program memory ( s3c7404) ? 8064-byte area for general-purpose program memory ( s3c7408) the vector address area is used mostly during reset operation and interrupts. these 16 bytes can alternately be used as general-purpose rom. the ref instruction references 2x1-byte or 2-byte instruction stored in reference area location 0020h ? 007fh. ref can also reference three-byte instruction such as jp or call. so that a ref instruction can reference these instruction, however, the jp or call must be shortened to a 2-byte format. to do this, jp or call is written to the reference area with the format tjp or tcall instead of the normal instruction name. unused location in the ref instruction look-up area can be allocated to general-purpose use.
product overview s3c7044/c7048/p7048 1 - 4 data memory overview the 512 x 4bit data memory has five areas: ? 32 x 4-bit working register area ? 224 x 4-bit general-purpose area in bank 0 which is also used as the stack area ? 256 x 4-bit general-purpose area in bank 1 ? 128 x 4-bit area in bank 15 for memory-mapped i/o addresses the data memory area is also organized as three memory banks ? bank0, bank1, and bank15. you use the select memory bank instruction (smb) to select one of the banks as working data memory. data stored in ram location are 1-, 4-, and 8-bit addressable. after a hardware reset, data memory initialization values must be defined by program code. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is logic zero, only location 00h?7fh of bank 0 and bank 15 can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed based on the current smb value. working registers the ram's working register area in data memory bank 0 is also divided into four register banks. each register bank has eight 4-bit registers. paired 4-bit registers are 8-bit addressable. register a can be used as a 4-bit accumulator and double register ea as an 8-bit extended accumulator; double registers wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for main programs and banks 1, 2, and 3 for interrupt service routines. bit sequential carrier the bit sequential carrier (bsc) mapped in data memory bank 15 is a 16-bit general register that you can manipulate using 1-, 4-, and 8-bit ram control instructions. using the bsc register, addresses and bit location can be specified sequentially using 1-bit indirect addressing instructions. in this way, a program can generate 16-bit data output by moving the bit location sequentially, incrementing or decrementing the value of the l register. you can also use direct addressing to manipulate data in the bsc.
s3c7044/c7048/p7048 product overview 1 - 5 control registers program status word the 8-bit program status word (psw) controls alu operation and instruction execution sequencing. it is also used to restore a program's execution environment when an interrupt has been serviced. program instructions can always address the psw regardless of the current value of data memory access enable flags. before an interrupt is processed, the psw is pushed onto the stack in data memory bank 0. when the routine is completed, psw values are restored. is1 is0 emb erb c sc2 sc1 sc0 interrupt status flags (is1, is0), the enable memory bank and enable register bank flags (emb, erb), and the carry flag ( c ) are 1- and 4-bit read/write or 8-bit read-only addressable. skip condition flags (sc0?sc2) can be addressed using 8-bit read instructions only. select bank (sb) register two 4-bit location called the sb register store address values used to access specific memory and register banks: the select memory bank register, smb, and the select register bank register, srb. 'smb n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data memory address in the smb register. the 'smb n' instruction is used to select register bank 0, 1, 2, or 3, and to store the address data in the srb. the instructions 'push sb' and 'pop sb' move smb and srb values to and from the stack for interrupts and subroutines. clock circuits system oscillation circuit generates the internal clock signals for the cpu and peripheral hardwares. the system clock can use a crystal, ceramic, or rc oscillation source, or an externally-generated clock signal. to drive s3c7044/c7048 using an external clock source, the external clock signal should be input to x in , and its inverted signal to x out . a 4-bit power control register is used to enable or disable oscillation, and to select the cpu clock. the internal system clock signal (fx) can be divided internally to produce three cpu clock frequencies ? fx/4, fx/8, or fx/64. interrupts interrupt requests can be generated internally by on-chip processes (intb, intt0, intt1, and ints) or externally by peripheral devices (int0, int1, and int4). there are two quasi-interrupts: int2 and intw. int2/ks0?ks7 detects rising/falling edges of incoming signals and intw detects time intervals of 0.5 seconds of 3.91 milliseconds at 4.19mhz. the following components support interrupt processing: ? interrupt enable flags ? interrupt request flags ? interrupt pr iority registers ? power-down termination circuit
product overview s3c7044/c7048/p7048 1 - 6 power-down to reduce power consumption, there are two power-down modes: idle and stop. the idle instruction initiates idle mode and the stop instruction initiates stop mode. in idle mode, only the cpu clock stops while peripherals and the oscillation source continue to operate normally. stop mode effects only the system clock. in stop mode system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. reset or an interrupt (with the exception of int0) can be used to terminate either idle or stop mode. reset reset when a reset signal occurs during normal operation or during power-down mode, the cpu enters idle mode when the reset operation is initiated. when the standard oscillation stabilization interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. i/o ports the s3c7044/c7048 has 9 i/o ports. pin addresses for all i/o ports are mapped to locations ff0h?ffch in bank 15 of the ram. there are 4 input pins, 24 configurable i/o pins, and 8 software n-channel open-drain i/o pins, for a total of 36 i/o pins. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. timers and timer/counters the timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch timer. the 8-bit basic timer generates interrupt requests at precise intervals, based on the selected cpu clock frequency. the programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock frequencies for output, and dividing external clock signals. the 8-bit timer/counter 0 generates a clock signal ( sck ) for the serial i/o interface. the watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. its functions include real-time and watch-time measurement, and frequency outputs for buzzer sound. serial i/o interface the serial i/o interface supports the transmission or reception of 8-bit serial data with an external device. the serial interface has the following functional components: ? 8-bit mode register ? clock selector circuit ? 8-bit buffer register ? 3-bit serial clock counter the serial i/o circuit can be set either to transmit-and-receive or to receive-only mode. msb-first or lsb-first transmission is also selectable. the serial interface operates with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter 0. to modify transmission frequency, the appropriate bits in the serial i/o mode register (smod) must be manipulated.
s3c7044/c7048/p7048 product overview 1 - 7 block diagram p4.0?p4.3 p5.0?p5.3 p6.0?p6.3 / ks0?ks3 p7.0?p7.3 / ks4?ks7 arithmetic and logic unit interrupt control block instruction register program counter program status word 512 x 4-bit data memory program memory 4 kbyte: s3c7404 8 kbyte: s3c7408 8-bit timer/ counter 0 stack pointer instruction decoder clock reset xin xout internal interrupts i/o port 4 i/o port 5 8-bit timer/ counter 1 i/o port 6 i/o port 7 int0, int1, int2,int4 ba s ic timer watch timer p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco i/o port 0 serial i/o p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 input port 1 p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz i/o port 2 p3.0 / tcl0 p3.1 / tcl1 p3.2 p3.3 i/o port 3 p8.0?p8.3 i/o port 8 figure 1 -1 . s3c7044/c7048/p0408 block diagram
product overview s3c7044/c7048/p7048 1 - 8 pin assignments p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p8.3 p8.2 p8.1 p8.0 p3.3 p3.2 p3.1/tcl1 p3.0/tcl0 v dd s3c7044/c7048 (42-sdip-600) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 v ss p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 x in x out reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 test 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 figure 1 -2 . s3c7044/c7048 pin assignment diagrams (42-sdip pakage)
s3c7044/c7048/p7048 product overview 1 - 9 p5.3 p5.2 p5.1 p5.0 reset x out x in p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 s3c7044/c7048 (44-qfp-1010b) 1 2 3 4 5 6 7 8 9 10 11 nc p8.0 p8.1 p8.2 p8.3 p0.0/ sck p0.1/so p0.2/si p0.3/btco p2.0/tclo0 p2.1/tclo1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 nc p3.3 p3.2 p3.1/tcl1 p3.0/tcl0 v dd test p4.3 p4.2 p4.1 p4.0 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 v ss p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p2.3/buz p2.2/clo figure 1 -3 . s3c7044/c7048 pin assignment diagrams (44-qfp pakage)
product overview s3c7044/c7048/p7048 1 - 10 pin descript io ns table 1 - 1. s3c7044/c7048/p0408 pin descri ption pin name pin type descript ion number share pin p0.0 p0.1 p0.2 p0.3 i / o 4-bit i/o port. 1-bit or 4-bit read / write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up re sistors are automatically disabled for output pins. 12 (28) 11 (27) 10 (26) 9 (25) sck so si btco p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are assignable by software to pins p1.0, p1.1, and p1.2. 4 (20) 3 (19) 2 (18) 1 (17) int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i/o same as port 0. 8 (24) 7 (23) 6 (22) 5 (21) tclo0 tclo1 clo buz p3.0 p3.1 p3.2 p3.3 i/o same as port 0. 20 (38) 19 (37) 18 (36) 17 (35) tcl0 tcl1 p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. n-channel open-drain output up to 9 volts. 1-bit and 4-bit read / write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. 8-bit unit pull-up resistors are assignable by mask option. 26?23 (44?41) 30?27 (4?1) ? p6.0?p6.3 p7.0?p7.3 i/o 4-bit i/o ports. 1-bit or 4-bit read / write and test is possible. port 6 pins are individually software configurable as input or output. 4-bit pull -up resistors are software assignable; pull-up re sistors are automatically disabled for output pins (port 6 only). ports 6 and 7 can be paired to enable 8-bit data transfer. 37?34 (11?8) 41?38 (15?12) ks0?ks3 ks4?ks7 p8.0?p8.3 i/o 4-bit i/o ports. 1-bit and 4-bit read / write and test is possible. pins are individually soft ware configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down resistors are auto matically disabled for output pins. 16?13 (32?29) ? note: parentheses indicate pin number for 44 qfp package.
s3c7044/c7048/p7048 product overview 1 - 11 table 1 - 1. s3c7044/c7048 pin descript ions (continued) pin name pin type descript ion number share pin sck i/o serial i/o interface clock signal 12 (28) p0.0 so i/o serial data output 11 (27) p0.1 si i/o serial data input 10 (26) p0.2 btco i/o basic timer clock output (2 hz, 16 hz, 64 hz, or 256 hz at 4.19 mhz) 9 (25) p0.3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. int0 is synchronized to system clock. 4, 3 (20, 19) p1.0, p1.1 int2 i quasi-interrupt with detect ion of rising edges 2 (18) p1.2 int4 i external interrupt with detect ion of rising and falling edges. 1 (17) p1.3 tclo0 i/o timer / counter 0 clock output 8 (24) p2.0 tclo1 i/o timer / counter 1 clock output 7 (23) p2.1 clo i/o clock output 6 (22) p2.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at 4.19 mhz for buzzer sound 5 (21) p2.3 tcl0 i/o external clock input for timer / counter 0 20 (38) p3.0 tcl1 i/o external clock input for timer / counter 1 19 (37) p3.1 ks0?ks3 ks4?ks7 i/o quasi-interrupt inputs with falling edge detect ion 37?34 (11?8) 41?38 (15?12) p6.0?p6.3 p7.0?p7.3 v dd ? power supply 21 (39) ? v ss ? ground 42 (16) ? reset i reset signal 31 (5) ? x in , x out ? crystal, ceramic, or rc oscillator signal for system clock (for external clock input, use x in and input x in 's reverse phase to x out ) 33, 32 (7, 6) ? test ? test signal input (must be connected to v ss ) 22 (40) ? nc ? no connect ion (must be connected to v ss ) (33, 34) ? note: parentheses indicate pin number for 44 qfp package.
product overview s3c7044/c7048/p7048 1 - 12 table 1 - 2. overview of s3c7044/c7048 pin data pin names share pins i/o type reset value circuit type p0.0?p0.3 sck , so, si, btco i/o input d-1 p1.0?p1.2 int0, int1, int2 i input a-3 p1.3 int4 i input b-4 p2.0?p2.3 tclo0, tclo1, clo, buz i/o input d p3.0?p3.1 tcl0, tcl1 i/o input d-1 p3.2?p3.3 ? i/o input d p4.0?p4.3 p5.0?p5.3 ? i/o (note) e-2 p6.0?p6.3 p7.0?p7.3 ks0?ks3 ks4?ks7 i/o input d-1 p8.0?p8.3 ? i/o input d-2 x in , x out ? ? ? ? reset ? i ? b test ? i ? ? nc ? ? ? ? v dd , v ss ? ? ? ? note : when pull-up resistors are provided, port 4 and port 5 pins are reset to high level; with no pull-ups, they are reset to high impedance.
s3c7044/c7048/p7048 product overview 1 - 13 pin circuit diagrams p - channel in n - channel v dd figure 1-4. pin circuit type a p - channel pull-up resistor pull-up resistor enable schmitt trigger in v dd figure 1-5. pin circuit type a-3 in v dd pull-up resistor schmitt trigger figure 1-6. pin circuit type b schmitt trigger in figure 1-7. pin circuit type b-4
product overview s3c7044/c7048/p7048 1 - 14 p - channel data output disable out n - channel v dd figure 1-8. pin circuit type c p - channel pull-up resistor resistor enable circuit type c data output disable circuit type a i/o v dd figure 1-9. pin circuit type d p - channel pull-up resistor resistor enable circuit type c data output disable schmitt trigger i/o v dd figure 1-10. pin circuit type d-1 n - channel pull-down resistor resistor enable circuit type c data output disable circuit type a i/o figure 1-11. pin circuit type d-2
s3c7044/c7048/p7048 product overview 1 - 15 data output disable v dd i/o n - channel figure 1-12. pin circuit type e-2
s3c7044/c7048/p7048 address spaces 2- 1 2 address spaces program memory (rom) overview rom maps for s3c7044/c7048 devices are mask programmable at the factory. in its standard configuration, the device's 4096 8-bit (s3c7044) or 8192 8-bit (s3c7048) program memory has four areas that are directly addressable by the program counter ( pc): ? 16-byte area for vector addresses ? 16-byte general-purpose area ? 96-byte instruction reference area ? 3968-byte general-purpose area: s3c7044 ? 8064-byte general-purpose area: s3c7048 general-purpose program memory two program memory areas are allocated for general-purpose use: one area is 16 bytes and the other is 3968 (s3c7044) or 8064 (s3c7048) bytes. vector addresses a 16-byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to initialize the corresponding service routines. the 16-byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and three-byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2-1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h?000fh 16 general-purpose program memory 0010h?001fh 16 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h?0fffh 0080h?1fffh 3968 (s3c7044) 8064 (s3c7048)
address spaces s3c70 44/c7048/p7048 2- 2 general-purpose memory areas the 16-byte area at rom locations 0010h?001fh and 8064-byte area at rom locations 0080h?1fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 16-byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 16-byte vector addresses are organized as follows: emb erb 0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 note: pc12 is only for s3c7048. in s3c7044, the value of pc12 is always "0". to set up the vector address area for specific programs, use the instruction ventn. the programming tip on the next page explains how to do this. general-purpose area (16 bytes) general-purpose area vector address area (16 bytes) instruction reference area (96 bytes) 0000h 000fh 0010h 0 01fh 0020h 007fh 0080h 1 fffh general-purpose area 0fffh 1000h s3c7044 (3,968 bytes) s3c7048 (8,064 bytes) figure 2-1. rom address structure 7 6 5 4 3 2 1 0 reset intb/int4 int0 int1 ints intt0 intt1 0000h 0002h 0004h 0006h 0008h 000ah 000ch figure 2-2. vector address map
s3c7044/c7048/p7048 address spaces 2- 3 f f p rogramming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0,reset ; emb 1, erb 0; jump to reset address vent1 0,0,intb ; emb 0, erb 0; jump to intb address vent2 0,0,int0 ; emb 0, erb 0; jump to int0 address vent3 0,0,int1 ; emb 0, erb 0; jump to int1 address vent4 0,0,ints ; emb 0, erb 0; jump to ints address vent5 0,0,intt0 ; emb 0, erb 0; jump to intt0 address vent6 0,0,intt1 ; emb 0, erb 0; jump to intt1 address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0,reset ; emb 1, erb 0; jump to reset address vent1 0,0,intb ; emb 0, erb 0; jump to intb address ; org 0006h ; int0 interrupt not used ; vent3 0,0,int1 ; emb 0, erb 0; jump to int1 address vent4 0,0,ints ; emb 0, erb 0; jump to ints address ; org 00c0h ; intt0 interrupt not used ; vent6 0,0,intt1 ; emb 0, erb 0; jump to intt1 address ; org 0010h ; intt0 interrupt not used 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h ; vent0 1,0,reset ; emb 1, erb 0; jump to reset address vent1 0,0,intb ; emb 0, erb 0; jump to intb address vent3 0,0,int1 ; emb 0, erb 0; jump to int0 address vent4 0,0,ints ; emb 0, erb 0; jump to int1 address vent5 0,0,intt0 ; emb 0, erb 0; jump to ints address vent6 0,0,intt1 ; emb 0, erb 0; jump to intt0 address ; org 0010h ; general-purpose rom area in this example, when an ints interrupt is generated, the corresponding vector area is not vent4 ints, but vent5 intt0. this causes an ints interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
address spaces s3c70 44/c7048/p7048 2- 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger byte sizes that are stored in addresses 0020h?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instructions, a single two-byte instruction, or three-byte instructions such as a jp or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: by the ref instructions to execute instructions larger than one byte, you can improve program size considerably. in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. f f programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) a incs hl ? ? ? abc ld ea,#00h ; 47, ea #00h org 0080 ; main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,# 00h (1-byte instruction) ? ? ?
s3c7044/c7048/p7048 address spaces 2- 5 data memory (ram) overview in its standard configuration, the 512 4 -bit data memory has four areas: ? 32 4-bit working register area ? 224 4 -bit general-purpose area (also used as stack area) ? 256 4 -bit general-purpose area ? 128 4-bit area for memory-mapped i/o addresses to make it easier to reference, the data memory area has three memory banks ? bank 0, bank 1, and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following reset . however, when reset signal is generated in power-down mode, the data memory contents are held. 000h 01fh 020h 0ffh 100h 1ffh f80h fffh working registers (32 x 4 bits) memory-mapped i/o address registers (256 x 4 bits) general-purpose registers and stack area (224 x 4 bits ) general-purpose registers (256 x 4 bits) ~ ~ bank 1 bank 15 bank 0 figure 2?3. data memory (ram) map
address spaces s3c70 44/c7048/p7048 2- 6 memory banks 0, 1, and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (100h?1ffh) the 256 nibbles of bank 1 (100h?1ffh) are for general-purpose use. bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h?07fh of bank 0 and bank 15 (f80h?fffh). with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines.
s3c7044/c7048/p7048 address spaces 2- 7 table 2-2. data memory organization and addressing addresses register areas bank emb value smb value 000h?01fh working registers 0 0, 1 0 020h?0ffh stack and general-purpose registers 100h?1ffh general-purpose registers 1 1 1 f80h?fffh i/o-mapped hardware registers 15 0, 1 15 f f programming tip ? clearing data memory banks 0 and 1 clear bank 0 of the data memory area: ramclr smb 1 ; ram (100h?1ffh) clear ld hl ,#00h ld a,#0h rmcl1 ld @hl,a incs hl jr rmcl1 ; smb 0 ; ram (010h?0ffh) clear ld hl,#10h rmcl0 ld @hl,a incs hl jr rmcl0
address spaces s3c70 44/c7048/p7048 2- 8 working registers working registers, mapped to ram address 000h-01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4- bit units or, using paired registers, as 8-bit units. 000h 0001 002h 003h 004h 005h 006h 007h 00fh 010h 017h 018h 01fh 008h a e l h x w z y a ... y register bank 1 register bank 2 register bank 3 a ... y a ... y working register bank 0 data memory bank 0 figure 2-4. working register map
s3c7044/c7048/p7048 address spaces 2- 9 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou - tines. following this convention helps to prevent possible data corruption during program execution due to con - tention in register bank addressing. table 2-3. working register organization and addressing erb setting srb settings selected register bank 3 2 1 0 0 0 0 x x always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note : 'x' means don't ca re. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e and a, can either be manipulated individually using 4-bit instructions, or together as register pairs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz and wl. registers a, l, x and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2-5. register pair configuration
address spaces s3c70 44/c7048/p7048 2- 10 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 8-bit accumulator 1-bit accumulator 4-bit accumulator figure 2-6. 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory using the pop instruction.
s3c7044/c7048/p7048 address spaces 2- 11 f f programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb 1, erb 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea register contents from stack pop y z ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb 1, erb 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
address spaces s3c70 44/c7048/p7048 2- 12 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp is mapped to ram addresses f80h?f81h, and can be read or written by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next in struction is executed. the sp can address stack registers in bank 0 (addresses 000h-0ffh) regardless of the current value of the en - able memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. f f p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 15 ; select memory bank 15 ld ea,#00h ; bit 0 of accumulator a is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) (sp) ? 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h?7fh, f80h?fffh)
s3c7044/c7048/p7048 address spaces 2- 13 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decremented by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decremented by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decremented by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. sp ? 2 sp ? 1 sp lower register upper register push (after push, sp sp ? 2) sp ? 6 sp ? 5 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp sp ? 6 sp ? 5 sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp call (after call, sp sp ? 6) 0 0 pc3 ? pc0 pc7 ? pc4 0 0 emb erb 0 0 0 0 pc12 0 pc11-pc8 interrupt (when int is acknowledged, sp sp ? 6) 0 0 pc3 ? pc0 pc7 ? pc4 is1 is0 emb erb psw c sc2 sc1 sc0 pc12 0 pc11-pc8 figure 2-7. push-type stack operations
address spaces s3c70 44/c7048/p7048 2- 14 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. lower register upper register pop (sp sp + 2) ret or sret ( sp sp + 6) 0 0 pc3 ? pc0 pc7 ? pc4 0 0 emb erb 0 0 0 0 pc12 0 pc11-pc8 iret (sp sp + 6) 0 0 pc3 ? pc0 pc7 ? pc4 is1 is0 emb erb psw c sc2 sc1 sc0 pc12 0 pc11-pc8 sp sp + 1 sp + 2 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 sp sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp + 6 figure 2-8. pop-type stack operations
s3c7044/c7048/p7048 address spaces 2- 15 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing (memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decrementing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2-4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 f f programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 a, bsc1 e ld ea,#59h ; ld bsc2,ea ; bsc2 a, bsc3 e sm b 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 c incs l jr agn ret
address spaces s3c70 44/c7048/p7048 2- 16 program counter (pc) a 13-bit program counter (pc) stores addresses for instruction fetches during program execution. whenever a reset operation or an interrupt occurs, bits pc12 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1-byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word, mapped to ram locations fb0h?fb1h, that defines system status and program execution status and which permits an interrupted process to resume operation after an interrupt request has been serviced. psw values are mapped as follows: fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read instructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or hardware interrupt. after the in - terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logic zero. table 2-5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
s3c7044/c7048/p7048 address spaces 2- 17 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. they are mapped to ram bit loca - tions fb0h.2 and fb0h.3, respectively. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next status. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2-6 shows the effects of is0 and is1 flag settings. table 2-6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt as determined in the interrupt priority register (ipr) is serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter - rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in - struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re -enable interrupt processing. f f programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt
address spaces s3c70 44/c7048/p7048 2- 18 emb flag (emb) the enable memory bank flag emb is mapped to registers fb0h?fb1h in bank 15 of the ram. the emb flag occupies bit location 1 in register fb0h. the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1, and 15 can be accessed by using the appropriate smb value. f f programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) a, bank 15 is selected ld 34h,a ; (034h) a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) a, bank 15 is selected ld 34h,a ; (034h) a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) a, bank 0 is selected ld 90h,a ; (f90 h) a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9h ld 90h,a ; (190h) a, bank 1 is selected ld 34h,a ; (134h) a, bank 1 is selected smb 0 ; select memory bank 0 ld 90h,a ; (090h) a, bank 0 is selected ld 34h,a ; (034h) a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) a, bank 15 is selected
s3c7044/c7048/p7048 address spaces 2- 19 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. f f programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea #34h ld hl,ea ; bank 0 hl ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ea 2. when e rb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea #34h ld hl,ea ; bank 1 hl bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz bank2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx bank 3 ea
address spaces s3c70 44/c7048/p7048 2- 20 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 indicate the current program skip conditions and are set and reset automatically during program execution. these flags are mapped to ram bit locations fb1h.0, fb1h.1, and fb1h.2 of the psw. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is mapped to bit location fb1h.3 in the psw. it is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2?7, affect the carry flag. table 2-7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag data transfer rrc a rotate right with carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. 'intn' refers to the specific interrupt being executed and is not an instruction.
s3c7044/c7048/p7048 address spaces 2- 21 f f programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c 1 ld ea,#0c3h ; ea #0c3h ld hl,#0aah ; hl #0aah adc ea,hl ; ea #0c3h + #0aah + #1h, c 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p5.0: ld h,#3h ; set the upper four bits of the address to the h register value ldb c,@h+0fh.3 ; c bit 3 of 3fh band c,p3.3 ; c c and p3.3 ldb p5.0,c ; output result from carry flag to p5.0
s3c7044/c7048/p7048 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1, or 15. the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1, or 15. direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram addre ss as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3c 7044/c7048/p7048 3 - 2 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. da da.b @hl @h + da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x 000h working registers bank 0 (general registers and stack) 01fh 020h 07fh 080h 0ffh 100h 1ffh f80h fffh bank 1 (general registers) bank 15 (peripheral hardware registers) fb0h fbfh ff0h fc0h smb = 15 smb = 15 ram areas addressing mode notes: smb = 0 smb = 0 smb = 1 smb = 1 figure 3 - 1. ram address structure
s3c7044/c7048/p7048 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0,reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 vent4 0,1,ints ; emb ? 0, erb ? 1, branch ints vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 vent6 0,1,intt1 ; emb ? 0, erb ? 1, branch intt1 ? ? ? reset emb
addressing modes s3c 7044/c7048/p7048 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1, or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h ?0ffh if smb = 1, 100h ?1ffh if smb = 15, f80h ?fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h?07fh in bank 0 and to locations f80h?fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h?0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independently of the current status of the emb flag. these exceptions are described in table 3?1. table 3 - 1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push pop fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, iex, irqx, i/o bits emb bitr ie4 fc0h?fffh 1-bit indirect addressing using the l register i/o band c,p3.@l
s3c7044/c7048/p7048 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con - sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3?2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 smb 2 smb 1 smb 0 0 0 srb 1 srb 0 sb register smb (f83h) srb (f82h) figure 3 - 2. smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the three available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1, or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting. the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3c 7044/c7048/p7048 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the s3c7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3 - 2. 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da.b direct: bit is indicated by the ram address (da), memory bank selection, and specified bit number (b). 0 f80h?fffh bank 15 all 1-bit addressable peripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 mema.b direct: bit is indicated by ad - dressable area (mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of reg - ister l as indicated by the up - per 10 bits of ram area (memb) and the upper two bits of register l. x fc0h?fffh bank 15 pn.n @h + da.b indirect: bit indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h?0ffh bank 0 all 1-bit addressable pe ripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 note : 'x' means don't care.
s3c7044/c7048/p7048 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 (bmod.3) ? 1 btst cflag ; if fbah.0 (irqw) = 1, skip bits bflag ; else if, fbah.0 (irqw) = 0, f85h.3 ( bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fb ah.0 (irqw) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
addressing modes s3c 7044/c7048/p7048 3 - 8 4-bit addressing table 3 - 3. 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 4-bit address indicated by the ram address (da) and the memory bank selection 0 f80h?fffh bank 15 all 4-bit ad dressable pe ripherals 1 000h?fffh smb = 0, 1, 15 (smb = 15) @hl indirect: 4-bit address indi - cated by the memory bank selection and register hl 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 4-bit ad dressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi - cated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indi - cated by register wl x 000h?0ffh bank 0 note : 'x' means don't care. + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh) ? a 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) smb 0 ld adata,a ; (046h ) ? a ld bdata,a ; (08eh) ? a
s3c7044/c7048/p7048 addressing modes 3 - 9 + + programming tip ? 4-bit addressing modes (continued) 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h ?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h ?066h) = a, skip sret decs l jr comp ret 2. if emb = "1", compare bank 0 locations 040h ?046h to bank 1 locations 160h?166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 1 (160h ?166h) = a, skip sret decs l jr comp ret
addressing modes s3c 7044/c7048/p7048 3 - 10 + + programming tip ? 4-bit addressing modes (con cluded ) 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h ?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 0 (060h ?066h) ? a jr trans 2. if emb = "1", exchange bank 0 locations 040h ?046h to bank 1 locations 160h?166h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; bank 1 (160h ?166h) ? a jr trans
s3c7044/c7048/p7048 addressing modes 3 - 11 8-bit addressing table 3 - 4. 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 8-bit address indicated by the ram address ( da = even number ) and memory bank selection 0 f80h?fffh bank 15 all 8-bit ad dressable pe ripherals (smb = 15) 1 000h?fffh smb = 0, 1, 15 @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0, 1, 15 all 8-bit addressable pe ripherals (smb = 15) + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld ea,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e
addressing modes s3c 7044/c7048/p7048 3 - 12 + + programming tip ? 8-bit addressing modes (continued) 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2. if emb = "1": adata equ 146h smb 1 ld hl,#adata ld ea,@hl ; a ? (146h), e ? (147h)
s3c7044/c7048/p7048 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4?1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register loca tions f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non-manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map s3c7044/c 7048/p7048 4 - 2 table 4 - 1. i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 ? ? ? f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod "0" .2 .1 "0" (1) w no no yes f89h .7 "0" .5 .4 ? ? ? f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h toe1 toe0 boe "0" r/w yes yes no f93h "0" tol1 tol0 "0" r yes yes no f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h fa0h tmod1 .3 .2 "0" "0" w .3 no yes fa1h "0" .6 .5 .4 fa2h fa3h fa4h tcnt1 r no no yes fa5h fa6h fa7h fa8h tref1 w no no yes fa9h
s3c7044/c7048/p7048 memory map 4 - 3 table 4 - 1 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit ? ? ? fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (2) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 .3 "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w fb6h imod2 "0" "0" .1 .0 w fb7h fb8h ie4 irq4 ieb irqb r/w yes yes no fb9h fbah "0" "0" iew irqw r/w yes yes no fbbh "0" "0" iet1 irqt1 fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 yes fc3h bsc3 ? ? fd0h clmod .3 "0" .1 .0 w no yes no ? ? ? fdch pumod1 pur3 pur2 pur1 pur0 w no no yes fddh "0" "0" pur7 pur6
memory map s3c7044/c 7048/p7048 4 - 4 table 4 - 1 . i/o map for memory bank 15 (concluded) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fdeh pumod2 "0" (3) pdr8 "0" "0" w no no yes fdfh "0" "0" "0" "0" fe0h smod .3 .2 .1 .0 w .3 no yes fe1h .7 .6 .5 "0" fe2h fe3h fe4h sbuf r/w no no yes fe5h fe6h fe7h fe8h pmg1 pm0.3 pm0.2 pm0.1 pm0.0 w no no yes fe9h pm7 "0" pm5 pm4 feah pmg2 pm2.3 pm2.2 pm2.1 pm2.0 yes febh pm3.3 pm3.2 pm3.1 pm3.0 fech pmg3 pm6.3 pm6.2 pm6.1 pm6.0 yes fedh "0" "0" "0" "0" feeh pmg4 (3) pm8.3 pm8.2 pm8.1 pm8.0 yes fefh "0" "0" "0" "0" ff0h port 0 .3 .2 .1 .0 r/w yes yes no ff1h port 1 .3 .2 .1 .0 r ff2h port 2 .3 .2 .1 .0 r/w no ff3h port 3 .3 .2 .1 .0 r/w ff4h port 4 .3 .2 .1 .0 r/w yes ff5h port 5 .3 / .7 .2 / .6 .1 / .5 .0 / .4 r/w ff6h port 6 .3 .2 .1 .0 r/w yes ff7h port 7 .3 / .7 .2 / .6 .1 / .5 .0 / .4 r/w ? ? ffch port 8 .3 .2 .1 .0 r/w yes yes no notes: 1. bit 0 in the wmod register must be set to logic "0". 2. the carry flag can be read or written by specific bit manipulation instructions only. 3. bit 7 in the pumod2 and bits 7 ?4 in the pmg4 must be set to logic "0".
s3c7044/c7048/p7048 memory map 4 - 5 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4 - 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions," in the context of the corresponding peripheral hardware module descriptions.
memory map s3c7044/c 7048/p7048 4 - 6 clmod ? clock output mode control register cpu fd0h bit identifier reset reset value read/write bit addressing clmod.3 clmod.2 clmod.1 ? .0 enable/disable clock output control bit bit 2 clock source and frequency selection control bits w w w w 4 0 0 0 0 3 2 1 0 .3 .2 .1 .0 0 1 0 disable clock output enable clock output always logic zero 0 0 select cpu clock source 0 1 select main system clock fx/8 (524 khz at 4.19 mhz) 1 0 select main system clock fx/16 (262 khz at 4.19 mhz) register id register name associated hardware module register location in ram bank 15 bit number in msb to lsb order bit identifier used for bit addressing type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) r w r/w = = = read-only write-only read/write register and bit ids used for bit addressing description of the effect of specific bit settings name of individual bit or related bits 1 select main system clock fx/64 (65.5 khz at 4.19 mhz) 1 4 4 4 bit value immediately following a reset figure 4 - 1 . register description format
s3c7044/c7048/p7048 memory map 4 - 7 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 .3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero .2 ? .0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: signal stabilization interval: fx/2 12 (1.02 khz) 220 / fx (250 ms) 0 1 1 input clock frequency: signal stabilization interval: fx / 2 9 (8.18 khz) 2 17 / fx (31.3 ms) 1 0 1 input clock frequency: signal stabilization interval: fx / 2 7 (32.7 khz) 2 15 / fx (7.82 ms) 1 1 1 input clock frequency: signal stabilization interval: fx / 2 5 (131 khz) 2 13 / fx (1.95 ms) notes : 1. signal stabilization interval is the time required to stabilize clock signal oscillation after stop mode is terminated by an interrupt. the stabilization interval can also be interpreted as "interrupt interval time". 2. when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 /fx) at 4.19 mhz. 3. 'fx' is the system clock rate given a clock frequency of 4.19 mhz.
memory map s3c7044/c 7048/p7048 4 - 8 clmod ? clock output mode register cpu fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 enable/disable clock output control bit 0 disable clock output 1 enable clock output .2 bit 2 0 always logic zero .1 ? .0 clock source and frequency selection control bits 0 0 select cpu clock source fx/4, fx/8, or fx/64 (1.05 mhz, 524 khz, or 65.6 khz) 0 1 select system clock fx/8 (524 khz) 1 0 select system clock fx/16 (262 khz) 1 1 select system clock fx/64 (65.5 khz) note : 'fx' is the system clock, given a clock frequency of 4.19 mhz.
s3c7044/c7048/p7048 memory map 4 - 9 imod0 ? external interrupt 0 (int0) mode register cpu fb4h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 interrupt sampling clock selection bit 0 select cpu clock as a sampling clock 1 select sampling clock frequency of the selected system clock (fx/64) .2 bit 2 0 always logic zero .1 and .0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag (irqx) cannot be set to logic one
memory map s3c7044/c 7048/p7048 4 - 10 imod1 ? external interrupt 1 (int1) mode register cpu fb5h bit 3 2 1 0 identifier "0" "0" "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 ? .1 bits 3?1 0 always logic zero .0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
s3c7044/c7048/p7048 memory map 4 - 11 imod2 ? external interrupt 2 (int2) mode register cpu fb6h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 and .2 bits 3 and 2 0 always logic zero .1 and .0 external interrupt 2 edge detection selection bit 0 0 interrupt request at int2 pin triggered by rising edge 0 1 interrupt request at ks4?ks7 triggered by falling edge 1 0 interrupt request at ks2?ks7 triggered by falling edge 1 1 interrupt request at ks0?ks7 triggered by falling edge
memory map s3c7044/c 7048/p7048 4 - 12 ie0, 1 , irq0, 1 ? int0, 1 interrupt enable/request flags cpu fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.)
s3c7044/c7048/p7048 memory map 4 - 13 ie2 , irq2 ? int2 interrupt enable/request flags cpu fbfh bit 3 2 1 0 identifier "0" "0" ie2 irq2 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 and .2 bits 3 and 2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin or ks0?ks7 pins 1 enable int2 interrupt requests at the int2 pin or ks0?ks7 pins irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising edge is detected at int2 or when a falling edge is detected at one of the ks0?ks7 pins. since int2 is a quasi-interrupt, irq2 flag must be cleared by software.)
memory map s3c7044/c 7048/p7048 4 - 14 ie4 , irq4 ? int4 interrupt enable/request flags cpu fb8h ieb, irqb ? intb interrupt enable/request flags cpu fb8h bit 3 2 1 0 identifier ie4 irq4 ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie4 int4 interrupt enable flag 0 disable interrupt requests at the int4 pin 1 enable interrupt requests at the int4 pin irq4 int4 interrupt request flag ? generate int4 interrupt (this bit is set and cleared automatically by hardware when rising and falling signal edge detected at int4 pin.) ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
s3c7044/c7048/p7048 memory map 4 - 15 ies , irqs ? ints interrupt enable/request flags cpu fbdh bit 3 2 1 0 identifier "0" "0" ies irqs reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 and .2 bits 3 and 2 0 always logic zero ies ints interrupt enable flag 0 disable ints interrupt requests 1 enable ints interrupt requests irqs ints interrupt request flag ? generate ints interrupt (this bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial i/o interface.)
memory map s3c7044/c 7048/p7048 4 - 16 iet0 , irqt0 ? intt0 interrupt enable/request flags cpu fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 and .2 bits 3 and 2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
s3c7044/c7048/p7048 memory map 4 - 17 iet1 , irqt1 ? intt1 interrupt enable/request flags cpu fbbh bit 3 2 1 0 identifier "0" "0" iet1 irqt1 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .2 and .3 bits 2 and 3 0 always logic 0 iet1 intt1 interrupt enable flag 0 disable intt1 interrupt requests 1 enable intt1 interrupt requests irqt1 intt1 interrupt request flag ? generate intt1 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt1 and tref1 registers match.)
memory map s3c7044/c 7048/p7048 4 - 18 iew , irqw ? intw interrupt enable/request flags cpu fbah bit 3 2 1 0 identifier "0" "0" iew irqw reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 and .2 bits 3 and 2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3.19 milliseconds.) note : since intw is a quasi-interrupt, the irqw flag must be cleared by software.
s3c7044/c7048/p7048 memory map 4 - 19 ipr ? interrupt priority register cpu fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit (msb) 0 disable all interrupt processing 1 enable processing of all interrupt service requests .2 ? .0 interrupt priority assignment bits 0 0 0 normal interrupt processing according to default priority settings 0 0 1 process intb and int4 interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 0 process ints interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process intt1 interrupts at highest priority note : during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown below. using the ipr settings, you can select specific interrupts for high-priority processing in the event of contention. when the high-priority (ipr) interrupt has been processed, waiting interrupts are handled according to their default priorities. the default priorities are as follows ('1' is highest priority; '6' is lowest priority): intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intt1 6
memory map s3c7044/c 7048/p7048 4 - 20 pcon ? power control register cpu fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 and .2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode .1 and .0 cpu clock frequency selection bits 0 0 select fx/64 1 0 select fx/8 1 1 select fx/4 note : 'fx' is the main system clock.
s3c7044/c7048/p7048 memory map 4 - 21 psw ? program status word cpu fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (note 1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (note 2) 8 8 8 1/4 1/4 1 1 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2 ? sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h?07fh in the bank 0 only 1 enable full access to data memory banks 0, 1, and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2, or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
memory map s3c7044/c 7048/p7048 4 - 22 pmg1 ? port i/o mode flags (group 1: ports 0, 4, 5, 7) i/o fe9h, fe8h bit 7 6 5 4 3 2 1 0 identifier pm7 "0" pm5 pm4 pm0.3 pm0.2 pm0.1 pm0.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm7 port 7 i/o mode selection flag 0 set port 7 to input mode 1 set port 7 to output mode .6 bit 6 0 always logic zero pm5 port 5 i/o mode selection flag 0 set port 5 to input mode 1 set port 5 to output mode pm4 port 4 i/o mode selection flag 0 set port 4 to input mode 1 set port 4 to output mode pm0.3 p0.3 i/o mode selection flag 0 set p0.3 to input mode 1 set p0.3 to output mode pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode
s3c7044/c7048/p7048 memory map 4 - 23 pmg2 ? port i/o mode flags (group 2: ports 2, 3) i/o febh, feah bit 7 6 5 4 3 2 1 0 identifier pm3.3 pm3.2 pm3.1 pm3.0 pm2.3 pm2.2 pm2.1 pm2.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm3.3 p3.3 i/o mode selection flag 0 set p3.3 to input mode 1 set p3.3 to output mode pm3.2 p3.2 i/o mode selection flag 0 set p3.2 to input mode 1 set p3.2 to output mode pm3.1 p3.1 i/o mode selection flag 0 set p3.1 to input mode 1 set p3.1 to output mode pm3.0 p3.0 i/o mode selection flag 0 set p3.0 to input mode 1 set p3.0 to output mode pm2.3 p2.3 i/o mode selection flag 0 set p2.3 to input mode 1 set p2.3 to output mode pm2.2 p2.2 i/o mode selection flag 0 set p2.2 to input mode 1 set p2.2 to output mode pm2.1 p2.1 i/o mode selection flag 0 set p2.1 to input mode 1 set p2.1 to output mode pm2.0 p2.0 i/o mode selection flag 0 set p2.0 to input mode 1 set p2.0 to output mode
memory map s3c7044/c 7048/p7048 4 - 24 pmg3 ? port i/o mode flags (group 3: port 6) i/o fedh, fech bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" pm6.3 pm6.2 pm6.1 pm6.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7?.4 bits 7?4 0 always logic zero pm6.3 p6.3 i/o mode selection flag 0 set p6.3 to input mode 1 set p6.3 to output mode pm6.2 p6.2 i/o mode selection flag 0 set p6.2 to input mode 1 set p6.2 to output mode pm6.1 p6.1 i/o mode selection flag 0 set p6.1 to input mode 1 set p6.1 to output mode pm6.0 p6.0 i/o mode selection flag 0 set p6.0 to input mode 1 set p6.0 to output mode
s3c7044/c7048/p7048 memory map 4 - 25 pmg4 ? port i/o mode flags (group 3: port 8) i/o feeh, fefh bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" pm8.3 pm8.2 pm8.1 pm8.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 ? .4 bits 7?4 0 always logic zero (must be set to zero) pm8.3 p8.3 i/o mode selection flag 0 set p8.3 to input mode 1 set p8.3 to output mode pm8.2 p8.2 i/o mode selection flag 0 set p8.2 to input mode 1 set p8.2 to output mode pm8.1 p8.1 i/o mode selection flag 0 set p8.1 to input mode 1 set p8.1 to output mode pm8.0 p8.0 i/o mode selection flag 0 set p8.0 to input mode 1 set p8.0 to output mode
memory map s3c7044/c 7048/p7048 4 - 26 pumod1 ? pull-up resistor mode register i/o fddh, fdch bit 7 6 5 4 3 2 1 0 identifier "0" "0" pur7 pur6 pur3 pur2 pur1 pur0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 and .6 bits 7 and 6 0 always cleared to logic zero pur7 connect/disconnect port 7 pull-up resistor control bit 0 disconnect port 7 pull-up resistor 1 connect port 7 pull-up resistor pur6 connect/disconnect port 6 pull-up resistor control bit 0 disconnect port 6 pull-up resistor 1 connect port 6 pull-up resistor pur3 connect/disconnect port 3 pull-up resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur2 connect/disconnect port 2 pull-up resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor pur1 connect/disconnect port 1 pull-up resistor control bit 0 disconnect port 1 pull-up resistor 1 connect port 1 pull-up resistor pur0 connect/disconnect port 0 pull-up resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor
s3c7044/c7048/p7048 memory map 4 - 27 pumod2 ? pull-up resistor mode register i/o fdfh, fdeh bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" "0" "0" pdr8 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7? .3 bits 7?3 0 always cleared to logic zero (bit 3 must be set to zero) pdr8 connect/disconnect port 8 pull-down resistor control bit 0 disconnect port 8 pull-down resistor 1 connect port 8 pull-down resistor .1 and .0 bits 1 and 0 0 always cleared to logic zero
memory map s3c7044/c 7048/p7048 4 - 28 smod ? serial i/o mode register sio fe1h, fe0h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 .7 ? .5 serial i/o clock selection and sbuf r/w status control bits 0 0 0 use an external clock at the sck pin; enable sbuf when sio operation is halted or when sck goes high 0 0 1 use the tol0 clock from timer/counter 0; enable sbuf when sio operation is halted or when sck goes high 0 1 x use the selected cpu clock (fx/4, 8, or 64; 'fx' is the system clock) then, enable sbuf read/write operation. 'x' means 'don't care.' 1 0 0 4.09 khz clock (fx/2 10 ) 1 1 1 262 khz clock (fx/2 4 ); note: you cannot select a fx/2 4 clock fre - quency if you have selected a cpu clock of fx/64 note : all khz frequency ratings assume a system clock of 4.19 mhz. .4 bit 4 0 always logic zero .3 initiate serial i/o operation bit 1 clear irqs flag and 3-bit clock counter to logic zero; then initiate serial trans - mission. when sio transmission starts, this bit is cleared by hardware to logic zero .2 enable/disable sio data shifter and clock counter bit 0 disable the data shifter and clock counter; the contents of irqs flag is retained when serial transmission is completed 1 enable the data shifter and clock counter; the irqs flag is set to logic one when serial transmission is completed .1 serial i/o transmission mode selection bit 0 receive-only mode 1 transmit-and-receive mode .0 lsb/msb transmission mode selection bit 0 transmit the most significant bit (msb) first 1 transmit the least significant bit (lsb) first
s3c7044/c7048/p7048 memory map 4 - 29 tmod0 ? timer/counter 0 mode register t/c0 f91h, f90h bit 3 2 1 0 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1 8 8 8 .7 bit 7 0 always logic zero .6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 internal system clock (fx) of 4.19 mhz/2 10 (4.09 khz) 1 0 1 select clock: fx/2 6 (65.5 khz at 4.19 mhz) 1 1 0 select clock: fx/2 4 (262 khz at 4.19 mhz) 1 1 1 select clock: fx (4.19 mhz) .3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 .1 bit 1 0 always logic zero .0 bit 0 0 always logic zero
memory map s3c7044/c 7048/p7048 4 - 30 tmod1 ? timer/counter 1 mode register t/c1 fa1h, fa0h bit 3 2 1 0 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1 8 8 8 .7 bit 7 0 always logic zero .6 ? .4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl1 pin on rising edge 0 0 1 external clock input at tcl1 pin on falling edge 1 0 0 internal system clock (fx) of 4.19 mhz/2 12 (1.02 khz) 1 0 1 select clock: fx/2 10 (4.09 khz at 4.19 mhz) 1 1 0 select clock: fx/2 8 (16.4 khz at 4.19 mhz) 1 1 1 select clock: fx/2 6 (65.5 khz at 4.19 mhz) .3 clear counter and resume counting control bit 1 clear tcnt1, irqt1, and tol1 and resume counting immediately (this bit is cleared automatically when counting starts.) .2 enable/disable timer/counter 0 bit 0 disable timer/counter 1; retain tcnt1 contents 1 enable timer/counter 1 .1 bit 1 0 always logic zero .0 bit 0 0 always logic zero
s3c7044/c7048/p7048 memory map 4 - 31 toe ? timer output enable flag register t/c f92h bit 3 2 1 0 identifier toe1 toe0 boe "0" reset reset value 0 0 0 0 read/write r/w r/w r/w w bit addressing 1/4 1/4 1/4 1/4 toe1 timer/counter 1 output enable flag 0 disable timer/counter 1 output to the tclo1 pin 1 enable timer/counter 1 output to the tclo1 pin toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output at the tclo0 pin 1 enable timer/counter 0 output at the tclo0 pin boe basic timer output enable flag 0 disable basic timer output at the btco pin 1 enable basic timer output at the btco pin .0 bit 0 0 always logic zero
memory map s3c7044/c 7048/p7048 4 - 32 wmod ? watch timer mode register wt f89h, f88h bit 3 2 1 0 3 2 1 0 identifier .7 "0" .5 .4 "0" .2 .1 "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 .7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output .6 bit 6 0 always logic zero .5 and .4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output .3 bit 3 0 always logic zero .2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer .1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91 ms .0 bit 0 0 always logic zero (must be set to zero)
s3c7044/c7048/p7048 oscillator circuits 6 - 1 6 oscillator circuits overview the s3c7044/c7048 has a system clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these on-chip circuits. specifically, a clock is required by the following peripheral modules: ? basic timer ? timer/counter 0 and 1 ? watch timer ? serial i/o interface ? clock output circuit the system clock frequency can be divided by 4, 8, or 64. by manipulating pcon bits 1 and 0, you can select one of the following frequencies as the cpu clock. fx 4 , fx 8 , fx 64 when the pcon register is cleared to zero after reset , the normal cpu operating mode is enabled, a system clock of fx/64 is selected. bits 3 and 2 of the pcon register can be manipulated by a stop or idle instruction to engage stop or idle power-down mode.
oscillator circuits s3c7044/c7048/p7048 6 - 2 xin xout oscillator stop 1/4 cpu clock oscillator control circuit wait release signal internal reset signal power-down release signal pcon.3,2 clear system oscillator circuit frequency dividing circuit 1/2 1/16 selector pcon.0 pcon.1 pcon.2 pcon.3 fx cpu stop signal (idle mode) idle stop watch timer basic timer timer/counters 0, 1 clock output circuit figure 6- 1 . clock circuit diagram
s3c7044/c7048/p7048 oscillator circuits 6 - 3 system oscillator circuits xin xout figure 6- 2 . crystal/ceramic oscillator xin xout figure 6- 3 . external oscillator
oscillator circuits s3c7044/c7048/p7048 6 - 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon is mapped to ram address fb3h and can be addressed di rectly by 4-bit write instructions or by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are controlled by the stop and idle instructions to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. reset sets pcon register values to logic zero. pcon.1 and pcon.0 divide the frequency (fx) by 64, 8, and 4. pcon.3 and pcon.2 enable normal cpu operating mode. table 6- 1 . power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 0 0 fx/64 1 0 fx/8 1 1 fx/4 f f programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
s3c7044/c7048/p7048 oscillator circuits 6 - 5 instruction cycle times the unit of time that equals one machine cycle varies depending on how the oscillator clock signal is divided (by 4, 8, or 64). table 6- 2 shows corresponding cycle times in microseconds. table 6- 2 . instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time (sec) fx/64 65.5 khz 15.3 fx/8 524.0 khz fx = 4.19 mhz 1.91 fx/4 1.05 mhz 0.95 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is mapped to ram address fd0h and is ad - dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fx/8, fx/16, or fx/64. table 6- 3 . clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64) 1.05 mhz, 524 khz, 65.5 khz 0 1 fx/8 524 khz 1 0 fx/16 262 khz 1 1 fx/64 65.5 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note: frequencies assume that fx = 4.19 mhz.
oscillator circuits s3c7044/c7048/p7048 6 - 6 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p2.2) pm2.2 p2.2 output latch clo clmod.3 clmod.2 clmod.1 clmod.0 clock selector clocks 4 (fx/8, fx/16, fx/64, cpu clock) figure 6-4. clo output pin circuit diagram clock output procedure to output clock pulses to the clo pin, follow this general procedure: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin (p2.2). 4. set the p2.2 mode flag (pm2.2) to output mode. 5. enable clock output by setting clmod.3 to logic one. f f programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb ; or bitr emb smb 15 ld ea,#4h ld pmg2,ea ; p2.2 ? output mode bitr p2.2 ; clear p2.2 output latch ld a,#9h ld clmod,a
s3c7044/c7048/p7048 interrupts 7 - 1 7 interrupts overview the s3c7044/c7048 's interrupt control circuit has five functional components: ? interrupt enable flags (iex) ? interrupt request flags (irqx) ? interrupt mask enable register (ime) ? int errupt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7- 1 . interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pin external interrupts int0, int1, int4 p1.0, p1.1, p1.3 internal interrupts intb, intt0, intt1, ints not applicable quasi-interrupts int2 p1.2, ports 6 and 7 (ks0?ks7) intw not applicable
interrupts s3c7044/c 7048/p7048 7 - 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt (intn) are set to logic one: ? interrupt enable flag (iex) ? interrupt master enable flag (ime) ? int errupt request flag (irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for reset s and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the pro - gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory using the pop instruction. power-down mode release an interrupt (with the exception of int0) can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
s3c7044/c7048/p7048 interrupts 7 - 3 request flag (irqx) <-- 1 iex = 1? interrupt is generated (int xx) retain value until iex = 1 generate corresponding vector interrupt and release power-down mode retain value until ime = 1 high-priority interrupt? ime = 1? is1,0 = 0,0? is1,0 = 0,1 ? are both interrupt sources of shared vector address used? store contents of pc and psw in the stack area; set pc contents to corresponding vector address is1,0 = 0,1 reset corresponding irqx flag irqx flag value remains 1 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction retain value until interrupt service routine is completed jump to interrupt start address is1,0 = 1,0 no no no no yes yes yes yes yes yes no no figure 7- 1 . interrupt execution flowchart
interrupts s3c7044/c 7048/p7048 7 - 4 # @ @ irqb irq4 irq0 irq1 irqs irqt0 irqt1 irqw irq2 imod1 imod0 intb int4 int0 int1 ints intt0 intt1 intw power-down mode release signal ime ipr is1 is0 interrupt control unit vector interrupt generator # = noise filtering circuit @ = edge detection circuit selector imod2 int2 ks0?ks7 iet1 iet0 ies ie1 ie0 ie4 ieb iew ie2 figure 7- 2 . interrupt control circuit diagram
s3c7044/c7048/p7048 interrupts 7 - 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter - rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7- 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one ("0" ? "1" or "1" ? "0"), and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt status flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) high-level interrupt generated high or low level interrupt processing (status 1) high level interrupt processing (status 2) figure 7- 3 . two-level interrupt handling
interrupts s3c7044/c 7048/p7048 7 - 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter - rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1 (see table 7- 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low -priority requests can be serviced in parallel (see figure 7- 4). table 7- 2 . is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined. ? ? int disable set ipr int enable low or high level interrupt generated normal program processing (status 0) low or high level interrupt generated single interrupt 2-level interrupt status 1 status 0 int enable modify status int disable high-level interrupt generated 3-level interrupt status 1 status 0 status 2 figure 7- 4 . multi-level interrupt handling
s3c7044/c7048/p7048 interrupts 7 - 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. the ipr is mapped to ram address fb2h, and its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7- 3 . standard interrupt priorities interrupt default priority intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intt1 6 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag is mapped to fb2h.3 and can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7- 4 . interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 normal interrupt handling according to default priority settings 0 0 1 process intb and int4 interrupts at highest priority 0 1 0 process int0 interrupts at highest priority 0 1 1 process int1 interrupts at highest priority 1 0 0 process ints interrupts at highest priority 1 0 1 process intt0 interrupts at highest priority 1 1 0 process intt1 interrupts at highest priority note : during normal interrupt processing, interrupts are processed in the order in which they occur. if two or more interrupts occur simultaneously, the processing order is determined by the default interrupt priority settings shown in table 7- 3. using the ipr settings, you can select specific interrupts for high-priority processing in the event of contention. when the high-priority (ipr) interrupt has been processed, waiting interrupts are handled according to their default priorities.
interrupts s3c7044/c 7048/p7048 7 - 8 f f programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0 and 1 mode registers (imod0, imod1) the following components are used to process external interrupts at the int0 and int1 pin: ? noise filtering circuit for int0 ? edge detection circuit ? two mode registers, imod0 and imod1 the mode registers are used to control the triggering edge of the input signal. imod0 and imod1 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. the int4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. fb4h imod0.3 "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 imod0 and imod1 bits are mapped to ram addresses fb4h (imod0) and fb5h (imod1), and are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7- 5 . imod0 and imod1 register organization imod0 imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fx/64 sampling clock 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 0 0 0 imod1.0 effect of imod1 settings 0 rising edge detection 1 falling edge detection
s3c7044/c7048/p7048 interrupts 7 - 9 external interrupt 0 and 1 mode registers (imod0, imod1) (c ontinued ) when a sampling clock rate of fx/64 is used for int0, an interrupt request flag must be cleared before 16 ma - chine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: ? to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock se lected by imod0. this is true even when the int0 pin is used for general-purpose input. ? since the int0 input sampling clock does not operate during stop or idle mode, you cannot use int0 to re - lease power-down mode. int0 cpu clock fx/64 int1 noise filter edge detection irq0 imod0 imod1 clock selector p1.1 p1.0 edge detection irq1 figure 7- 5 . circuit diagram for int0 and int1 pins when modifying the imod0 and imod1 registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod0 or imod1 register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with an ei instructions.
interrupts s3c7044/c 7048/p7048 7 - 10 external interrupt 2 mode register (imod2) the mode register for external interrupts at the int2 pin, imod2, is a 4-bit register at ram address fb6h. imod2 is addressable only by 4-bit write instructions. reset clears all imod2 bits to logic zero. fb6h "0" "0" imod2.1 imod2.0 when imod2 is cleared to logic zero, int2 uses the rising edge of an incoming signal as the interrupt request trigger. if a rising edge is detected at the int2 pin, or when a falling edge is detected at any one of the pins ks0? ks7, the irq2 flag is set to logic one and a release signal for power-down mode is generated. table 7- 6 . imod2 register bit settings imod2 0 0 imod2.1 imod2.0 effect of imod2 settings 0 0 select rising edge at int2 pin 0 1 select falling edge at ks4?ks7 1 0 select falling edge at ks2?ks7 1 1 select falling edge at ks0?ks7
s3c7044/c7048/p7048 interrupts 7 - 11 int2 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 irq2 1. all of the pins used for key interrupt on a falling edge at ks0-ks7 must always be configured to input mode. 2. if anyone of the ks0-ks7 pins used for interrupt stays low, a key interrupt is not generated. since all ks0-ks7 pins are anded, the falling edge detection circuit cannot detects a falling edge. 3. you can configure any pin of ks0-ks3 to normal input or output regardless of low state if you do not use it for a interrupt generation by imod2 setting. notes: falling edge detection circuit imod2 clock selector rising edge detection circuit figure 7- 6 . circuit diagram for int2 and ks0?ks7 pins
interrupts s3c7044/c 7048/p7048 7 - 12 f f programming tip ? using int2 as a key input interrupt when the int2 interrupt is used as a key interrupt, the selected key interrupt source pin must be set to input: 1. when ks0 ?ks7 are selected (eight pins): bits emb smb 15 ld a,#3h ld imod2,a ; (imod2) ? #3h, ks0?ks7 falling edge select ld ea,#0fh ld pmg1,ea ; p7 ? input mode ld ea,#00h ld pmg3,ea ; p6 ? input mode ld ea,#30h ld pumod1,ea ; enable p6 and p7 pull-up resistors 2. when ks2 ?ks7 are selected (six pins): bits emb smb 15 ld a,#2h ld imod2,a ; (imod2) ? #2h, ks2?ks7 falling edge select ld ea,#0fh ld pmg1,ea ; p7 ? input mode ld ea,#0ch ld pmg3,ea ; p6.2 ?p6.3 ? input mode ld ea,#30h ld pumod1,ea ; enable p6 and p7 pull-up resistors 3. when ks4 ?ks7 are selected (four pins), p7 must be specified as a key strobe signal input: bits emb smb 15 ld a,#1h ld imod2,a ; (imod2) ? #1h, ks4?ks7 falling edge select ld ea,#0fh ld pmg1,ea ; p7 ? input mode ld ea,#20h ld pumod1,e a ; enable p7 pull-up resistor
s3c7044/c7048/p7048 interrupts 7 - 13 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each in - terrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3), and is mapped to bit address fb2h.3. it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). interrupt enable flags (iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logic one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags are mapped to the ram address area fb8h?fbfh, and can be read, written, or tested directly by 1-bit instructions (bits and bitr). iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. interrupt request flags (irqx) interrupt request flags, located in the ram area fb8h-fbfh, are read/write addressable by 1-bit or 4-bit in - structions.irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated.
interrupts s3c7044/c 7048/p7048 7 - 14 interrupt master enable flag (ime) the interrupt master enable flag, ime, inhibits or enables all interrupt processing. therefore, even when an irqx flag and its corresponding iex flag is enabled, an interrupt request will not be serviced until the ime flag is set to logic one. the ime flag is the most significant bit of the 4-bit ipr register at ram location fb2h. ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts the ime flag can be manipulated using ei and di instructions, independent of the current value of the enable memory bank (emb) flag. interrupt enable flags (ie x ) interrupt enable flags are used to control the execution of service routines for specific interrupt requests. the enable flag has priority over a request flag ? even if the irqx flag is enabled, the interrupt request will not be ser viced until the corresponding iex flag is set to logic one. using 1-bit or 4-bit instructions and direct addressing, you can read, write, or test iex (and irqx) flags despite the current enable memory bank (emb) value. the iex and irqx flags are mapped to ram area fb8h?fbfh. table 7- 7 . interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah 0 0 iew irqw fbbh 0 0 iet1 irqt1 fbch 0 0 iet0 irqt0 fbdh 0 0 ies irqs fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2 notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
s3c7044/c7048/p7048 interrupts 7 - 15 interrupt request flags (irq x ) when an interrupt request flag (irqx) is set, a software-generated interrupt is enabled for the corresponding in - terrupt. irqx flags can be written by 1- or 4-bit ram control instructions. irqx flags are then cleared automatically when the interrupt has been serviced. exceptions to the general rule are the watch timer interrupt request flag (irqw) and the external interrupt 2 request flag (irq2); these flags must be cleared by software after the interrupt service routine execution is completed. when two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: ? when only one interrupt is enabled, the irqx flag is cleared automatically when the interrupt has been serviced. ? when two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. in this case, the irqx setting must be cleared manually using a btstz instruction. table 7- 8 . interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and-re - ceive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intt1 i signals for tcnt1 and tref1 registers match 6 irqt1 int2 (note) e rising edge detected at int2 or else a falling edge is detected at any of the ks0?ks7 pins ? irq2 intw i time interval of 0.5 secs or 3.19 msecs ? irqw note: the quasi-i nterrupt int2 is only used for testing incoming signals.
interrupts s3c7044/c 7048/p7048 7 - 16 f f programming tip ? enabling the intb and int4 interrupts to simultaneously enable intb and int4 interrupts: intb di btstz irqb ; irqb = 1 ? jr int4 ; if no, int4 interrupt; if yes, intb interrupt is processed ? ? ? ei iret ; int4 bitr irq4 ; int4 is processed ? ? ? ei iret
s3c7044/c7048/p7048 power-down 8 - 1 8 power-down overview the s3c7044/c7048 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program) in idle mode, the cpu clock stops while peripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in stop mode, system clock oscillation is halted (assuming it is currently operating), and peripheral hard ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, serial i/o, timer/counters, and watch timer ? and on external interrupt requests, is detailed in table 8 - 1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or stop modes are terminated either by a reset , or by an interrupt with the exception of int0, which are enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset input, a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution is started immediately after the instruction which issues the request to enter power-down mode. the interrupt request flag remains set to logic one. ? if the ime flag = "1", two instructions are executed after the power-down mode release. then, the vectored interrupt is initiated. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = 0 condition. that is, a vector interrupt is not generated.
power-down s3c7044/c 7048/p7048 8 - 2 table 8 - 1 . hardware operation during power-down modes operation stop mode (stop) idle mode (idle) clock oscillator system clock oscillation stops cpu clock oscillation stops (system clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates timer/counter 1 operates only if tcl1 is selected as the counter clock timer/counter 1 operates watch timer watch timer operation is stopped watch timer operates external interrupts int1, int2, and int4 are acknowledged; int0 is not serviced int1, int2, and int4 are acknowledged; int0 is not serviced cpu all cpu operations are disabled all cpu operations are disabled power-down mode release signal interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input
s3c7044/c7048/p7048 power-down 8 - 3 idle mode timing diagrams clock signal stop instruction oscillation stabilization (31.3 ms / 4.19 mhz) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops reset figure 8 - 1 . timing when idle mode is released by reset reset oscillation stabilization (bmod setting) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops mode release signal stop instruction clock signal int ack (ime = 1) figure 8 - 2 . timing when idle mode is released by an interrupt
power-down s3c7044/c 7048/p7048 8 - 4 stop mode timing diagrams clock signal stop instruction oscillation stabilization (31.3 ms / 4.19 mhz) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops reset figure 8 - 3 . timing when stop mode is released by reset reset oscillation stabilization (bmod setting) normal mode idle mode normal mode oscillation resumes stop mode oscillation stops mode release signal stop instruction clock signal int ack (ime = 1) figure 8 - 4 . timing when stop mode is release by an interrupt
s3c7044/c7048/p7048 power-down 8 - 5 i/o port pin configuration for power-down the following method describes how to configure i/o port pins to reduce power consumption during power-down modes (stop, idle): condition 1: if the microcontroller is not configured to an external device: 1. connect unused port pins according to the information in table 8 - 2. 2. disable all pull-up resistors for output pins by making the appropriate modifications to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be unexpected surges of current through the pull-up. 3. disable pull-up resistors for input p ins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. condition 2: if the microcontroller is configured to an external device and the external device's v dd source is turned off in power-down mode. 1. connect unused port pins according to the information in table 8 - 2. 2. disable the pull-up resistors of output pins by making the appropriate modifica tions to the pull-up resistor mode register, pumod. reason: if output goes low when the pull-up resistor is enabled, there may be un - expected surges of current through the pull-up. 3. disable pull-up resistors for input pins configured to v dd or v ss levels in order to check the current input option. reason: if the input level of a port pin is set to v ss when a pull-up resistor is enabled, it will draw an unnecessarily large current. 4. disable the pull-up resistors of input pins connected to the external de vice by making the necessary modi - fications to the pumod register. 5. configure the output pins that are connected to the external device to low level. reason: when the exter nal device's v dd source is turned off, and if the microcontroller's output pins are set to high level, v dd ? 0.7 v is supplied to the v dd of the external device through its input pin. this causes the device to operate at the level v dd ? 0.7 v. in this case, total current consumption would not be reduced. 6. determine the correct output pin state necessary to block current pass in according with the external tran - sistors (pnp, npn).
power-down s3c7044/c 7048/p7048 8 - 6 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8 - 2. table 8 - 2 . unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco input mode: connect to v dd output mode: no connection p1.0 / int0 ? p1.2 / int2 connect to v dd p1.3 / int4 connect to v ss p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz p3.0 / tcl0 p3.1 / tcl1 p3.2 p3.3 p4.0?p4.3 p5.0?p5.3 p6.0 / ks0 ? p6.3 / ks3 p7.0 / ks4 ? p7.3 / ks7 input mode: connect to v dd output mode: no connection p8.0?p8.3 input mode: connect to v ss output mode: no connection nc connect to v ss
s3c7044/c7048/p7048 reset reset 9 - 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9 - 1 below. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? general-purpose registers e, a, l, h, x, w, z, and y ? serial i/o buffer register (sbuf) oscillation stabilization (31.3 ms / 4.19 mhz) idle mode operating mode reset input normal mode or power-down mode reset operation figure 9 - 1. timing for oscillation stabilization after reset reset
reset reset s3c7044/c7048/p7048 9 - 2 hardware reset values after reset reset table 9 - 1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation. table 9 - 1. hardware register values after reset reset hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower six bits of address 0000h are transferred to pc12?8, and the contents of 0001h to pc7?0. lower six bits of address 0000h are transferred to pc12?8, and the contents of 0001h to pc7?0. program status word (psw): carry flag (c) values retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined bank selection registers (smb, srb) 0, 0 0, 0 clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod1/2) 0 0 note: the values of the 0f8 h?0fdh are not retained when a reset signal is input.
s3c7044/c7048/p7048 reset reset 9 - 3 table 9 - 1. hardware register values after reset reset (continued) hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 output enable flag (boe) 0 0 timer/counters 0 and 1: count registers (tcnt0/1) 0 0 reference registers (tref0/1) ffh, ffh ffh, ffh mode registers (tmod0/1) 0 0 output enable flags (toe0/1) 0 0 watch timer: watch timer mode register (wmod) 0 0 serial i/o interface: sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined
s3c7044/c7048/p7048 i/o ports 10 - 1 10 i/o ports overview the s3c7044/c7048 has one input port and eight i/o ports. pin addresses for all i/o ports are mapped to locations ff0h?ffch in bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. there are total of four input pins and 32 configurable i/o pin for a maximum number of 36 i/o pins. port mode flags port mode flags (pm) are used to configure i/o ports 0, 4, 5, and 7 (port mode group 1), ports 2 and 3 (port mode group 2), port 6 (port mode group 3), and port 8 (port mode group 4) to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in four 8-bit registers in ram area fe8h?fefh, and are addressable by 8-bit write instructions only. pumod control register the pull-up mode registers (pumod1 and 2) are 8-bit registers used to assign internal pull-up resistors by software to specific i/o ports and pull-down resistors to port 8 . when configurable i/o ports 0, 2, 3, 6, and 8 serves as an output pin, its assigned pull-up/down resistor is automatically disabled, even though the pin's pull-up/down resis tor is enabled by a corresponding bit setting in the pull-up resistor mode register (pumod). pumod1 and 2 are mapped to ram address fdch?fdfh and are addressable by 8-bit write instructions only. reset clears pumod register values to logic zero , automatically disconnecting all software-assignable port pull-up and down resis tors.
i/o ports s3c7044/c7 048/p7048 10- 2 table 10 - 1 . i/o port overview port i/o pins pin names address function description 0 i/o 4 p0.0?p0.3 ff0h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as in - put or output. 4-bit pull-up resistors are assignable by software. 1 i 4 p1.0?p1.3 ff1h 4-bit input port. 1-bit and 4-bit read and test is possible. 3-bit pull-up resistors are software assignable to pins p1.0, p1.1, and p1.2. 2 i/o 4 p2.0?p2.3 ff2h same as port 0. 3 i/o 4 p3.0?p3.3 ff3h same as port 0. 4, 5 i/o 8 p4.0?p4.3 p5.0?p5.3 ff4h ff5h 4-bit i/o ports. n-channel open-drain output up to 9 volts. 1 -bit and 4-bit read/write/test is possible. ports 4 and 5 can be paired to sup port 8-bit data transfer. 8-bit unit pull-up resistors are assignable by mask option . 6, 7 i/o 8 p6.0?p6.3 p7.0?p7.3 ff6h ff7h 4-bit i/o ports. port 6 pins are individually soft ware configurable as input or output. 1-bit and 4 -bit read/write/test is possible. 4-bit pull -up resistors are software assignable. ports 6 and 7 can be paired for 8-bit data transfer. 8 i/o 4 p8.0?p8.1 ffch 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as in - put or output. 4-bit pull-down resistors are assignable by software. table 10 - 2 . port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p7 ea,p4 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
s3c7044/c7048/p7048 i/o ports 10 - 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports 0 and 2?8 to input or output mode by setting or clearing the corresponding i/o buffer. pm flags are stored in four 8-bit registers in ram area fe8h?fefh, and are ad - dressable by 8-bit write instructions only. for convenient program reference, pm flags are organized into four groups ? pmg1, pmg2, pmg3, and pmg4 as shown in table n. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logic zero, automatically configuring the corresponding i/o ports to input mode. table 10 - 3 . port mode groups port mode group id corresponding i/o ports port mode group address pmg1 ports 0, 4, 5, and 7 fe8h?fe9h pmg2 ports 2 and 3 feah?febh pmg3 port 6 fech?fedh pmg4 ports 8 feeh?fefh table 10 - 4 . port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe8h pm0.3 pm0.2 pm0.1 pm0.0 fe9h pm7 "0" pm5 pm4 pmg2 feah pm2.3 pm2.2 pm2.1 pm2.0 febh pm3.3 pm3.2 pm3.1 pm3.0 pmg3 fech pm6.3 pm6.2 pm6.1 pm6.0 fedh 0 0 0 0 pmg4 (2) feeh pm8.3 pm8.2 pm8.1 pm8.0 fefh 0 0 0 0 notes: 1. if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode. all flags are cleared to "0" following reset . 2. the higher 4 bits in the pmg4 must be set to "0". f f programming tip ? configuring i/o ports as input or output configure p0.3 and p2 as an output port and the other ports as input ports: bits emb smb 15 ld ea,#08h ld pmg1,ea ; p0.3 ? output, p0.0?0.2, p4, p5, p7 ? input ld ea,#0fh ld pmg2,ea ; p2.0 ?2.3 ? output, p3.0?3.3 ? input ld ea,#00h ld pmg3,ea ; p6 ? input ld pmg4,ea ; p8 ? input
i/o ports s3c7044/c7 048/p7048 10- 4 pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod1 and 2) are 8-bit registers used to assign internal pull-up resistors by soft ware to specific i/o ports and pull-down resistor to port 8. i/o ports 4 and 5 are an exception, since these port pins may only be assigned internal pull-up resistors via mask option. when configurable i/o ports 0, 2, 3, 6, and 8 are used as an output pin, its assigned pull-up or pull-down resistor is automatically disabled, even though the pin's pull-up or pull-down is enabled by a corresponding pumod bit setting. pumod1 and pumod2 are mapped to ram addresses fdch?fddh and fdeh?fdfh respectively, and are addressable by 8-bit write instructions only. reset clears pumod register values to logic zero, automatically disconnecting all software-assignable port pull-up and down resis tors. table 10 - 5 . pull-up resistor mode register (pumod) organization pumod id address bit 3 bit 2 bit 1 bit 0 pumod1 fdch pur3 pur2 pur1 pur0 fddh "0" "0" pur7 pur6 pumod2 fdeh "0" (2) pdr8 "0" "0" fdfh "0" "0" "0" "0" notes: 1. when bit = "1", pull-up resistors are assigned to the corresponding i/o port: pur3 for port 3, pur2 for port 2, and so on. if bit pdr8 is set to 1, pull-down resistors are assigned to port 8. 2. bit 3 in the pumod2 must be set to "0". f f programming tip ? enabling and disabling i/o port pull-up resistors p6 and p7 enable pull-up resistors, p0?p3 disable pull-up resistors. bits emb smb 15 ld ea,#30h ld pumod1,ea ; p6 and p7 enable
s3c7044/c7048/p7048 i/o ports 10 - 5 port 0 circuit diagram sck si btco pm0.2 pm0.3 pm0.1 pm0.0 v dd when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: p0.0/ sck p0.1/so p0.2/si p0.3/btco pur0 pur0 pur0 pur0 sck so p0.2 latch p0.1 latch p0.0 latch p0.3 latch figure 10 - 1 . port 0 circuit diagram
i/o ports s3c7044/c7 048/p7048 10- 6 port 1 circuit diagram v dd v dd v dd int0 int1 int2 int4 p1.0 / int0 pur1 p1.1 / int1 p1.2 / int2 p1.3 / int4 n/r = noise reduction imod0 n/r circuit figure 10 - 2 . port 1 circuit diagram
s3c7044/c7048/p7048 i/o ports 10 - 7 port 2, 3, 6 circuit diagram v dd 1, 4, 8 1, 4, 8 x = port number (2, 3, 6) when a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: purx purx purx purx m u x pmx.2 pmx.3 pmx.1 pmx.0 px.0 px.1 px.2 px.3 output latch figure 10 - 3 . port 2, 3, and 6 circuit diagram
i/o ports s3c7044/c7 048/p7048 10- 8 port 4, 5 circuit diagram mask option n-channel open-drain 8 x = 4 and 5 (port 4 and port 5) 1, 4, 8 1, 4, 8 v dd v dd v dd v dd pmx m u x px.0 px.1 px.2 px.3 output latch figure 10 - 4 . port 4 and 5 circuit diagram
s3c7044/c7048/p7048 i/o ports 10 - 9 port 7 circuit diagram 8 1, 4 1, 4 v dd v dd v dd v dd m u x output latch p7.0 / ks4 p7.1 / ks5 p7.2 / ks6 p7.3 / ks7 pm7 pur7 figure 10 - 5 . port 7 circuit diagram
i/o ports s3c7044/c7 048/p7048 10- 10 port 8 circuit diagram 8 1, 4 1, 4 p8.b pm8.b output latch m u x when a port pin acts as an output, its pull-down resistor is automatically disabled, even though the port's pull-down resistor is enabled by bit settings to the pumod register. note: pdr8 (b = 0, 1, 2, 3) figure 10 - 6 . port 8 circuit diagram
s3c7044/c7048/p7048 timers and timer/counters 11 - 1 11 timers and timer/counters overview the s3c7044/c7048 microcontroller has four timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counters (tc0, 1) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer. it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. when the contents of the basic timer counter register bcnt overflows, a pulse is output to the basic timer output pin, btco. the basic timer also functions as a 'watchdog' timer and is used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counters (tc0, 1) are programmable timer/counters that are used primarily for event counting and for clock frequency modification and output. in addition, tc0 generates a clock signal that can be used by the serial i/o interface. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, system clock interval timing, buzzer output generation.
timers and timer/counters s3c7044/c7048/p7048 11 - 2 basic timer (bt) overview the 8-bit basic timer (bt) has four functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? output enable flag (boe) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. timer pulses are output from the basic timer's counter register bcnt to the output pin btco when an overflow occurs in the counter register bcnt. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod is set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs (3 255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of specific system events. each time bcnt overflows, an overflow signal is sent to the basic timer clock output pin, btco. the sequence of the btco output operation is as follows: ? set the boe flag to logic one ? set the output latch for pin p0.3 to logic zero ? set the port mode flag for p0.3 (pm0.3) to logic one when the irqb flag is set and the interrupt is requested, the bcnt overflow signal is sent to the p0.3 latch to be output through the btco pin. oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when stop mode is released by an interrupt. when a reset signal is input, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19 mhz.
s3c7044/c7048/p7048 timers and timer/counters 11 - 3 table 11 - 1 . basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or reset 4-bit f85h 4-bit write- only; bmod.3: 1-bit writeable "0" bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h?f87h 8-bit read-only u ( note ) boe flag controls output of basic timer out - put latch to the btco pin 1-bit f92h.1 1-bit read/write "0" note: 'u' means the value is undetermined after a reset . "clear" signal bits instruction bmod.3 bmod.2 bmod.1 bmod.0 clock selector bcnt irqb interrupt request overflow cpu clock start signal (power-down release) 1-bit r/w clock input clear irqb clear bcnt btco / p0.3 4 8 boe p0.3 latch figure 11 - 1 . basic timer circuit diagram
timers and timer/counters s3c7044/c7048/p7048 11 - 4 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register located at ram address f85h. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer ? control the frequency of clock signal input to the basic timer ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fx/2 12 to fx/2 5 , are se lectable. since bmod's reset value is logic zero, the default clock frequency setting is fx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 11 - 2 . basic timer mode register (bmod) organization bmod.3 basic timer enable/disable control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 0 0 0 fx/2 12 (1.02 khz) 2 20 /fx (250 ms) 0 1 1 fx/2 9 (8.18 khz) 2 17 /fx (31.3 ms) 1 0 1 fx/2 7 (32.7 khz) 2 15 /fx (7.82 ms) 1 1 1 fx/2 5 (131 khz) 2 13 /fx (1.95 ms) notes : 1. clock frequencies and oscillation stabilization assume a system oscillator clock frequency (fx) of 4.19 mhz. 2. fx = system clock frequency. 3. oscillation stabilization time is the time requir ed to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
s3c7044/c7048/p7048 timers and timer/counters 11 - 5 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it is mapped to ram addresses f86h?f87h and can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incremented to hexadecimal 'ffh' ( 3 255 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer output enable flag (boe) the 1-bit basic timer output enable flag, boe, is mapped to the second bit of a 4-bit register at ram location f92h. it can be addressed by 1 -bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h toe1 toe0 boe 0 the boe flag value enables and disables basic timer output to the btco pin at i/o port 0 (p0.3). when boe is logic zero, basic timer output to the btco pin is disabled; when it is logic one, bt output to the btco pin is enabled. a reset clears the boe flag to "0", disabling basic timer output to the btco pin. when the boe flag is set to "1" and the bcnt register overflows, the overflow signal is sent to the btco pin. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set counter buffer bit (bmod.3) to logic one to restart the basic timer 2. bcnt is then incremented by one after each clock pulse corresponding to bmod selection 3. bcnt overflows if bcnt 3 255 (bcnt = ffh) 4. when an overflow occurs, the irqb flag is set by hardware to logic one 5. the interrupt request is generated 6. bcnt is then cleared by hardware to logic zero 7. basic timer resumes counting clock pulses
timers and timer/counters s3c7044/c7048/p7048 11 - 6 f f programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
s3c7044/c7048/p7048 timers and timer/counters 11 - 7 8-bit timer/counters 0 and 1 (tc0, tc1) overview the s3c7044/c7048 's tc0 and tc1 are identical except that they have different counter clock sources, which are controlled by the tmodn register. timer/counters 0 and 1 (tc0, tc1) are used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc can be used to measure specific time intervals. a timer/counter has a reloadable counter that consists of two parts: an 8-bit reference register, trefn (n = 0, 1) into which you write the counter reference value, and an 8-bit counter register ,tcntn (n = 0, 1) whose value is automatically incremented by counter logic. 8-bit mode register, tmodn (n = 0, 1), is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmodn register during program execution. tc function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock fre - quency. external event counter counts various system "events" based on edge detection of external clock sig - nals at the tc input pin, tcln (n = 0, 1). to start the event counting operation, tmodn.2 is set to "1" and tmodn.6 is cleared to "0". arbitrary frequency output outputs clock frequencies to the tc output pin, tclon (n = 0, 1). external signal divider divides the frequency of an incoming external clock signal according to a modi fiable reference value (trefn), and outputs the modified frequency to the tclon pin. serial i/o clock source tc0 can output a modifiable clock signal for use as the sck clock source.
timers and timer/counters s3c7044/c7048/p7048 11 - 8 tc component summary mode register (tmodn) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcln pin. reference register (trefn) stores the reference value for the desired number of clock pulses between interrupt requests. counter register (tcntn) counts internal or external clock pulses based on the bit settings in tmodn and trefn. clock selector circuit together with the mode register (tmodn), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determ ines when to generate an interrupt by comparing the current value of the counter register (tcntn) with the reference value previously programmed into the reference register (trefn). output latch (toln) where a tc clock pulse is stored pending output to the serial i/o circuit or to the tc output pin, tclon. when the contents of the tcntn and trefn registers coincide, the timer/counter interrupt request flag (irqtn) is set to "1", the status of toln is in verted, and an interrupt is generated. output enable flag (toen) must be set to logic one before the contents of the toln latch can be output to tclon. interrupt request flag (irqtn) cleared when tc operation starts and the tc interrupt service routine is executed and set to one whenever the counter value and reference value coincide. interrupt enable flag (ietn) must be set to logic one before the interrupt requests generated by timer/counters can be processed. table 11 - 3 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 tmod1 control controls tc0 and tc1 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h fa0h?fa1h 8-bit write- only; (tmodn.3 is also 1 -bit writeable) "0" tcnt0 tcnt1 counter counts clock pulses matching the tmodn frequency setting 8-bit f94h?f95h fa4h?fa5h 8-bit read-only "0" tref0 tref1 reference stores reference value for the timer/counters interval setting 8-bit f96h?f97h fa8h?fa9h 8-bit write-only ffh toe0 toe1 flag controls timer/counters output to the tclon pin 1-bit f92h.2 f92h.3 1-bit write-only "0"
s3c7044/c7048/p7048 timers and timer/counters 11 - 9 tcln tclon serial i/o (tc0 only) clock selector tcntn 8-bit comparator toln p2.n latch toen irqtn pm2.n tmodn.7 tmodn.6 tmodn.5 tmodn.4 tmodn.3 tmodn.2 tmodn.1 tmodn.0 trefn clear inverted clear set clear clocks (fx/2 , fx/2 , fx/2 , fx) 10 6 4 8 8 8 figure 11 - 2 . tc0 circuit diagram tc enable/disable procedure enable timer/counter ? set tmodn.2 to logic one ? set the tc interrupt enable flag ietn to logic one ? set tmodn.3 to logic one tcntn, irqtn, and toln are cleared to logic zero, and timer/counter operation starts. disable timer/counter ? set tmodn.2 to logic zero clock signal input to the counter register tcntn is halted. the current tcntn value is retained and can be read if necessary.
timers and timer/counters s3c7044/c7048/p7048 11 - 10 programmable timer/counter function timer/counters can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc mode register tmodn is used to activate the timer/counter and to select the clock frequency. the reference register trefn stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcntn, counts the incoming clock pulses, which are compared to the trefn value as tcntn is incremented. when there is a match (trefn = tcntn), an interrupt request is generated. to program timer/counter to generate interrupt requests at specific intervals, choose one of four internal clock frequencies (divisions of the system clock, fx) and load a counter reference value into the reference register. the count register is incremented each time an internal counter pulse is detected with the reference clock frequency specified by tmodn.4?tmodn.6 settings. to generate an interrupt request, the tc interrupt request flag (irqtn) is set to logic one, the status of toln is inverted, and the interrupt is generated. the content of the counter register is then cleared to 00h and tc continues counting. the interrupt request mechanism for tc includes an interrupt enable flag (ietn) and an interrupt request flag (irqtn). tc operation sequence the general sequence of operations for using tc can be summarized as follows: 1. set tmodn.2 to "1" to enable tc0 and tc1 2. set tmodn.6 to "1" to enable the system clock (fx) input 3. set tmodn.5 and tmodn.4 bits to desired internal frequency (fx/2 n ) 4. load a value to trefn to specify the interval between interrupt requests 5. set the tc interrupt enable flag (ietn) to "1" 6. set tmodn.3 bit to "1 " to clear tcntn, irqtn, and toln, and start counting 7. tcntn increments with each internal clock pulse 8. when the comparator shows tcntn = trefn, the irqtn flag is set to "1" 9. output latch (toln) logic toggles high or low 10. interrupt request is generated 11. tcntn is cleared to 00h and counting resumes 12. programmable timer/counter operation continues until tmodn.2 is cleared to "0".
s3c7044/c7048/p7048 timers and timer/counters 11 - 11 event counter function timer/counters can monitor or detect system 'events' by using the external clock input at the tcln pin as the counter source. the tc mode register selects rising or falling edge detection for incoming clock signals. the counter register is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmodn.4?tmodn.6 settings, the operation sequence for tc's event counter function is identical to its programmable timer/counter function. to activate the tc event counter function, ? set tmodn.2 to "1" to enable tc; ? clear tmodn.6 to "0" to select the external clock source at the tcln pin; ? select tcln edge detection for rising or falling signal edges by loading the appropriate values to tmodn.5 and tmodn.4. ? p3.0 and p3.1 must be set to input mode. table 11 - 4 . tmodn settings for tcln edge detection tmodn.5 tmodn.4 tcln edge detection 0 0 rising edges 0 1 falling edges
timers and timer/counters s3c7044/c7048/p7048 11 - 12 tc clock frequency output using timer/counters, a modifiable clock frequency can be output to the timer/counter clock output pin, tclon. to select the clock frequency, load the appropriate values to the tc mode register, tmodn. the clock interval is selected by loading the desired reference value into the reference register trefn. in summary, the operational sequence required to output a tc-generated clock signal to the tclon pin is as follows: 1. load a reference value to trefn. 2. set the internal clock frequency in tmodn. 3. i nitiate tcn clock output to tclon (tmodn.2 = "1"). 4. set port 2 mode flag (pm2.0 and pm 2.1) to "1". 5. set p2.0 and p2.1 output latches to "0". 6. set toen flag to "1". each time tcntn overflows and an interrupt request is generated, the state of the output latch toln is in verted and the tc-generated clock signal is output to the tclon pin. f f programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#01h ld pmg2,ea ; p2.0 ? output mode bitr p2.0 ; p2.0 clear bits toe0
s3c7044/c7048/p7048 timers and timer/counters 11 - 13 tc0 serial i/o clock generation timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. use tmod0 and tref0 register settings to select the frequency and interval of the tc0 clock signals to be used as sck input to the serial interface. the generated clock signal is then sent directly to the serial i/o clock selector circuit ? not through the port 2.0 latch and tclo0 pin (the toe0 flag may be disabled). tc external input signal divider by selecting an external clock source and loading a reference value into the tc reference register, trefn, you can divide the incoming clock signal by the trefn value and then output this modified clock frequency to the tclon pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the trefn register 2. clear tmodn.6 to "0" to enable external clock input at the tcln pin 3. set tmodn.5 and tmodn.4 to desired tcln signal edge detection 4. set port 2 mode flag (pm2.0, pm2.1) to out put ("1") 5. set p2.0 and p2.1 output latches to "0" 6. set toen flag to "1" to enable output of the divided frequency to the tclon pin f f programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divide by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,#01h ld pmg2,ea ; p2.0 ? output mode bitr p2.0 ; p2.0 clear bits toe0
timers and timer/counters s3c7044/c7048/p7048 11 - 14 tc mode register (tmod n ) tmodn are the 8-bit mode control registers for timer/counter 0 and 1. they are located at ram addresses f90h?f91h, fa0h?fa1h respectively, and are addressable by 8-bit write instructions. one bit, tmodn.3, is also 1-bit writeable. reset clears all tmodn bits to logic zero and disables tc operations. f90h tmod0.3 tmod0.2 "0" "0" tmod0 f91h "0" tmod0.6 tmod0.5 tmod0.4 fa0h tmod1.3 tmod1.2 "0" "0" tmod1 fa1h "0" tmod1.6 tmod1.5 tmod1.4 tmodn.2 is the enable/disable bit for timer/counter 0 and 1. when tmodn.3 is set to "1", the contents of tcntn, irqtn, and toln are cleared, counting starts from 00h, and tmodn.3 is automatically reset to "0" for normal tc operation. when tc operation stops (tmodn.2 = "0"), the contents of the counter register tcntn are retained until tc is re-enabled. the tmodn.6, tmodn.5, and tmodn.4 bit settings are used together to select the tc clock source. this selection involves two variables: ? synchroniza tion of timer/counter operations with either the rising edge or the falling edge of the clock sig nal input at the tcln pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc operation. table 11 - 5 . tc mode register (tmodn) organization bit name setting resulting tc0 function address tmodn.7 0 always logic zero f91h (tmod0) tmodn.6 fa1h (tmod1) tmodn.5 0,1 specify input clock edge and internal frequency tmodn.4 tmodn.3 1 clear tcntn, irqtn, and toln and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) f90h (tmod0) fa0h (tmod1) tmodn.2 0 disable timer/counter; retain tcntn contents 1 enable timer/counter tmodn.1 0 always logic zero tmodn.0 0 always logic zero
s3c7044/c7048/p7048 timers and timer/counters 11 - 15 table 11 - 6 . tmodn.6, tmodn.5, and tmodn.4 bit settings tmodn.6 tmodn.5 tmodn.4 tc0 counter source tc1 counter source 0 0 0 external clock input (tcl0) on rising edges external clock input (tcl1) on rising edges 0 0 1 external clock input (tcl0) on falling edges external clock input (tcl1) on falling edges 1 0 0 fx/2 10 (4.09 khz) fx/2 12 (1.02 khz) 1 0 1 fx /2 6 (65.5 khz) fx /2 10 (4.09 khz) 1 1 0 fx/2 4 (262 khz) fx/2 8 (16.4 khz) 1 1 1 fx = 4.19 mhz fx/2 6 (65.5 khz) note : 'fx' = system clock of 4.19 mhz. f f programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
timers and timer/counters s3c7044/c7048/p7048 11 - 16 tc counter register (tcnt n ) the 8-bit counter register, tcntn, is mapped to ram addresses f94h?f95h and fa4h?fa5h respectively. it is read-only and can be addressed by 8-bit ram control instructions. reset sets all counter register values to logic zero (00h). whenever tmodn.3 is enabled, tcntn is cleared to logic zero and counting resumes. the tcntn register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmodn register (specifically, tmodn.6?tmodn.4). each time tcntn is incremented, the new value is compared to the reference value stored in the reference register, trefn. when tcntn = trefn, an overflow occurs in the counter register, the interrupt request flag, irqtn, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. ~ ~ count clock tcntn toln timer start instruction (tmodn.3 is set) trefn reference value = n 0 1 2 n-1 n 0 1 2 n-1 0 1 2 n interval time irqtn set irqtn set match match 3 ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ figure 11 - 3 . tc timing diagram
s3c7044/c7048/p7048 timers and timer/counters 11 - 17 tc reference register (tref n ) the tc reference register trefn is an 8-bit write-only register that is mapped to ram locations f96h?f97h and fa8h?fa9h respectively. it is addressable by 8-bit ram control instructions. reset initializes the trefn value to 'ffh'. trefn is used to store a reference value to be compared to the incrementing tcntn register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the counter value. when tcntn = trefn, the tc output latch (toln) is inverted and an interrupt request is generated to signal the interval or event. the trefn value, together with the tmodn clock frequency selection, determines the specific tc timer interval. use the following formula to calculate the correct value to load to the trefn reference register: tc timer interval = (trefn value + 1) 1 tmodn frequency setting ( assuming a trefn value 1 0 ) tc output enable flag (toe n ) the 1-bit timer/counter output enable flag toen controls output from timer/counter to the tclon pin. toen is mapped to ram locations f92h.2?f92h.3 and is addressable by 1-bit read and write instructions. bit 3 bit 2 bit 1 bit 0 f92h toe1 toe0 boe 0 when you set the toen flag to "1", the contents of toln can be output to the tclon pin. whenever a reset occurs, toen is automatically set to logic zero, disabling all tc output. even when the toe0 flag is disabled, timer/counter 0 can continue to output an internally-generated clock frequency, via tol0, to the serial i/o clock selector circuit. tc output latch (tol n ) toln is the output latch for timer/counter 0 and 1. when the 8-bit comparator detects a correspondence between the value of the counter register tcntn and the reference value stored in the trefn register, the toln value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of toln is switched, the tc signal is output. tc output may be directed to the tclon pin. tc0 signal can also be output directly to the serial i/o clock selector circuit as the sck signal. assuming tc is enabled, when bit 3 of the tmodn register is set to "1", the toln latch is cleared to logic zero, along with the counter register and the interrupt request flag, irqtn, and counting resumes immedi ately. when tcn is disabled (tmodn.2 = "0"), the contents of the toln latch are retained and can be read, if necessary.
timers and timer/counters s3c7044/c7048/p7048 11 - 18 f f programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref 0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
s3c7044/c7048/p7048 timers and timer/counters 11 - 19 watch timer overview the watch timer is a multi-purpose timer consisting of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the system clock. it is also used as a clock source for generating buzzer output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register, wmod.2, to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5- second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a system clock source the watch timer can generate interrupts based on the system clock frequency. the system clock (fx) is used as the signal source, according to the following for mula: watch timer clock (fw) = system clock (fx) 128 = 32.768 khz (assuming fx = 4.19 mhz) buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal at 4.19 mhz to the buz pin. to select the buz frequency you want, load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit at f89h.3 is set to "1" ? the output latch for i/o port 2.3 is cleared to "0" ? the port 2.3 output mode flag (pm2.3) set to 'output' mode timing tests in high-speed mode by setting wmod.1 (f88h.1) to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms at 4.19 mhz. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high-speed mode is useful for timing events for program debugging sequences.
timers and timer/counters s3c7044/c7048/p7048 11 - 20 8 selector circuit irqw gnd fx/128 fw (32.768 khz) mux fw/2 7 fw/2 14 enable / clock selector fx = system clock (assumed to be 4.19 mhz) fw = watch timer frequency buz wmod.7 0 wmod.5 wmod.4 0 wmod.2 wmod.1 0 p2.3 latch pm2.3 disable fw/8 (4 khz) fw/4 (8 khz) fw/2 (16 khz) fw/16 (2 khz) frequency dividing circuit figure 11 - 4 . watch timer circuit diagram
s3c7044/c7048/p7048 timers and timer/counters 11 - 21 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. reset sets all wmod bits to logic zero. f88h "0" wmod.2 wmod.1 "0" f89h wmod.7 "0" wmod.5 wmod.4 in brief, wmod settings control the following watch timer functions: ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? buzzer frequency selection (wmod.4) (wmod.5) ? enable/disable buzzer output (wmod.7) table 11 - 7 . watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 "0" always logic zero wmod.5 ? .4 0 0 2 khz buzzer (buz) signal output f89h 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 "0" always logic zero wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer f88h wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 always logic zero (must be set to zero) note : system clock frequency (fx) is assumed to be 4.19 mhz.
timers and timer/counters s3c7044/c7048/p7048 11 - 22 f f programming tip ? using the watch timer 1. select a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#80h ld pmg2,ea ; p2.3 ? output mode bitr p2.3 ; clear p2.3 output latch ld ea,#84h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
s3c7044/c7048/p7048 serial i/o interfac e 12 - 1 12 serial i/o interfac e overview the serial i/o interface (sio) has the following functional components: ? 8-bit mode register (smod) ? clock selector circuit ? 8-bit buffer register (sbuf) ? 3-bit serial clock counter using the serial i/o interface, you can exchange 8-bit data with an external device. you control the transmission frequency by the appropriate bit settings to the smod register. the serial interface can run off an internal or an external clock source, or the tol0 signal that is generated by the 8-bit timer/counter 0, tc0. if you use the tol0 clock signal, its frequency can be modified to adjust the serial data transmission rate. sio operation sequence the general sequence of operations for the serial i/o interface may be summarized as follows: 1. set sio mode to transmit-and-receive or to receive-only. 2. select msb-first or lsb-first transmission mode. 3. set the sck clock signal in the mode register, smod. 4. set sio interrupt enable flag (ies) to "1". 5. initiate sio transmission by setting bit 3 of the smod to "1". 6. when the sio operation is completed, irqs flag is set and an interrupt is generated.
s erial i/o interface s3c7044/c7048/p7048 12 - 2 * instruction execution fx: system clock 8 internal bus internal bus lsb or msb first sbuf (8-bit) si clock selector r q d tol0 fx/2 10 cpu clk fx/2 4 r s q so smod.7 smod.6 smod.5 - smod.3 smod.2 smod.1 smod.0 q0 q1 q2 3-bit counter clear overflow p0.0/ sck irqs ck bits * 8 figure 12 - 1. serial i/o interface circuit diagram
s3c7044/c7048/p7048 serial i/o interfac e 12 - 3 serial i/o mode register (smod) the serial i/o mode register, smod, is an 8-bit register that specifies the operation mode of the serial interface. smod is mapped to ram address fe0h?fe1h and its reset value is logic zero. smod is organized in two 4- bit registers, as follows: fe0h smod.3 smod.2 smod.1 smod.0 fe1h smod.7 smod.6 smod.5 0 smod register settings enable you to select either msb-first or lsb-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. smod is a write-only register and can be addressed only by 8-bit ram control instructions. one exception to this is smod.3, which can be written by a 1-bit ram control instruction. when smod.3 is set to 1, the contents of the serial interface interrupt request flag, irqs, and the 3-bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to logic zero. table 12 - 1. sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode; output buffer is off 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol0 clock from tc0 0 1 x cpu clock: fx/4, fx/8, fx/64 enable sbuf read/write 1 0 0 4.09 khz clock: fx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 1 1 1 262 khz clock: fx/2 4 notes : 1. 'fx' = system clock; 'x' means 'don't care.' 2. khz frequency ratings assume a system clock (fx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fx/2 4 clock if the cpu clock is fx/64 .
s erial i/o interface s3c7044/c7048/p7048 12 - 4 serial i/o timing diagrams sck si so irqs di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transmit complete set smod.3 figure 12 - 2. sio timing in transmit/receive mode sck si so irqs di7 di6 di5 di4 di3 di2 di1 di0 transmit complete set smod.3 high impedance figure 12 - 3. sio timing in receive-only mode
s3c7044/c7048/p7048 serial i/o interfac e 12 - 5 serial i/o buffer register (sbuf) when the serial interface operates in transmit-and-receive mode (smod.1 = "1"), transmit data in the sio buffer register are output to the so pin (p0.1) at the rate of one bit for each falling edge of the sio clock. receive data is simultaneously input from the si pin (p0.2) to sbuf at the rate of one bit for each rising edge of the sio clock. when receive-only mode is used, incoming data is input to the sio buffer at the rate of one bit for each rising edge of the sio clock. sbuf can be read or written using 8-bit ram control instructions. it is mapped to addresses fe4h?fe5h. following a reset , the value of sbuf is undetermined. f f programming tip ? setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock freq uency of fx/2 4 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output ld ea,#48h ; ld sbuf,ea ; ld ea,#0eeh ld smod,ea ; sio data transfer external device sck / p0.0 so / p0.1 2. use cpu clock to transfer and receive serial data at high speed: bitr emb ld ea, #03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea, tdata ; tdata address = bank0 (20h-7fh) ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies ; sio interrupt enable stest btstz irqs jr stest ld ea,sbuf ld rdata,ea ; rdata address = bank0 (20h-7fh)
s erial i/o interface s3c7044/c7048/p7048 12 - 6 f f programming tip ? setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode: bits emb ld ea, #03h ld pmg1 ,ea ; p0.0 / sck and p0.1 / so ? output, p0.2/si ? input ld ea, tdata ; tdata address = bank0 (20h-7fh) ld sbuf,ea ld ea,#8fh ld smod,ea ; sio start ei bits ies ; sio interrupt enable ? ? ? ints push sb ; store smb, srb push ea ; store e a bitr e mb ld ea,tdata ; ea ? receive data ; tdata address = bank0 (20h-7fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h-7fh) bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2
s3c7044/c7048/p7048 serial i/o interfac e 12 - 7 f f programming tip ? setting transmit/receive modes for serial i/o (continued) 4. transmit and receive an external clock in lsb-first mode: bit r emb ld ea, #02h ld pmg ,ea ; p0.1 / so ? output, p0.0 / sck and p0.2 / si ? i nput ld ea,tdata ; tdata address = bank0 (20h-7fh) ld sbuf, ea ld ea,#0fh ld smod,ea ; sio start ei bits ies ; sio interrupt enable ? ? ? ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data ; tdata address = bank0 (20h-7fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h-7fh) bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2 high speed sio transmission
s3c7044/c7048/p7048 electrical data 13- 1 13 electrical data in this section, information on s3c7044/c7048 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when in itiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c 7044/c7048/p7048 13- 2 table 13-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports except 4 and 5 ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) ma + 15 (note) all i/o ports, total + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty .
s3c7044/c7048/p7048 electrical data 13- 3 table 13-2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih4 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6, 7, and reset 0.8 v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd ports 4 and 5 are open-drain v ih4 x in and x out v dd ? 0.1 input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1 output high voltage v oh i oh = ? 1 ma ports except 1, 4, and 5 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma, ports 4, 5 only ? ? 2 v v dd = 1.8 to 5.5 v i ol = 1.6ma 0.4 v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma all output ports except ports 4,5 2 v dd = 1.8 to 5.5 v i ol = 1.6ma 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in and x out 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20
electrical data s3c 7044/c7048/p7048 13- 4 table 13-2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output high leakage current i loh v o = v dd, all output pins ? ? 3 a output low leakage current i lol v o = 0 v, all output pins ? ? ? 3 a pull-up resistor r l1 v i = 0 v; v dd = 5 v ports 0, 1 (not p1.3), 2, 3, 6, 7 25 47 100 k w v dd = 3 v 50 95 200 r l2 v o = v dd ? 2v; v dd = 5v ports 4 and 5 only 15 47 70 v dd = 3 v 10 45 60 r l3 v dd = 5 v; v i = 0v; reset 100 220 400 v dd = 3 v 200 450 800 pull-down r l4 v dd = 5 v; v i = v dd ; port 8 25 47 100 k w resistor v dd = 3 v 50 95 200 supply i dd1 run mode; v dd = 5 v 10% 6.0 mhz ? 3.9 8.0 ma current (1) crystal oscillator; c1 = c2 = 22 pf 4.19 mhz 2.9 5.5 v dd = 3 v 10% 6.0 mhz 1.8 4.0 4.19 mhz 1.3 3.0 i dd2 run mode; v dd = 5 v 10% 6.0 mhz ? 1.3 2.5 ma crystal oscillator, c1 = c2 = 22 pf 4.19 mhz 1.2 1.8 v dd = 3 v 10% 6.0 mhz 0.5 1.5 4.19 mhz 0.44 1.0 i dd3 stop mode; v dd = 5 v 10% ? 0.2 3 a stop mode; v dd = 3 v 10% 0.1 2 notes 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. the supply current assumes a cpu clock of fx/4.
s3c7044/c7048/p7048 electrical data 13- 5 table 13-3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3 v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 1.8 v to 5.5 v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c 7044/c7048/p7048 13- 6 table 13-4. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out i/o capacitance c io table 13-5. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 1.8 v to 5.5 v 0.95 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 1.8 v to 5.5v 1 tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 1.8 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? s internal sck source 670 v dd = 1.8 v to 5.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh, t kl v dd = 2.7 v to 5.5 v external sck source 335 ? ? s internal sck source t kcy / 2 ? 50 v dd = 1.8 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 ? 150
s3c7044/c7048/p7048 electrical data 13- 7 table 13-5. a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 1.8 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 1.8 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 (2) ? ? m s int1, int2, int4, ks0 - ks7 10 reset input low width t rsl input 10 ? ? m s notes 1. r(1kohm) a nd c(100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data s3c 7044/c7048/p7048 13- 8 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 2 3 4 5 6 7 supply voltage (v) 1.05 khz 1.5 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) figure 13-1. standard operating voltage range table 13-6. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.5 ? 5.5 v data retention supply current i dddr v dddr = 1.5 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait t wait released by reset ? 2 17 /fx ? ms time (1) released by interrupt ? (2) ? ms notes 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c7044/c7048/p7048 electrical data 13- 9 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 13-2. stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 13-3. stop mode release timing when initiated by interrupt request
electrical data s3c 7044/c7048/p7048 13- 10 timing waveforms (continued) 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 13-4. a.c. timing measurement points (except for x in ) xin t xl t xh 1 / fx v dd ? 0.1 v 0.1 v figure 13-5. clock timing measurement at x in tcl t til t tih 1 / f ti 0.8 v dd 0.2 v dd figure 13-6. tcl timing
s3c7044/c7048/p7048 electrical data 13- 11 reset t rsl 0.2 v dd figure 13-7. input timing for reset reset signal int0, 1, 2, 4 ks0 to ks7 t intl t inth 0.8 v dd 0.2 v dd figure 13-8. input timing for external interrupts and quasi-interrupts
electrical data s3c 7044/c7048/p7048 13- 12 sck tkl tkh tkcy 0.8 vdd input data output data 0.2 vdd 0.8 vdd 0.2 vdd si so tkso tsik tksi figure 13-9. serial data transfer timing
s3c7044/c7048/p7048 echanical data 14 - 1 14 mechanical data this section contains the following information about the device package: ? 42-sdip-600 package dimensions in millimeters ? 44-qfp-1010b package dimensions in millimeters n o t e : d i m e n s i o n s a r e i n m i l l i m e t e r s . 4 2 - s d i p - 6 0 0 1 4 . 0 0 0 . 2 0 . 5 0 0 . 1 3 9 . 1 0 0 . 2 0 ~ 1 5 0 . 2 5 + 0 . 1 ? 0 . 0 5 # 1 # 2 1 # 4 2 # 2 2 1 5 . 2 4 ( 1 . 7 7 ) 1 . 0 0 0 . 1 1 . 7 7 8 0 . 5 1 m i n 3 . 5 0 0 . 2 3 . 3 0 0 . 3 5 . 0 8 m a x figure 14 - 1. 42-sdip-600 package dimensions
mechanical data s3c 7044/c7048/p7048 14 - 2 n o t e : d i m e n s i o n s a r e i n m i l l i m e t e r s . 4 4 - q f p - 1 0 1 0 b 1 3 . 2 0 0 . 3 0 1 0 . 0 0 0 . 2 # 4 4 1 3 . 2 0 0 . 3 0 1 0 . 0 0 0 . 2 # 1 0 . 8 0 0 . 8 0 0 . 2 0 0 . 1 5 + 0 . 1 ? 0 . 0 5 0 . 1 m a x 0 . 0 m i n 2 . 0 5 0 . 1 2 . 3 0 m a x 0 ~ 8 0 . 3 5 + 0 . 1 0 - 0 . 0 5 1 . 0 0 figure 14 - 2. 44-qfp-1010b package dimensions
s3c7044/c7048/p7048 S3P7048 otp 15- 1 15 S3P7048 otp overview the S3P7048 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c7044/c7048 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P7048 is fully compatible with the s3c7044/c7048, both in function and in pin configuration. because of its simple programming requirements, the S3P7048 is ideal for use as an evaluation chip for the s3c7044/c7048. p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/ sck p8.3 p8.2 p8.1 p8.0 p3.3 p3.2 sdat /p3.1/tcl1 sclk /p3.0/tcl0 v dd /v dd S3P7048 (42-sdip-600) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 v ss / v ss p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 x in x out reset/ reset reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 test/ test 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 note: the bolds indicate an otp pin name. figure 15-1. S3P7048 pin assignments (42-sdip package)
S3P7048 otp s3c7044/c7048/p7048 15- 2 p5.3 p5.2 p5.1 p5.0 reset reset /reset x out x in p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 S3P7048 (44-qfp-1010b) 1 2 3 4 5 6 7 8 9 10 11 nc p8.0 p8.1 p8.2 p8.3 p0.0/ sck p0.1/so p0.2/si p0.3/btco p2.0/tclo0 p2.1/tclo1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 nc p3.3 p3.2 sdat /p3.1/tcl1 sclk /p3.0/tcl0 v dd /v dd test /test p4.3 p4.2 p4.1 p4.0 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 v ss /v ss p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p2.3/buz p2.2/clo note: the bolds indicate an otp pin name. figure 15-2. S3P7048 pin assignments (44-qfp package)
s3c7044/c7048/p7048 S3P7048 otp 15- 3 table 15-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p3.1 sdat 19 (37) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p3.0 sclk 20 (38) i/o serial clock pin. input only pin. test v pp (test) 22 (40) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 31 (5) i chip initialization v dd /v ss v dd /v ss 21/42(39/16) i logic power supply pin. v dd should be tied to +5 v during programming. note: ( ) means the 44-qfp otp pin number. table 15-2. comparison of S3P7048 and s3c7044/c7048 features characteristic S3P7048 s3c7044/c7048 program memory 8 k-byte eprom 4 k-byte mask rom: s3c7044 8 k-byte mask rom: s3c7048 operating voltage (v dd ) 2.0 v to 5.5 v 1.8 v to 5.5v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 42sdip, 44qfp 42sdip, 44qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P7048, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 15-3 below. table 15-3. operating mode selection criteria v dd vpp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P7048 otp s3c7044/c7048/p7048 15- 4 table 15-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 ? v ih4 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6, 7, and reset 0.8 v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd ports 4 and 5 are open-drain v ih4 x in and x out v dd ? 0.1 input low voltage v il1 all input pins except those specified below for v il2 ?v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6, 7, and reset 0.2 v dd v il3 x in and x out 0.1 output high voltage v oh i oh = ? 1 ma ports except 1, 4, and 5 v dd ? 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma, ports 4, 5 only ? ? 2 v v dd = 2.0 to 5.5 v i ol = 1.6ma 0.4 v ol2 v dd = 4.5 v to 5.5 v i ol = 4 ma all output ports except ports 4,5 2 v dd = 2.0 to 5.5 v i ol = 1.6ma 0.4 input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v i = v dd x in and x out 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? ? 3 a i lil2 v i = 0 v x in and x out only ? 20
s3c7044/c7048/p7048 S3P7048 otp 15- 5 table 15-4. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output high leakage current i loh v o = v dd, all output pins ? ? 3 a output low leakage current i lol v o = 0 v, all output pins ? ? ? 3 a pull-up resistor r l1 v i = 0 v; v dd = 5 v ports 0, 1 (not p1.3), 2, 3, 6, 7 25 47 100 k w v dd = 3 v 50 95 200 r l2 v o = v dd ? 2v; v dd = 5v ports 4 and 5 only 15 47 70 v dd = 3 v 10 45 60 r l3 v dd = 5 v; v i = 0v; reset 100 220 400 v dd = 3 v 200 450 800 pull-down r l4 v dd = 5 v; v i = v dd ; port 8 25 47 100 k w resistor v dd = 3 v 50 95 200 supply i dd1 run mode; v dd = 5 v 10% 6.0 mhz ? 3.9 8.0 ma current (1) crystal oscillator; c1 = c2 = 22 pf 4.19 mhz 2.9 5.5 v dd = 3 v 10% 6.0 mhz 1.8 4.0 4.19 mhz 1.3 3.0 i dd2 run mode; v dd = 5 v 10% 6.0 mhz ? 1.3 2.5 ma crystal oscillator, c1 = c2 = 22 pf 4.19 mhz 1.2 1.8 v dd = 3 v 10% 6.0 mhz 0.5 1.5 4.19 mhz 0.44 1.0 i dd3 stop mode; v dd = 5 v 10% ? 0.2 3 a stop mode; v dd = 3 v 10% 0.1 2 notes 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. the supply current assumes a cpu clock of fx/4.
S3P7048 otp s3c7044/c7048/p7048 15- 6 table 15-5. a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 s v dd = 2.0 v to 5.5 v 0.95 tcl0, tcl1 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 2.0 v to 5.5v 1 tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 2.0 v to 5.5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? s internal sck source 670 v dd = 2.0 v to 5.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh, t kl v dd = 2.7 v to 5.5 v external sck source 335 ? ? s internal sck source t kcy / 2 ? 50 v dd = 2.0 v to 5.5 v external sck source 1600 internal sck source t kcy / 2 ? 150
s3c7044/c7048/p7048 S3P7048 otp 15- 7 table 15-5. a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5.5 v external sck source 600 internal sck source 500 output delay for sck to so t kso (1) v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 (2) ? ? m s int1, int2, int4, ks0 - ks7 10 reset input low width t rsl input 10 ? ? m s notes 1. r (1k w ) and c (100pf) are the load resistance and load capacitance of the so output line. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
S3P7048 otp s3c7044/c7048/p7048 15- 8 cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) supply voltage (v) 1.05 khz 1.5 mhz 15.625 khz cpu clock 4.2 mhz 6 mhz 400 khz main osc. freq. ( divided by 4 ) 1 2 3 4 5 6 7 figure 15-3. standard operating voltage range
s3c7044/c7048/p7048 S3P7048 otp 15- 9 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 15-4. otp programming algorithm
s3c7044/c7048/p7048 development tools 16- 1 16 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c8 , s3c9 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area upto the maximum rom size of the target device automatically. target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the s3c7c0404/c0408 microcontroller and otp programmer (gang) are now available .
development tools s3c7044/c7048/p704 8 16- 2 ram break/ display unit target application system probe adapter tb7014/018 tb7044/048 target board prom/mtp writer unit trace/timer unit sam4 base unit power supply unit pod rs-232c ibm-pc at or compatible bus smds2+ eva chip figure 16-1. smds product configuration (smds2+)
s3c7044/c7048/p7048 development tools 16- 3 tb7014/018, tb7044/048 target board the tb7014/018, tb7044/048 target board is used for the s3c7044/c7048/p7048 microcontroller. it is supported by the smds2+ development system. sm1250a tb7014/018 tb7044/048 144 qfp s3e7040 eva chip 1 25 external triggers ch1 ch2 off on to user_vcc rese 100-pin connector 1 36 4 0-pin connector 1 44 22 23 j10 74hc11 ra1 p4.0 p4.1 p4.2 p4.3 p5.0 p5.1 p5.2 p5.3 sw1 figure 16-2 . tb7014/018, tb7044/048 target board configuration
development tools s3c7044/c7048/p704 8 16- 4 table 16-1. power selection settings for tb7014/018, tb7044/048 'to user_vcc' settings operating mode comments to user_vcc on off target system smds2/smds2+ tb7014/018 tb7044/048 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_vcc on off target system smds2/smds2+ external v cc v ss v cc tb7014/018 tb7044/048 the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 16-2. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) for the smds2+ breakpoint and trace functions. idle led this led is on when the evaluation chip ( s3e7040 ) is in idle mode. stop led this led is on when the evaluation chip ( s3e7040 ) is in stop mode.
s3c7044/c7048/p7048 development tools 16- 5 j101 4 2 -pin sdip connector p1.3/int4 p1.2/int2 p1.1/int1 p1.0/int0 p2.3/buz p2.2/clo p2.1/tclo1 p2.0/tclo0 p0.3/btco p0.2/si p0.1/so p0.0/sck p8.3 p8.2 p8.1 p8.0 p3.3 p3.2 p3.1/tcl1/dsat p3.0/tcl0/sclk v ss p7.0/ks4 p7.1/ks5 p7.2/ks6 p7.3/ks7 p6.0/ks0 p6.1/ks1 p6.2/ks2 p6.3/ks3 reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 test v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 figure 16-3. 40 -pin connector for tb7014/018, tb7044/048 4 0-pin dip connector target board target system target cable for 42-sdip package part name: ap42sd-d order code: sm6509 1 40 20 21 j101 1 40 20 21 1 42 21 22 figure 16-4 . tb7014/018, tb7044/048 adapter cable for 4 2-s di p package ( s3c7044/c7048/p7048 )

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