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1/61 february 2003 m58lw032a 32 mbit (2mb x16, uniform block, burst) 3v supply flash memory features summary n wide x16 data bus for high bandwidth n supply voltage Cv dd = 2.7 to 3.6v core supply voltage for pro- gram, erase and read operations Cv ddq = 1.8v to v dd for i/o buffers n synchronous/asynchronous read C synchronous burst read C asynchronous random read C asynchronous address latch controlled read C page read n access time C synchronous burst read up to 56mhz C asynchronous page mode read 90/25ns and 110/25ns C random read 90ns, 110ns. n programming time C 16 word write buffer C18 m s word effective programming time n 64 uniform 32 kword memory blocks n block protection/ unprotection n program and erase su spend n 128 bit protection register n common flash interface n 100, 000 program/er ase cycles per block n electronic signature C manufacturer code: 0020h C device code m58lw032a: 8816h figure 1. packages tsop56 (n) 14 x 20 mm tbga64 (za) 10 x 13 mm tbga
m58lw032a 2/61 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tsop56 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. tbga64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address inputs (a1-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 valid data ready (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ready/busy (rb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 program/erase enable (v pp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 automatic low power.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 synchronous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 x-latency bits (m13-m11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 y-latency bit (m9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3/61 m58lw032a valid data ready bit (m8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 burst type bit (m7).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 valid clock edge bit (m6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 burst length bit (m2-m0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6. burst configuration x-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. burst configuration x-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 read query command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 write to buffer and program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 set burst configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 block protect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 blocks unprotect command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 7. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. read protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. protection register memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . 25 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 program status (bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 v pp status (bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 block protection status (bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reserved (bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
m58lw032a 4/61 figure 9. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11. asynchronous bus read ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. asynchronous bus read ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. asynchronous latch controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . 33 table 16. asynchronous latch controlled bus read ac characteristics . . . . . . . . . . . . . . . . . . . 33 figure 13. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14. asynchronous write ac waveform, write enable controlled . . . . . . . . . . . . . . . . . . . 35 figure 15. asynchronous latch controlled write ac waveform, write enable controlled. . . . . . 35 table 18. asynchronous write and latch controlled write ac characteristics, write enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. asynchronous write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . 37 figure 17. asynchronous latch controlled write ac waveforms, chip enable controlled . . . . . 37 table 19. asynchronous write and latch controlled write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18. synchronous burst read ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19. synchronous burst read - continuous - valid data ready output . . . . . . . . . . . . . . . 40 table 20. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20. reset, power-down and power-up ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 21. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 21. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline . . . . . . . 42 table 22. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data 42 figure 22. tbga64 10x13mm - 8x8 ball array 1mm pitch, package outline . . . . . . . . . . . . . . . . 43 table 23. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package mechanical data . . . . . . . . . 43 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 24. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 appendix b. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 27. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 28. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 29. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 30. block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 31. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 appendix c. flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 23. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 50
5/61 m58lw032a figure 24. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 51 figure 25. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 26. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 53 figure 27. block protect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 28. blocks unprotect flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 56 figure 30. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 57 figure 31. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 58 figure 32. command interface and program erase controller flowchart (c). . . . . . . . . . . . . . . . 59 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
m58lw032a 6/61 summary description the m58lw032 is a 32 mbit (2mb x16) non-vola- tile memory that can be read, erased and repro- grammed. these operations can be performed using a single low voltage (2.7v to 3.6v) core sup- ply. on power-up the memory defaults to read mode with an asynchronous bus where it can be read in the same way as a non-burst flash mem- ory. the memory is divided into 64 blocks of 512kbit that can be erased independently so it is possible to preserve valid data while old data is erased. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. the write buffer allows the microprocessor to pro- gram from 1 to 16 words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. a word program command is available to program a single word. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cy- cles. individual block protection against program or erase is provided for data security. all blocks are protected during power-up. the protection of the blocks is non-volatile; after power-up the protec- tion status of each block is restored to the state when power was last removed. software com- mands are provided to allow protection of some or all of the blocks and to cancel all block protection bits simultaneously. all program or erase opera- tions are blocked when the program erase enable input vpp is low. the reset/power-down pin is used to apply a hardware reset to the memory and to set the de- vice in power-down mode. in asynchronous mode chip enable, output en- able and write enable signals control the bus op- eration of the memory. an address latch input can be used to latch addresses. together they allow simple, yet powerful, connection to most micropro- cessors, often without additional logic. in synchronous mode all bus read operations are synchronous with the clock. chip enable and out- put enable select the bus read operation and the address is latched using the latch enable input. the signals are compatible with most micropro- cessor burst interfaces. the device includes a 128 bit protection register. the protection register is divided into two 64 bit segments, the first one is written by the manufac- turer (contact stmicroelectronics to define the code to be written here), while the second one is programmable by the user. the user programma- ble segment can be locked. the memory is available in tsop56 (14 x 20 mm) and tbga64 (10 x 13mm, 1mm pitch) packages.
7/61 m58lw032a figure 2. logic diagram table 1. signal names ai04320 21 a1-a21 w dq0-dq15 v dd m58lw032a e v ss 16 g rp l v ddq k r v pp v ssq rb a1-a21 address inputs dq0-dq15 data inputs/outputs e chip enable g output enable k clock l latch enable r valid data ready rb ready/busy rp reset/power-down v pp program/erase enable w write enable v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground nc not connected internally du do not use
m58lw032a 8/61 figure 3. tsop56 connections dq3 dq9 dq2 dq0 dq6 a16 a17 a18 dq14 dq12 dq10 rb v ddq dq4 dq7 ai04321 m58lw032a 14 1 15 28 29 42 43 56 dq8 v dd dq1 dq11 nc a20 a21 nc a19 w r e l k a6 a3 a8 a9 a10 a2 a7 v pp a1 a4 a5 a12 a13 a11 a15 a14 rp v ss dq13 dq15 v dd dq5 g v ss v ssq nc nc
9/61 m58lw032a figure 4. tbga64 connections (top view through package) ai04322 dq6 a1 v ssq v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ss dq13 d a16 a20 e a9 c a17 a21 a11 a15 k a8 b a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 a6 v pp a18 a10 a12 rp dq15 rb dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss du du du du du du du du du du l du r du
m58lw032a 10/61 figure 5. block addresses note: also see appendix a, table 25 for a full listing of the block addresses ai05500 512 kbit or 32 kwords 1fffffh 1f8000h 512 kbit or 32 kwords 00ffffh 008000h 512 kbit or 32 kwords 007fffh 000000h m58lw032a word (x16) bus width address lines a1-a21 512 kbit or 32 kwords 1f7fffh 1f0000h
11/61 m58lw032a signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a1-a21). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. chip enable and latch enable must be low when selecting the addresses. the address inputs are latched on the rising edge of chip enable, write enable or latch enable, whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the address is internally latched in an erase or program operation. data inputs/outputs (dq0-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , the data bus outputs data from the mem- ory array, the electronic signature, the block pro- tection status, the cfi information or the contents of the status register. the data bus is high imped- ance when the chip is deselected, output enable is high, v ih, or the reset/power-down signal is low, v il . when the program/erase controller is active the ready/busy status is given on dq7. chip enable (e ). the chip enable, e , input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level, i dd1 . output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation. when output enable, g , is at v ih the outputs are high impedance. output enable, g , can be used to inhibit the data output during a burst read operation. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able (also see latch enable, l ). reset/power-down (rp ). the reset/power- down pin can be used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/ power-down low, v il , for at least t plph . when reset/power-down is low, v il , the status regis- ter information is cleared and the power consump- tion is reduced to power-down level. the device is deselected and outputs are high impedance. if re- set/power-down goes low, v il ,during a block erase, a write to buffer and program or a block protect/unprotect the operation is aborted and the data may be corrupted. in this case the ready/ busy pin stays low, v il , for a maximum timing of t plph + t phrh, until the completion of the reset/ power-down pulse. after reset/power-down goes high, v ih , the memory will be ready for bus read and bus write operations after t phqv . note that ready/busy does not fall during a reset, see ready/busy out- put section. in an application, it is recommended to either as- sociate the reset/power-down pin, rp , with the reset signal of the microprocessor, or to ensure that the reset/power-down pin is kept low during power-on. otherwise, if a reset operation occurs while the memory is performing an erase or pro- gram operation, the memory may output the sta- tus register information instead of being initialized to the default asynchronous random read. latch enable (l ). the bus interface is config- ured to latch the address inputs on the rising edge of latch enable, l . in synchronous bus operations the address is latched on the active edge of the clock when latch enable is low, v il or on the ris- ing of latch enable, whichever occurs first. once latched, the addresses may change without affect- ing the address used by the memory. when latch enable is low, v il , the latch is transparent. clock (k). the clock, k, is used to synchronize the memory with the external bus during synchro- nous bus read operations. the clock can be con- figured to have an active rising or falling edge. bus signals are latched on the active edge of the clock during synchronous bus operations. in synchro- nous burst read mode the address is latched on the first active clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. valid data ready (r). the valid data ready output, r, is an open drain output that can be used to identify if the memory is ready to output data or not. the valid data ready output is only active during synchronous burst read operations when the burst length is set to continuous. the valid data ready output can be configured to be active on the clock edge of the invalid data read cycle or
m58lw032a 12/61 one cycle before. valid data ready low, v ol , in- dicates that the data is not, or will not be valid. val- id data ready in a high-impedance state indicates that valid data is or will be available. unless synchronous burst read has been select- ed, valid data ready is high-impedance. it may be tied to other components with the same valid data ready signal to create a unique system ready signal. the valid data ready, r, output has an internal pull-up resistor of approximately 1 m w powered from v ddq , designers should use an external pull- up resistor of the correct value to meet the external timing requirements for valid data ready rising. refer to figure 19. ready/busy (rb ). the ready/busy output, rb , is an open-drain output that can be used to identify if the program/erase controller is currently active. when ready/busy is high impedance, the memo- ry is ready for any read, program or erase opera- tion. ready/busy is low, v ol , during program and erase operations. when the device is busy it will not accept any additional program or erase com- mands except program/erase suspend. when the program/erase controller is idle, or suspended, ready busy can float high through a pull-up resis- tor. the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. ready/busy is not low during a reset unless the reset was applied when the program/erase con- troller was active; ready/busy can rise before re- set/power-down rises. program/erase enable (v pp ). the program/ erase enable input, v pp, is used to protect all blocks, preventing program and erase operations from affecting their data. program/erase enable must be kept high during all program/erase controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid any condition that would result in data corruption. v ss ground. ground, v ss, is the reference for the core power supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). see fig- ure 10, ac measurement load circuit.
13/61 m58lw032a bus operations there are 12 bus operations that control the mem- ory. each of these is described in this section, see tables 2 and 3, bus operations, for a summary. the bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. on power-up or after a hardware reset the mem- ory defaults to asynchronous latch enable con- trolled read and asynchronous bus write, no other bus operation can be performed until the burst control register has been configured. the electronic signature, cfi or status register will be read in asynchronous mode or single syn- chronous burst mode. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. asynchronous bus operations for asynchronous bus operations refer to table 3 together with the text below. asynchronous bus read. asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, status register, cfi and block protection status) in the command interface. a valid bus operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable, output enable and latch enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 11, asynchronous bus read ac waveforms, and table 15, asyn- chronous bus read ac characteristics, for details of when the output becomes valid. asynchronous latch controlled bus read. asynchronous latch controlled bus read opera- tions read from the memory cells or specific regis- ters in the command interface. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the ris- ing edge of address latch. once latched, the ad- dress inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure 12, asynchronous latch controlled bus read ac waveforms and table 16, asyn- chronous latch controlled bus read ac charac- teristics for details on when the output becomes valid. note that, since the latch enable input is transpar- ent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation. asynchronous page read. asynchronous page read operations are used to read from several ad- dresses within the same memory page. each memory page is 4 words and has the same a3- a21, only a1 and a2 may change. valid bus operations are the same as asynchro- nous bus read operations but with different tim- ings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings ap- ply again. see figure 13, asynchronous page read ac waveforms and table 17, asynchro- nous page read ac characteristics for details on when the outputs become valid. asynchronous bus write. asynchronous bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address in- puts and setting latch enable low, v il . the ad- dress inputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. the data in- puts/outputs are latched by the command inter- face on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole asyn- chronous bus write operation. see figures 14, and 16, asynchronous write ac waveforms, and tables 18 and 19, asynchronous write and latch controlled write ac characteristics, for details of the timing requirements. asynchronous latch controlled bus write. asynchronous latch controlled bus write opera- tions write to the command interface in order to send commands to the memory or to latch ad- dresses and input data to program. bus write op- erations are asynchronous, the clock, k, is dont care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing latch enable low, v il . the address inputs are latched by the com- mand interface on the rising edge of latch enable, chip enable or write enable, whichever occurs first. the data inputs/outputs are latched by the command interface on the rising edge of chip en- able or write enable, whichever occurs first. out-
m58lw032a 14/61 put enable must remain high, v ih , during the whole asynchronous bus write operation. see figures 15 and 17 asynchronous latch controlled write ac waveforms, and tables 18 and 19, asynchronous write and latch controlled write ac characteristics, for details of the timing re- quirements. output disable. the data inputs/outputs are in the high impedance state when the output enable is high. standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high imped- ance state regardless of output enable or write enable. the supply current is reduced to the standby supply current, i dd1 . during program or erase operations the memory will continue to use the program/erase supply current, i dd3 , for program or erase operations un- til the operation completes. automatic low power. if there is no change in the state of the bus for a short period of time during asynchronous bus read operations the memory enters auto low power mode where the internal supply current is reduced to the auto-standby supply current, i dd5 . the data inputs/outputs will still output data if a bus read operation is in progress. automatic low power is only available in asyn- chronous read modes. power-down. the memory is in power-down mode when reset/power-down, rp , is low. the power consumption is reduced to the power-down level, i dd2 , and the outputs are high impedance, independent of chip enable, output enable or write enable. table 2. asynchronous bus operations note: 1. x = dont care v il or v ih . high = v ih or v hh . bus operation step e g w rp l a1-a21 dq0-dq15 asynchronous bus read v il v il v ih high v il address data output asynchronous latch controlled bus read address latch v il v il v ih high v il address high z read v il v il v ih high v ih x data output asynchronous page read v il v il v ih high v il address data output asynchronous bus write v il v ih v il high v il address data input asynchronous latch controlled bus write address latch v il v ih v il high v il address data input output disable v il v ih v ih high x x high z standby v ih x x high x x high z power-down x x x v il x x high z
15/61 m58lw032a synchronous bus operations for synchronous bus operations refer to table 3 together with the text below. synchronous burst read. synchronous burst read operations are used to read from the memo- ry at specific times synchronized to an external ref- erence clock. the burst type, length and latency can be configured. the different configurations for synchronous burst read operations are de- scribed in the burst configuration register sec- tion. a valid synchronous burst read operation begins when the address is set on the address inputs, write enable is high, v ih , and chip enable and latch enable are low, v il , during the active edge of the clock. the address is latched on the first ac- tive clock edge when latch enable is low, or on the rising edge of latch enable, whichever occurs first. the data becomes available for output after the x-latency specified in the burst control regis- ter has expired. the output buffers are activated by setting output enable low, v il . see figures 6 and 7 for examples of synchronous burst read operations. in continuous burst mode one burst read opera- tion can access the entire memory sequentially. if the starting address is not associated with a page (4 word) boundary the valid data ready, r, out- put goes low, v il , to indicate that the data will not be ready in time and additional wait-states are re- quired. the valid data ready output timing (bit m8) can be changed in the burst configuration register. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figures 18, 19 and table 20. table 3. synchronous burst read bus operations note: 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. 3. t = transition, see m6 in the burst configuration register for details on the active edge of k. bus operation step e g rp k (3) l a1-a21 dq0-dq15 synchronous burst read address latch v il x v ih t v il address input read v il v il v ih t x data output read abort v ih x v ih x x high z
m58lw032a 16/61 burst configuration register the burst configuration register is used to config- ure the type of bus access that the memory will perform. the burst configuration register bits are described in table 4. they specify the selection of the burst length, burst type, burst x and y laten- cies and the read operation. see figures 6 and 7 for examples of synchronous burst read configu- rations. the burst configuration register is set through the command interface and will retain its informa- tion until it is re-configured, the device is reset, or the device goes into reset/power-down mode. the burst configuration register is read using the read electronic signature command at address 05h. read select bit (m15). the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to 1, bus read operations are asynchronous; when the read select but is set to 0, bus read operations are synchronous. on reset or power-up the read select bit is set to 1 for asynchronous access. x-latency bits (m13-m11). the x-latency bits are used during synchronous bus read opera- tions to set the number of clock cycles between the address being latched and the first data be- coming available. for correct operation the x-la- tency bits can only assume the values in table 4, burst configuration register. internal clock divider bit (m10). the internal clock divider bit is used to divide the internal clock by two. when m10 is set to 1 the internal clock is divided by two, which effectively means that the x and y-latency values are multiplied by two, that is the number of clock cycles between the address being latched and the first data becoming avail- able will be twice the value set in m13-m11, and the number of clock cycles between consecutive reads will be twice the value set in m9. for exam- ple 8-1-1-1 will become 16-2-2-2. when m10 is set to 0 the internal clock runs normally and the x and y-latency values are those set in m13-m11 and m9. y-latency bit (m9). the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x-latency value and the setting in m9. when the y-latency is 1 the data changes each clock cycle; when the y-latency is 2 the data changes every second clock cycle. see table 4, burst configuration register for valid combina- tions of the y-latency, the x-latency and the clock frequency. valid data ready bit (m8). the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is 0 the valid data ready output pin is driven low for the active clock edge when invalid data is output on the bus. when the valid data ready bit is 1 the valid data ready output pin is driven low one clock cycle prior to invalid data being output on the bus. burst type bit (m7). the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is 0 the memory outputs from interleaved ad- dresses; when the burst type bit is 1 the memory outputs from sequential addresses. see tables 5, burst type definition, for the sequence of ad- dresses output from a given starting address in each mode. valid clock edge bit (m6). the valid clock edge bit, m6, is used to configure the active edge of the clock, k, during synchronous burst read opera- tions. when the valid clock edge bit is 0 the fall- ing edge of the clock is the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. burst length bit (m2-m0). the burst length bits set the maximum number of words that can be output during a synchronous burst read opera- tion. table 4, burst configuration register gives the valid combinations of the burst length bits that the memory accepts; tables 5, burst type definition, give the sequence of addresses output from a giv- en starting address for each length. m5 m4 and m3 are reserved for future use.
17/61 m58lw032a table 4. burst configuration register note: 1. 4 - 2 - 2 - 2 (represents x-y-y-y) is not allowed. 2. x latencies can be calculated as: (t avqv C t llkh + t qvkh ) + t system margin < (x -1) t k. (x is an integer number from 4 to 8 and t k is the clock period). 3. y latencies can be calculated as: t khqv + t system margin + t qvkh < y t k. 4. t system margin is the time margin required for the calculation. address bit mnemonic bit name reset value value description 16 m15 read select 1 0 synchronous burst read 1 asynchronous bus read (default at power-up) 15 m14 reserved 14 to 12 m13-m11 x-latency (2) xxx 001 reserved 010 x-latency = 4, 4-1-1-1 (use only with y-latency = 1) (1) 011 x-latency = 5, 5-1-1-1, 5-2-2-2 100 x-latency = 6, 6-1-1-1, 6-2-2-2 101 x-latency = 7, 7-1-1-1, 7-2-2-2 110 x-latency = 8, 8-1-1-1, 8-2-2-2 11 m10 internal clock divider x 0 x and y-latencies remains as set in m13-m11 and m9 1 divides internal clock, x and y-latencies multiplied by 2 10 m9 y-latency (3) x 0 y-latency = 1 1 y-latency = 2 9m8 valid data ready x 0 r valid low during valid clock edge 1 r valid low one cycle before valid clock edge 8 m7 burst type x 0 interleaved 1 sequential 7m6 valid clock edge x 0 falling clock edge 1 rising clock edge 6 to 4 m5-m3 reserved 3 to 1 m2-m0 burst length xxx 001 4 words 010 8 words 111 continuous
m58lw032a 18/61 table 5. burst type definition figure 6. burst configuration x-1-1-1 starting address x4 sequential x4 interleaved x8 sequential x8 interleaved continuous 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10.. 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7-8-9-10-11.. 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8-9-10-11-12.. 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9-10-11-12-13.. 4 C C 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-2-13-14.. 5 C C 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 5-6-7-8-9-10-11-12-13-14.. 6 C C 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 6-7-8-9-10-11-12-13-14-15.. 7 C C 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13-14-15-16.. 8 C C C C 8-9-10-11-12-13-14-15-16-17.. ai05512 k dq l add valid dq dq dq dq 4-1-1-1 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 0123456789 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid
19/61 m58lw032a figure 7. burst configuration x-2-2-2 ai05513 k l add dq valid dq dq dq 5-2-2-2 6-2-2-2 7-2-2-2 8-2-2-2 0123456789 valid valid valid valid valid valid valid valid nv nv nv nv nv nv nv nv nv nv nv=not valid
m58lw032a 20/61 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands are summarized in table 6, commands. refer to table 6 in conjunction with the text descriptions below. after power-up or a reset operation the memory enters read mode. synchronous read operations and latch con- trolled bus read operations can only be used to read the memory array. the electronic signature, cfi or status register will be read in asynchro- nous mode or single synchronous burst mode. once the memory returns to read memory array mode the bus will resume the setting in the burst configuration register automatically. read memory array command. the read mem- ory array command returns the memory to read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. once the command is is- sued the memory remains in read mode until an- other command is issued. from read mode bus read commands will access the memory array. while the program/erase controller is executing a program, erase, block protect, blocks unprotect or protection register program operation the memory will not accept the read memory array command until the operation completes. read electronic signature command. the read electronic signature command is used to read the manufacturer code, the device code, the block protection status, the burst configuration regis- ter and the protection register. one bus write cy- cle is required to issue the read electronic signature command. once the command is is- sued subsequent bus read operations read the manufacturer code, the device code, the block protection status, the burst configuration regis- ter or the protection register until another com- mand is issued. refer to table 7, read electronic signature, table 8, read protection register and figure 8, protection register memory map for in- formation on the addresses. read query command. the read query com- mand is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations read from the common flash in- terface memory area. see appendix b, tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the common flash interface (cfi) memory area. read status register command. the read sta- tus register command is used to read the status register. one bus write cycle is required to issue the read status register command. once the command is issued subsequent bus read opera- tions read the status register until another com- mand is issued. the status register information is present on the output data bus (dq1-dq7) when both chip en- able and output enable are low, v il . see the section on the status register and table 10 for details on the definitions of the status reg- ister bits clear status register command. the clear sta- tus register command can be used to reset bits 1, 3, 4 and 5 in the status register to 0. one bus write is required to issue the clear status register command. the bits in the status register are sticky and do not automatically return to 0 when a new write to buffer and program, erase, block protect, blocks unprotect or protection register program com- mand is issued. if any error occurs then it is essen- tial to clear any error bits in the status register by issuing the clear status register command before attempting a new program, erase or resume command. block erase command. the block erase com- mand can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is protected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read opera- tions read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/erase suspend command. all other commands will be ignored. typical erase times are given in table 9. see appendix c, figure 25, block erase flow- chart and pseudo code, for a suggested flowchart on using the block erase command. word program command. the word program command is used to program a single word in the memory array. two bus write operations are re- quired to issue the command; the first write cycle sets up the word program command, the second write cycle latches the address and data to be pro- grammed in the internal state machine and starts the program/erase controller.
21/61 m58lw032a if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. write to buffer and program command. the write to buffer and program command is used to program the memory array. up to 16 words can be loaded into the write buffer and programmed into the memory. each write buffer has the same a5-a21 addresses. four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. is- sue the set up command with the selected memory block address where the program op- eration should occur (any address in the block where the values will be programmed can be used). any bus read operations will start to out- put the status register after the 1st cycle. 2. use one bus write operation to write the same block address along with the value n on the data inputs/output, where n+1 is the number of words to be programmed. 3. use n+1 bus write operations to load the ad- dress and data for each word into the write buffer. the addresses must have the same a5- a21. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. invalid address combinations or failing to follow the correct sequence of bus write cycles will set an error in the status register and abort the oper- ation without affecting the data in the memory ar- ray. the status register should be cleared before re-issuing the command. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. see appendix c, figure 23, write to buffer and program flowchart and pseudo code, for a sug- gested flowchart on using the write to buffer and program command. program/erase suspend command. the pro- gram/erase suspend comm and is used to pause a write to buffer and program or erase operation. the command will only be accepted during a pro- gram or an erase operation. it can be issued at any time during an erase operation but will only be accepted during a write to buffer and program command if the program/erase controller is run- ning. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/ erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (bit 7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 9. during program/erase suspend the read memo- ry array, read status register, read electronic signature, read query and program/erase re- sume commands will be accepted by the com- mand interface. additionally, if the suspended operation was erase then the word program, write to buffer and program, and the program suspend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed cor- rectly. see appendix c, figure 24, program suspend & resume flowchart and pseudo code, and figure 26, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command. the pro- gram/erase resume command can be used to re- start the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. once the com- mand is issued subsequent bus read operations read the status register. set burst configuration register command. the set burst configuration register command is used to write a new value to the burst configura- tion control register which defines the burst length, type, x and y latencies, synchronous/ asynchronous read mode and the valid clock edge configuration.
m58lw032a 22/61 two bus write cycles are required to issue the set burst configuration register command. once the command is issued the memory returns to read mode as if a read memory array command had been issued. the value for the burst configuration register is presented on a1-a16. m0 is on a1, m1 on a2, etc.; the other address bits are ignored. block protect command. the block protect command is used to protect a block and prevent program or erase operations from changing the data in it. two bus write cycles are required to is- sue the block protect command; the second bus write cycle latches the block address in the inter- nal state machine and starts the program/erase controller. once the command is issued subse- quent bus read operations read the status reg- ister. see the section on the status register for details on the definitions of the status register bits. typical block protection times are given in table 9. the block protection bits are non-volatile, once set they remain set through reset and power- down/power-up. they are cleared by a blocks un- protect command. see appendix c, figure 27, block protect flow- chart and pseudo code, for a suggested flowchart on using the block protect command. blocks unprotect command. the blocks un- protect command is used to unprotect all of the blocks. two bus write cycles are required to issue the blocks unprotect command; the second bus write cycle starts the program/erase controller. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. typical block protection times are given in table 9. see appendix c, figure 28, blocks unprotect flowchart and pseudo code, for a suggested flow- chart on using the blocks unprotect command. protection register program command. the protection register program command is used to program the 64 bit user segment of the protection register. the segment is programmed 16 bits at a time. the memory must be reset by issuing the read memory array command before the protec- tion register program command can be issued. two write cycles are required to issue the protec- tion register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the user-programmable segment can be locked by programming bit 1 of the protection register lock location to 0 (see table 8). bit 0 of the pro- tection register lock location locks the factory programmed segment and is programmed to 0 in the factory. the locking of the protection register is not reversible, once the lock bits are pro- grammed no further changes can be made to the values stored in the protection register, see fig- ure 8, protection register memory map. attempt- ing to program a previously protected protection register will result in a status register error. the protection register program cannot be sus- pended. see appendix c, figure 29, protection register program flowchart and pseudo code, for the flowchart for using the protection register program command.
23/61 m58lw032a table 6. commands note: 1. x dont care; ra read address, rd read data, ida identifier address, idd identifier data, srd status register data, pa p rogram address; pd program data, qa query address, qd query data, ba any address in the block, bcr burst configuration register value. 2. base address, refer to figure 8 and table 8 for more information. 3. for identifier addresses and data refer to table 7, read electronic signature. 4. for query address and data refer to appendix b, cfi. table 7. read electronic signature note: 1. sba is the start base address of each block, bcr is burst configuration register data, prd is protection register data. 2. base address, refer to figure 8 and table 8 for more information. command cycles bus operations 1st cycle 2nd cycle subsequent final op. addr. data op. addr. data op. addr. data op. addr. data read memory array 3 2 write x ffh read ra rd read electronic signature 3 2 write x 90h read ida (3) idd (3) read status register 2 write x 70h read x srd read query 3 2 write x 98h read qa (4) qd (4) clear status register 1 write x 50h block erase 2 write x 20h write ba d0 word program 2 write x 40h 10h write pa pd write to buffer and program 4 + n write ba e8h write ba n write pa pd write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set burst configuration register 2 write x 60h write bcr 03h block protect 2 write x 60h write ba 01h blocks unprotect 2 write x 60h write x d0h protection register program 2 write x c0h write pra prd code address (a21-a1) data (dq15-dq0) manufacturer code 000000h 0020h device code 000001h 8816h block protection status sba+02h 0000h (block unprotected) 0001h (block protected) burst configuration register 000005h bcr protection register 000080h (2) prd
m58lw032a 24/61 table 8. read protection register figure 8. protection register memory map word use a8a7a6a5a4a3a2a1 lock factory, user 10000000 0 factory (unique id) 10000001 1 factory (unique id) 10000010 2 factory (unique id) 10000011 3 factory (unique id) 10000100 4 user 10000101 5 user 10000110 6 user 10000111 7 user 10001000 ai05501 user programmable unique device number protection register lock 1 0 88h 85h 84h 81h 80h word address
25/61 m58lw032a table 9. program, erase times and program erase endurance cycles note: t a = 0 to 70c; v dd = 2.7v to 3.6v; v ddq =1.8v parameters m58lw032a unit min typ max block (521kb) erase 1.1 s program write buffer 290 s program suspend latency time 20 s erase suspend latency time 25 s block protect time 18 s blocks unprotect time 0.75 s program/erase cycles (per block) 100,000 cycles
m58lw032a 26/61 status register the status register provides information on the current or previous program, erase, block protect or blocks unprotect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, blocks unprotect and program/erase re- sume commands. the status register can be read from any address. the status register can only be read using asyn- chronous bus read operations. once the memory returns to read memory array mode the bus will resume the setting in the burst configuration reg- ister automatically. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable pin or by dis-activating (chip enable, v ih ) and then reactivating (chip en- able and output enable, v il ) the device. status register bits 5, 4, 3 and 1 are associated with various error conditions and can only be reset with the clear status register command. the sta- tus register bits are summarized in table 10, sta- tus register bits. refer to table 10 in conjunction with the following text descriptions. program/erase controller status (bit 7). the pro- gram/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is low, v ol , the program/erase controller is active and all other status register bits are high imped- ance; when the bit is high, v oh , the program/ erase controller is inactive. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, block protect and blocks unprotect operations the program/erase control- ler status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase con- troller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status and block protection status bits should be tested for errors. erase suspend status (bit 6). the erase sus- pend status bit indicates that an erase operation has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is high (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is low, v ol , the program/erase controller is active or has com- pleted its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status (bit 5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). when the erase status bit is low, v ol , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. when the erase status bit is high, v oh , the erase operation has failed. de- pending on the cause of the failure other status register bits may also be set to high, v oh . n if only the erase status bit (bit 5) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. n if the failure is due to an erase or blocks unprotect with v pp low, v ol , then v pp status bit (bit 3) is also set high, v oh . n if the failure is due to an erase on a protected block then block protection status bit (bit 1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then program status bit (bit 4) is also set high, v oh . once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status (bit 4). the program status bit is used to identify a program or block protect fail- ure. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive). when the program status bit is low, v ol , the memory has successfully verified that the write buffer has programmed correctly or the block is protected. when the program status bit is high, v oh , the program or block protect operation has
27/61 m58lw032a failed. depending on the cause of the failure other status register bits may also be set to high, v oh . n if only the program status bit (bit 4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the write buffer has programmed correctly or that the block is protected. n if the failure is due to a program or block protect with v pp low, v ol , then v pp status bit (bit 3) is also set high, v oh . n if the failure is due to a program on a protected block then block protection status bit (bit 1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then erase status bit (bit 5) is also set high, v oh . once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pp status (bit 3). the v pp status bit can be used to identify if a word program, erase, block protection or blocks unprotection operation has been attempted when v pp is low, v il . the v pp status bit cannot be used during a write to buffer and program operation. when the v pp status bit is low, v ol , no word pro- gram, erase, block protection or blocks unprotec- tion operations have been attempted with v pp low, v il , since the last clear status register com- mand, or hardware reset. when the v pp status bit is high, v oh , a word program, erase, block pro- tection or blocks unprotection operation has been attempted with v pp low, v il . once set high, the v pp status bit can only be reset by a clear status register command or a hard- ware reset. if set high it should be reset before a new program, erase, block protection or blocks unprotection command is issued, otherwise the new command will appear to fail. program suspend status (bit 2). the program suspend status bit indicates that a program oper- ation has been suspended and is waiting to be re- sumed. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is low, v ol , the program/erase controller is active or has completed its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status (bit 1). the block pro- tection status bit can be used to identify if a pro- gram or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, v ol , no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is high, v oh , a program (program status bit 4 set high) or erase (erase status bit 5 set high) operation has been attempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. reserved (bit 0). bit 0 of the status register is reserved. its value should be masked.
m58lw032a 28/61 table 10. status register bits operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 rb result (hex) program/erase controller active 0 v ol v ol v ol v ol v ol v ol v ol n/a write buffer not ready 0 v ol v ol v ol v ol v ol v ol v ol n/a write buffer ready 1000000 hi-z 80h write buffer ready in erase suspend 1100000 hi-z c0h program suspended 1000010 hi-z 84h program suspended in erase suspend 1100010 hi-z c4h program/block protect completed successfully 1000000 hi-z 80h program completed successfully in erase suspend 1100000 hi-z c0h program/block protect failure due to incorrect command sequence 1011000 hi-z b0h program failure due to incorrect command sequence in erase suspend 1111000 hi-z f0h word program/block protect failure due to v pp error 1001100 hi-z 98h word program failure due to v pp error in erase suspend 1101100 hi-z d8h program failure due to block protection 1001001 hi-z 92h program failure due to block protection in erase suspend 1101001 hi-z d2h program/block protect failure due to cell failure 1001000 hi-z 90h program failure due to cell failure in erase suspend 1101000 hi-z d0h erase suspended 1100000 hi-z c0h erase/blocks unprotect completed successfully 1000000 hi-z 80h erase/blocks unprotect failure due to incorrect command sequence 1011000 hi-z b0h erase/blocks unprotect failure due to v pp error 1010100 hi-z a8h erase failure due to block protection 1010001 hi-z a2h erase/blocks unprotect failure due to failed cells in block 1010000 hi-z a0h
29/61 m58lw032a maximum rating stressing the device above the ratings listed in ta- ble 11, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 11. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.6 v ddq +0.6 v v dd , v ddq supply voltage C0.6 5.0 v
m58lw032a 30/61 dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 12, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 12. operating and ac measurement conditions figure 9. ac measurement input output waveform figure 10. ac measurement load circuit table 13. capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter m58lw032a units 90 110 min max min max supply voltage (v dd ) 2.7 3.6 2.7 3.6 v input/output supply voltage (v ddq ) 1.8 v dd 1.8 v dd v ambient temperature (t a ) grade 1 0 70 0 70 c grade 6 C40 85 C40 85 c load capacitance (c l ) 30 30 pf clock rise and fall times 3 3 ns input rise and fall times 4 4 ns input pulses voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages 0.5 v ddq 0.5 v ddq v ai00610 v ddq 0v 0.5 v ddq ai03459 1.3v dq s c l c l includes jig capacitance 3.3k w 1n914 device under test 0.1f v dd v ddq 0.1f symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
31/61 m58lw032a table 14. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , g = v ih , f add = 6mhz 20 ma i ddb supply current (burst read) e = v il , g = v ih , f clock = 50mhz 30 ma i dd1 supply current (standby) e = v ih , rp = v ih 40 m a i dd5 supply current (auto low-power) e = v il , rp = v ih 40 m a i dd2 supply current (reset/power-down) rp = v il 40 a i dd3 supply current (program or erase, block protect, blocks unprotect) program or erase operation in progress 30 ma i dd4 supply current (erase/program suspend) e = v ih 40 a v il input low voltage C0.5 0.3 v ddq v v ih input high voltage 0.7 v ddq v ddq + 0.5 v v ol output low voltage i ol = 100a 0.2 v v oh output high voltage i oh = C100a v ddq C0.2 v v lko v dd supply voltage (erase and program lockout) 2v
m58lw032a 32/61 figure 11. asynchronous bus read ac waveforms note: asynchronous read m15 = 1 table 15. asynchronous bus read ac characteristics. symbol parameter test condition m58lw032a unit 90 110 t avav address valid to address valid e = v il , g = v il min 90 110 ns t av qv address valid to output valid e = v il , g = v il max 90 110 ns t elqx chip enable low to output transition g = v il min 0 0 ns t elqv chip enable low to output valid g = v il max 90 110 ns t glqx output enable low to output transition e = v il min 0 0 ns t glqv output enable low to output valid e = v il max 25 25 ns t ehqx chip enable high to output transition g = v il min 0 0 ns t ghqx output enable high to output transition e = v il min 0 0 ns t axqx address transition to output transition e = v il , g = v il min 0 0 ns t ehqz chip enable high to output hi-z g = v il max 25 25 ns t ghqz output enable high to output hi-z e = v il max 20 20 ns ai05502 e g a1-a21 dq0-dq15 valid taxqx telqx tavqv tglqv tehqz tghqx output tavav tehqx tghqz tglqx telqv l
33/61 m58lw032a figure 12. asynchronous latch controlled bus read ac waveforms note: asynchronous read m15 = 1 table 16. asynchronous latch controlled bus read ac characteristics note: for other timings see table 15, asynchronous bus read characteristics. symbol parameter test condition m58lw032a unit 90 110 t avl l address valid to latch enable low e = v il min 0 0 ns t avlh address valid to latch enable high e = v il min 10 10 ns t lhll latch enable high to latch enable low min 10 10 ns t lllh latch enable low to latch enable high e = v il min 10 10 ns t elll chip enable low to latch enable low min 0 0 ns t ellh chip enable low to latch enable high min 10 10 ns t llqx latch enable low to output transition e = v il , g = v il min 0 0 ns t llqv latch enable low to output valid e = v il , g = v il min 90 110 ns t lhax latch enable high to address transition e = v il min 6 6 ns t glqx output enable low to output transition e = v il min 0 0 ns t glqv output enable low to output valid e = v il max 25 25 ns t ehlx chip enable high to latch enable transition min 0 0 ns ai05503 l e g a1-a21 dq0-dq15 valid tehlx tlhll tlhax tavll telll tlllh tehqx tghqz tllqv tglqv output tavlh tellh tghqx tllqx tehqz tglqx
m58lw032a 34/61 figure 13. asynchronous page read ac waveforms note: asynchronous read m15 = 1 table 17. asynchronous page read ac characteristics note: for other timings see table 15, asynchronous bus read characteristics. symbol parameter test condition m58lw032a unit 90 110 t axqx1 address transition to output transition e = v il , g = v il min 6 6 ns t avqv1 address valid to output valid e = v il , g = v il max 25 25 ns ai05504 e g a3-a21 dq0-dq15 valid taxqx telqx tavqv tglqv tehqx tghqz output output a1-a2 taxqx1 valid valid tghqx tehqz telqv tglqx tavqv1 l
35/61 m58lw032a figure 14. asynchronous write ac waveform, write enable controlled figure 15. asynchronous latch controlled write ac waveform, write enable controlled ai05505 dq0-dq15 rb w a1-a21 e g input valid twheh tavwh twlwh telwl v pp twhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl l ai05506 dq0-dq15 rb w a1-a21 e g input valid twheh tavlh twlwh telll v pp tlhax twhwl twhdx tdvwh tvphwh twhgl tghwl twhbl tlllh telwl l tlhgl tlhwh twllh
m58lw032a 36/61 table 18. asynchronous write and latch controlled write ac characteristics, write enable controlled. symbol parameter test condition m58lw032a unit 90 110 t avlh address valid to latch enable high min 10 10 ns t av wh address valid to write enable high e = v il min 50 50 ns t dvwh data input valid to write enable high e = v il min 50 50 ns t elwl chip enable low to write enable low min 0 0 ns t elll chip enable low to latch enable low min 0 0 ns t lhax latch enable high to address transition min 6 6 ns t lhgl latch enable high to output enable low min 95 95 ns t lhwh latch enable high to write enable high min 0 0 ns t lllh latch enable low to latch enable high min 10 10 ns t llwh latch enable low to write enable high min 50 50 ns t vphwh program/erase enable high to write enable high min 0 0 ns t whax write enable high to address transition e = v il min 10 10 ns t whbl write enable high to ready/busy low max 500 500 ns t whdx write enable high to input transition e = v il min 10 10 ns t wheh write enable high to chip enable high min 0 0 ns t ghwl output enable high to write enable low min 20 20 ns t whgl write enable high to output enable low min 35 35 ns t whwl write enable high to write enable low min 30 30 ns t wlwh write enable low to write enable high e = v il min 70 70 ns t wllh write enable low to latch enable high e = v il min 10 10 ns
37/61 m58lw032a figure 16. asynchronous write ac waveforms, chip enable controlled figure 17. asynchronous latch controlled write ac waveforms, chip enable controlled ai05507 dq0-dq15 rb e a1-a21 w g input valid tehwh taveh teleh twlel v pp tehax tehel tehdx tdveh tvpheh tehgl tghel tehbl l ai05508 dq0-dq15 rb e a1-a21 w g input valid tehwh tavlh teleh twlll v pp tlhax tehel tehdx tdveh tvpheh tehgl tghel tehbl tlllh twlel l tehax taveh tlhgl tlheh tellh
m58lw032a 38/61 table 19. asynchronous write and latch controlled write ac characteristics, chip enable controlled symbol parameter test condition m58lw032a unit 90 110 t avlh address valid to latch enable high min 10 10 ns t ave h address valid to chip enable high w = v il min 50 50 ns t dveh data input valid to chip enable high w = v il min 50 50 ns t wlel write enable low to chip enable low min 0 0 ns t wlll write enable low to latch enable low min 0 0 ns t lhax latch enable high to address transition min 6 6 ns t lhgl latch enable high to output enable low min 35 35 ns t lheh latch enable high to chip enable high min 0 0 ns t lllh latch enable low to latch enable high min 10 10 ns t lleh latch enable low to chip enable high min 50 50 ns t vpheh program/erase enable high to chip enable high min 0 0 ns t ehax chip enable high to address transition w = v il min 10 10 ns t ehbl chip enable high to ready/busy low max 500 500 ns t ehdx chip enable high to input transition w = v il min 10 10 ns t ehwh chip enable high to write enable high min 0 0 ns t ghel output enable high to chip enable low min 20 20 ns t ehgl chip enable high to output enable low min 35 35 ns t ehel chip enable high to chip enable low min 30 30 ns t eleh chip enable low to chip enable high w = v il min 70 70 ns t ellh chip enable low to latch enable high w = v il min 10 10 ns
39/61 m58lw032a figure 18. synchronous burst read ac waveform note: valid clock edge = rising (m6 = 1) ai05509 dq0-dq15 a1-a21 l e g k valid tkhax tqvkh x+2y x+y x x-1 2 1 0 tkhll tllkh telkh tavkh tehqz tghqz tglkh q1 q2 q3 tkhqx x+2y+1 x+2y+2 tkhqv tlllh tlhax tavlh tellh tghqx tehqx
m58lw032a 40/61 figure 19. synchronous burst read - continuous - valid data ready output note: 1. valid data ready = valid low during valid clock edge (m8 = 0) 2. v= valid output, nv= not valid output. 3. r is an open drain output with an internal pull up resistor of 1m w. depending on the valid data ready pin capacitance load an external pull up resistor must be chosen according to the system clock period. table 20. synchronous burst read ac characteristics note: for other timings see table 15, asynchronous bus read characteristics. symbol parameter test condition m58lw032a unit 90 110 t avkh address valid to active clock edge e = v il min 7 7 ns t av lh address valid to latch enable high e = v il min 10 10 ns t elkh chip enable low to active clock edge e = v il min 10 10 ns t ellh chip enable low to latch enable high e = v il min 10 10 ns t glkh output enable low to valid clock edge e = v il , l = v ih min 20 20 ns t khax valid clock edge to address transition e = v il min 5 5 ns t khll valid clock edge to latch enable low e = v il min 0 0 ns t khlh valid clock edge to latch enable high e = v il min 0 0 ns t khqx valid clock edge to output transition e = v il , g = v il , l = v ih min 3 3 ns t llkh latch enable low to valid clock edge e = v il min 6 6 ns t lllh latch enable low to latch enable high e = v il min 6 6 ns t khqv valid clock edge to output valid e = v il , g = v il , l = v ih max 10 10 ns t qvkh output valid to active clock edge e = v il , g = v il , l = v ih min 5 5 ns t rlkh valid data ready low to valid clock edge e = v il , g = v il , l = v ih min 5 5 ns ai05510 k output (2) v v nv nv v v trlkh r v (3)
41/61 m58lw032a figure 20. reset, power-down and power-up ac waveform table 21. reset, power-down and power-up ac characteristics symbol parameter m58lw032a unit 90 110 t phqv reset/power-down high to data valid max 150 150 ns t plph reset/power-down low to reset/power-down high min 100 100 ns t plrh reset/power-down low to ready high max 30 30 s t vdhph supply voltages high to reset/power-down high min 0 0 s ai05521 rb w rp e, g vdd, vddq tvdhph tplph tplrh power-up and reset reset during program or erase dq0-dq15 tphqv
m58lw032a 42/61 package mechanical figure 21. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package outline note: drawing is not to scale. table 22. tsop56 - 56 lead plastic thin small outline, 14 x 20 mm, package mechanical data symbol mm inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.17 0.27 0.0067 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 13.90 14.10 0.5472 0.5551 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n56 56 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
43/61 m58lw032a figure 22. tbga64 10x13mm - 8x8 ball array 1mm pitch, package outline note: drawing is not to scale. table 23. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.850 0.0335 b 0.400 0.500 0.0157 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 C C 0.2756 C C ddd 0.100 0.0039 e 1.000 C C 0.0394 C C e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 C C 0.2756 C C fd 1.500 C C 0.0591 C C fe 3.000 C C 0.1181 C C sd 0.500 C C 0.0197 C C se 0.500 C C 0.0197 C C e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
m58lw032a 44/61 part numbering table 24. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m58lw032a 90 n 1 t device type m58 architecture l = page mode, burst mode operating voltage w = v dd = 2.7v to 3.6v; v ddq = 1.8v to v dd device function 032a = 32 mbit (x16), uniform block speed 90 = 90ns 110 = 110ns package n = tsop56: 14 x 20 mm za = tbga64: 10 x 13 mm, 1mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option t = tape & reel packing
45/61 m58lw032a appendix a. block address table table 25. block addresses block number address range (x16 bus width) 64 1f8000h-1fffffh 63 1f0000h-1f7fffh 62 1e8000h-1effffh 61 1e0000h-1e7fffh 60 1d8000h-1dffffh 59 1d0000h-1d7fffh 58 1c8000h-1cffffh 57 1c0000h-1c7fffh 56 1b8000h-1bffffh 55 1b0000h-1b7fffh 54 1a8000h-1affffh 53 1a0000h-1a7fffh 52 198000h-19ffffh 51 190000h-197fffh 50 188000h-18ffffh 49 180000h-187fffh 48 178000h-17ffffh 47 170000h-177fffh 46 168000h-16ffffh 45 160000h-167fffh 44 158000h-15ffffh 43 150000h-157fffh 42 148000h-14ffffh 41 140000h-147fffh 40 138000h-13ffffh 39 130000h-137fffh 38 128000h-12ffffh 37 120000h-127fffh 36 118000h-11ffffh 35 110000h-117fffh 34 108000h-10ffffh 33 100000h-107fffh 32 0f8000h-0fffffh 31 0f0000h-0f7fffh 30 0e8000h-0effffh 29 0e0000h-0e7fffh 28 0d8000h-0dffffh 27 0d0000h-0d7fffh 26 0c8000h-0cffffh 25 0c0000h-0c7fffh 24 0b8000h-0bffffh 23 0b0000h-0b7fffh 22 0a8000h-0affffh 21 0a0000h-0a7fffh 20 098000h-09ffffh 19 090000h-097fffh 18 088000h-08ffffh 17 080000h-087fffh 16 078000h-07ffffh 15 070000h-077fffh 14 068000h-06ffffh 13 060000h-067fffh 12 058000h-05ffffh 11 050000h-057fffh 10 048000h-04ffffh 9 040000h-047fffh 8 038000h-03ffffh 7 030000h-037fffh 6 028000h-02ffffh 5 020000h-027fffh 4 018000h-01ffffh 3 010000h-017fffh 2 008000h-00ffffh 1 000000h-007fffh block number address range (x16 bus width)
m58lw032a 46/61 appendix b. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 26, 27, 28, 29, 30 and 31 show the addresses used to re- trieve the data. table 26. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. sba is the start base address for each block. table 27. cfi - query address and data output note: 1. query data are always presented on dq7-dq0. dq15-dq8 are set to '0'. 2. offset 19h defines a which points to the alternate algorithm extended query address table. offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (sba+02)h block status register block-related information address a21-a1 data instruction 10h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 11h 52h "r" 12h 59h "y" 13h 01h primary vendor: command set and control interface id code 14h 00h 15h 31h primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 00h alternate algorithm extended query address table 1ah (2) 00h
47/61 m58lw032a table 28. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. table 29. device geometry definition address a21-a1 data description 1bh 27h (1) v dd min, 2.7v 1ch 36h (1) v dd max, 3.6v 1dh 00h (2) v pp min C not available 1eh 00h (2) v pp max C not available 1fh 04h 2 n s typical time-out for word, dword prog C not available 20h 08h 2 n s, typical time-out for max buffer write 21h 0ah 2 n ms, typical time-out for erase block 22h 00h (3) 2 n ms, typical time-out for chip erase C not available 23h 04h 2 n x typical for word dword time-out max C not available 24h 04h 2 n x typical for buffer write time-out max 25h 04h 2 n x typical for individual block erase time-out maximum 26h 00h (3) 2 n x typical for chip erase max time-out C not available address a21-a1 data description 27h 16h n where 2 n is number of bytes memory size 28h 29h 01h 00h device interface 2ah 05h maximum number of bytes in write buffer, 2 n 2bh 00h 2ch 01h bit7-0 = number of erase block regions in device 2dh 3fh number (n-1) of erase blocks of identical size; n=64 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (128k bytes) 30h 01h
m58lw032a 48/61 table 30. block status register note: 1. ba specifies the block address location, a21-a17. 2. not supported. address a21-a1 data selected block information (ba+2)h (1) bit0 0 block unprotected 1 block protected bit1 0 last erase operation ended successfully (2) 1 last erase operation not ended successfully (2) bit7-2 0 reserved for future features
49/61 m58lw032a table 31. extended query information note: 1. bit7 to bit4 are coded in hexadecimal and scaled in volt while bit3 to bit0 are in binary code decimal and scaled in mv. address offset address a21-a2 data (hex) x16 bus width description (p)h 31h 50h "p" query ascii string - extended table (p+1)h 32h 52h "r" (p+2)h 33h 49h "i" (p+3)h 34h 31h major version number (p+4)h 35h 31h minor version number (p+5)h 36h ceh optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, protect/unprotect supported (1=yes) bit4, queue erase supported (0=no) bit5, instant individual block locking (0=no) bit6, protection bits supported (1=yes) bit7, page read supported (1=yes) bit8, synchronous read supported (1=yes) bits 9 to 31 reserved for future use (p+6)h 37h 01h (p+7)h 38h 00h (p+8)h 39h 00h (p+9)h 3ah 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h 3bh 01h block status register bit0, block protect bit status active (1=yes) bit1, block lock-down bit status, not supported bits 2 to 15 reserved for future use (p+b)h 3ch 00h (p+c)h 3dh 33h v dd optimum program/erase voltage conditions (p+d)h 3eh 00h v pp optimum program/erase voltage conditions (p+e)h 3fh 01h otp protection: no. of protection register fields (p+f)h 40h 80h protection registers start address, least significant bits (p+10)h 41h 00h protection registers start address, most significant bits (p+11)h 42h 03h n where 2 n is number of factory reprogrammed bytes (p+12)h 43h 03h n where 2 n is number user programmable bytes (p+13)h 44h 04h page read: 2 n bytes (n = bits 0-7) (p+14)h 45h 03h synchronous mode configuration fields (p+15)h 46h 01h n where 2 n+1 is the number of words for the burst length = 4 (p+16)h 47h 02h n where 2 n+1 is the number of words for the burst length = 8 (p+17)h 48h 07h burst continuous
m58lw032a 50/61 appendix c. flow charts figure 23. write to buffer and program flowchart and pseudo code write to buffer e8h command, block address ai05511 start read status register no b7 = 1 write buffer data, start address yes x = n yes no end no write to buffer timeout write n (1) , block address yes x = 0 write next buffer data, next program address (2) x = x + 1 program buffer to flash confirm d0h read status register no b7 = 1 yes full status register check (3) try again later note 1: n+1 is number of words to be programmed note 2: next program address must have same a5-a21. note 3: a full status register check must be done to check the program operation's success.
51/61 m58lw032a figure 24. program suspend & resume flowchart and pseudo code write 70h ai00612 read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b2 = 0, program completed read memory array instruction: C write ffh C one or more data reads from other blocks write d0h program erase resume command: C write d0h to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
m58lw032a 52/61 figure 25. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clear status register command) before further program or eras e oper- ations. write 20h ai00613b start write d0h to block address read status register yes no b7 = 1 yes no b3 = 0 no b4, b5 = 0 v pp invalid error (1) command sequence error erase command: C write 20h C write d0h to block address (a12-a17) (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while b7 = 1 if b3 = 1, v pp invalid error: C error handler if b4, b5 = 1, command sequence error: C error handler yes no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: C error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: C error handler
53/61 m58lw032a figure 26. erase suspend & resume flowchart and pseudo code write 70h ai00615 read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while b7 = 1 if b6 = 0, erase completed read memory array command: C write ffh C one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
m58lw032a 54/61 figure 27. block protect flowchart and pseudo code write 01h block address ai06157b yes no b7 = 1 start write 60h block address write ffh block protect sucessful b3 = 1 b4, b5 = 1,1 b4 = 1 v pp invalid error invalid command sequence error block protect error yes yes yes no no no block protect command C write 60h, block adress C write 01h, block adress do: C read status register ( toggle g or e, do not use the read status register command) while b7 = 1 if b3 = 1, v pp invalid error read memory array command: C write ffh if b4 = 1, b5 = 1 invalid command sequence error if b4 = 1, block protect error read status register (toggle g or e ) end
55/61 m58lw032a figure 28. blocks unprotect flowchart and pseudo code write d0h ai06158b yes no b7 = 1 start write 60h write ffh blocks unprotect sucessful b3 = 1 b4, b5 = 1,1 b5 = 1 v pp invalid error invalid command sequence error blocks unprotect error yes yes yes no no no block unprotect command C write 60h, block adress C write d0h, block adress while b7 = 1 if b3 = 1, v pp invalid error read memory array command: C write ffh if b4 = 1, b5 = 1 invalid command sequence error if b5 = 1, blocks unprotect error do: C read status register ( toggle g or e, do not use the read status register command) read status register (toggle g or e ) end
m58lw032a 56/61 figure 29. protection register program flowchart and pseudo code note: pr = protection register write pr address, pr data ai06159b yes no b7 = 1 start write c0h write ffh read status register (toggle g or e ) pr program sucessful b4 = 1 v pp invalid error protection register program error protection register protection error yes yes yes no no no protection register program command C write c0h C write protection register address, protection register data do: C read status register (toggle g or e, do not use the read status register command) while b7 = 1 read memory array command: C write ffh if b4 = 1 protection register program error b3 = 1 if b3 = 1 v pp invalid error b1 = 1 if b1 = 1 program error due to protection register protection write ffh read memory array command C write ffh end
57/61 m58lw032a figure 30. command interface and program erase controller flowchart (a) ai03618 read signature yes no 90h read status yes 70h no clear status yes 50h no program buffer load yes e8h no erase set-up yes 20h (1) no erase command error yes ffh wait for command write read array yes d0h no a b no c cfi query yes 98h no d0h yes no program command error note 1. the erase command (20h) can only be issued if the flash is not already in erase suspend.
m58lw032a 58/61 figure 31. command interface and program erase controller flowchart (b) read status yes no 70h b erase yes ready ? no a b0h no read status yes ready ? no erase suspend yes d0h read array yes erase suspended read status (read status) yes (erase resume) no read status 90h no read signature yes 98h no cfi query yes e8h no program buffer load yes c ai03619 program/erase controller status bit in the status register read status d0h yes no no program command error wait for command write ffh yes read array no
59/61 m58lw032a figure 32. command interface and program erase controller flowchart (c). read status yes no 70h b program yes ready ? no c b0h no read status yes ready ? no program suspend yes d0h read array yes program suspended read status (read status) yes no (program resume) no read status 90h no read signature yes 98h no cfi query yes ai00618 program/erase controller status bit in the status register read status read array yes no ffh wait for command write
m58lw032a 60/61 revision history table 32. document revision history date version revision details february 2001 -01 first issue (data brief) 17-sep-2001 -02 expanded to full product preview. 27-sep-2001 -03 changes on table 18, asynchronous write and latch controlled write ac characteristics, write enable controlled changes on table 20, synchronous burst read ac characteristics 1-feb-2002 -04 status register section and table clarified, burst configuration register table clarified, block protect, blocks unprotect and protection register program flowcharts added, reset, power-down and power-up ac characteristics table modified. 12-mar-2002 -05 document status changed to preliminary data. table 18, twhgl timing modified, table 19, tlhgl and tehgl timings modified. i dd5 modified in dc characteristics table, t lead removed from absolute maximum ratings table. tfbga64 not connected pins changed to do not use. 07-may-2002 -06 reference to temporary unprotect removed from word program command section, tfbga package dimensions added to description. block protect and blocks unprotect flowcharts clarified, protection register program description and flowchart clarified, status register v pp status bit description clarified. document status changed to datasheet. 04-jul-2002 -07 110ns speed class added. 06-aug-2002 7.1 revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot. (revision version 07 equals 7.0). description of reset/power-down pin, rp , specified. v dd , v ddq , v ss and v ssq pin descriptions modified. table 24,ordering information scheme modified. 11-feb-2003 7.2 revision history moved to end of document. block protect setup command address modified in table 6, commands. cfi, extended query information table descriptions clarified. protection register program flowchart and pseudo code clarified. table 9, program, erase times and program erase endurance cycles modified.
61/61 m58lw032a information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

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