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general description the DS3503 features two synchronized stepping digital potentiometers: one 7-bit potentiometer with rw as its output, and another potentiometer with y as its output. both potentiometers reference the rh and rl terminals and feature an output voltage range of up to 15.5v. in addition, both potentiometer outputs can be stepped up and down by configuring the control registers. programming is accomplished by an i 2 c-compatible interface that can operate at speeds of up to 400khz. applications tft-lcd v com calibration instrumentation and industrial controls mechanical potentiometer replacement features ? 128 wiper tap points ? full-scale resistance: 5k ? programmable logic lets wr step up and down with timing controlled by sync input ? second potentiometer output pin (y) centered at position 40h ? i 2 c-compatible serial interface ? digital operating voltage: 2.7v to 3.6v ? analog operating voltage: 4.5v to 15.5v ? operating temperature: -40? to +100? ? 10-pin ?op package DS3503 nv, i 2 c, stepper potentiometer ________________________________________________________________ maxim integrated products 1 ordering information rev 0; 11/08 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package DS3503u+ -40c to +100c 10 sop DS3503u+t&r -40c to +100c 10 sop + denotes a lead-free/rohs-compliant package. t&r = tape and reel. typical operating circuit appears at end of data sheet. period period 1 lsb 1 lsb wr code 64 (40h) wr+stepcount code 64 (40h) + stepcount code 64 (40h) - stepcount code 64 (40h) wr-stepcount rw y DS3503 i o out i 2 c logic ivr eeprom address i 2 c rd bus scl sda scl sda v+ v cc gnd sync step control register mux wr register address 7-bit pot step counter and control logic i 2 c wr bus count period (2 bits) step count (2 bits) rh rl 7-bit pot rh rl functional diagram sop 29v+ gnd 1 10 scl sda rl v cc 38 47rw sync rh y5 6 top view DS3503 pin configuration
DS3503 nv, i 2 c, stepper potentiometer 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40? to +100?) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc relative to gnd ...............-0.5v to +6.0v voltage range on v+ relative to gnd ..................-0.5v to +17v voltage range on sda, scl, and sync relative to v cc ........-0.5v to (v cc + 0.5v), not to exceed 6.0v voltage range on rh, rl, rw, and y .......................-0.5v to v+ voltage range across rh and rl .............................-0.5v to v+ operating temperature range .........................-40? to +100? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units v cc supply voltage v cc (note 1) +2.7 +3.6 v v+ voltage v+ > v cc (note 1) +4.5 +15.5 v input logic 0 (scl, sda, sync) v il (note 1) -0.3 0.3 x v cc v input logic 1 (scl, sda, sync) v ih (note 1) 0.7 x v cc v cc + 0.3 v switch current (all switches) i sw 3 ma resistor current i res 3 ma sync frequency f sync 1 mhz electrical characteristics (v cc = +2.7v to +3.6v, t a = -40? to +100?, unless otherwise noted.) parameter symbol conditions min typ max units v cc standby current i stby v cc = +3.6v, i 2 c inactive (note 2) 10 a v cc supply current (nv read or write) i cc f scl = 400khz (note 3) 3 ma v+ bias current i v+ +1 a input leakage (sda, scl, sync) i l -1 +1 a low-level output voltage (sda) v ol 3ma sink current 0 0.4 v dcp wiper response time t dcp 1 s i/o capacitance c i/o 5 10 pf power-up recall voltage v por min v cc when nv memory is recalled (note 4) 1.2 2.6 v power-up memory recall delay t d v cc > v por to initial memory recall done (note 5) 3 ms wiper resistance r w v+ = 15.0v 5000 end-to-end resistance (rh to rl) r total 5 k r total tolerance -20 +20 % ch, cl, cw capacitance c pot 10 pf
DS3503 nv, i 2 c, stepper potentiometer _______________________________________________________________________________________ 3 voltage-divider characteristics (v cc = +2.7v to +3.6v, t a = -40? to +100?, with rl = 0v, rh = v+, y, and rw unloaded, unless otherwise noted.) parameter symbol conditions min typ max units integral nonlinearity inl (note 6) -1 +1 lsb differential nonlinearity dnl (note 7) -0.5 +0.5 lsb output matching -1 +1 lsb zero-scale error zs error (note 8) 0 0.5 2 lsb full-scale error fs error (note 9) -2 -1 0 lsb ratiometric temp coefficient tcv wr/ivr set to 40h 4 ppm/c i 2 c ac electrical characteristics (v cc = +2.7v to +3.6v, t a = -40? to +100?, timing referenced to v il(max) and v ih(min) . see figure 2.) parameter symbol conditions min typ max units scl clock frequency f scl (note 10) 0 400 khz bus-free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd:sta 0.6 s low period of scl t low 1.3 s high period of scl t high 0.6 s data hold time t hd:dat 0 0.9 s data setup time t su:dat 100 ns start setup time t su:sta 0.6 s sda and scl rise time t r (note 11) 20 + 0.1c b 300 ns sda and scl fall time t f (note 11) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 s sda and scl capacitive loading c b (note 11) 400 pf eeprom write time t w (note 12) 10 20 ms pulse-width suppression time at sda and scl inputs t in (note 13) 50 ns sda and scl input buffer hysteresis 0.05 x v cc v
DS3503 nv, i 2 c, stepper potentiometer 4 _______________________________________________________________________________________ note 1: all voltages are referenced to ground. currents entering the ic are specified positive and currents exiting the ic are negative . note 2: i stby is specified with sda = scl = v cc and resistor pins floating. note 3: i cc is specified with the following conditions: scl = 400khz, sda pulled up, and rl, rw, rh, and y floating. note 4: this is the minimum v cc voltage that causes nv memory to be recalled. note 5: this is the time from v cc > v por until initial memory recall is complete. note 6: integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis- tor setting. expected value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting. inl = [v(rw) i - (v(rw) 0 ]/lsb(ideal) - i, for i = 0...127. note 7: differential nonlinearity is the deviation of the step-size change between two lsb settings from the expected step size. the expected lsb step size is the slope of the straight line from measured minimum position to measured maximum position. dnl = [v(rw) i+1 - (v(rw) i ]/lsb(ideal) - 1, for i = 0...126. note 8: zs error = code 0 wiper voltage divided by one lsb (ideal). note 9: fs error = (code 127 wiper voltage - v+) divided by one lsb (ideal). note 10: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward-compatible with i 2 c stan- dard mode timing. note 11: cb?otal capacitance of one bus line in picofarads. note 12: eeprom write time begins after a stop condition occurs. note 13: pulses narrower than max are suppressed. nonvolatile memory characteristics (v cc = +2.7v to +3.6v, unless otherwise noted.) parameter symbol conditions min typ max units eeprom write cycles t a = +70c 30,000 writes supply current vs. supply voltage DS3503 toc01 supply voltage (v) supply current ( a) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 1 2 3 4 5 0 2.7 3.6 sda = scl = v cc , v+ = 15v, sync = gnd rw, rh, rl, and y are floating supply current vs. temperature DS3503 toc02 temperature ( c) supply current ( a) 80 60 40 20 0 -20 2 3 4 5 1 -40 100 sda = scl = v cc = 3.3v, v+ = 15v, sync = gnd rw, rh, rl, and y are floating supply current vs. scl frequency DS3503 toc03 scl frequency (khz) supply current ( a) 350 300 250 200 150 100 50 2 4 6 8 10 12 14 0 0 400 sda = v cc = 3.6v, v+ = 15v sync = gnd, scl = 3.6v p-p rw, rh, rl, and y are floating typical operating characteristics (t a = +25?, unless otherwise noted.)
supply current vs. sync frequency DS3503 toc04 sync frequency (khz) supply current ( a) 800 600 400 200 1 2 3 4 5 0 0 1000 sda = scl = v cc = 3.3v v+ = 15v, sync = 3.3v p-p rw, rh, rl, and y are floating integral nonlinearity vs. potentiometer setting DS3503 toc05 potentiometer setting (dec) integral nonlinearity (lsb) 120 100 60 80 40 20 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 sda = scl = v cc = 3.3v, v+ = 15v differential nonlinearity vs. potentiometer setting DS3503 toc06 potentiometer setting (dec) differential nonlinearity (lsb) 120 100 60 80 40 20 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.5 0 sda = scl = v cc = 3.3v, v+ = 15v delta between rw and y vs. potentiometer setting DS3503 toc07 potentiometer setting (dec) differential nonlinearity (lsb) 120 100 60 80 40 20 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 sda = scl = v cc = 3.3v, v+ = 15v stepcount = 31 DS3503 nv, i 2 c, stepper potentiometer _______________________________________________________________________________________ 5 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.) pin description name pin function sda 1 i 2 c serial data. input/output for i 2 c data. gnd 2 ground terminal v cc 3 supply voltage terminal sync 4 stepping clock input. the rising edge updates the outputs. y 5 code 40h centered dac output rh 6 high terminal of potentiometer rw 7 wiper terminal of potentiometer rl 8 low terminal of potentiometer v+ 9 wiper bias voltage scl 10 i 2 c serial clock. input for i 2 c clock.
DS3503 nv, i 2 c, stepper potentiometer 6 _______________________________________________________________________________________ detailed description the DS3503 contains two potentiometers whose out- puts can be stepped up and down by configuring the control registers. one potentiometer, with output rw, is controlled by the initial value register/wiper register (ivr/wr). the other potentiometer is fixed at setting 40h, and its output is on the y pin. by using the config- uration registers and the sync pin, the outputs from these two potentiometers can be stepped up and down. digital potentiometers the rw potentiometer consists of 127 resistors in series connected between the rh and rl pins. between each resistance and at the two end points, rh and rl, solid-state switches enable rw to be connect- ed within the resistive network. the wiper position and the output on rw are decoded based on the value in wr. if rh, rl, and rw are externally connected in a voltage-divider configuration, the voltage on rw can be easily calculated using the following equation: where wr is the wiper position in decimal (0?27). the factory default setting for this potentiometer is 40h. the y potentiometer is also referenced to the rh and rl terminals, but is centered at a 40h setting. memory map the DS3503 contains three registers for controlling the outputs of the two potentiometers, pins rw and y. table 1 shows the memory map. ivr/wr is accessed at register address 00h and contains the power-on and current values of the rw potentiometer. the step control register (scr) controls the stepping function for both potentiometers. the control register (cr) con- trols the write functionality of the ivr/wr. initial value register/wiper register (ivr/wr) programming ivr sets the initial power-up value of the rw wiper position. ivr/wr can be visualized as a volatile register (wr) in parallel with a nonvolatile regis- ter (ivr). on power-up, the data stored in ivr is loaded into wr, which sets the position of the potentiometer? wiper. the factory default value for ivr is 40h. see the stepping section for information about clamping. vv wr vv rw rl rh rl =+ ? 127 () name address (hex) access nonvolatile volatile ivr/wr 00h r/w initial value register (ivr), factory setting = 40h wiper register (wr) scr 01h r/w step control register, factory setting = 00h cr 02h r/w control register soft-por aah r/w soft power-on reset register table 1. memory map
DS3503 nv, i 2 c, stepper potentiometer _______________________________________________________________________________________ 7 step control register (scr) scr determines the stepping functionality for the rw and y potentiometers (see the stepping section). the five lsbs, bits 4:0, control the stepcount, which is the number of steps up and down the wiper moves when stepping is enabled. bits 5 and 6 control the period, which is the number of pulses of the sync pin required to perform one step. setting stepcount to all zeros disables stepping for the DS3503. control register (cr) cr located at register address 02h determines how i 2 c data is written to ivr/wr at 00h. when cr is set to a value of 00h, i 2 c writes to memory address 00h write to both wr and ivr. when cr is set to a value of 80h, i 2 c writes to memory address 00h write only to wr. regardless of the cr setting, all i 2 c reads of address 00h return the contents of wr. cr is volatile and powers up as 00h, so i 2 c writes are to both the ivr and wr locations. the data that is stored in eeprom and sram remains unchanged if the value of cr is changed. table 3 defines cr. stepping the DS3503 can step the rw output up to wr+step- count and down to wr-stepcount when stepping is enabled. stepping is enabled when a nonzero step- count value is programmed into scr and pulses are applied to the sync input pin. stepping is disabled when stepcount = 0 or no pulses are applied on the sync input pin. the falling edge of the sync pulse updates the outputs. the y potentiometer output is cre- ated by adding to position 40h (code 64 decimal) the same counter value as is added to wr to form the input to the rw potentiometer. the wr value is internally limited (clamped) to a minimum of stepcount and maximum of 127 - stepcount. when stepping is enabled, the rw wiper position is controlled by wr plus a counter value (count in the functional diagram). count increments or decre- ments when the number of sync pulses received since the last count change is equal to period. scr bits 6:5 set period equal to 32, 64, 128, or 256 sync puls- es (see table 2). after power-up or after any i 2 c write to ivr/wr, cr, or scr, stepping is initially disabled until 512 plus bit name function 4:0 stepcount bit 4 is the msb; bit 0 is the lsb. these 5 bits define the number of steps in an up or down cycle. maximum is 31, minimum is 0. a stepcount of zero corresponds to a disabled counter. 0, 0: period = 32 sync pulses 0, 1: period = 64 sync pulses 1, 0: period = 128 sync pulses 6:5 period 1, 1: period = 256 sync pulses 7 reserved table 2. step control register description (01h) bit name function 6:0 reserved 7 ivr/wr address mode 0: read wr; write ivr and wr at address 00h. 1: read wr; write wr at address 00h. table 3. control register description (02h)
DS3503 nv, i 2 c, stepper potentiometer 8 _______________________________________________________________________________________ period/2 pulses have been applied to the sync input. during this disable time, the power-up or new wr value is applied to the rw potentiometer and position 40h (code 64 decimal) is applied to the y potentiometer. additionally, the step counter is cleared during this disable time. after the initialization pulses, stepping is enabled again. the rw potentiometer starts from the power-up or new wr value and the y potentiometer starts from position 40h (code 64 decimal). the step counter starts from zero in the up direction. the stepping function is further described as follows: an internal counter called periodcount is set equal to period. the input to the rw potentiometer is wr + count; the input to the y potentiometer is code 64 + count. when a sync pulse is received: periodcount = periodcount - 1 if periodcount = 0 (underflow), the following actions occur: if direction is up: count = min (count + 1, stepcount) rw = min (127 - stepcount, wr + count); y = 64 + count periodcount is reset to period if direction is down: count = max (count - 1, -stepcount) rw = max (stepcount, wr - count); y = 64 - count periodcount is reset to period if count = stepcount, direction is changed from up to down. if count = -stepcount, direction is changed from down to up. in this way the rw output steps up to wr+step- count, then steps down to wr-stepcount, and then repeats the cycle. the outputs of the rw and y dacs change by one lsb = (vrh - vrl)/127 per period. stepcount and period are programmable from i 2 c and are stored in the nonvolatile scr (table 2). the stepcount 5-bit value programmed into scr<4:0> controls the stepping range reflected in the rw or y outputs per table 4, assuming stepcount < ivr < 127 - stepcount: example 1: wr = 41h (65 decimal): scr<4:0> = stepcount = 10000 (16 decimal) rw range: 49 ? 81 (decimal) y range: 48 ? 80 (decimal) example 2: wr = 50h (80 decimal): scr<4:0> = stepcount = 11000 (24 decimal) rw range: 56 ? 104 (decimal) y range: 40 ? 88 (decimal) example 3: clamping at lower rail wr = 10h (16 decimal): scr<4:0> = stepcount = 11111 (31 decimal) rw range: 0 ? 62 (decimal) y range: 33 ? 95 (decimal) example 4: clamping at upper rail wr = 70h (112 decimal): scr<4:0> = stepcount = 11111 (31 decimal) rw range: 65 ? 127 (decimal) y range: 33 ? 95 (decimal) scr<4:0> (binary) dac range 0 0000 stepping disabled; wr is output 0 0001 wr-1 to wr+1 0 0010 wr-2 to wr+2 0 0011 wr-3 to wr+3 0 0100 wr-4 to wr+4 0 0101 wr-5 to wr+5 . . . . . . 1 1110 wr-30 to wr+30 . . . . . . 1 1111 wr-31 to wr+31 table 4. dac stepping range
DS3503 nv, i 2 c, stepper potentiometer _______________________________________________________________________________________ 9 soft power-on reset register (soft-por) by writing register aah's msb to 1, a soft power-on reset (soft-por) can be generated. when the msb is set to 1, the power-up default values of registers 00h, 01h, and 02h are recalled, and the msb of aah self- clears. this soft-por can be used to recall power-on settings without cycling power to the DS3503. i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. (see figure 2 and the i 2 c ac electrical characteristics table for additional information.) master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac- tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi- cally to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit name function 6:0 reserved 7 soft por 0: default value. 1: recalls values of ivr, cr, and scr from eeprom. table 5. soft power-on reset register description (aah) scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 2. i 2 c timing diagram
DS3503 nv, i 2 c, stepper potentiometer 10 ______________________________________________________________________________________ bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl dur- ing a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the cur- rent scl pulse. remember that the master gener- ates all scl clock pulses, including when it is reading bits from the slave. acknowledge (ack and nack): an acknowledge (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by trans- mitting a 0 during the 9th bit. a device performs a nack by transmitting a 1 during the 9th bit. timing for the ack and nack is identical to all other bit writes (figure 2). an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or indicates that the device is not receiving data. byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. the 8 bits transmitted by the master are done according to the bit-write definition and the acknowledgment is read using the bit-read definition. byte read: a byte read is an 8-bit information trans- fer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ack using the bit-write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. the DS3503? slave address is 50h (see figure 1). when the r/ w bit is 0 (such as in 50h), the master is indicating it will write data to the slave. if r/ w = 1 (51h in this case), the master is indicating it wants to read from the slave. if an incorrect slave address is written, the DS3503 assumes the master is communicating with another i 2 c device and ignores the communication until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must gen- erate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. remember the master must read the slave? acknowledgment during all byte-write operations. when writing to the DS3503, the potentiometer adjusts to the new setting once it has acknowledged the new data that is being written, and the eeprom is written following the stop condition at the end of the write command. to change the setting without changing the eeprom, termi- nate the write with a repeated start condition before the next stop condition occurs. using a repeated start condition prevents the t w delay required for the eeprom write cycle to finish. acknowledge polling: any time a eeprom byte is written, the DS3503 requires the eeprom write time (t w ) after the stop condition to write the contents of the byte to eeprom. during the eeprom write time, the device will not acknowledge its slave address because it is busy. it is possible to take advantage of this phe- nomenon by repeatedly addressing the DS3503, which allows communication to continue as soon as the DS3503 is ready. the alternative to acknowledge polling is to wait for a maximum period of t w to elapse before attempting to access the device. eeprom write cycles: the DS3503? eeprom write cycles are specified in the nonvolatile memory characteristics table. the specification shown is at the worst-case temperature (hot) as well as at room tem- perature. writing to wr/ivr with cr = 80h does not count as a eeprom write. 01 1 0 r/w 0 0 0 msb lsb slave address 50h figure 1. DS3503 slave address byte
DS3503 nv, i 2 c, stepper potentiometer ______________________________________________________________________________________ 11 reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read opera- tion occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, because requiring the master to keep track of the memory address counter is impracti- cal, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. see figure 3 for a read example using the repeated start condition to specify the starting memory location. applications information power-supply decoupling to achieve the best results when using the DS3503, decouple both the power-supply pin (v cc ) and the wiper-bias voltage pin (v+) with a 0.01? or 0.1? capacitor. use a high-quality ceramic surface-mount capacitor if possible. surface-mount components mini- mize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high- frequency response for decoupling applications. sda and scl pullup resistors sda is an i/o with an open-collector output that requires a pullup resistor to realize high-logic levels. a master using either an open-collector output with a pullup resistor or a push-pull output driver must be used for scl. pullup resistor values should be chosen to ensure that the rise and fall times listed in the i 2 c ac electrical characteristics are within specification. a typ- ical value for the pullup resistors is 4.7k . slave address start start 0 1 0 1 0 0 0 r/w slave ack slave ack slave ack msb lsb msb lsb msb lsb b7 b6 b5 b4 b3 b2 b1 b0 read/ write register address b7 b6 b5 b4 b3 b2 b1 b0 data stop single-byte write -write step control register (scr) to 1fh single-byte read -read control register (cr) start repeated start 51h master nack stop 01010000 00000 010 02h 01010 001 01010000 00000 001 00011111 50h 01h 1fh stop data example i 2 c transactions typical i 2 c write transaction 50h a) b) slave ack slave ack slave ack slave ack slave ack slave ack figure 3. i 2 c communication examples
DS3503 nv, i 2 c, stepper potentiometer maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. v cc 3.0v gnd rl rw y v+ rh scl i 2 c c lcd v com r1 g1 b1 gate 1 gate 2 gate 3 c stor tft sync 15.0v sda DS3503 typical operating circuit package type package code document no. 10 ?op u10+2 21-0061 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .

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