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? semiconductor components industries, llc, 2008 september, 2008 ? rev. 4 1 publication order number: ncp1395/d NCP1395A/b high performance resonant mode controller the NCP1395A/b offers everything needed to build a reliable and rugged resonant mode power supply. its unique architecture includes a 1.0 mhz voltage controller oscillator whose control mode brings flexibility when an oring function is a necessity, e.g. in multiple feedback paths implementations. protections featuring various reaction times, e.g. immediate shutdown or timer ? based event, brown ? out, broken optocoupler detection etc., contribute to a safer converter design, without enge ndering additional circuitry complexity. an adjustable deadtime also helps lowering the shoot ? through current contribution as the switching frequency increases. finally, an onboard operational transconductance amplifier allows for various configurations, including constant output current working mode or traditional voltage regulation. features ? high frequency operation from 50 khz up to 1.0 mhz ? selectable minimum switching frequency with 3% accuracy ? adjustable deadtime from 150 ns to 1.0 s ? startup sequence via an adjustable soft ? start ? brown ? out protection for a simpler pfc association ? latched input for severe fault conditions, e.g. overtemperature or ovp ? timer ? based input with auto ? recovery operation for delayed event reaction ? enable input for immediate event reaction or simple on/off control ? operational transconductance amplifier (ota) for multiple feedback loops ? v cc operation up to 20 v ? low startup current of 300 a max ? common collector optocoupler connection ? internal temperature shutdown ? b version features 10 v v cc startup threshold for auxiliary supply usage ? easy no ? load operation and low standby power due to programmable skip ? cycle ? these are pb ? free devices typical applications ? lcd/plasma tv converters ? high power ac ? dc adapters for notebooks ? industrial and medical power sources ? offline battery chargers pdip ? 16 p suffix case 648 pin connections http://onsemi.com marking diagrams x = a or b a = assembly location wl = wafer lot yy, y = year ww = work week g = pb ? free package so ? 16 d suffix case 751b 1395xdr2g awlyww 1 16 1 2 3 4 5 6 7 8 16 15 14 12 11 10 9 (top view ) fb fmin fmax dt css ctimer bo agnd ninv out vcc b pgnd slow fault a 13 fast fault see detailed ordering and shipping information in the package dimensions section on page 25 of this data sheet. ordering information 16 1 16 1 ncp1395xp awlyywwg
NCP1395A/b http://onsemi.com 2 ncp1395 fmin fmax deadtime soft ? start timer bo slow fault ncp5181 power ground v cc = 15 v hv analog ground + v out figure 1. typical application example 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1 2 3 4 8 7 6 5
NCP1395A/b http://onsemi.com 3 pin function description pin no. symbol function description 1 fmin timing resistor connecting a resistor to this pin, sets the minimum oscillator frequency reached for vfb is below 1.3 v. 2 fmax frequency clamp a resistor sets the maximum frequency excursion. 3 dt deadtime a simple resistor adjusts the deadtime length. 4 css soft ? start select the soft ? start duration. 5 fb feedback applying a voltage above 1.3 v on this pin increases the oscillation frequency up to fmax. 6 ctimer timer duration sets the timer duration in presence of a fault. 7 bo brown ? out detects low input voltage conditions. when brought above vlatch, it fully latches off the controller. 8 agnd analog ground ? 9 pgnd power ground ? 10 a low side output drives the low side power mosfet. 11 b high side output drives the upper side power mosfet. 12 vcc supplies the controller ? 13 fast fault quick fault detection fast shutdown pin, stops all pulses when brought high. please look in the description for more details about the fast ? fault sequence. 14 slow fault slow fault detection when asserted, the timer starts to countdown and shuts down the controller at the end of its time duration. 15 out opamp output internal transconductance amplifier. 16 ninv opamp noninverting non ? inverting pin of the opamp.
NCP1395A/b http://onsemi.com 4 vref fmin vdd imin vfb = < vfb_off c idt ? + + dt adj. i = imax for vfb = 5 v i = 0 for vfb < vfb_off vref vdd imin vfb = < vfb_off vref vdd imax vfb = 5 fmax vdd itimer if fault itimer else 0 ? + timer + vref pon reset fault vdd iss ss fb rfb ? + + vfb_fault ? + g = 1 > 0 only if v(fb) > vfb_off idt vref vdd + vfb_off dt deadtime adjustment vdd ? + bo + vbo agnd ? + + vlatch 20 s noise filter clk d s q q r s q q r pon reset 50% dc temperature shutdown vcc management pon reset fault timeout fault + - + vref_fb vref gm ninv out bo reset ff + - slow fault + vref fault ss reset on a version only + - + vref fault fast fault 20 v v cc timeout fault ss uvlo fault b a pgnd figure 2. internal circuit architecture ibo
NCP1395A/b http://onsemi.com 5 maximum ratings rating symbol value unit power supply v oltage, pin 12 v cc 20 v transient current injected into v cc when internal zener is activated ? pulse width < 10 ms ? 10 ma power supply voltage, all pins (except pins 10 and 11) ? ? 0.3 to 10 v thermal resistance, junction ? to ? air, pdip version r ja 130 c/w thermal resistance, junction ? to ? air, soic version r ja 100 c/w storage temperature range ? ? 60 to +150 c esd capability, human body model ? 2 kv esd capability, machine model ? 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model 2000v per jesd22 ? a114 ? b machine model method 200v per jesd22 ? a115 ? a. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
NCP1395A/b http://onsemi.com 6 electrical characteristics (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 11 v, unless otherwise noted.) characteristic pin symbol min typ max unit supply section turn ? on threshold level, v cc going up ? a version 12 vcc on 12.3 13.3 14.3 v turn ? on threshold level, v cc going up ? b version 12 vcc on 9.3 10.3 11.3 v minimum operating voltage after turn ? on 12 vcc (min) 8.3 9.3 10.3 v minimum hysteresis between vcc on and vcc (min) ? a version 12 vhystea ? 3.0 ? v minimum hysteresis between vcc on and vcc (min) ? b version 12 vhysteb ? 1.0 ? v startup current, v cc < vcc on 12 istartup ? ? 300 a v cc level at which the internal logic gets reset 12 vcc reset ? 5.9 ? v internal ic consumption, no output load on pins 11/12, fsw = 300 khz 12 icc1 ? 1.6 ? ma internal ic consumption, 100 pf output load on pin 11 / 12, fsw = 300 khz 12 icc2 ? 2.3 ? ma consumption in fault mode (all drivers disabled, vcc > vcc (min) ) 12 icc3 ? 1.3 ? ma voltage control oscillator (vco) minimum switching frequency, rt = 120 k on pin 1, vpin 5 = 0 v, dt = 300 ns 1 fsw min 48.5 50 51.5 khz maximum switching frequency, rfmax = 22 k on pin 2, vpin 5 > 6.0 v, dt = 300 ns ? t j = 25 c (note 3) 2 fsw max 0.9 1.0 1.11 mhz feedback pin swing above which f = 0 5 fbsw ? 6.0 ? v vco v cc rejection, v cc = 1.0 v, in percentage of fsw ? psrr ? 0.2 ? %/v operating duty cycle 11 ? 10 dc 48 50 52 % reference voltage for all current generations (fosc, dt) 1, 3 vref 1.86 2.0 2.14 v delay before any driver restart in fault mode ? tdel ? 20 ? s feedback section internal pulldown resistor 5 rfb ? 20 ? k ota internal of fset voltage 16 vref_fb 2.325 2.5 2.675 v voltage on pin 5 below which the fb level has no vco action 5 vfb_off ? 1.3 ? v voltage on pin 5 below which the controller considers a fault 5 vfb_fault ? 0.6 ? v input bias current 16 ibias ? ? 100 na dc transconductance gain 15 otag ? 250 ? s gain product bandwidth, rload = 5.0 k 15 gbw ? 1.0 ? mhz drive output output voltage rise time @ cl = 100 pf, 10 ? 90% of output signal 11 ? 10 t r ? 20 ? ns output v oltage fall ? time @ cl = 100 pf, 10 ? 90% of output signal 11 ? 10 t f ? 20 ? ns source resistance 11 ? 10 r oh 20 60 120 sink resistance 11 ? 10 r ol 30 60 130 deadtime with r dt = 127 k from pin 3 to gnd 3 t_dead 270 300 390 ns maximum deadtime with r dt = 540 k from pin 3 to gnd 3 t_dead ? max ? 1.0 ? s minimum deadtime, r dt = 30 k from pin 3 to gnd 3 t_dead ? min ? 150 ? ns 3. room temperature only, please look at characterization data for evolution versus junction temperature.
NCP1395A/b http://onsemi.com 7 electrical characteristics (continued) (for typical values t j = 25 c, for min/max values t j = ? 40 c to +125 c, max t j = 150 c, v cc = 11 v, unless otherwise noted.) characteristic pin symbol min typ max unit timers timer charge current 6 itimer ? 150 ? a timer duration with a 1.0 f capacitor and a 1.0 m resistor 6 t ? timer ? 25 ? ms timer recurrence in permanent fault, same values as above 6 t ? timerr ? 1.4 ? s voltage at which pin 6 stops output pulses 6 vtimeron 3.7 4.1 4.5 v voltage at which pin 6 restarts output pulses 6 vtimeroff 0.9 1.0 1.1 v soft ? start ending voltage, v fb = 1.0 v 4 vss ? 2.0 ? v soft ? start charge current 4 iss 75 note 5 95 115 a soft ? start duration with a 220 nf capacitor (note 4) 4 t ? ss ? 5.0 ? ms protection reference voltage for fast input 13 vreffaultf 1.0 1.05 1.1 v reference voltage for slow input 14 vreffaults 0.98 1.03 1.08 v hysteresis for fast input 13 hystefaultf ? 50 ? mv hysteresis for slow input 14 hystefaults ? 40 ? mv propagation delay for fast fault input drive shutdown 13 tpfault ? 70 120 ns brown ? out input bias current 7 ibobias ? 0.02 ? a brown ? out level 7 vbo 0.98 1.03 1.08 v hysteresis current, vpin 7 > vbo ? a version 7 ibo_a 23 28 33 a hysteresis current, vpin 7 > vbo ? b version 7 ibo_b 70 83 96 a latching v oltage 7 vlatch 3.7 4.1 4.5 v temperature shutdown ? tsd 140 ? ? c hysteresis ? tsdhyste ? 40 ? c 4. the a version does not activate soft ? start when the fast ? fault is released, this is for skip cycle implementation. the b version does activate the soft ? start upon release of the fast ? fault input. 5. minimum current occurs at t j = 0 c.
NCP1395A/b http://onsemi.com 8 typical characteristics ? a version figure 3. vccon a figure 4. vccmin figure 5. fsw min figure 6. fsw max figure 7. reference (vref_fb) figure 8. pulldown resistor (rfb) 13.0 13.1 13.2 13.3 13.4 13.5 ? 40 20 80 voltage (v) temperature ( c) 140 0 60 120 ? 20 40 100 9.0 9.2 9.4 9.6 9.8 10 ? 40 20 80 voltage (v) temperature ( c) 14 0 0 60 120 ? 20 40 100 48 48.5 49 49.5 50 ? 40 20 80 frequency (khz) temperature ( c) 140 0 60 120 ? 20 40 100 0.7 0.8 0.9 1.0 1.1 ? 40 20 80 frequency (mhz) temperature ( c) 14 0 0 60 120 ? 20 40 100 18 19 20 21 22 23 ? 40 20 80 rfb (k ) temperature ( c) 140 0 60 120 ? 20 40 100 2.50 2.55 2.60 2.65 2.70 ? 40 20 80 vref_fb (v) temperature ( c) 14 0 0 60 120 ? 20 40 100
NCP1395A/b http://onsemi.com 9 typical characteristics ? a version figure 9. source resistance (roh) figure 10. sink resistance (rol) figure 11. t_dead_min a figure 12. t_dead_a figure 13. fast fault (vreffault ff) figure 14. t_dead_max a 40 50 60 70 80 90 ? 40 20 80 roh ( ) temperature ( c) 140 0 60 120 ? 20 40 100 130 150 170 190 210 ? 40 20 80 dt_min (ns) temperature ( c) 140 0 60 120 ? 20 40 100 300 310 320 330 350 ? 40 20 80 dt_nom (ns) temperature ( c) 14 0 0 60 120 ? 20 40 100 100 40 50 60 70 80 90 ? 40 20 80 rol ( ) temperature ( c) 14 0 0 60 120 ? 20 40 100 100 110 230 250 340 700 800 900 1000 1100 ? 40 20 80 dt_max (ns) temperature ( c) 140 0 60 120 ? 20 40 100 1.00 1.02 1.04 1.06 1.10 ? 40 20 80 vreffaultff (v) temperature ( c) 14 0 0 60 120 ? 20 40 100 1200 1300 1.08
NCP1395A/b http://onsemi.com 10 typical characteristics ? a version figure 15. brown ? out reference (vbo) figure 16. brown ? out hysteresis current (ibo) figure 17. latch level (vlatch) 1.02 1.025 1.03 1.035 1.04 ? 40 20 80 vbo (v) temperature ( c) 140 0 60 120 ? 20 40 100 4.0 4.05 4.1 4.15 4.2 ? 40 20 80 vlatch (v) temperature ( c) 140 0 60 120 ? 20 40 100 25 26 27 28 29 30 ? 40 20 80 ibo ( a) temperature ( c) 14 0 0 60 120 ? 20 40 100
NCP1395A/b http://onsemi.com 11 typical characteristics ? b version figure 18. vccon b figure 19. vccmin figure 20. fsw min figure 21. fsw max figure 22. reference (vref_fb) figure 23. pulldown resistor (rfb) 10 10.2 10.4 10.6 10.8 11 ? 40 20 80 vccon (v) temperature ( c) 140 0 60 120 ? 20 40 100 9.0 9.2 9.4 9.6 9.8 10 ? 40 20 80 vccmin (v) temperature ( c) 14 0 0 60 120 ? 20 40 100 48 48.5 49 49.5 50 ? 40 20 80 frequency (khz) temperature ( c) 140 0 60 120 ? 20 40 100 0.7 0.8 0.9 1.0 1.1 ? 40 20 80 frequency (mhz) temperature ( c) 14 0 0 60 120 ? 20 40 100 18 19 20 21 22 23 ? 40 20 80 rfb (k ) temperature ( c) 140 0 60 120 ? 20 40 100 2.50 2.55 2.60 2.65 2.70 ? 40 20 80 vref_fb (v) temperature ( c) 14 0 0 60 120 ? 20 40 100
NCP1395A/b http://onsemi.com 12 typical characteristics ? b version figure 24. source resistance (roh) figure 25. sink resistance (rol) figure 26. t_dead_min b figure 27. t_dead_b figure 28. fast fault (vreffault ff) figure 29. t_dead_max b 40 50 60 70 80 90 ? 40 20 80 roh ( ) temperature ( c) 140 0 60 120 ? 20 40 100 130 150 170 190 210 ? 40 20 80 dt_min (ns) temperature ( c) 140 0 60 120 ? 20 40 100 300 310 320 330 350 ? 40 20 80 dt_nom (ns) temperature ( c) 14 0 0 60 120 ? 20 40 100 100 40 50 60 70 80 90 ? 40 20 80 rol ( ) temperature ( c) 14 0 0 60 120 ? 20 40 100 100 110 230 250 340 700 800 900 1000 1100 ? 40 20 80 dt_max (ns) temperature ( c) 140 0 60 120 ? 20 40 100 1.00 1.02 1.04 1.06 1.10 ? 40 20 80 vreffaultff (v) temperature ( c) 14 0 0 60 120 ? 20 40 100 1200 1300 1.08
NCP1395A/b http://onsemi.com 13 typical characteristics ? b version figure 30. brown ? out reference (vbo) figure 31. brown ? out hysteresis current (ibo) figure 32. latch level (vlatch) 1.02 1.025 1.03 1.035 1.04 ? 40 20 80 vbo (v) temperature ( c) 140 0 60 120 ? 20 40 100 4.0 4.05 4.1 4.15 4.2 ? 40 20 80 vlatch (v) temperature ( c) 140 0 60 120 ? 20 40 100 70 75 80 85 90 ? 40 20 80 ibo ( a) temperature ( c) 14 0 0 60 120 ? 20 40 100
NCP1395A/b http://onsemi.com 14 application information the NCP1395A/b includes all necessary features to help build a rugged and safe switch ? mode power supply featuring an extremely low standby power. the below bullets detail the benefits brought by implementing the NCP1395A/b controller: ? wide frequency range: a high ? speed voltage control oscillator allows an output frequency excursion from 50 khz up to 1.0 mhz on a and b outputs. ? adjustable deadtime: due to a single resistor wired to ground, the user has the ability to include some deadtime, helping to fight cross ? conduction between the upper and the lower transistor. ? adjustable soft ? start: every time the controller starts to operate (power on), the switching frequency is pushed to the programmed maximum value and slowly moves down toward the minimum frequency, until the feedback loop closes. the soft ? start sequence is activated in the following cases: a) normal startup b) back to operation from an off state: during hiccup faulty mode, brown ? out or temperature shutdown (tsd). in the NCP1395A, the soft ? start is not activated back to operation from the fast fault input, unless the feedback pin voltage reaches 0.6 v. to the opposite, in the b version, the soft ? start is always activated back from the fast fault input whatever the feedback level is. ? adjustable minimum and maximum frequency excursion: in resonant applications, it is important to stay away from the resonating peak to keep operating the converter in the right region. due to a single external resistor, the designer can program its lowest frequency point, obtained in lack of feedback voltage (during the startup sequence or in short ? circuit conditions). internally trimmed capacitors offer a 3% precision on the selection of the minimum switching frequency. the adjustable upper stop being less precise to 15%. ? low startup current: when directly powered from the high ? voltage dc rail, the device only requires 300 a to startup. in case of an auxiliary supply, the b version offers a lower startup threshold to cope with a 12 v dc rail. ? brown ? out detection: to avoid operation from a low input voltage, it is interesting to prevent the controller from switching if the high ? voltage rail is not within the right boundaries. also, when teamed with a pfc front ? end circuitry, the brown ? out detection can ensure a clean startup sequence with soft ? start, ensuring that the pfc is stabilized before energizing the resonant tank. the a version features a 28 a hysteresis current for the lowest consumption and the b version slightly increases this current to 83 a in order to improve the noise immunity. ? adjustable fault timer duration: when a fault is detected on the slow fault input or when the fb path is broken, a timer starts to charge an external capacitor. if the fault is removed, the timer opens the charging path and nothing happens. when the timer reaches its selected duration (via a capacitor on pin 6), all pulses are stopped. the controller now waits for the discharge via an external resistor of pin 6 capacitor to issue a new clean startup sequence with soft ? start. ? cumulative fault events: in the NCP1395A/b, the timer capacitor is not reset when the fault disappears. it actually integrates the information and cumulates the occurrences. a resistor placed in parallel with the capacitor will offer a simple way to adjust the discharge rate and thus the auto ? recovery retry rate. ? fast and slow fault detection: in some application, subject to heavy load transients, it is interesting to give a certain time to the fault circuit, before activating the protection. on the other hand, some critical faults cannot accept any delay before a corrective action is taken. for this reason, the NCP1395A/b includes a fast fault and a slow fault input. upon assertion, the fast fault immediately stops all pulses and stays in the position as long as the driving signal is high. when released low (the fault has gone), the controller has several choices: in the a version, pulses are back to a level imposed by the feedback pin without soft ? start, but in the b version, pulses are back through a regular soft ? start sequence. ? skip cycle possibility: the absence of soft ? start on the NCP1395A fast fault input offers an easy way to implement skip cycle when power saving features are necessary. a simple resistive connection from the feedback pin to the fast fault input, and skip can be implemented. ? onboard transconductance op amp: a transconductance amplifier is used to implement various options, like monitoring the output current and maintaining it constant. ? broken feedback loop detection: upon startup or any time during operation, if the fb signal is missing, the timer starts to charge a capacitor. if the loop is really broken, the fb level does not grow up before the timer ends counting. the controller then stops all pulses and waits that the timer pin voltage collapses to 1.0 v typically before a new attempt to restart, via the soft ? start. if the optocoupler is permanently broken, a hiccup takes place.
NCP1395A/b http://onsemi.com 15 ? finally, two circuit versions, a and b: the a and b versions differ because of the following changes: 1. the startup thresholds are different, the a starts to pulse for v cc = 12.8 v whereas the b pulses for v cc = 10 v. the turn off levels are the same, however. the a is recommended for consumer products where the designer can use an external startup resistor, whereas the b is more recommended for industrial/medical applications where a 12 v auxiliary supply directly powers the chip. 2. the a version does not activate the soft ? start upon release of the fast fault input. this is to let the designer implement skip cycle. to the opposite, the b version goes back to operation upon the fast fault pin release via a soft ? start sequence. voltage ? controlled oscillator the vco section features a high ? speed circuitry allowing an internal operation from 100 khz up to 2.0 mhz. however, as a division by two internally creates the two q and qbar outputs, the final effective signal on output a and b switches between 50 khz and 1.0 mhz. the vco is configured in such a way that if the feedback pin goes up, the switching frequency also goes up. figure 33 shows the architecture of this oscillator. vref vdd fmin rt ? m sets fmin for v(fb) < vfb_off cint imin + - 0 to i_fmax idt fbinternal max fsw max + - + clk d s q q r ab vref vdd rdt sets the deadtime dt imin vdd fmax rt ? max sets the maximum fsw vcc fb rfb 20 k + - + vfb < vb_fault start fault timer figure 33. simplified vco architecture vb_fault
NCP1395A/b http://onsemi.com 16 the designer needs to program the maximum switching frequency and the minimum switching frequency. in llc configurations, for circuits working above the resonant frequency, a high precision is required on the minimum frequency, hence the 3% specification. this minimum switching frequency is actually reached when no feedback closes the loop. it can happen during the startup sequence, a strong output transient loading or in a short ? circuit condition. by installing a resistor from pin 1 to agnd, the minimum frequency is set. using the same philosophy, wiring a resistor from pin 2 to agnd will set the maximum frequency excursion. to improve the circuit protection features, we have purposely created a dead zone, where the feedback loop has no action. this is typically below 1.3 v. figure 34 details the arrangement where the internal voltage (that drives the vco) varies between 0 and 3.6 v. however, to create this swing, the feedback pin (to which the optocoupler emitter connects), will need to swing typically between 1.3 v and 6.0 v. v cc fb rfb ? + to vco 0 to 3.6 v + 1.3 v vfb = 1.3 ? 6 v figure 34. the opamp arrangement limits the vco internal modulation signal between 0 and 5.0 v. this technique allows us to detect a fault on the converter in case the fb pin cannot rise above 1.3 v (to actually close the loop) in less than a duration imposed by the programmable timer. please refer to the fault section for detailed operation of this mode. as shown in figure 34, the internal dynamics of the vco control voltage will be constrained between 0 v and 3.6 v, whereas the feedback loop will drive pin 5 (fb) between 1.3 v and 6.0 v. if we take the external excursion numbers, 1.3 v = 50 khz, 6.0 v = 1.0 mhz, then the vco slope will then be 1meg ? 50 k 4.7 202 khz v. figures 35 and 36 portray the frequency evolution depending on the feedback pin voltage level in a different frequency clamp combination. vfb f a&b 1.3 v 6 v fmin fmax ? ???? ???? ???? fsw = 950 khz vfb = 4.7v 0.6 v vfb f a&b 1.3 v 6 v fmin fmax ???? ???? ???? fsw = 950 khz vfb = 4.7v 0.6 v figure 35. maximal default excursion, rt = 120 k on pin 1 and rfmax = 35 k on pin 2. vfb 1.3 v 6 v fmin fmax fault area ???? ???? fsw = 300 khz vfb = 4.7 v f a&b 0.6 v ? ? fsw = 300 khz vfb = 4.7 v f a&b 0.6 v figure 36. here a different minimum frequency was programmed as well as a different maximum frequency excursion. please note that the previous small signal vco slope has now been reduced to 300 k/5.0 = 62.5 khz/v. this offers a mean to magnify the feedback excursion on systems where the load range does not generate a wide switching frequency excursion. due to this option, we will see how it becomes possible to observe the feedback level and implement skip cycle at light loads. it is important to note that the frequency evolution does not have a real linear relationship with the feedback voltage. this is due to the deadtime presence which stays constant as the switching period changes.
NCP1395A/b http://onsemi.com 17 the selection of the three setting resistors (fmax, fmin and deadtime) requires the usage of the selection charts displayed below: figure 37. maximum switching frequency resistor selection depending on the adopted minimum switching frequency. 100 300 500 700 900 20 170 320 fmax (khz) rfmax (k ) 120 270 70 220 370 1100 fmin = 200 khz fmin = 50 khz v cc = 11 v fb = 6.5 v dt = 300 ns figure 38. minimum switching frequency resistor selection 40 60 80 100 120 20 80 fmin (khz) rfmin (k ) 60 120 40 100 140 v cc = 11 v fb = 1 v dt = 300 ns 160 180 200 figure 39. dead ? time resistor selection 0 100 200 300 400 500 0 300 600 dt (ns) rdt (k ) 200 500 100 400 600 700 800 900 1000 1100 v cc = 11 v oring capability if for a particular reason, there is a need for having a frequency variation linked to an event appearance (instead of abruptly stopping pulses), then the fb pin lends itself very well to the addition of other sweeping loops. several diodes can easily be used to perform the job in case of reaction to a fault event or to regulate on the output current (cc operation). figure 40 shows how to do it. v cc fb in1 in2 20 k vco figure 40. due to the fb configuration, loop oring is easy to implement.
NCP1395A/b http://onsemi.com 18 deadtime control deadtime control is an absolute necessity when the half ? bridge configuration comes to play. the deadtime technique consists of inserting a period during which both high and low side switches are of f. of course, the deadtime amount differs depending on the switching frequency, hence the ability to adjust it on this controller. the option ranges between 150 ns and 1.0 s. the deadtime is actually made by controlling the oscillator discharge current. figure 41 portrays a simplified vco circuit based on figure 33. vdd icharge: fsw min + fsw max idis ct rdt dt vref + 3 v ? 1 v ? + clk d s q q r ab figure 41. deadtime generation during the discharge time, the clock comparator is high and unvalidates the and gates: both outputs are low. when the comparator goes back to the high level, during the timing capacitor ct recharge time, a and b outputs are validated. by connecting a resistor rdt to ground, it creates a current whose image serves to discharge the ct capacitor: we control the deadtime. the typical range evolves between 150 ns (rdt = 30 k ) and 1.0 s (rdt = 600 k ). figure 44 shows the typical waveforms obtained on the output. soft ? start sequence in resonant controllers, a soft ? start is needed to avoid suddenly applying the full current into the resonating circuit. in this controller, a soft ? start capacitor connects to pin 4 and offers a smooth f requency variation upon startup: when the circuit starts to pulse, the vco is pushed to the maximum switching frequency imposed by pin 2. then, it linearly decreases its frequency toward the minimum frequency selected by a resistor on pin 1. of course, practically, the feedback loop is suppose to take over the vco lead as soon as the output voltage has reached the target. if not, then the minimum switching frequency is reached and a fault is detected on the feedback pin (typically below 600 mv). figure 43 depicts a typical frequency evolution with soft ? start.
NCP1395A/b http://onsemi.com 19 1 ires1 2 vout ? 20.0 ? 10.0 0 10.0 20.0 ires1 in amperes plot1 1 200u 600u 1.00m 1.40m 1.80m time in seconds 169 171 173 175 177 vout in volts plot2 2 ss action ires target is reached vout figure 42. soft ? start behavior figure 43. a typical startup sequence on an llc converter please note that the soft ? start will be activated in the following conditions: ? a startup sequence ? during auto ? recovery burst mode ? a brown ? out recovery ? a temperature shutdown recovery the fast fault input undergoes a special treatment. since we want to implement skip cycle through the fast fault input on the NCP1395A, we cannot activate the soft ? start every time the feedback pin stops the operations in low power mode. therefore, when the fast fault pin is released, no soft ? start occurs to offer the best skip cycle behavior. however, it is very possible to combine skip cycle and true fast fault input, e.g. via oring diodes driving pin 13. in that case, if a signal maintains the fast fault input high long enough to bring the feedback level down (that is to say below 0.6 v) since the output voltage starts to fall down, then the soft ? start is activated after the release of the pin. in the b version tailored to operate from an auxiliary 12 v power supply, the soft ? start is always activated upon the fast fault input release, whatever the feedback condition is.
NCP1395A/b http://onsemi.com 20 1 vct 2 clock 5 difference 0 1.00 2.00 3.00 4.00 vct in volts plot1 1 0 4.00 8.00 12.0 16.0 clock in volts plot2 2 56.2u 65.9u 75.7u 85.4u 95.1u time in seconds ? 8.00 ? 4.00 0 4.00 8.00 difference in volts plot3 5 figure 44. t ypical oscillator waveforms brown ? out protection the brown ? out circuitry (bo) offers a way to protect the resonant converter from low dc input voltages. below a given level, the controller blocks the output pulses, above it, it authorizes them. the internal circuitry, depicted by figure 42, offers a possibility to observe the high ? voltage (hv) rail. a resistive divider made of rupper and rlower, brings a portion of the hv rail on pin 7. below the turn ? on level, a current source ibo is off. therefore, the turn ? on level solely depends on the division ratio brought by the resistive divider. 1 vin 2 vcmp 20.0u 60.0u 100u 140u 180u time in seconds 0 4.00 8.00 12.0 16.0 vcmp in volts 50.0 150 250 350 450 vin in volts plot1 1 2 250 volts 351 volts vin bo figure 45. the internal brown ? out configuration with an offset current source vdd + vbo ? + on/off ibo bo vbulk rupper rlower bo figure 46. simulation results for 350/250 on/off levels
NCP1395A/b http://onsemi.com 21 to the contrary, when the internal bo signal is high (a and b pulse), the ibo source is activated and creates a hysteresis. the hysteresis level actually depends on the circuit: NCP1395A features a 28 a whereas the ncp1395b uses a 83 a current. changes are implemented to a) reduce the standby power on the NCP1395A b) improve the noise immunity on the ncp1395b. knowing these values, it becomes possible to select the turn ? on and turn ? off levels via a few lines of algebra: ibo is off v( ) vbulk1 rlower rlower rupper (eq. 1) ibo is on v( ) vbulk2 rlower rlower rupper ibo rlower rupper rlower rupper (eq. 2) we can now extract rlower from equation 1 and plug it into equation 2, then solve for rupper: rupper rlower vbulk1 ? vbo vbo rlower vbo vbulk1 ? vbulk2 ibo (vbulk1 ? vbo) if we decide to turn on our converter for vbulk1 equals 350 v, and turn it off for vbulk2 equals 250 v, then we obtain: ibo = 28 a rupper = 3.6 m rlower = 10 k the bridge power dissipation is 400 2 /3.601 m = 45 mw when the front ? end pfc stage delivers 400 v. ibo = 83 a rupper = 1.2 m rlower = 3.4 k the bridge power dissipation is 132 mw when the front ? end pfc stage delivers 400 v. figure 46 simulation result confirms our calculations. latch ? off protection there are some situations where the converter shall be fully turned off and stay latched. this can happen in presence of an overvoltage (the feedback loop is drifting) or when an overtemperature is detected. due to the addition of a comparator on the bo pin, a simple external circuit can lift up this pin above vlatch (5.0 v typical) and permanently disable pulses. the v cc needs to be cycled down below 5.0 v typically to reset the controller. ? + 20 s rc to permanent latch + vlatch vdd ? + bo + vbo bo rlower rupper vbulk v cc q1 ntc vout figure 47. adding a comparator on the bo pin offers a way to latch ? off the controller. ibo in figure 47, q1 is blocked and does not bother the bo measurement as long as the ntc and the optocoupler are not activated. as soon as the secondary optocoupler senses an ovp condition, or the ntc reacts to a high ambient temperature, q1 base is brought to ground and the bo pin goes up, permanently latching off the controller.
NCP1395A/b http://onsemi.com 22 protection circuitry this resonant controller differs from competitors due to its protection features. the device can react to various inputs like: ? fast events input: like an overcurrent condition, a need to shutdown (sleep mode) or a way to force a controlled burst mode (skip cycle at low output power): as soon as the input level exceeds 1.0 v typical, pulses are immediately stopped. on the a version, when the input is released, the controller performs a clean startup sequence without soft ? start unless the feedback voltage goes down below 0.6 v during fault time (please see above for details). the b version restarts with a soft ? start sequence. ? slow events input: this input serves as a delayed shutdown, where an event like a transient overload does not immediately stopped pulses but start a timer. if the event duration lasts longer than what the timer imposes, then all pulses are disabled. the voltage on the timer capacitor (pin 3) starts to decrease until it reaches 1.0 v. the decrease rate is actually depending on the resistor the user will put in parallel with the capacitor, giving another flexibility during design. figure 48 depicts the architecture of the fault circuitry. vdd itimer reset uvlo output current image rtimer ctimer ctimer ninv + - on/off 1 = fault 0 = ok + vref fault + - + vtimeron vtimeroff 1 = ok 0 = fault + - vref fault + - + vref out cc regulation compensation slow fault fast fault + 1 = ok 0 = fault driving logic ss a a b b reset to fb fast input figure 48. this circuit combines a slow and fast input for improved protection features
NCP1395A/b http://onsemi.com 23 in this figure, the internal opamp is used to perform a kind of constant current operation (cc) by taking the lead when the other voltage loop is gone (cv). due to the oring capability on the fb pin, the op amp regulates in constant current mode. when the output reaches a low level close to a complete short ? circuit, the opamp output is maximum. with a resistive divider on the slow fault, this condition can be detected to trigger the delayed fault. if no opamp shall be used, its input must be grounded. slow input on this circuit, the slow input goes to a comparator. when this input exceeds 1.0 v typical, the current source itimer turns on, charging the external capacitor ctimer. if the fault duration is long enough, when ctimer voltage reaches the vtimeron level (4.0 v typical), then all pulses are stopped. itimer turns off and the capacitor slowly discharges to ground via a resistor installed in parallel with it. as a result, the designer can easily determine the time during which the power supply stays locked by playing on rtimer. now, when the timer capacitor voltage reaches 1.0 v typical (vtimeroff), the comparator instructs the internal logic to issues pulses as on a clean soft ? start sequence (soft ? start is activated). please note that the discharge resistor cannot be lower than 4.0 v/itimer, otherwise the voltage on ctimer will never reach the turn ? off voltage of 4.0 v. in both cases, when the fault is validated, both outputs a and b are internally pulled down to ground. fast fault fb v cc figure 49. a resistor can easily program the capacitor discharge time. figure 50. skip cycle can be implemented via two resistors on the fb pin to the fast fault input. fast input the fast input is not af fected by a delayed action. as soon as its voltage exceeds 1.0 v typical, all pulses are off and maintained off as long as the fault is present. when the pin is released, pulses come back without soft ? start for the a version, with soft ? start for the b version. due to the low activation level of 1.0 v, this pin can observe the feedback pin via a resistive divided and thus implement skip cycle operation. the resonant converter can be designed to lose regulation in light load conditions, forcing the fb level to increase. when it reaches the programmed level, it triggers the fast fault input and stops pulses. then v out slowly drops, the loop reacts by decreasing the feedback level which, in turn, unlocks the pulses: vout goes up again and so on: we are in skip cycle mode. startup behavior when the v cc voltage grows up, the internal current consumption is kept to istup, allowing to crank up the converter via a resistor connected to the bulk capacitor. when v cc reaches the v cc on level, output a goes high first and then output b. this sequence will always be the same, whatever triggers the pulse delivery: fault, off to on etc pulsing the output a high first gives an immediate charge of the bootstrap capacitor when an integrated high voltage half ? bridge driver is implemented such as on semiconductor?s ncp5181. then, the rest of pulses follow, delivered at the highest switching value, set by the resistor on pin 2. the soft ? start capacitor ensures a smooth frequency decrease to either the programmed minimum value (in case of fault) or to a value corresponding to the operating point if the feedback loop closes first. figure 51 shows typical signals evolution at power on.
NCP1395A/b http://onsemi.com 24 ss t ss fb a b a&b timer fault! 0.6v slopes are similar a b 4v 1v vcc from an auxiliary supply t ss vcc on vcc (min) ss t ss fb a b a&b timer fault! 0.6v slopes are similar a b 4v 1v vcc from an auxiliary supply t ss vcc on vcc (min) figure 51. at power on, output a is first activated and the frequency slowly decreases via the soft ? start capacitor. figure 51 depicts an auto ? recovery situation, where the timer has triggered the end of output pulses. in that case, the v cc level was given by an auxiliary power supply, hence its stability during the hiccup. a similar situation can arise if the user selects a more traditional startup method, with an auxiliary winding. in that case, the vcc (min) comparator stops the output pulses whenever it is activated, that is to say, when v cc falls below 10.3 v typical. at this time, the v cc pin still receives its bias current from the startup resistor and heads toward vcc on via the vcc capacitor. when the voltage reaches vcc on , a standard sequence takes place, involving a soft ? start. figure 52 portrays this behavior.
NCP1395A/b http://onsemi.com 25 vcc on ss t ss fb a b a&b timer fault! 0.6v a b 4v 1v vcc from a startup resistor t ss vcc (min) fault is released vcc on ss t ss fb a b a&b timer fault! 0.6v a b 4v 1v vcc from a startup resistor t ss vcc (min) fault is released figure 52. when the v cc is too low, all pulses are stopped until v cc goes back to the startup voltage. as described in the data sheet, two startup levels vcc on are available, via two circuit versions. the NCP1395A features a large hysteresis to allow a classical startup method with a resistor connected to the bulk capacitor. then, at the end of the startup sequence, an auxiliary winding is supposed to take over the controller supply voltage. to the opposite, for applications where the resonant controller is powered from a standby power supply, the startup level of the ncp1395b of 10 v typically allows a direct a connection from a 12 v source. simple on/off operation is therefore feasible. ordering information device package shipping ? NCP1395Apg pdip ? 16 (pb ? free) 25 units / rail NCP1395Adr2g soic ? 16 (pb ? free) 2500 tape & reel ncp1395bpg pdip ? 16 (pb ? free) 25 units / rail ncp1395bdr2g soic ? 16 (pb ? free) 2500 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d.
NCP1395A/b http://onsemi.com 26 package dimensions pdip ? 16 p suffix case 648 ? 08 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
NCP1395A/b http://onsemi.com 27 soic ? 16 case 751b ? 05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different a pplications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical e xperts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc prod uct could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney f ees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was neglig ent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1395/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc a sales representative

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