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d a t a sh eet product speci?cation supersedes data of 1998 sep 08 2003 apr 14 integrated circuits pcf8578 lcd row/column driver for dot matrix graphic displays
2003 apr 14 2 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 7 functional description 7.1 mixed mode 7.2 row mode 7.3 multiplexed lcd bias generation 7.4 power-on reset 7.5 internal clock 7.6 external clock 7.7 timing generator 7.8 row/column drivers 7.9 display mode controller 7.10 display ram 7.11 data pointer 7.12 subaddress counter 7.13 i 2 c-bus controller 7.14 input filters 7.15 ram access 7.16 display control 7.17 test pin 8i 2 c-bus protocol 8.1 command decoder 9 characteristics of the i 2 c-bus 9.1 bit transfer 9.2 start and stop conditions 9.3 system configuration 9.4 acknowledge 10 limiting values 11 handling 12 dc characteristics 13 ac characteristics 14 application information 15 chip dimensions and bonding pad locations 16 chip-on-glass information 17 package outlines 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 data sheet status 20 definitions 21 disclaimers 22 purchase of philips i 2 c components 2003 apr 14 3 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 1 features single chip lcd controller/driver stand-alone or may be used with up to 32 pcf8579s (40960 dots possible) 40 driver outputs, configurable as 32 8 , 24 16 , 16 24 or 8 32 rows/columns selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32 externally selectable bias configuration, 5 or 6 levels 1280-bit ram for display data storage and scratch pad display memory bank switching auto-incremented data loading across hardware subaddress boundaries (with pcf8579) provides display synchronization for pcf8579 on-chip oscillator, requires only 1 external resistor power-on reset blanks display logic voltage supply range 2.5 to 6 v maximum lcd supply voltage 9 v low power consumption i 2 c-bus interface ttl/cmos compatible compatible with most microcontrollers optimized pinning for single plane wiring in multiple device applications (with pcf8579) space saving 56-lead plastic mini-pack and 64 pin quad flat pack compatible with chip-on-glass technology. 2 applications automotive information systems telecommunication systems point-of-sale terminals computer terminals instrumentation. 3 general description the pcf8578 is a low power cmos lcd row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. the device has 40 outputs, of which 24 are programmable, configurable as 32 8 , 24 16 , 16 24 or 8 32 rows/columns. the pcf8578 can function as a stand-alone lcd controller/driver for use in small systems, or for larger systems can be used in conjunction with up to 32 pcf8579s for which it has been optimized. together these two devices form a general purpose lcd dot matrix driver chip set, capable of driving displays of up to 40960 dots. the pcf8578 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (i 2 c-bus). communication overheads are minimized by a display ram with auto-incremented addressing and display bank switching. 4 ordering information type number package name description version pcf8578t vso56 plastic very small outline package; 56 leads sot190-1 pcf8578u/2 - chip with bumps in tray - pcf8578h lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2 2003 apr 14 4 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 5 block diagram fig.1 block diagram. (1) operates at lcd voltage levels, all other blocks operate at logic levels. the pin numbers given in parenthesis refer to the lqfp64 package. v ss c39 - c32 r31/c31 - r8/c8 r7 - r0 17 - 56 (29 to 35, 37, 38 to 46 48 to 62, 63, 64, 1 to 6) msa842 v dd pcf8578 v lcd v 2 v 3 v 4 v 5 9 (20) 10 (21) 11 (22) 12 (23) 13 (24) 14 (25) 6 (12) output controller row/column drivers (1) display mode controller y decoder and sensing amplifiers 32 x 40-bit display ram x decoder display decoder ram data pointer subaddress counter timing generator i c-bus controller 2 input filters command decoder power-on reset oscillator test 2 (8) 1 (7) scl sda n.c. n.c. sa0 15, 16 (14, 15, 17 to 19 26 to 28 36, 47) 7 (13) (16) 8 (11) 5 (10) 4 (9) 3 r osc osc clk sync yx 2003 apr 14 5 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 6 pinning symbol pin description vso56 lqfp64 sda 1 7 i 2 c-bus serial data input/output scl 2 8 i 2 c-bus serial clock input sync 3 9 cascade synchronization output clk 4 10 external clock input/output v ss 5 11 ground (logic) test 6 12 test pin (connect to v ss ) sa0 7 13 i 2 c-bus slave address input (bit 0) osc 8 16 oscillator input v dd 9 20 positive supply voltage v 2 to v 5 10 to 13 21 to 24 lcd bias voltage inputs v lcd 14 25 lcd supply voltage n.c. 15, 16 14, 15, 17 to 19, 26 to 28, 36, 47 not connected c39 to c32 17 to 24 29 to 35, 37 lcd column driver outputs r31/c31 to r8/c8 25 to 48 38 to 46, 48 to 62 lcd row/column driver outputs r7 to r0 49 to 56 63, 64, 1 to 6 lcd row driver outputs 2003 apr 14 6 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.2 pin configuration (vso56). 1 2 3 4 5 6 7 8 9 10 11 12 13 44 43 42 41 40 39 38 37 36 35 34 33 32 31 14 15 16 17 18 19 20 22 23 24 25 26 21 46 45 47 48 49 50 51 52 53 54 55 56 27 28 30 29 msa839 r27/c27 r26/c26 r25/c25 r24/c24 r23/c23 r22/c22 r21/c21 r20/c20 r19/c19 r18/c18 r17/c17 r16/c16 r15/c15 r14/c14 r13/c13 r12/c12 r11/c11 r10/c10 r9/c9 r8/c8 r7 r6 r5 r4 r3 r2 r1 r0 r28/c28 r29/c29 r30/c30 r31/c31 c32 c33 c34 c35 c36 c37 c38 c39 n.c. n.c. v lcd v 2 v 3 v 4 v 5 v dd osc sa0 test clk sync scl sda v ss pcf8578t 2003 apr 14 7 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.3 pin configuration (lqfp64). handbook, full pagewidth pcf8578h mbh588 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 scl clk test sa0 n.c. n.c. osc v ss sync sda r0 r1 r2 r3 r4 r5 r6 r7 r21/c21 r20/c20 r19/c19 r18/c18 r17/c17 r16/c16 r15/c15 r14/c14 r13/c13 r12/c12 r11/c11 r10/c10 r9/c9 r8/c8 r31/c31 c35 c34 c33 n.c. c32 c39 n.c. n.c. n.c. n.c. n.c. n.c. v lcd v dd v 5 v 4 v 3 v 2 c38 c37 c36 r30/c30 r29/c29 r28/c28 r27/c27 r26/c26 r24/c24 r25/c25 r23/c23 n.c. r22/c22 2003 apr 14 8 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 7 functional description the pcf8578 row/column driver is designed for use in one of three ways: stand-alone row/column driver for small displays (mixed mode) row/column driver with cascaded pcf8579s (mixed mode) row driver with cascaded pcf8579s (mixed mode). 7.1 mixed mode in mixed mode, the device functions as both a row and column driver. it can be used in small stand-alone applications, or for larger displays with up to 15 pcf8579s (31 pcf8579s when two slave addresses are used). see table 1 for common display configurations. 7.2 row mode in row mode, the device functions as a row driver with up to 32 row outputs and provides the clock and synchronization signals for the pcf8579. up to 16 pcf8579s can normally be cascaded (32 when two slave addresses are used). timing signals are derived from the on-chip oscillator, whose frequency is determined by the value of the resistor connected between osc and v ss . commands sent on the i 2 c-bus from the host microcontroller set the mode (row or mixed), configuration (multiplex rate and number of rows and columns) and control the operation of the device. the device may have one of two slave addresses. the only difference between these slave addresses is the least significant bit, which is set by the logic level applied to sa0. the pcf8578 and pcf8579 also have subaddresses. the subaddress of the pcf8578 is only defined in mixed mode and is fixed at 0. the ram may only be accessed in mixed mode and data is loaded as described for the pcf8579. bias levels may be generated by an external potential divider with appropriate decoupling capacitors. for large displays, bias sources with high drive capability should be used. a typical mixed mode system operating with up to 15 pcf8579s is shown in fig.5 (a stand-alone system would be identical but without the pcf8579s). table 1 possible displays con?gurations notes 1. using 15 pcf8579s. 2. using 16 pcf8579s. application multiplex rate mixed mode row mode typical applications rows columns rows columns stand alone 1 : 8 8 32 -- small digital or alphanumerical displays 1:16 16 24 -- 1:24 24 16 -- 1:32 32 8 -- with pcf8579 1 : 8 8 (1) 632 (1) 8 4 (2) 640 (2) alphanumeric displays and dot matrix graphic displays 1:16 16 (1) 624 (1) 16 2 (2) 640 (2) 1:24 24 (1) 616 (1) 24 (2) 640 (2) 1:32 32 (1) 608 (1) 24 (2) 640 (2) 2003 apr 14 9 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 7.3 multiplexed lcd bias generation the bias levels required to produce maximum contrast depend on the multiplex rate and the lcd threshold voltage (v th ). v th is typically defined as the rms voltage at which the lcd exhibits 10% contrast. table 2 shows the optimum voltage bias levels for the pcf8578 as functions of v op (v op =v dd - v lcd ), together with the discrimination ratios (d) for the different multiplex rates. a practical value for v op is obtained by equating v off(rms) with v th . figure 4 shows the first 4 rows of table 2 as graphs. table 3 shows the relative values of the resistors required in the configuration of fig.5 to produce the standard multiplex rates. table 2 optimum lcd voltages table 3 multiplex rates and resistor values for fig.5 7.4 power-on reset at power-on the pcf8578 resets to a defined starting condition as follows: 1. display blank 2. 1 : 32 multiplex rate, row mode 3. start bank, 0 selected 4. data pointer is set to x, y address 0, 0 5. character mode 6. subaddress counter is set to 0 7. i 2 c-bus interface is initialized. data transfers on the i 2 c-bus should be avoided for 1 ms following power-on, to allow completion of the reset action. parameter multiplex rate 1:8 1:16 1:24 1:32 0.739 0.800 0.830 0.850 0.522 0.600 0.661 0.700 0.478 0.400 0.339 0.300 0.261 0.200 0.170 0.150 0.297 0.245 0.214 0.193 0.430 0.316 0.263 0.230 1.447 1.291 1.230 1.196 3.370 4.080 4.680 5.190 resistors multiplex rate (n) n = 8 n = 16, 24, 32 r1 r r r2 r r3 v 2 v op --------- v 3 v op --------- v 4 v op --------- v 5 v op --------- v off rms () v op --------------------- - v on rms () v op --------------------- d v on rms () v off rms () --------------------- - = v op v th --------- n2 C () r 3n C () r n3 C () r fig.4 v bias /v op as a function of the multiplex rate. 1:8 1:16 1:32 1.0 0 0.8 msa838 1:24 0.6 0.4 0.2 multiplex rate v bias v op v 5 v 4 v 3 v 2 v bias =v 2 , v 3 , v 4 , v 5 . see table 2. 2003 apr 14 10 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... r osc osc v ss sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss pcf8579 40 columns scl v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd pcf8578 v lcd v dd v 2 v 5 v ss v dd / v ss lcd display v dd r1 c r2 c r3 c r2 c r1 c v ss v dd / v lcd subaddress 1 v ss v dd / 40 n columns n rows host microcontroller scl sda msa843 fig.5 typical mixed mode configuration. 2003 apr 14 11 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.6 lcd row/column waveforms. msa841 v dd v 2 v v v v 3 4 5 lcd t frame column sync v dd v 2 v v v v 3 4 5 lcd row 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sync v dd v 2 v v v v 3 4 5 lcd column v dd v 2 v v v v 3 4 5 lcd row 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sync v dd v 2 v v v v 3 4 5 lcd column v dd v 2 v v v v 3 4 5 lcd row 0 15 sync 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 v dd v 2 v v v v 3 4 5 lcd column v dd v 2 v v v v 3 4 5 lcd row 0 0 1 2 3 4 5 67 on off 1:8 1:16 1:24 1:32 column display 2003 apr 14 12 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.7 lcd drive mode waveforms for 1 : 8 multiplex rate. msa840 v dd v 2 v v v v 3 4 5 lcd t frame row 1 r1 (t) v dd v 2 v v v v 3 4 5 lcd row 2 r2 (t) v dd v 2 v v v v 3 4 5 lcd col 1 c1 (t) v dd v 2 v v v v 3 4 5 lcd col 2 c2 (t) dot matrix 1:8 multiplex rate 0.261 v op 0.261 v op 0 v v op v op v state 1 (t) v state 2 (t) 0.261 v op 0.261 v op 0 v v op v op 0.478 v op 0.478 v op state 1 (off) state 2 (on) v state 1 (t) = c1(t) r1(t): v on(rms) v op = 1 8 8 1 8 1 () 8 = 0.430 v state 2 (t) = c2(t) r2(t): v off(rms) v op = 8 1 8 1 () 8 = 0.297 2 2 () general relationship (n = multiplex rate) v on(rms) v op = 1 n n 1 n 1 () n v off(rms) v op = n 1 n 1 () n 2 2 () 2003 apr 14 13 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.8 lcd drive mode waveforms for 1 : 16 multiplex rate. msa836 v dd v 2 v v v v 3 4 5 lcd t frame row 1 r1 (t) v dd v 2 v v v v 3 4 5 lcd row 2 r2 (t) v dd v 2 v v v v 3 4 5 lcd col 1 c1 (t) v dd v 2 v v v v 3 4 5 lcd col 2 c2 (t) dot matrix 1:16 multiplex rate state 1 (off) state 2 (on) 0.2 v op 0.2 v op 0 v v op v op v state 1 (t) 0.2 v op 0.2 v op 0 v v op v op v state 2 (t) 0.6 v op 0.6 v op v state 1 (t) = c1(t) r1(t): v on(rms) v op = 1 16 16 1 16 1 () 16 = 0.316 v state 2 (t) = c2(t) r2(t): v off(rms) v op = 16 1 16 1 () 16 = 0.254 2 2 () general relationship (n = multiplex rate) v on(rms) v op = 1 n n 1 n 1 () n v off(rms) v op = n 1 n 1 () n 2 2 () 2003 apr 14 14 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 7.5 internal clock the clock signal for the system may be generated by the internal oscillator and prescaler. the frequency is determined by the value of the resistor r osc , see fig.9. for normal use a value of 330 k w is recommended. the clock signal, for cascaded pcf8579s, is output at clk and has a frequency 1 6 (multiplex rate 1 : 8, 1 : 16 and 1 : 32) or 1 8 (multiplex rate 1 : 24) of the oscillator frequency. fig.9 oscillator frequency as a function of external oscillator resistor, r osc . to avoid capacitive coupling, which could adversely affect oscillator stability, r osc should be placed as closely as possible to the osc pin. if this proves to be a problem, a filtering capacitor may be connected in parallel to r osc . 10 msa837 10 2 10 3 10 4 1 10 3 10 10 2 f osc (khz) r(k w ) osc 7.6 external clock if an external clock is used, osc must be connected to v dd and the external clock signal to clk. table 4 summarizes the nominal clk and sync frequencies. 7.7 timing generator the timing generator of the pcf8578 organizes the internal data flow of the device and generates the lcd frame synchronization pulse sync, whose period is an integer multiple of the clock period. in cascaded applications, this signal maintains the correct timing relationship between the pcf8578 and pcf8579s in the system. 7.8 row/column drivers outputs r0 to r7 and c32 to c39 are fixed as row and column drivers respectively. the remaining 24 outputs r8/c8 to r31/c31 are programmable and may be configured (in blocks of 8) to be either row or column drivers. the row select signal is produced sequentially at each output from r0 up to the number defined by the multiplex rate (see table 1). in mixed mode the remaining outputs are configured as columns. in row mode all programmable outputs (r8/c8 to r31/c31) are defined as row drivers and the outputs c32 to c39 should be left open-circuit. using a 1 : 16 multiplex rate, two sets of row outputs are driven, thus facilitating split-screen configurations, i.e. a row select pulse appears simultaneously at r0 and r16/c16, r1 and r17/c17 etc. similarly, using a multiplex rate of 1 : 8, four sets of row outputs are driven simultaneously. driver outputs must be connected directly to the lcd. unused outputs should be left open-circuit. in 1 : 8 r0 to r7 are rows; in 1 : 16 r0 to r15/c15 are rows; in 1 : 24 r0 to r23/c23 are rows; in 1 : 32 r0 to r31/c31 are rows. table 4 signal frequencies required for nominal 64 hz frame frequency; note 1. notes 1. a clock signal must always be present, otherwise the lcd may be frozen in a dc state. 2. r osc = 330 k w . oscillator frequency f osc (2) (hz) frame frequency f sync (hz) multiplex rate (n) division ratio clock frequency f clk (hz) 12288 64 1 : 8, 1 : 16, 1 : 32 6 2048 12288 64 1 : 24 8 1536 2003 apr 14 15 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 7.9 display mode controller the configuration of the outputs (row or column) and the selection of the appropriate driver waveforms are controlled by the display mode controller. 7.10 display ram the pcf8578 contains a 32 40-bit static ram which stores the display data. the ram is divided into 4 banks of 40 bytes (4 8 40 bits). during ram access, data is transferred to/from the ram via the i 2 c-bus. the first eight columns of data (0 to 7) cannot be displayed but are available for general data storage and provide compatibility with the pcf8579. there is a direct correspondence between x-address and column output number. 7.11 data pointer the addressing mechanism for the display ram is realized using the data pointer. this allows an individual data byte or a series of data bytes to be written into, or read from, the display ram, controlled by commands sent on the i 2 c-bus. 7.12 subaddress counter the storage and retrieval of display data is dependent on the content of the subaddress counter. storage takes place only when the contents of the subaddress counter agree with the hardware subaddress. the hardware subaddress of the pcf8578, valid in mixed mode only, is fixed at 0000. 7.13 i 2 c-bus controller the i 2 c-bus controller detects the i 2 c-bus protocol, slave address, commands and display data bytes. it performs the conversion of the data input (serial-to-parallel) and the data output (parallel-to-serial). the pcf8578 acts as an i 2 c-bus slave transmitter/receiver in mixed mode, and as a slave receiver in row mode. a slave device cannot control bus communication. 7.14 input ?lters to enhance noise immunity in electrically adverse environments, rc low-pass filters are provided on the sda and scl lines. 7.15 ram access ram operations are only possible when the pcf8578 is in mixed mode. in this event its hardware subaddress is internally fixed at 0000 and the hardware subaddresses of any pcf8579 used in conjunction with the pcf8578 must start at 0001. there are three ram access modes: character half-graphic full-graphic. these modes are specified by bits g1 to g0 of the ram access command. the ram access command controls the order in which data is written to or read from the ram (see fig.10). to store ram data, the user specifies the location into which the first byte will be loaded (see fig.11): device subaddress (specified by the device select command) ram x-address (specified by the load x-address command) ram bank (specified by bits y1 and y0 of the ram access command). subsequent data bytes will be written or read according to the chosen ram access mode. device subaddresses are automatically incremented between devices until the last device is reached. if the last device has subaddress 15, further display data transfers will lead to a wrap-around of the subaddress to 0. 7.16 display control the display is generated by continuously shifting rows of ram data to the dot matrix lcd via the column outputs. the number of rows scanned depends on the multiplex rate set by bits m1 and m0 of the set mode command. the display status (all dots on/off and normal/inverse video) is set by bits e1 and e0 of the set mode command. for bank switching, the ram bank corresponding to the top of the display is set by bits b1 and b0 of the set start bank command. this is shown in fig.12. this feature is useful when scrolling in alphanumeric applications. 7.17 test pin the test pin must be connected to v ss . 2003 apr 14 16 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... msa849 01234567891011 0 246810121416182022 1357911131517192123 0 4 8 12 16 20 24 28 32 36 40 44 1 5 9 13 17 21 25 29 33 37 41 45 2 6 10 14 18 22 26 30 34 38 42 46 3 7 11 15 19 23 27 31 35 39 43 47 ram data bytes are written or read as indicated above full-graphic mode lsb msb bank 0 bank 1 bank 2 bank 3 pcf8578/pcf8579 system ram 1 k 16 half-graphic mode character mode 1 byte 4 bytes ram 2 bytes 4 bytes 40-bits driver 1 driver 2 driver k pcf8578/pcf8579 pcf8579 fig.10 ram access mode. 2003 apr 14 17 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... msa835 s a 0 s 011110 0a slave address / rw 0 110110 a device select 1 0 000100 a load x-address 1 1 111000 a ram access 0 last command s a 0 s 011110 1a slave address / rw data a read write data a data a device select: subaddress 12 ram access: character mode bank 1 load x-address: x-address = 8 ram bank 0 bank 1 bank 2 bank 3 fig.11 example of commands specifying initial data byte ram locations. 2003 apr 14 18 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.12 relationship between display and set start bank; 1 : 32 multiplex rate and start bank = 2. msa851 bank 0 top of lcd bank 1 bank 2 bank 3 lcd ram 2003 apr 14 19 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 8i 2 c-bus protocol two 7-bit slave addresses (0111100 and 0111101) are reserved for both the pcf8578 and pcf8579. the least significant bit of the slave address is set by connecting input sa0 to either 0 (v ss )or1(v dd ). therefore, two types of pcf8578 or pcf8579 can be distinguished on the same i 2 c-bus which allows: 1. one pcf8578 to operate with up to 32 pcf8579s on the same i 2 c-bus for very large applications 2. the use of two types of lcd multiplex schemes on the same i 2 c-bus. in most applications the pcf8578 will have the same slave address as the pcf8579. the i 2 c-bus protocol is shown in fig.13. all communications are initiated with a start condition (s) from the i 2 c-bus master, which is followed by the desired slave address and read/write bit. all devices with this slave address acknowledge in parallel. all other devices ignore the bus transfer. in write mode (indicated by setting the read/write bit low) one or more commands follow the slave address acknowledgement. the commands are also acknowledged by all addressed devices on the bus. the last command must clear the continuation bit c. after the last command a series of data bytes may follow. the acknowledgement after each byte is made only by the (a0, a1, a2 and a3) addressed pcf8579 or pcf8578 with its implicit subaddress 0. after the last data byte has been acknowledged, the i 2 c-bus master issues a stop condition (p). in read mode, indicated by setting the read/write bit high, data bytes may be read from the ram following the slave address acknowledgement. after this acknowledgement the master transmitter becomes a master receiver and the pcf8578 becomes a slave transmitter. the master receiver must acknowledge the reception of each byte in turn. the master receiver must signal an end of data to the slave transmitter, by not generating an acknowledge on the last byte clocked out of the slave. the slave transmitter then leaves the data line high, enabling the master to generate a stop condition (p). display bytes are written into, or read from, the ram at the address specified by the data pointer and subaddress counter. both the data pointer and subaddress counter are automatically incremented, enabling a stream of data to be transferred either to, or from, the intended devices. in multiple device applications, the hardware subaddress pins of the pcf8579s (a0 to a3) are connected to v ss or v dd to represent the desired hardware subaddress code. if two or more devices share the same slave address, then each device must be allocated a unique hardware subaddress. 2003 apr 14 20 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.13 (a) master transmits to slave receiver (write mode); (b) master reads after sending command string (write commands; read data); (c) master reads slave immediately after sending slave address (read mode). msa830 s a 0 s 011110 0ac command a p a display data slave address / rw acknowledge by all addressed pcf8578s / pcf8579s acknowledge by a0, a1, a2 and a3 selected pcf8578s / pcf8579s only n 0 byte(s) n 0 byte(s) 1 byte update data pointers and if necessary, subaddress counter (a) msa832 s a 0 s 011110 0ac command a slave address / rw acknowledge by all addressed pcf8578s / pcf8579s n 1 byte (b) a data s a 0 s 011110 1a slave address / rw p 1 data n bytes last byte update data pointers and if necessary subaddress counter acknowledge from master no acknowledge from master at this moment master transmitter becomes a master receiver and pcf8578/pcf8579 slave receiver becomes a slave transmitter msa831 s a 0 s 011110 1a data a p 1 data slave address / rw acknowledge by all addressed pcf8578s / pcf8579s last byte n bytes update data pointers and if necessary, subaddress counter (c) acknowledge from master no acknowledge from master 2003 apr 14 21 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 8.1 command decoder the command decoder identifies command bytes that arrive on the i 2 c-bus. the most-significant bit of a command is the continuation bit c (see fig.14). when this bit is set, it indicates that the next byte to be transferred will also be a command. if the bit is reset, it indicates the conclusion of the command transfer. further bytes will be regarded as display data. commands are transferred in write mode only. the five commands available to the pcf8578 are defined in tables 5 and 6. fig.14 general information of command byte. msa833 rest of opcode c msb lsb c = 0; last command. c = 1; commands continue. table 5 summary of commands note 1. c = command continuation bit. d = may be a logic 1 or 0. command opcode (1) description set mode c 1 0 d d d d d multiplex rate, display status, system type set start bank c 1 1 1 1 1 d d de?nes bank at top of lcd device select c 1 1 0 d d d d de?nes device subaddress ram access c 1 1 1 d d d d graphic mode, bank select (d d d d 3 12 is not allowed; see set start bank opcode) load x-address c 0 d d d d d d 0 to 39 2003 apr 14 22 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 table 6 de?nition of pcf8578/pcf8579 commands command opcode options description set mode c 1 0 t e1 e0 m1 m0 see table 7 de?nes lcd drive mode see table 8 de?nes display status see table 9 de?nes system type set start bank c 1 1 1 1 1 b1 b0 see table 10 de?nes pointer to ram bank corresponding to the top of the lcd; useful for scrolling, pseudo-motion and background preparation of new display device select c 1 1 0 a3 a2 a1 a0 see table 11 four bits of immediate data, bits a0 to a3, are transferred to the subaddress counter to de?ne one of sixteen hardware subaddresses ram access c 1 1 1 g1 g0 y1 y0 see table 12 de?nes the auto-increment behaviour of the address for ram access see table 13 two bits of immediate data, bits y0 to y1, are transferred to the x-address pointer to de?ne one of forty display ram columns load x-address c 0 x5 x4 x3 x2 x1 x0 see table 14 six bits of immediate data, bits x0 to x5, are transferred to the x-address pointer to de?ne one of forty display ram columns 2003 apr 14 23 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 table 7 set mode option 1 table 8 set mode option 2 table 9 set mode option 3 table 10 set start bank option 1 lcd drive mode bits m1 m0 1 : 8 mux (8 rows) 0 1 1 : 16 mux (16 rows) 1 0 1 : 24 mux (24 rows) 1 1 1 : 32 mux (32 rows) 0 0 display status bits e1 e0 blank 0 0 normal 0 1 all segments on 1 0 inverse video 1 1 system type bit t pcf8578 row only 0 pcf8578 mixed mode 1 start bank pointer bits b1 b0 bank 0 0 0 bank 1 0 1 bank 2 1 0 bank 3 1 1 table 11 device select option 1 table 12 ram access option 1 note 1. see opcode for set start bank in table 6. table 13 device select option 1 table 14 device select option 1 description bits decimal value 0 to 15 a3 a2 a1 a0 ram access mode bits g1 g0 character 0 0 half-graphic 0 1 full-graphic 1 0 not allowed (note 1) 1 1 description bits decimal value 0 to 3 y1 y0 description bits decimal value 0 to 39 x5 x4 x3 x2 x1 x0 2003 apr 14 24 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 9 characteristics of the i 2 c-bus the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl) which must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this moment will be interpreted as control signals. 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as the start condition (s). a low-to-high transition of the data line while the clock is high, is defined as the stop condition (p). 9.3 system con?guration a device transmitting a message is a 'transmitter', a device receiving a message is the 'receiver'. the device that controls the message flow is the 'master' and the devices which are controlled by the master are the 'slaves'. 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. each data byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal the end of a data transmission to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. fig.15 bit transfer. mba607 data line stable; data valid change of data allowed sda scl 2003 apr 14 25 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.16 definition of start and stop condition. mba608 sda scl p stop condition sda scl s start condition fig.17 system configuration. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl fig.18 acknowledgement on the i 2 c-bus. the general characteristics and detailed specification of the i 2 c-bus are available on request. handbook, full pagewidth mba606 - 1 start condition s scl from master data output by transmitter data output by receiver clock pulse for acknowledgement 1 2 8 9 2003 apr 14 26 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 10 limiting values in accordance with the absolute maximum rating system (iec 60134). 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter min. max. unit v dd supply voltage - 0.5 + 8.0 v v lcd lcd supply voltage v dd - 11 v dd v v i1 input voltage sda, scl, clk, test, sa0 and osc v ss - 0.5 v dd + 0.5 v v i2 input voltage v 2 to v 5 v lcd - 0.5 v dd + 0.5 v v o1 output voltage sync and clk v ss - 0.5 v dd + 0.5 v v o2 output voltage r0 to r7, r8/c8 to r31/c31 and c32 to c39 v lcd - 0.5 v dd + 0.5 v i i dc input current - 10 + 10 ma i o dc output current - 10 + 10 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 + 50 ma p tot total power dissipation per package - 400 mw p o power dissipation per output - 100 mw t stg storage temperature - 65 + 150 c 2003 apr 14 27 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 12 dc characteristics v dd = 2.5 to 6 v; v ss =0v;v lcd =v dd - 3.5 v to v dd - 9v;t amb = - 40 to + 85 c; unless otherwise speci?ed. notes 1. outputs are open; inputs at v dd or v ss ; i 2 c-bus inactive; external clock with 50% duty factor. 2. resets all logic when v dd 2003 apr 14 29 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 fig.20 driver timing waveforms. msa834 0.7 v dd 0.3 v dd 1/ f clk t psync 0.7 v dd 0.3 v dd sync clk 0.5 v 0.5 v t plcd c39 to c32, r31/c31 to r8/c8 and r7 to r0 (v v = 9 v) dd lcd t psync fig.21 i 2 c-bus timing waveforms. handbook, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat 2003 apr 14 30 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 14 application information osc sda sa0 clk sync v lcd scl v ss v 3 v 4 v dd pcf8578 v 2 v 5 lcd display msa844 r7 r8/ c8 r9/ c9 r10/ c10 r11/ c11 r12/ c12 r13/ c13 r14/ c14 r15/ c15 r16/ c16 r17/ c17 r18/ c18 r19/ c19 r20/ c20 r21/ c21 r22/ c22 r23/ c23 r24/ c24 r25/ c25 r26/ c26 r6 r5 r4 r3 r2 r1 r0 r27/ c27 c32 r31/ c31 r30/ c30 r29/ c29 r28/ c28 c33 c34 c35 c36 c37 c38 c39 n.c. n.c. test osc r fig.22 stand-alone application using 8 rows and 32 columns. 2003 apr 14 31 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... fig.23 segment driver application for up to 384 segments. (1) can be used for creating blinking characters. 0 16 17 39 0 1 2 3 r8 r15 lcd display ram pcf8578 bank (using 1:16 mux, the first character data must be loaded in bank 0 and 1 starting at byte number 16) one line of 24 digits 7 segment one line of 12 digits star-burst (mux 1:16) total: 384 segments pcf8578: segment driver application r0 r7 a b c d e f g dp a b f g c e d dp 1-byte lsb msb 1 12 mlb423 (1) c16 c17 c39 alternate display bank alternate display bank free ram 2003 apr 14 32 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... r osc osc v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 1 40 columns subaddress 0 v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd pcf8578 (row mode) v lcd v dd v 2 v 5 v ss unused columns 8 scl sda v dd v ss 32 rows r r r r c c c c c v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 2 40 columns subaddress 1 v dd v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 k 40 columns v dd subaddress k 1 1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.) lcd display v dd (4 2 3)r v ss msa845 fig.24 typical lcd driver system with 1 : 32 multiplex rate. 2003 apr 14 33 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... r osc osc v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 1 40 columns subaddress 0 v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd pcf8578 (row mode) v lcd v dd v 2 v 5 v ss v dd / v ss unused columns 16 8 rows scl sda v dd v ss 1:16 multiplex rate 16 x 40 x k dots (k 16) (10240 dots max.) 16 rows r r r r r c c c c c v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 1 40 columns subaddress 0 v dd v ss v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 40 columns v dd v ss subaddress k 1 k v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 2 40 columns subaddress 1 v dd v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 k 40 columns v dd subaddress k 1 1:16 multiplex rate 16 x 40 x k dots (k 16) (10240 dots max.) lcd display v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 2 40 columns subaddress 1 v dd v ss v dd msa847 fig.25 split screen application with 1 : 16 multiplex rate for improved contrast. 2003 apr 14 34 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... r osc osc v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 1 40 columns subaddress 0 v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd pcf8578 (row mode) v lcd v dd v 2 v 5 v ss v dd / v ss unused columns 8 scl sda v dd v ss 1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.) 32 rows r r r r c c c c c v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 1 40 columns subaddress 0 v dd v ss v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 40 columns v dd v ss subaddress k 1 k v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 2 40 columns subaddress 1 v dd v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v ss v ss pcf8579 k 40 columns v dd subaddress k 1 1:32 multiplex rate 32 x 40 x k dots (k 16) (20480 dots max.) lcd display v ss scl sda sa0 clk sync v 3 v 4 v dd v lcd a0 a1 a2 a3 v dd pcf8579 2 40 columns subaddress 1 v dd v ss v dd 32 (4 2 3)r msa846 fig.26 split screen application with 1 : 32 multiplex rate. 2003 apr 14 35 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... sda v lcd scl v ss v dd pcf8578 lcd display msa852 osc r n.c. n.c. r31/c31 r0 r r r r (4 2 3)r n.c. c0 c27 c28 c39 pcf8579 n.c. c0 c27 c28 c39 pcf8579 to other pcf8579s fig.27 example of single plane wiring, single screen with 1 : 32 multiplex rate (pcf8578 in row driver mode). 2003 apr 14 36 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 15 chip dimensions and bonding pad locations fig.28 bonding pad locations. chip area: 14.93 mm 2 . bonding pad dimensions: 120 m m 120 m m. the numbers given in the small squares refer to the pad numbers. mbh589 v dd v ss sda 4.88 mm 3.06 mm v lcd v 2 osc sa0 test clk scl v 3 v 4 v 5 c39 c38 c37 c36 c35 c34 c33 c32 r31/c31 r30/c30 r29/c29 r28/c28 r27/c27 r26/c26 r25/c25 r24/c24 r23/c23 r0 r1 r2 r3 r4 r5 54 sync r6 r7 r8/c8 r9/c9 r10/c10 r11/c11 r12/c12 r13/c13 r14/c14 r15/c15 r16/c16 r17/c17 r18/c18 r19/c19 r20/c20 r21/c21 r22/c22 x pcf8578 y 0 0 1 2 3 4 5 6 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 2003 apr 14 37 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 table 15 bonding pad locations (dimensions in m m); all x/y coordinates are referenced to centre of chip, see fig.28 pad number symbol x y pins vso56 lqfp64 1 sda 174 2241 1 7 2 scl - 30 2241 2 8 3 sync - 234 2241 3 9 4 clk - 468 2241 4 10 5v ss - 726 2241 5 11 6 test - 1014 2241 6 12 7 sa0 - 1308 2241 7 13 8 osc - 1308 1917 8 16 9v dd - 1308 1113 9 20 10 v 2 - 1308 873 10 21 11 v 3 - 1308 663 11 22 12 v 4 - 1308 459 12 23 13 v 5 - 1308 255 13 24 14 v lcd - 1308 51 14 25 15 c39 - 1308 - 1149 17 29 16 c38 - 1308 - 1353 18 30 17 c37 - 1308 - 1557 19 31 18 c36 - 1308 - 1773 20 32 19 c35 - 1308 - 1995 21 33 20 c34 - 1308 - 2241 22 34 21 c33 - 1014 - 2241 23 35 22 c32 - 726 - 2241 24 37 23 r31/c31 - 468 - 2241 25 38 24 r30/c30 - 234 - 2241 26 39 25 r29/c29 - 30 - 2241 27 40 26 r28/c28 174 - 2241 28 41 27 r27/c27 468 - 2241 29 42 28 r26/c26 672 - 2241 30 43 29 r25/c25 876 - 2241 31 44 30 r24/c24 1080 - 2241 32 45 31 r23/c23 1308 - 2241 33 46 32 r22/c22 1308 - 1977 34 48 33 r21/c21 1308 - 1731 35 49 34 r20/c20 1308 - 1515 36 50 35 r19/c19 1308 - 1305 37 51 36 r18/c18 1308 - 1101 38 52 37 r17/c17 1308 - 897 39 53 38 r16/c16 1308 - 693 40 54 2003 apr 14 38 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 39 r15/c15 1308 - 489 41 55 40 r14/c14 1308 - 285 42 56 41 r13/c13 1308 - 81 43 57 42 r12/c12 1308 123 44 58 43 r11/c11 1308 351 45 59 44 r10/c10 1308 603 46 60 45 r9/c9 1308 1101 47 61 46 r8/c8 1308 1305 48 62 47 r7 1308 1515 49 63 48 r6 1308 1731 50 64 49 r5 1308 1977 51 1 50 r4 1308 2241 52 2 51 r3 1080 2241 53 3 52 r2 876 2241 54 4 53 r1 672 2241 55 5 54 r0 468 2241 56 6 - n.c. -- 15, 16 14, 15, 17 to 19, 26 to 28, 36, 47 pad number symbol x y pins vso56 lqfp64 2003 apr 14 39 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 16 chip-on-glass information msa850 v dd pcf8578 v lcd v 3 v 4 pcf8579 c39 c38 c37 v dd v lcd n.c. a2 a3 v 3 v 4 a1 a0 v ss test sa0 clk scl sda c0 c1 sync v dd v lcd v 4 v 5 v 3 v 2 sa0 osc c39 c38 v ss test clk scl sda r0 sync r osc r1 r2 r0 to r31 sync scl sda v ss clk v lcd v 3 v 4 sync scl sda v ss clk c0 c1 c2 lcd display v dd fig.29 typical chip-on-glass application (viewed from the underside of the chip). if inputs sa0 and a0 to a3 are left unconnected they are internally pulled to v dd . 2003 apr 14 40 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 17 package outlines unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 0.3 0.1 3.0 2.8 0.25 0.42 0.30 0.22 0.14 21.65 21.35 11.1 11.0 0.75 15.8 15.2 1.45 1.30 0.90 0.55 7 0 o o 0.1 0.1 dimensions (inch dimensions are derived from the original mm dimensions) 1.6 1.4 sot190-1 97-08-11 03-02-19 w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a x (a ) 3 a y 56 29 28 1 pin 1 index 0.012 0.004 0.12 0.11 0.017 0.012 0.0087 0.0055 0.85 0.84 0.44 0.43 0.0295 2.25 0.089 0.62 0.60 0.057 0.051 0.035 0.022 0.004 0.2 0.008 0.004 0.063 0.055 0.01 0 5 10 mm scale vso56: plastic very small outline package; 56 leads sot190-1 a max. 3.3 0.13 notes 1. plastic or metal protrusions of 0.3 mm (0.012 inch) maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm (0.01 inch) maximum per side are not included. 2003 apr 14 41 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2 2003 apr 14 42 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferably be kept: below 220 c for all the bga packages and packages with a thickness 3 2.5mm and packages with a thickness <2.5 mm and a volume 3 350 mm 3 so called thick/large packages below 235 c for packages with a thickness <2.5 mm and a volume <350 mm 3 so called small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2003 apr 14 43 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable 2003 apr 14 44 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 19 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 apr 14 45 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 22 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2003 apr 14 46 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 notes 2003 apr 14 47 philips semiconductors product speci?cation lcd row/column driver for dot matrix graphic displays pcf8578 notes ? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403512/05/pp 48 date of release: 2003 apr 14 document order number: 9397 750 11026 |
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