1 of 2:10 differential clock/data fanout buffe r fastedge? series cy2dp3110 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07469 rev. *i revised august 18, 2005 features ? ten ecl/pecl differential outputs ? one ecl/pecl differential or single-ended inputs (clka) ? one hstl differential or single-ended inputs (clkb) ? hot-swappable/-insertable ? 29 ps typical outp ut-to-output skew ? 95 ps typical part-to-part skew ? 400 ps typical propagation delay ? 0.1 ps typical rms phase jitter ? 1.5 ghz operation (2.7 ghz maximum toggle frequency) ? pecl and hstl mode supply range: v cc = 2.5v 5% to 3.3v5% with v ee = 0v ? ecl mode supply range: v e e = ?2.5v 5% to ?3.3v5% with v cc = 0v ? industrial temperature range: ?40c to 85c ? 32-pin tqfp package ? temperature compensation like 100k ecl ? pin-compatible with mc100es6111 functional description the cy2dp3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. the device is implemented on sige technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 ghz. the device features two differential input paths that are multi- plexed internally. this mux is controlled by the clk_sel pin. the cy2dp3110 may function not only as a differential clock buffer but also as a signal-level translator and fanout on hstl single-ended signal to 10 ecl/pecl differential loads. an ex- ternal bias pin, vbb, is provided for this purpose. in such an application, the vbb pin should be connected to either one of the clka# or clkb# inputs and bypassed to ground via a 0.01- f capacitor. traditionally, in ecl, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point. since the cy2dp3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in com- munication systems. furthermore, advanced circuit design schemes, such as internal te mperature compens ation, ensure that the cy2dp3110 delivers consistent performance over various platforms block diagram pin configuration vbb vee vee vcc clka clka# clkb clkb# clk_sel vee vcc q0 q0# q1 q1# q2 q2# q3 q3# q4 q4# q5 q5# q6 q6# q8 q8# q9 q9# q7 q7# v bb cy2dp3110 vcc q0 q0# q1 q1# q2 q2# vcc vcc q9# q9 q8# q8 q7# q7 vcc q3 q3# q4 q4# q5 q5# q6 q6# vcc clk_sel clka clka# vbb clkb clkb# vee 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 2 of 10 governing agencies the following agencies provide specifications that apply to the cy2dp3110. the agency name and relevant specification is listed below in ta ble 2 . pin definitions [1, 2, 3] pin name i/o type description 2 clk_sel i,pd ecl/pecl input clock select. 3 clka i,pd [1] ecl/pecl differential input clocks . 4 clka# i,pd/pu ecl/pecl differential input clocks . 5vbbobias reference voltage output. 6 clkb, i,pd hstl alternate differential input clocks . 7 clkb# i,pd/pu hstl alternate differential input clocks . 8vee?pwrpower negative power supply. 1,9,16, 25,32 vcc +pwr power positive power supply. 31,29,27,24,22,20,18, 15,13,11 q(0:9) o ecl/pecl ecl/pecl differential output clocks . 30,28,26,23,21,19,17, 14,12,10 q#(0:9) o ecl/pecl ecl/pecl differential output clocks . table 1. control operation clk_sel 0 clka, clka# input pair is active (default condition with no connection to pin) clka can be driven with ecl- or pecl-compatibl e signals with respective power configurations 1 clkb, clkb# input pair is active. clkb can be driven with hstl compatible si gnals with respective power configurations table 2. agency name specification jedec jesd 020b (msl) jesd 8-6 (hstl) jesd 51 (theta ja) jesd 8?2 (ecl) jesd 65?b (skew,jitter) mil-spec 883e method 1012.1 (thermal theta jc) notes: 1. in the i/o column, the following notation is used: i for input, o for output, pd for pull-down, pu for pull-up, and pwr for p ower. 2. in ecl mode (negative power supply mode), v ee is either ?3.3v or ?2.5v and v cc is connected to gnd (0v). in pecl mode (positive power supply mode), v ee is connected to gnd (0v) and v cc is either +3.3v or +2.5v. in both modes, the input and output levels are referenced to the most positive supply (v cc ) and are between v cc and v ee . 3. v bb is available for use for single-ended bias mode for |3.3v| supplies (not |2.5v|).
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 3 of 10 absolute maximum ratings parameter description condition min. max. unit v cc positive supply voltage non-functional ?0.3 4.6 v v ee negative supply voltage non-functional -4.6 0.3 v t s temperature, storage non-functional ?65 +150 c t j temperature, junction non-functional 150 c esd h esd protection human body model 2000 v m sl moisture sensitivity level 3 n.a. gate count total number of used gates assembled die 50 gates multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supp ly sequencing is not required. operating conditions parameter description condition min. max. unit i bb output reference current relative to v bb |200| ua lu i latch up immunity functional, typical 100 ma t a temperature, operating am bient functional ?40 +85 c ? jc dissipation, junction to case functional 35 [4] c/w ? ja dissipation, junction to ambient functional 76 [4] c/w i ee maximum quiescent supply current v ee pin 130 [5] ma c in input pin capacitance 3pf l in pin inductance 1nh v in input voltage relative to v cc [6] ?0.3 v cc + 0.3 v v tt output termination voltage relative to v cc [6] v cc ? 2 v v out output voltage relative to v cc [6] ?0.3 v cc + 0.3 v i in input current [7] v in = v il , or v in = v ih l150l ua pecl/hstl dc electrical specifications parameter description condition min. max. unit v cc operating voltage 2.5v 5%, v ee = 0.0v 3.3v 5%, v ee = 0.0v 2.375 3.135 2.625 3.465 v v v cmr pecl input differential cross point voltage [8] differential operation 1.2 v cc v v x hstl input differential crosspoint volt- age [9] standard load differential operation 0.68 0.9 v v oh output high voltage i oh = ?30 ma [10] v cc ? 1.25 v cc ? 0.7 v v ol output low voltage v cc = 3.3v 5% v cc = 2.5v 5% i ol = ?5 ma [10] v cc ? 1.995 v cc ?1.995 v cc ? 1.5 v cc ? 1.3 v v v ih input voltage, high single-ended operation v cc ? 1.165 v cc ? 0.880 [11] v v il input voltage, low single-ended operation v cc ? 1.945 [11] v cc ? 1.625 v v bb [3] output reference voltage relative to v cc [6] v cc ? 1.620 v cc ? 1.220 v notes: 4. theta ja eia jedec 51 test board conditions (typical value); theta jc 883e method 1012.1 5. power calculation: v cc * i ee +0.5 (i oh + i ol ) (v oh ? v ol ) (number of differential outputs used); i ee does not include current going off chip. 6. where v cc is 3.3v5% or 2.5v5%. 7. inputs have internal pull-up/pull-down or biasing resistors which affect the input current. 8. refer to figure 1 . 9. v x (ac) is the crosspoint of the differential hstl input signal. normal ac operation is obtained when the crosspoint is within the v x (ac) range and the input swing lies within the v dif (ac) specification. violation of v x (ac) or v dif (ac) impacts the device propagation delay, device and part-to-part skew. refer to figure 2 . 10. equivalent to a termination of 50 ? to vtt. i ohmin =(v ohmin ? v tt )/50; i ohmax =(v ohmax ? v tt )/50; i olmin =(v olmin ? v tt )/50; i olmax =(v olmax ? v tt )/50. 11. v il will operate down to v ee ; v ih will operate up to v cc .
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 4 of 10 ecl dc electrical specifications parameter description condition min. max. unit v ee negative power supply ?2.5v 5%, v cc = 0.0v ?3.3v 5%, v cc = 0.0v ?2.625 ?3.465 ?2.375 ?3.135 v v cmr ecl input differential cross point voltage [8] differential operation v ee + 1.2 0v v v oh output high voltage i oh = ?30 ma [10] ?1.25 ?0.7 v v ol output low voltage v ee = ?3.3v 5% v ee = ?2.5v 5% i ol = ?5 ma [10] ?1.995 ?1.995 ?1.5 ?1.3 v v ih input voltage, high single- ended operation ?1.165 ?0.880 [11] v v il input voltage, low single-ended operation ?1.945 [11] ?1.625 v v bb [3] output reference voltage ?1.620 ?1.220 v ac electrical specifications parameter description condition min. typ. max. unit v pp pecl/ecl differential input voltage [8] differential operation 0.1 1.3 v v cmro output common voltage range (typ.) v cc ? 1.425 v f clk input frequency 50% duty cycle standard load ? 1.5 ghz t pd propagation delay clka or clkb to output pair [13] pecl, ecl < 660 mhz hstl < 1 ghz 280 280 400 400 650 750 ps ps v dif hstl differential input voltage [12] duty cycle standard load differential operation 0.4 ? 1.9 v v o output voltage (peak-to-peak; see figure 2 ) < 1 ghz 0.375 ? ? v tsk (o) output-to-output skew <660 mhz [13] , see figure 3 ?2950ps tsk (pp) part-to-part output skew [13] ?95150ps t jit(per) output period jitter (peak) [14] 156.25 mhz [13] ?7.215ps t jit(pn) output rms phase jitter [13, 14] (see figure 6 ) 156.25 mhz, 3.3v, broadband ? 0.165 ? ps 156.25 mhz, 3.3v, filtered ? 0.151 ? ps 312.5 mhz, 3.3v, broadband ? 0.141 ? ps 312.5 mhz, 3.3v, filtered ? 0.107 ? ps tsk (p) output pulse skew [15] 660 mhz [13] , see figure 3 ??50ps t r ,t f output rise/fall time (see figure 2 ) 50% duty cycle differential 20% to 80% 0.08 ? 0.3 ps notes: 12. v dif (ac) is the minimum differential hstl input voltage swing re quired to maintain ac characteristics including tkpd and device-to -device skew. 13. 50% duty cycle; standard load; differential operation. 14. typical jitter measurements are taken at room temperature and nominal voltage. for further information regarding jitter, ple ase refer to the application note ?understanding data sheet jitter specifications for cypress timing products.? 15. output pulse skew is the absolute diff erence of the propagation delay times: | t plh ? t phl |.
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 5 of 10 timing definitions vih vil vcmr vpp vcmr min = vee + 1.2 vpp range 0.1v - 1.3v vcmr max = vcc vcc vee figure 1. pecl/ecl input waveform definitions vih vil vx vdif vcc = 3.3v vx m ax = 0.9v vx m in = 0.68 v d if = > = 0.4v m in vcc vee vee = 0.0v figure 2. hstl differential input waveform definitions tr, tf, 20-80% vo figure 3. ecl/lvpecl output vo vpp tpd in p u t clock o utput clock another o utput clock tplh, tphl ts k (o ) figure 4. propagation delay (t pd ), output pulse skew (|t plh -t phl |), and output-to-output skew (t sk(o) ) for both clka or clkb to output pair, pecl/ecl to pecl/ecl
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 6 of 10 test configuration standard test load using a di fferential pulse generator and differential measurement instrument. supplemental parametric information pulse generator z = 50 ohm zo = 50 ohm vtt vtt r t = 50 ohm zo = 50 ohm vtt 5" 5" vtt r t = 50 ohm dut cy2dp3110 r t = 50 ohm r t = 50 ohm figure 5. cy2dp3110 ac test reference figure 6. typical phase-noise characterist ics at 156.25 mhz, 3.3v, room temperature -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 10 hz 100 hz 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 mhz 10 gbe filter raw phase noise data raw data plus 10 gbe filter rms phase jitter: 0.151 ps typical @ 156.25 mhz, 10 gbe filter (1.875 mhz ? 20 mhz) 0.165 ps typical @ 156.25 mhz, broadband (raw data from 10 hz ? 20 mhz) -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 1.e+01 1.e+02 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 1.e+08 offset frequency (hz) ssb phase noise (dbc/hz) 10 hz 100 hz 1 khz 10 khz 100 khz 1 mhz 10 mhz 100 mhz 10 gbe filter raw phase noise data raw data plus 10 gbe filter rms phase jitter: 0.151 ps typical @ 156.25 mhz, 10 gbe filter (1.875 mhz ? 20 mhz) 0.165 ps typical @ 156.25 mhz, broadband (raw data from 10 hz ? 20 mhz)
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 7 of 10 applications information termination examples vtt zo = 50 ohm vtt 5" 5" cy2dp3110 r t = 50 ohm r t = 50 ohm vcc vee figure 7. standard lvpecl ? pecl output termination vtt zo = 50 ohm vtt 5" 5" cy2dp3110 r t = 50 ohm r t = 50 ohm vcc vee vbb (3.3v) figure 8. driving a pecl/ecl single-ended input 3.3v zo = 50 ohm 3.3v 5" 5" cy2dp3110 120 ohm 120 ohm vcc =3.3v vee = 0v lvds 51 ohm (2 places) 33 ohm (2 places) lvpecl to lvds figure 9. low-voltage po sitive emitter-coupled logic (lvpecl) to a low-voltage differential sig- naling (lvds) interface
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 8 of 10 figure 10. termination for lvpecl to htsl interface for vcc=2.5v wo uld use x=50 ohms, y=2300 ohms, and z=1000 ohms. see application note titled, ?pecl translation, saw oscillators, and specs? for other signalling standards and supplies. vcc vdd-2 y x z one output is shown for clarity ordering information part number package type product flow CY2DP3110AI 32-pin tqfp industrial, ?40 to 85 c CY2DP3110AIt 32-pin tqfp ? tape and reel industrial, ?40 to 85 c lead-free cy2dp3110axi 32-pin tqfp industrial, ?40 to 85 c cy2dp3110axit 32-pin tqfp ? tape and reel industrial, ?40 to 85 c
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 9 of 10 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety a pplications, unless pursuant to an express written agreement with cypress. package drawing and dimensions fastedge is a trademark of cypress semi conductor. all product and company name s mentioned in this document are the trademarks of their respective holders. 32-lead thin plastic quad flatpack 7 x 7 x 1.4 mm a32.14 51-85088-*b dimensions in mm
fastedge? series cy2dp3110 document #: 38-07469 rev. *i page 10 of 10 document history page document title: cy2dp3110 fastedge? series 1 of 2:10 differential clock/data fanout buffer document number: 38-07469 rev. ecn no. issue date orig. of change description of change ** 121284 11/12/02 rgl new data sheet *a 126251 04/15 /03 rgl added vbb in the block diagram corrected specs that does not match eros/iros changed v ohmin in pecl output table to v cc -1.2v shifted table on ecl levels to match pecl added power-up requirements to absolute maximum conditions changed title (comlink to fastedge) *b 127696 06/12/03 rgl changed operation val ue from 3.0 ghz to 1.5 ghz in features modified note 21: reduced swing value from up to 3 ghz to 2.2 ghz *c 128731 08/04/03 rgl specified ttb value from tbd to 250 ps specified vo (pp) values from tbds to 0.34 ps(min) at < 1.5 ghz, 0.30 ps (typ) at 2.2 ghz changed jitter value from 10 ps to 1 ps (intrinsic) *d 130299 11/19/03 rgl corrected the ?vcco? to ?vcc? in the pin configuration diagram. *e 227708 see ecn rgl/ggk changed the max. dissipation, junction to ambient from 100 to 70c/w added junction temperature(t j ) parameter of 150c max replaced i cc calculation with power calculation in the footnote *f 229393 see ecn rgl/ggk provided data for tbd?s to match the device *g 247626 see ecn rgl/ggk changed v oh and v ol to match the char data *h 381816 see ecn rgl/ggk added phase-noise information; added typical information added lead-free devices *i 392887 see ecn rgl/ggk changed typical values for output rms phase jitter
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