product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 1 general information 1 g b 128 m x64 ddr 2 sdram non - ecc unbuffered so dimm 200 - pin description the vl470t 28 63 a is a 128 mx64 ddr2 sdram high densi ty sodimm. this single rank memory module consists of eight cmos 128mx8 bits with 8 banks ddr2 synchronous drams in bga packages and a 2k eeprom in an 8 - pin tssop package. this module is a 200 - pin small - outline dual in - line memory module and is intended for mounting into an edge connector socket. decoupling capacitors are mounted on the printed circuit board for each ddr2 sdram. features pin description 200 - pin, small - outline dual in - line memory module (sodimm) jedec pin out fast data transfer rate: pc2 - 53 00 vdd = vddq = 1.8v +/ - 0.1v jedec standard 1.8v (sstl_18 compatible) vddspd = 1.7v to 3.6v differential data strobe (dqs, dqs# ) option differential clock inputs (ck, ck#) four - bit pre - fetch architecture dll aligns dq and dqs transition with ck nominal and dynamic on - die termination (odt) programmable cas# latency: 5 ( ddr2 - 667 ) write latency = read latency - 1 tck eight internal component banks for concurrent operation programmable burst; length (4, 8) ad justable data - output drive strength auto & self refresh, (8k/64ms refresh) serial prese nce detect (spd) with eeprom gold edge contacts lead - free, rohs compliant pcb: height 30.00mm (1.181), double sided component operating temperature (t oper ) : - commercial (0 o c <= tc <= 95 o c ) - industrial ( - 40 o c <= tc <= 95 o c ) note s : double refresh rate is required when 85 o c < t oper < = 95 o c. t oper is dram case temperature . pin name function a0~a13 address inputs a10/ap address input/ autoprecharge ba0~ba2 bank address inputs dq0~dq63 data input/output dqs0~dqs7 data strobes dqs0#~dqs7# data strobes complement dm0~dm7 data masks ck0, ck0#, ck1, ck1# clock input s odt0 on - die termination control cke0 clock enables cs0# chip selects ras# row address strobes cas# column address strobes we# write enable vdd voltage supply vss ground sa0~sa1 spd address sda spd data input/output scl spd clock input vddspd spd voltage supply vref sstl_18 reference voltage nc no connect order information: vl 470t2863a - e6 s x - x operating temperature blank: commercial s1: industrial screening dram die ( option) dram manufacturer s - samsung module speed e6 : pc2 - 53 00 @ cl 5 vl: lead - free/rohs
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 2 p i n configuration 200 - p i n ddr 2 s o d i m m f r o n t 200 - p i n ddr 2 s o d i m m b a c k p i n n a m e p i n n a m e p i n n a m e p i n n a m e p i n n a m e p i n n a m e p i n n a m e p i n n a m e 1 v r e f 5 1 d q s 2 10 1 a1 15 1 d q 4 2 2 vs s 5 2 d m 2 10 2 a0 15 2 d q 4 6 3 vs s 5 3 vs s 10 3 v d d 15 3 d q 4 3 4 d q 4 5 4 vs s 10 4 v d d 15 4 d q 4 7 5 d q 0 5 5 d q 1 8 10 5 a 10 / a p 15 5 vs s 6 d q 5 5 6 d q 2 2 10 6 ba 1 15 6 vs s 7 d q 1 5 7 d q 1 9 10 7 ba 0 15 7 d q 4 8 8 vs s 5 8 d q 2 3 10 8 r as # 15 8 d q 5 2 9 vs s 5 9 vs s 10 9 w e # 15 9 d q 4 9 1 0 d m 0 6 0 vs s 1 1 0 c s 0 # 16 0 d q 5 3 1 1 d q s 0 # 6 1 d q 2 4 11 1 v d d 16 1 vs s 1 2 vs s 6 2 d q 2 8 1 1 2 v d d 16 2 vs s 1 3 d q s 0 6 3 d q 2 5 1 1 3 c as # 16 3 nc 1 4 d q 6 6 4 d q 2 9 1 1 4 o t d 0 16 4 c k 1 1 5 vs s 6 5 vs s 1 1 5 c s 1 #* 16 5 vs s 1 6 d q 7 6 6 vs s 1 1 6 a 1 3 16 6 c k 1 # 1 7 d q 2 6 7 d m 3 1 1 7 v d d 16 7 d q s 6 # 1 8 vs s 6 8 d q s 3 # 1 1 8 v d d 16 8 vs s 1 9 d q 3 6 9 n c 1 1 9 o d t 1* 16 9 d q s 6 2 0 d q 1 2 7 0 d q s 3 12 0 n c 17 0 d m 6 2 1 vs s 7 1 vs s 12 1 vs s 17 1 vs s 2 2 d q 1 3 7 2 vs s 12 2 vs s 17 2 vs s 2 3 d q 8 7 3 d q 2 6 12 3 d q 3 2 17 3 d q 5 0 2 4 vs s 7 4 d q 3 0 12 4 d q 3 6 17 4 d q 5 4 2 5 d q 9 7 5 d q 2 7 12 5 d q 3 3 17 5 d q 5 1 2 6 d m 1 7 6 d q 3 1 12 6 d q 3 7 17 6 d q 5 5 2 7 vs s 7 7 vs s 12 7 vs s 17 7 vs s 2 8 vs s 7 8 vs s 12 8 vs s 17 8 vs s 2 9 d q s 1 # 7 9 c ke 0 12 9 d q s 4 # 17 9 d q 5 6 3 0 c k 0 8 0 c ke 1* 13 0 d m 4 18 0 d q 6 0 3 1 d q s 1 8 1 v d d 13 1 d q s 4 18 1 d q 5 7 3 2 c k 0 # 8 2 v d d 13 2 vs s 18 2 d q 6 1 3 3 vs s 8 3 n c 13 3 vs s 18 3 vs s 3 4 vs s 8 4 n c 13 4 d q 3 8 18 4 vs s 3 5 d q 1 0 8 5 ba 2 13 5 d q 3 4 18 5 d m 7 3 6 d q 1 4 8 6 a14 * 13 6 d q 3 9 18 6 d q s 7 # 3 7 d q 1 1 8 7 v d d 13 7 d q 3 5 18 7 vs s 3 8 d q 1 5 8 8 v d d 13 8 vs s 18 8 d q s 7 3 9 vs s 8 9 a 1 2 13 9 vs s 18 9 d q 5 8 4 0 vs s 9 0 a 1 1 14 0 d q 4 4 19 0 vs s 4 1 vs s 9 1 a9 14 1 d q 4 0 19 1 d q 5 9 4 2 vs s 9 2 a7 14 2 d q 4 5 19 2 d q 6 2 4 3 d q 1 6 9 3 a8 14 3 d q 4 1 19 3 vs s 4 4 d q 2 0 9 4 a6 14 4 vs s 19 4 d q 6 3 4 5 d q 1 7 9 5 v d d 14 5 vs s 19 5 s d a 4 6 d q 2 1 9 6 v d d 14 6 d q s 5 # 19 6 vs s 4 7 vs s 9 7 a5 14 7 d m 5 19 7 s c l 4 8 vs s 9 8 a4 14 8 d q s 5 19 8 sa 0 4 9 d q s 2 # 9 9 a3 14 9 vs s 19 9 v dd sp d 5 0 n c 10 0 a2 15 0 vs s 20 0 sa 1 ( *): these pins are not used on this module.
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 3 function block diagram cs0# dq24 dq12 cs# dm dq43 dq9 dq7 dq1 dq3 dq39 cs0# 3 ohms +/-5% d0-d7 dq17 dq1 dq53 dq36 dq4 dm4 dq7 dq23 dq5 dm0 sa1 vss dm dq35 dq1 dq49 dqs dqs7# dqs5 dqs dq47 dq16 dq5 dqs dq22 dm dq2 ras#: ddr2 sdrams d0~d7 dq58 dq45 dqs# dqs6# cs# vss notes: dq3 dq6 dq0 d6 dq5 dq31 a0~a13: ddr2 sdrams d0~d7 dq46 dq15 dq4 dq13 dm dqs# ba0~ba2: ddr2 sdrams d0~d7 dq40 dq50 we# d1 dq8 dq7 dm dq6 dq7 dq59 cas#: ddr2 sdrams d0~d7 dq38 dq4 a0 dq32 1. unless otherw ise noted, resistor values are 22 ohms +/-5% dq3 dq37 dq7 dq1 dq48 dq33 ba0~ba2 dq7 dq26 dq4 cs0#: ddr2 sdrams d0~d7 dq63 * wire per clock loading dq3 dq44 dq2 dq2 dq25 cs# dq1 dq6 dm2 dqs dqs3 dq7 dm dqs3# dq2 cs# dq20 d5 dq14 dq4 cs# table/wiring diagrams dq0 clock input d2 dq0 dq7 d4 dq3 dqs dq6 dqs dq30 dq6 dqs1 dq0 dqs4 vddspd dqs# dqs dq2 serial pd dq3 dq3 dm5 dqs2 dq62 dq0 d0-d7 dq42 dq60 dq1 cs# dq1 dq11 sa0 dq5 dqs2# dqs# dq4 dq34 scl dq0 dm dq54 vdd/ vddq ras# dq3 wp a2 dqs dqs6 * clock wiring ddr2 sdrams cke0: ddr2 sdrams d0~d7 vref dm7 dq0 dq5 dq27 4 sdrams dqs# dqs# dq2 dq2 cke0 dq6 dq4 d0-d7 odt0: ddr2 sdrams d0~d7 dq52 dq7 dq6 dq28 d7 dq0 *ck0, ck0# odt0 dq4 dqs7 dm3 dqs# dq2 *ck1, ck1# dqs5# d3 dq1 dq4 dq21 dq57 dq61 dq29 dm1 dq10 cs# dm dq5 dq18 vss dqs# dq51 dq55 sda dq6 dq1 cs# dqs0 dq2 dq5 dm6 dqs0# dq3 serial pd dq5 d0 4 sdrams dq6 dq0 dqs4# dq5 dq56 a0~a13 dq19 dqs1# a1 dq41 we#: ddr2 sdramsd0~d7 cas#
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 4 absolute maximum ratings symbol parameter m in max unit vdd voltage on vdd pin relative to vss - 1.0 2.3 v vddq voltage on vddq pin relative to vss - 0. 5 2.3 v vddl voltage on vdd l pin relative to vss - 0.5 2.3 v vin, vout voltage on any pin relative to vss - 0. 5 2.3 v tstg storage temperature - 55 1 00 0 c il input leakage current; any input 0v product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 5 operating temperature condition symbol parameter rating units notes t oper operating temperature commercial 0 to +95 0 c 1,2 industrial - 40 to +85 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions , please refer to jedec jesd5 1 - 2. 2. at - 40 to +85 o c, operation temperature range, all dram specifications will be supported . the refresh rate is required to double when 85 o c < toper <= 95 o c . input dc logic level all voltages referenced to vss symbol parameter min max unit vih(dc) input high (logic 1) voltage vref + 0.1 25 v ddq + 0. 300 v vil(dc) input low (logic 0) voltage - 0.300 vref - 0.1 25 v input ac logic level all voltages referenced to vss symbol parameter min max unit vih(ac) input high (logic 1) voltage vref + 0.2 0 0 - v vil(ac) input low (logic 0) voltage - vref - 0.2 0 0 v input/output capacitance ta=25 0 c, f=100mhz parameter symbol e 6 ( ddr2 - 667 ) unit min max input capacitance (a0~a1 3 , ba0~ba2, ras#, cas#, we#) cin1 12 18 pf input capacitance ( cke0, odt0, cs0#) cin2 12 18 pf input capacitance (ck 0 , ck 0 #) , ( ck 1 , ck 1 #) cin3 8 12 pf input/output capacitance (dq, dqs, dqs#, dm) cio 6.5 7.5 pf
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 6 idd specification condition symbol e 6 ( ddr2 - 667 ) unit operating one bank active - pre - charge current; t ck = t ck(idd) ; t rc = t rc(idd) ; t ras = t ras min(idd) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching idd0* 344 ma operating one bank active - read - pre - charge current; iout = 0ma; bl = 4; cl = cl(idd); al = 0; t ck = t ck(idd) ; t rc = t rc(idd) ; t ras = t ras min(idd) ; t rcd = t rcd(idd) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as idd4w idd1* 384 ma pre - charge power - down current; all banks idle; t ck = t ck(idd) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating idd2p** 80 ma pre - charge quiet standby current; all banks idle; t ck = t ck(idd) ; cke is high; other control and address bus inputs are stable; data bus inputs are floating idd2q** 160 ma pre - charge standby current; all banks idle; t ck = t ck(idd) ; cke is high; other control and address bus inputs are stable; data bus inputs are switching idd2n** 192 ma active power - down current; all banks open; t ck = t ck(idd) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating. fast pdn exit mrs(12) = 0 idd3p** 176 ma slow pdn exit mrs(12) = 1 120 ma active standby current; all banks open; t ck = t ck(idd) ; t rp = t rp(idd) ; t ras = t ras max(idd) ; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching . idd3n** 240 ma operating burst write current; all banks open; continuous burst writes; bl = 8; cl = cl(idd); al = 0; t ck = t ck(idd) ; t ras = t ras max(idd) ; t rp = t rp(idd) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching idd4w* 480 ma operat ing burst read current; all banks open; continuous burst reads; iout = 0ma; bl = 4; cl = cl(idd); al = 0; t ck = t ck(idd) ; t ras = t ras max(idd) ; t rp = t rp(idd) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as idd4w. idd4r* 560 ma burst refresh current; t ck = t ck(idd) ; refresh command at every t rfc(idd) interval; cke is high; cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching. idd5** 800 ma self refresh current; ck and ck# at 0v; cke < 0.2v; other control and address bus inputs are floating; data bus inputs are floating. normal idd6** 80 ma operating bank interleave read current; all bank interleaving reads; iout = 0ma; bl = 8; cl = cl(idd); al = t rcd(idd) - 1*t ck(idd) ; t ck = t ck(idd) ; t rc = t rc(idd) ; t rrd = t rrd(idd) ; t rcd = 1*t ck(idd) ; cke is high; cs# is high between valid commands; address bus inputs are stable during deselects ; data bus inputs are switching. idd7* 1160 ma notes: idd specification is based on samsung f - die components. *: value calculated as one module rank in this operating condition, and all other module ranks in idd2p ( cke low) mode. **: value calculated reflects all module ranks in this operating condition.
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 7 ac timing parameters & specifications parameter symbol e7 ( ddr2 - 800) e6 ( ddr2 - 667) d5 ( ddr2 - 533) unit min max min max min max clock timing clock cycle time cl6 tck(6) 2,500 8,000 - - - - ps cl5 tck(5) 3,000 8,000 3,000 8,000 - - ps cl4 tck(4) 3,750 8,000 3,750 8,000 3,750 8,000 ps ck high - level width tch(avg) 0.48 0.52 0.48 0.52 0.48 0.52 tck ck low - level width tcl(avg) 0.48 0.52 0.48 0.52 0.48 0.52 tck half clock period thp min ( tch, tcl) - min ( tch, tcl) - min ( tch, tcl) - ps clock jitter tjit - 100 100 - 125 125 - 125 125 ps data timing dq output access time from ck/ck# tac - 400 400 - 450 +450 - 500 500 ps data - out high impedance window from ck/ck# thz - tac(max) - tac(max) - tac ( max) ps data - out low impedance window from ck/ck# tlz (dq) 2 x tac(m i n ) tac(max) 2 x tac(m i n ) tac(max) 2 x tac(m i n ) tac(max) ps dq and dm input setup time relative to dqs tds 50 - 100 - 100 - ps dq and dm input hold time relative to dqs tdh 125 - 175 - 225 - ps dq and dm input pulse width ( for each input) tdipw 0.35 - 0.35 - 0.35 - tck data hold skew factor tqhs - 300 - 340 - 400 ps dq - dqs hold, dqs to first dq to go non - valid, per access tqh thp - tqhs - thp - tqhs - thp - tqhs - ps data valid output window (dvw) tdvw tqh - tdqsq - tqh - tdqsq - tqh - tdqsq - ns data strobe timing dqs input high pulse width tdqsh 0.35 - 0.35 - 0.35 - tck dqs input low pulse width tdqsl 0.35 - 0.35 - 0.35 - tck dqs output access time from ck/ck# tdqsck - 350 +350 - 400 +400 - 450 +450 ps dqs failing edge to ck rising - setup time tdss 0.2 - 0.2 - 0.2 - tck dqs failing edge from ck rising - hold time tdsh 0.2 - 0.2 - 0.2 - tck dqs - dq skew, dqs to last dq valid, per group, per access tdqsq - 200 - 240 - 300 ps dqs read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck dqs read preamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck dqs read preamble setup time twpres 0 - 0 - 0 - ps dqs read preamble twpre 0.35 - 0.35 - 0.35 - tck dqs read preamble twpst 0.4 0.6 0.4 0.6 0.4 0.6 tck first dqs latching transition to associated clock edge tdqss - 0.25 0.25 - 0.25 0.25 - 0.25 0.25 tck write command to first dqs latching transition - wl - tdqss wl+ tdqss wl - tdqss wl+ tdqss wl - tdqss wl+ tdqss tck command and address timing address and control input pulse width for each input tipw 0.6 - 0.6 - 0.6 - tck address and control input setup time tis 175 - 200 - 250 - ps address and control input hold time tih 250 - 275 - 375 - ps cas# to cas# command delay tccd 2 - 2 - 2 - tck active to active (same bank) command trc 60 - 60 - 60 - ns active to active command period for 1kb page size products trrd 7.5 - 7.5 - 7.5 - ns active to active command period for 2kb page size products trrd 10 - 10 - 10 - ns
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 8 ac timing parameters & specifications parameter symbol e7 ( ddr2 - 800) e6 ( ddr2 - 667) d5 ( ddr2 - 533) unit min max min max min max active to read or write delay trcd 15 - 15 - 15 - ns four activate window for 1kb page size products tfaw 35 - 37.5 - 37.5 - ns four activate window for 2kb page size products tfaw 45 - 50 - 50 - ns active to precharge command tras 45 70,000 45 70,000 45 70,000 ns internal read to precharge command delay trtp 7.5 - 7.5 - 7.5 - ns write recovery time twr 15 - 15 - 15 - ns auto precharge write recovery + precharge time tdal twr + trp - twr + trp - twr + trp - tck internal write to read command delay twtr 7.5 - 7.5 - 7.5 - ns precharge command period trp 15 - 15 - 15 - ns precharge all command period <1gb trpa 15 - 15 - 15 - ns 1gb 17.5 - 18 - 18.75 - ns load mode command cycle time tmrd 2 - 2 - 2 - tck cke low to ck, ck# uncertainty tdelay tis+tck +tih - tis+tck +tih - tis+tck +tih - ns refresh, self - refresh refresh to active or refresh to refresh command interval trfc 127.5 - 127.5 - 127.5 - ns average periodic refresh interval 0 o c tcase85 o c trefi - 7.8 - 7.8 - 7.8 us 85 o c tcase95 o c - 3.9 - 3.9 - 3.9 us exit self refresh to non - read command txsnr t rfc(min) +10 - t rfc(min) +10 - t rfc(min) +10 - ns exit self refresh to read txsrd 200 - 200 - 200 - tck exit self refresh timing reference tisxr tis - tis - tis - ps odt odt turn - on delay taond 2 2 2 2 2 2 tck odt turn - on taon t ac(min) t ac(max)+ 700 t ac(min) t ac(max)+ 700 t ac(min) t ac(max)+ 1,000 ps odt turn - off delay taofd 2.5 2.5 2.5 2.5 2.5 2.5 tck odt turn - off taof t ac(min) t ac(max)+ 600 t ac(min) t ac(max)+ 600 t ac(min) t ac(max)+ 600 ps odt turn - on(power - down mode) taonpd t ac(min)+ 2,000 2 x tck + t ac(max)+ 1,000 t ac(min)+ 2,000 2 x tck + t ac(max)+ 1,000 t ac(min)+ 2,000 2 x tck + t ac(max)+ 1,000 ps odt turn - off (power - down mode) taofpd t ac(min)+ 2,000 2.5 x tck + t ac(max)+ 1,000 t ac(min)+ 2,000 2.5 x tck + t ac(max)+ 1,000 t ac(min)+ 2,000 2.5 x tck + t ac(max)+ 1,000 ps odt to power - down entry latency tanpd 3 - 3 - 3 - tck odt power - down exit latency taxpd 8 - 8 - 8 - tck power down exit active power - down to read command, mr[bit12=0] txard 2 - 2 - 2 - tck exit active power - down to read command, mr[bit12=1] txards 8 - al - 7 - al - 6 - al - tck exit precharge power - down to any non - read command txp 2 - 2 - 2 - tck cke minimum high/low time tcke 3 - 3 - 3 - tck
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 9 package dimensions note: 1. all dimensions are in millimeters with tolerance +/ - 0.15mm unless otherwise specified. 2. the dimensional diagram is for reference only. 67.60 16.26 typ pin 200 4.0 +/- 0.10 (2x) typ pin 1 1.80 (2x) pin 199 0.60 typ 3.40 max 11.40 typ back view 6.00 typ 2.15 typ 63.60 typ 0.45 typ 1.0 +/- 0.10 47.40 typ 20.00 2.55 typ 3.50 typ front view 1.0 +/- 0.10 pin 2 0.5 r 30.00 4.20 typ
product specifications part no.: vl470t2863a - e6s rev: 1 .0 tel 949.888.2444 C 30052 tomas, rancho santa margarita, ca 92688 usa C www.virtium.com 10 revision history: date rev. page changes 10 / 2 4 /201 2 1.0 all spec release
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