general description the ds1843 is a sample-and-hold circuit useful for cap- turing fast signals where board space is constrained. it includes a differential, high-speed switched capacitor input sample stage, offset nulling circuitry, and an out- put buffer. the ds1843 is optimized for use in optical line transmission (olt) systems for burst-mode rssi measurement in conjunction with an external sense resistor. applications gigabit passive optical network (gpon) olt gigabit ethernet passive optical network (gepon) olt gpon optical network unit sample and hold features fast sample time < 300ns hold time > 100? low input offset buffered output small, 8-pin ?fn (2mm x 2mm) pb-free package ds1843 fast sample-and-hold circuit ________________________________________________________________ maxim integrated products 1 ordering information v outn main memory eeprom/sram a/d config/results, system status bits, alarms/warnings, lookup tables, user memory controller v inp v cc v inn sen gnd v outp v cc den sda scl mon1 bias dac 12-bit adc mod dac bmd sen strobe strobe mon4 mon3p mon3n analog mux 3.3v 3.3v temp sensor i 2 c interface ds1843 ds1842/ max4007 r in c s c s c in c in control logic typical operating circuit 19-4539; rev 1; 2/12 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. trl = tape and reel. part temp range pin-package ds1843d+ -40c to +85c 8 dfn ds1843d+trl -40c to +85c 8 dfn pin configuration appears at end of data sheet.
ds1843 fast sample-and-hold circuit 2 _______________________________________________________________________________________ absolute maximum ratings recommended operating conditions (t a = -40c to +85c, unless otherwise noted.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc .............................................-0.5v to +6v voltage range on v outp , v outn , v inp , v inn , sen, den ............................-0.5v to (v cc + 0.5v)* continuous power dissipation (t a = +70c) dfn (derate 4.8mw/c above +70c).....................380.6mw operating temperature range ...........................-40c to +85c storage temperature range .............................-55c to +125c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units supply voltage v cc (note 1) +2.97 +5.5 v dc electrical characteristics (v cc = +2.97v to +5.5v, t a = -40c to +85c, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (note 1) 5.7 9 ma input capacitance c in all pins (note 2) 7 pf sample capacitance c s v inn and v inp (note 2) 5 pf logic-input low v il sen and den inputs 0.3 x v cc v logic-input high v ih sen and den inputs 0.7 x v cc v input leakage i in v inn or v inp, sen = 0 1 a input voltage v in v in = v inp - v inn 0 1.0 v output voltage v out v out = v outp - v outn ; 100k load on each output pin 0 1.0 v output impedance r outmax (note 2) 1 1.3 k output capacitive load c out capacitance for stable operation 50 pf v cc = 2.9v, 1s sample time, v in = 6mv 3.6 6.1 mv total input referenced voltage offset: differential v os-diff voltco (v cc = 2.9v to 5.5v) 1 mv/v v cc = 2.9v, 1s sample time, v in = 6mv 3.4 8 mv total input referenced voltage offset: single-ended v os-se voltco (v cc = 2.9v to 5.5v) 1 mv/v * subject to not exceeding +6v.
ds1843 fast sample-and-hold circuit _______________________________________________________________________________________ 3 note 1: all voltages are referenced to ground. currents entering the ic are specified positive and currents exiting the ic are negative . note 2: guaranteed by design. note 3: v out at the end of the 10? hold time is within specified level of v in during the sample window; a 50 ? resistor connected in series to both v inp and v inn (v inp - v inn = 1v). external capacitance to ground for both v inp and v inn is approximately 10pf. note 4: the sampling capacitor must be removed from the input signal before the input signal changes. therefore, the sen pin must be low for a short period of time, t del , before the input changes. note 5: v out at the end of the hold time is within 1% of v in during the sample window (v inp - v inn = 1v). note 6: voltage step applied across v outp to v outn through a 5pf capacitor connected to each pin. this models the load presented by an adc while it is sampling the ds1843? output. see the output buffer section. settled within 1% of initial voltage. ac electrical characteristics (v cc = +2.97v to +5.5v, t a = -40? to +85?, unless otherwise noted.) (see the timing diagram .) parameter symbol conditions min typ max units sample time minimum t s v out is within 0.4db (note 3) 300 ns delay time minimum t del (note 4) 10 ns output time t out delay from sen falling edge until valid output at v out to 1% accuracy 2 s hold time t hold (note 5) t out 100 s 1v step, den = high 2 output step recovery time (note 6) t rec 3v step, den = high or low 3.5 s timing diagram v inp - v inn v outp - v outn external adc data t adc:st = external adc sampling time. t adc:ct = external adc conversion time. den is connected to v cc for differential output. note: this timing diagram is applicable for single-ended and differential output configurations. sen t s t del t out t adc:st data valid t adc:ct t rec t hold voltage invalid
ds1843 fast sample-and-hold circuit 4 _______________________________________________________________________________________ i cc vs. v cc ds1843 toc01 v cc (v) i cc (ma) 5.0 4.5 4.0 3.5 3.0 5.4 5.5 5.6 5.7 5.8 5.9 5.3 2.5 5.5 den = gnd den = v cc i cc vs. temperature ds1843 toc02 temperature ( c) i cc (ma) 60 35 10 -15 5.5 5.7 5.9 6.1 6.3 6.5 5.3 -40 85 den = v cc v cc = 5v v cc = 3.3v i cc vs. temperature ds1843 toc03 temperature ( c) i cc (ma) 60 35 10 -15 5.5 5.7 5.9 6.1 6.3 6.5 5.3 -40 85 den = gnd v cc = 5v v cc = 3.3v output hold time vs. temperature ds1843 toc04 temperature ( c) output hold time (seconds) 60 35 10 -15 10 100 1000 1 -40 85 den = v cc output hold time vs. temperature ds1843 toc05 temperature ( c) output hold time (seconds) 60 35 10 -15 10 100 1000 1 -40 85 den = gnd differential output during sampling (v inp = 6mv) ds1843 toc06 500ns/div 5mv/div v outp v outn v sen v outp - v outn 100mv/div 1.5v/div single-ended output during sampling (v inp = 6mv) ds1843 toc07 20ns/div 2mv/div 1.5v/div 100mv/div v outp v sen zoomed v outp zoom 500ns/div differential output, transient with 10% v cc step (v inp = 6mv) ds1843 toc08 100 = = single-ended output, transient with 10% v cc step (v inp = 6mv) ds1843 toc09 100 = = typical operating characteristics (t a = +25c, unless otherwise noted.)
ds1843 fast sample-and-hold circuit _______________________________________________________________________________________ 5 differential output, transient with 10% v cc step (v inp = 1v) ds1843 toc10 100 = = single-ended output, transient with 10% v cc step (v inp = 1v) ds1843 toc11 100 = = differential output step recovery, 1v output step (v inp = 6mv) ds1843 toc12 50 () () () single-ended step recovery, 1v output step (v inp = 1v) ds1843 toc13 50 () () () single-ended output, step recovery, 1v output step (v inp = 1v, zoomed in) ds1843 toc14 50ns/div 500mv/div 500mv/div v outp differential output step recovery, 1v output step (v inp = 1v) ds1843 toc15 50 () () () () differential output step recovery, 1v output step (v inp = 1v, zoomed in) ds1843 toc16 50ns/div v outp v outp - v outn (200mv/div) v outn (200mv/div) 200mv/div typical operating characteristics (continued) (t a = +25c, unless otherwise noted.)
ds1843 fast sample-and-hold circuit 6 _______________________________________________________________________________________ detailed description the ds1843 consists of a fully differential sampling capacitor, switches, and a differential output buffer. it is designed to operate in fiber optic burst-mode systems; however, it can be used in other applications requiring a fast sample-and-hold circuit. the output can be con- figured for single-ended operations. input sampling capacitor the input voltage is sampled using a 5pf capacitor on the positive input and another on the negative input. the capacitors are connected to the input when sen is high. in addition to the sampling capacitors, the inputs also have parasitic capacitance (c in ). these capaci- tors must fully charge before sen is switched to low in order to ensure accurate sampling. an rc time con- stant is created by the resistance of the voltage source connected to the ds1843s input and the capacitances on this node. see the applications information section for details. output buffer after sampling is complete, the sampling capacitor is switched to the output buffer. this buffer requires a small amount of time to settle, t out . when an adc is used to measure the ds1843s output, a step occurs at the adcs input caused by the adcs internal sampling capacitor. the ds1843s recovery time, t rec , is depen- dent on the size of the adcs sampling capacitor and the voltage applied across the adc. to maximize accuracy, the adcs sampling speed (adc clock fre- quency) should be reduced until the adcs conversion window (t adc:st , as shown in the timing diagram ) is larger than the ds1843s recovery time. refer to the adcs documentation for t adc:st . sampling time and output error as the sampling time (t s ) is decreased, the output error increases. the output error is largely dependent on the settling time of the sampling capacitor and, to a lesser degree, the output buffers gain error and offset volt- age. settling time can be reduced by driving the ds1843 with a lower impedance. in a typical fiber optic application, a current is applied across a 5k ? resistor. by using a stronger current source, the resistance and the settling time can be reduced (see the applications information section for details). pin description pin name function 1 v cc power-supply input 2 v inp positive voltage input. input to sample circuit. 3 v inn negative voltage input. input to sample circuit. 4 den differential output enable. connect to v cc for differential output or gnd for single-ended output. 5 gnd ground terminal 6 v outn sampled voltage negative output. buffered output of the hold capacitor. keep unconnected or connect to gnd for single-ended output mode. 7 v outp sampled voltage positive output and single-ended output. buffered output of the hold capacitor. 8 sen sample enable. enables input sampling. this input is pulsed. block diagram ds1843 v outn c s c s v cc v inp v inn sen gnd c in c in v outp control logic den
ds1843 fast sample-and-hold circuit _______________________________________________________________________________________ 7 applications information power-supply decoupling to achieve the best results when using the ds1843, decouple the power-supply pin, v cc , with a 0.01f or 0.1f capacitor. use a high-quality x7r or equivalent ceramic surface-mount capacitor. ds1843 estimated settling time the settling time is dependent on the gain ratio of the current mirror used at the input of the ds1843. for example, the max4007 includes a 10:1 ratio current mirror. this requires a 5k ? resistor to create a 1v full- scale output with 2ma current input to the max4007. this resistor can be decreased to 2.5k ? by using the ds1842, which has a 5:1 ratio current mirror. variable definitions: r in : input resistor. the current mirror creates a voltage across this resistor. r sw : resistance of series switch that connects internal circuitry to input pins after t ist time. c in : 7pf parasitic (esd) capacitor. c par : external parasitic capacitance. a current mirror's output and typical trace capacitance are less than 10pf. c s : 5pf sample capacitor. t ist : internal settling time based on t s from the ac elec- trical specification. the minimum t s includes one time constant. t ist removes this time constant. t rc : rc settling time of the input. figure 1 shows the simplified diagram of input imped- ances for settling time calculations. sample time is divided into two parts: 1) t ist : internal settling time (max 250ns). during this time, voltage v in (v inp - v inn ) rises with a time con- stant of: r in x (c in + c par ) 2) t rc : during this period two things happen: a. input v in keeps increasing from its value at t ist to its final value with a new time constant of: b. r sw and c s track this v in (input) with a time con- stant of r sw x c s , which is 12.5ns (worst case). example: approximate accuracy calculations can be done for an input voltage based on the above impedance values. these calculations can be divided into three parts. 1) accuracy of input at t ist (250ns): where t 1 = t ist = 250ns. at t ist the internal circuit tags input impedance. this causes charge redistribution to occur, which causes a dip in the input voltage. the worst-case value of the input voltage at t ist is: v c cc c e in t s in par s t ist ist @ =? ++ () ? ? ? ? ? ? ? ? ? ? 11 r rcc in in in par v + () ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? accuracy e t rcc in in par =? ? + () ? ? ? ? 1 1 rcc rc in in par sw s + () () + () ? ? ? ? ? ? 2 2 ds1843 c s c s c in c par c in input model r sw v inp v inn r sw r in current mirror output figure 1. input impedances for settling time calculations diagram
2) accuracy of internal circuitry between t s - t ist : where t 2 = (t s - t ist ) and (r sw x c s ) ~ = 12ns. 3) total accuracy of input at sampling time, t s : where newrc r c c r c in in par sw s =+ () () + () ? ? ? ? 2 2 ? ? ? accuracy v e in t t newrc ist =?? () ? ? ? ? ? ? ? ? ? 11 1 2 @ ? ? ? ? ? ? ? ? ? ? ? ? ? () e t rc sw s 2 accuracy e t rc sw s =? ? () 1 2 1 2 3 8 7 4 6 5 sen v outp v outn + v cc v inp v inn den gnd top view ds1843 dfn (2mm 2mm) pin configuration fast sample-and-hold circuit ds1843 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a "+", "#", or "-" in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 dfn l822+1 21-0164 90-0005
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