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| d a t a sh eet product speci?cation supersedes data of 2002 sep 10 2003 may 21 integrated circuits TZA3012AHW 30 mbits/s up to 3.2 gbits/s a-rate ? fibre optic receiver
2003 may 21 2 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW features single 3.3 v power supply i 2 c-bus and pin programmable fibre optic receiver. dual limiter features dual limiting input with 12 mv sensitivity received signal strength indicator (rssi) loss of signal (los) indicator with threshold adjust differential overvoltage protection. data and clock recovery features supports shd/sonet bit rates at 155.52, 622.08, 2488.32 and 2666.06 mbits/s (stm16/oc48 + fec) supports gigabit ethernet at 1250 and 3125 mbits/s supports fibre channel at 1062.5 and 2125 mbits/s itu-t compliant jitter tolerance frequency lock indicator stable clock signal when input data absent outputs for recovered data and clock loop mode. demultiplexer features 1:16, 1:10, 1:8 or 1:4 demultiplexing ratio lvpecl or cml demultiplexer outputs frame detection for sdh/sonet and ge frames parity bit generation loop mode inputs to demultiplexer. additional features with the i2c-bus a-rate tm(1) supports any bit rate from 30 mbits/s to 3.2 gbits/s with one reference frequency programmable frequency resolution of 10 hz four reference frequency ranges adjustable swing of data, clock and parallel outputs programmable polarity of all rf i/os exchangeable pin designations of rf clock with data for all i/os for optimum connectivity reversible pin designations of parallel data bus bits for optimum connectivity slice level adjustment to improve bit error rate (ber) mute function for a forced logic 0 output state programmable parity programmable 32-bit frame detection. applications any optical transmission system with bit rates between 30 mbits/s and 3.2 gbits/s physical interface ic in receive channels transponder applications dense wavelength division multiplexing (dwdm) systems. general description the TZA3012AHW is a fully integrated optical network receiver containing a dual limiter, data and clock recovery (dcr) and a demultiplexer with demultiplexing ratios 1:16, 1:10, 1:8 or 1:4. the a-rate feature allows the ic to operate at any bit rate between 30 mbits/s and 3.2 gbits/s using a single reference frequency. the receiver supports loop modes with serial clock and data inputs and outputs. all clock signals are generated using a fractional n synthesizer with 10 hz resolution giving a true, continuous rate operation. for full configuration flexibility, the receiver is programmable by pin or via the i 2 c-bus. (1) a-rate is a trademark of koninklijke philips electronics n.v. ordering information type number package name description version TZA3012AHW htqfp100 plastic thermal enhanced thin quad ?at package; 100 leads; body 14 14 1 mm; exposed die pad sot638 - 1 2003 may 21 3 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram pagewidth rssi1 los1 dloop enlinq dloopq cloopq enba dmxr1 cloop dmxr0 21 20 13 33 6 7 12 9 10 16 17 19 5 87 88 84 85 91 523031 34 27 2 2 390 32 dmx 1 : 4 1 : 8 1 : 10 1 : 16 parity generator and bus swap d00 to d15 parity parityq d00q to d15q poclk inwindow enloutq winsize crefq prscloq los2 rssi2 cref prsclo i.c. rref ui cs(dr0) sda(dr1) scl(dr2) losth2 in2q in2 in1q in1 insel losth1 interrupt controller TZA3012AHW rssi rssi los los switch lim lim phase detector i 2 c-bus lpf frequency window detector 24 23 22 4 28, 29 14 16 2 2 2 2 38 41 42 36 37 39 16 c c d d 44, 46, 48, 53 55, 57, 59, 61, 64, 66, 68, 70 72, 77, 79, 81 poclkq fp fpq 94 95 cout coutq 97 98 92 dout doutq int mgu314 16 45, 47, 49, 54 56, 58, 60, 62, 65, 67, 69, 71 73, 78, 80, 82 v cca 8, 11, 15, 18 4 v ccd 1, 35, 40, 43, 51 75, 76, 83, 86, 89, 93, 96, 99 v cco 25 v dd 26, 50, 63, 74, 100 v ee 13 lim = limiting amplifier. rssi = receiving signal strength indicator. los = loss of signal detector. lpf = low-pass filter. dmx = demultiplexer. fig.1 simplified block diagram. 2003 may 21 4 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW pinning symbol pin description v ee die pad common ground plane v ccd 1 supply voltage (digital part) prsclo 2 prescaler output prscloq 3 prescaler inverted output ui 4 user interface select los1 5 ?rst input channel loss of signal output rssi1 6 ?rst input channel received signal strength indicator output losth1 7 ?rst input channel loss of signal threshold input v cca 8 supply voltage (analog part) in1 9 ?rst channel input in1q 10 ?rst channel inverted input v cca 11 supply voltage (analog part) insel 12 input selector winsize 13 wide and narrow frequency detect window select rref 14 reference resistor input v cca 15 supply voltage (analog part) in2 16 second channel input in2q 17 second channel inverted input v cca 18 supply voltage (analog part) losth2 19 second input channel loss of signal threshold input rssi2 20 second input channel received signal strength indicator output los2 21 los output of second input channel cs(dr0) 22 chip select (data rate select 0) sda(dr1) 23 i 2 c-bus serial data (data rate select 1) scl(dr2) 24 i 2 c-bus serial clock (data rate select 2) v dd 25 supply voltage (digital part) v ee 26 ground inwindow 27 frequency window detector output i.c. 28 internally connected i.c. 29 internally connected dmxr0 30 demultiplexing ratio select 0 dmxr1 31 demultiplexing ratio select 1 v cco 32 supply voltage (clock generator) cref 33 reference clock input crefq 34 reference clock inverted input v ccd 35 supply voltage (digital part) fp 36 frame pulse output fpq 37 frame pulse inverted output parity 38 parity output parityq 39 parity inverted output v ccd 40 supply voltage (digital part) poclk 41 parallel clock output poclkq 42 parallel clock inverted output v ccd 43 supply voltage (digital part) d00 44 parallel data 00 output d00q 45 parallel data 00 inverted output d01 46 parallel data 01 output d01q 47 parallel data 01 inverted output d02 48 parallel data 02 output d02q 49 parallel data 02 inverted output v ee 50 ground v ccd 51 supply voltage (digital part) enba 52 byte alignment enable input d03 53 parallel data 03 output d03q 54 parallel data 03 inverted output d04 55 parallel data 04 output d04q 56 parallel data 04 inverted output d05 57 parallel data 05 output d05q 58 parallel data 05 inverted output d06 59 parallel data 06 output d06q 60 parallel data 06 inverted output d07 61 parallel data 07 output d07q 62 parallel data 07 inverted output v ee 63 ground d08 64 parallel data 08 output d08q 65 parallel data 08 inverted output d09 66 parallel data 09 output d09q 67 parallel data 09 inverted output d10 68 parallel data 10 output d10q 69 parallel data 10 inverted output d11 70 parallel data 11 output d11q 71 parallel data 11 inverted output d12 72 parallel data 12 output symbol pin description 2003 may 21 5 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW d12q 73 parallel data 12 inverted output v ee 74 ground v ccd 75 supply voltage (digital part) v ccd 76 supply voltage (digital part) d13 77 parallel data 13 output d13q 78 parallel data 13 inverted output d14 79 parallel data 14 output d14q 80 parallel data 14 inverted output d15 81 parallel data 15 output d15q 82 parallel data 15 inverted output v ccd 83 supply voltage (digital part) cloop 84 loop mode clock input cloopq 85 loop mode clock inverted input v ccd 86 supply voltage (digital part) dloop 87 loop mode data input dloopq 88 loop mode data inverted input v ccd 89 supply voltage (digital part) symbol pin description enloutq 90 line loop back enable input (active low) enlinq 91 diagnostic loop back enable input (active low) int 92 interrupt output v ccd 93 supply voltage (digital part) cout 94 recovered clock output coutq 95 recovered clock inverted output v ccd 96 supply voltage (digital part) dout 97 recovered data output doutq 98 recovered data inverted output v ccd 99 supply voltage (digital part) v ee 100 ground symbol pin description 2003 may 21 6 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v dd scl(dr2) sda(dr1) cs(dr0) los2 rssi2 losth2 v cca in2q in2 v cca rref winsize insel v cca in1q in1 v cca losth1 rssi1 los1 ui prscloq prsclo v ccd v ccd enba d03 d03q d04 d04q d05 d05q d06 d06q d07 d07q v ee d08 d08q d09 d09q d10 d10q d11 d11q d12 d12q v ee v ccd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 v ee v ccd doutq dout v ccd coutq cout v ccd int enlinq enloutq v ccd dloopq dloop v ccd cloopq cloop v ccd d15q d15 d14q d14 d13q d13 v ccd v ee inwindow i.c. i.c. dmxr0 dmxr1 v cco cref crefq v ccd fp fpq parity parityq v ccd poclk poclkq v ccd d00 d00q d01 d01q d02 d02q v ee 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mgu315 TZA3012AHW fig.2 pin configuration. 2003 may 21 7 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW functional description the TZA3012AHW receives data from an incoming bit stream having a bit rate from 30 mbits/s up to 3.2 gbits/s. two line inputs with limiting amplifiers are available. an internal dcr synchronizes the internal clock generator to the incoming data. the recovered serial data and clock are demultiplexed at ratios of 1:16, 1:10, 1:8 or 1:4. choice of user interface the TZA3012AHW can be controlled either via the i 2 c-bus or using programming pins dr0 to dr2. pin ui selects the user interface required. i 2 c-bus control and a-rate functionality are enabled when pin ui is either open circuit or connected to v cc . pre-programmed mode is enabled when pin ui is connected to v ee ; see table 1. table 1 truth table for pin ui in i 2 c-bus control mode, the chip is configured using the i 2 c-bus pins sda and scl. during i 2 c-bus read or write actions, pin cs must be high. when pin cs is low, the programmed configuration remains active but signals sda and scl are ignored. this allows several TZA3012AHWs in the application with the same i 2 c-bus address to be selected separately. the i 2 c-bus address of the TZA3012AHW is shown in table 2. table 2 i 2 c-bus address of the TZA3012AHW the function and content of the i 2 c-bus registers are described in section i 2 c-bus registers. some functions in the TZA3012AHW can be controlled either by the i 2 c-bus or a designated pin. the method required is specified by an extra bit named i2c 2003 may 21 8 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 5 channel selection both limiters can be made active by setting bit bothon in i 2 c-bus register limcnf. this allows hot switching, where the second channel can be selected quickly if the first channel loses its signal. note that even when both limiters are active, only one channel is selected at any time; see table 6. when only one limiter is active, the time taken to deactivate its limiter and activate the limiter in the other channel takes 4 m s typical. table 6 channel and limiter selection with bit bothon received signal strength indicator (rssi) the strength of signal present at each rf input is measured by a logarithmic detector and represented by an analog voltage at pins rssi1 and rssi2 for channels 1 and 2, respectively. the rssi has a sensitivity of 17 mv/db typical for an input voltage swing v i(p-p) range of 5 mv to 500 mv; see fig.4. rssi output voltage v rssi can be calculated using the following formula: both logarithmic detectors are always active to allow the input with the strongest signal to be selected. loss of signal (los) indicator in addition to the analog rssi output, the TZA3012AHW also provides a digital los indication output on pins los1 and los2. the rssi level is internally compared with a los threshold voltage level, which can be set either by an external resistor connected to pins losth1 and losth2, or by using an internal d/a converter. the method used is determined by bit i2creflvl1 in i 2 c-bus register limlos1cnf (address bdh) for channel 1, or bit i2creflvl2 in i 2 c-bus register limlos2cnf (address bfh) for channel 2. using the internal d/a converter requires a value representing the threshold voltage to be programmed into i 2 c-bus registers limlos1th (address bch) or limlos2th (address beh). this allows separate los threshold levels to be specified per channel. if the received signal strength is below the default hysteresis value of 3 db, the corresponding los pin will be high. alternative hysteresis values from 0 to 7 db in steps of 1 db can be specified using bits hys1 and hys2 in i 2 c-bus registers limlos1cnf and limlos2cnf respectively. if required, the polarity of the los indicator outputs can be inverted by setting bits los1pol and los2pol in the same registers. the los function can be disabled by setting bit los1 or los2 to logic 0 for channel 1 or channel 2 respectively. the los function is also available using i 2 c-bus registers interrupt and status; see sections interrupt register and status register. if bit los1 or los2 in register interrupt is not masked, a loss of signal condition will generate an interrupt signal at pin los1 or pin los2. bits los1 and los2 are masked by default; see section interrupt generation. i 2 c bit pin insel selected channel i2cinsel insel 0 x low channel 2; limiter 2 active 0 x high channel 1; limiter 1 active 1 0 x channel 2; limiter 2 active 1 1 x channel 1; limiter 1 active i 2 c bit bothon pin insel selected channel selected inputs 0 high channel 1; limiter 1 active in1 and in1q 1 high channel 1; limiters 1 and 2 active in1 and in1q 0 low channel 2; limiter 2 active in2 and in2q 1 low channel 2; limiters 1 and 2 active in2 and in2q handbook, halfpage mdb385 50 w in inq 50 w v ee v cca fig.3 limiter input termination configuration. v rssi v rssi(32 mv) s rssi 20log v i(p-p) 32 mv ---------------- - + = 2003 may 21 9 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl555 0 5 0.3 0.6 0.9 1.2 v rssi (v) s rssi 10 32 10 2 10 3 500 300 v i(p-p) (mv) fig.4 v rssi as a function of v i(p-p) . setting losth reference level by external resistor if the internal d/a converter is not used, the reference voltage level on pin losth1 (or losth2) can be set by connecting an external resistor (r2) from the relevant pin to ground. the voltage on the pin is determined by the ratio between r2 and r1; see fig.5. for resistor r1 a value of 10 to 20 k w is recommended, giving a current of 120 to 60 m a. the losth voltage equals voltage v ref represents a temperature stabilized and accurate reference voltage of 1.2 v. the minimum threshold level corresponds to 0 v and the maximum to 1.2 v. hence, the value of r2 may not be higher than r1. the accuracy of the losth voltage depends mainly on carefully choosing the values of the two external resistors. instead of using resistors (r1 and r2) to set the los threshold, an accurate external voltage source can also be used. if no resistor is connected to losth1 (or losth2), or an external voltage higher than 2 3 v cc is applied to the pin, the los detection circuit (including the rssi reading for that channel) is automatically switched off to reduce power dissipation. this auto power off only works if ui = v ee , i.e. manual control of the TZA3012AHW. in i 2 c-bus mode, several i 2 c-bus bits allow flexible configuration. r2 r1 ------- - v ref rssi los compare losth1 losth2 1.2 v v ref rref los mgu318 v cca gnd r2 r1 10 k w i fig.5 setting the losth reference level by external resistors. 2003 may 21 10 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW slice level adjustment the TZA3012AHW uses a slice level circuit to counter the affects of asymmetrical noise that can occur in some optical transmission systems. the slice level circuit improves pre-detection signal-to-noise ratio by adding a dc offset to the input signal. the offset required will depend on the characteristics of the photo detector in the optical front-end and the amplitude of the received signal. the slice level is adjustable between - 50 mv and + 50 mv in 512 steps of 0.2 mv. the slice level function is enabled by setting bits sl1 and sl2 in i 2 c-bus registers limlos1cnf (address bdh) and limlos2cnf (address bfh) for channel 1 and channel 2 respectively. the slice level is set by sign and magnitude convention. the sign, either positive or negative (polarity), is set by i 2 c-bus bits sl1sgn and sl2sgn. the magnitude, 0 to 50 mv in 256 steps, is set by an 8-bit d/a converter via i 2 c-bus register limslice1 (address c0h) and limslice2 (c1h) for channel 1 and channel 2 respectively. the introduced offset is not present at inputs in and inq to prevent the logarithmic rssi detector from detecting the offset as a valid input signal. data and clock recovery (dcr) the TZA3012AHW recovers the clock and data contents from the incoming bit stream; see fig.6. the dcr uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition at any bit rate between 30 mbits/s and 3.2 gbits/s. the dcr contains a voltage controlled oscillator (vco), frequency window detector (fwd), octave divider m, main divider n, fractional divider k, reference divider r, and a phase detector. the internal vco is phase-locked to a reference clock signal of typically 19.44 mhz applied to pins cref and crefq. the fwd is a conventional frequency locked pll, which, at power-up, initially applies a coarse adjustment to the free running vco frequency. the fwd checks the vco frequency, which has to be within a 1000 ppm (parts per million) window around the desired frequency. the fwd then compares the divided vco frequency (also available on pins prsclo and prscloq) with the reference frequency, usually 19.44 mhz, on pins cref and crefq. if the vco frequency is found to be outside this window, the fwd disables the data phase detector (dpd) and forces the vco to a frequency within the window. as soon as the in window condition occurs, which is visible on pin inwindow, the dpd starts acquiring lock on the incoming bit stream. since the vco frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. although the vco is now locked to the incoming bit stream, the fwd is still supervising the vco frequency and takes over control if the vco drifts outside the predefined frequency window. this might occur during a loss of signal situation. due to the fwd, the vco frequency is always close to the required bit rate, enabling rapid phase acquisition if the lost input signal returns. the default frequency window of 1000 ppm means that the reference frequency does not need to be highly accurate or stable. any crystal-based oscillator that generates a reasonably accurate frequency, such as 100 ppm, is suitable. 2003 may 21 11 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth + data phase detector up recovered data data in cref(q) prsclo(q) mgu346 recovered clock dout(q) to demultiplexer limiting amplifier prescaler output octave divider main divider reference input reference divider cout(q) ? m ? n down ? r charge pump loop filter frequency window detector up down voltage controlled oscillator (vco) charge pump 9 n [ 8:0 ] k [ 21:0 ] 22 fraction calculator fig.6 block diagram of data and clock recovery. fractional n synthesizer the dcr uses a fractional n-type synthesizer to provide the a-rate functionality that allows the dcr to synchronize to incoming data, regardless of its bit rate. the dcr has a 22-bit fractional n capability which allows any combination of bit rate and reference frequency between 18 r and 21 r mhz, where r is the reference division factor. the lsb (bit k[0]) of the fractional divider, should be set to logic 1 to avoid limit cycles. these are cycles of less than maximum length that generate spurs in the frequency spectrum. this leaves 21 bits (k[21:1]) available for programming the fraction, allowing a resolution frequency of approximately 10 hz at a fixed reference frequency. programming the reference clock pre-programmed operation requires a reference clock frequency of between 18 and 21 mhz connected to pins cref and crefq. however, to obtain the bit rates in table 3, the reference clock frequency must be 19.44 mhz. for sdh/sonet applications, a reference clock frequency of 19.44 r mhz is preferred. i 2 c-bus control operation allows any one of four possible reference clock frequency ranges to be selected by programming reference divider r using bits refdiv in i 2 c-bus register dcrcnf (address b6 h). the refdiv bit settings, reference clock frequency ranges, and division factor are shown in table 7. the reference frequency is always divided internally to the lowest range of 18 to 21 mhz. table 7 truth table for bits refdiv in i 2 c-bus register dcrcnf refdiv r division factor sdh/sonet reference frequency (mhz) reference frequency range (mhz) 00 1 19.44 18 to 21 01 2 38.88 36 to 42 10 4 77.76 72 to 84 11 8 155.52 144 to 168 2003 may 21 12 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW programming the dcr the following dividers are used to program the clock synthesizer: the main divider n, the fractional divider k and the octave divider m. the division factor for m is obtained by first determining in which octave the desired bit rate belongs as shown in figure 7 and tables 8 and 9. table 8 octave designation and m division factor table 9 common optical transmission protocols and corresponding octaves once the octave and m division factor are known, the division factors for n and k can be calculated for a given reference frequency using the flowchart in fig.8. lowest bit rate (mbits/s) highest bit rate (mbits/s) octave m division factor 1800 3200 0 1 900 1800 1 2 450 900 2 4 225 450 3 8 112.5 225 4 16 56.25 112.5 5 32 28.125 56.25 6 64 handbook, halfpage 28.125 56.25 112.5 225 450 654 3 2 1 0 900 1800 mbits/s 3200 mgu316 fig.7 allocation of octaves for common bit rates shown on a logarithmic scale. protocol bit rate (mbits/s) octave 10ge 3125.00 0 2xhdtv 2970.00 0 stm16/oc48 + fec 2666.06 0 stm16/oc48 2488.32 0 dv-6000 2380.00 0 fibre channel 2125.00 0 hdtv 1485.00 1 d-1 video 1380.00 1 dv-6010 1300.00 1 gigabit ethernet (ge) 1250.00 1 fibre channel 1062.50 1 opticonnect 1062.50 1 isc 1062.50 1 stm4/oc12 622.08 2 dv-6400 595.00 2 fibre channel 425.00 3 opticonnect 265.63 3 fibre channel 212.50 4 escon/sbcon 200.00 4 stm1/oc3 155.52 4 fddi 125.00 4 fast ethernet 125.00 4 fibre channel 106.25 5 oc1 51.84 6 2003 may 21 13 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mgw570 0.25 < k < 0.75 no yes k 0.25 ? k = k + 0.5 no yes k 3 0.75 ? no yes k 3 1 ? no decimal to binary conversion of fractional part yes k j = 1 write k j into registers b3h, b4h and b5h k j = 0 k j = 1 k = k - 1 end convert n to binary and write into registers b1h and b2h j = j - 1 j = 21 k = k 2 k = k - 0.5 n = 2 n + 1 n = 2 n - 1 n = 2 n n = 2 n j = 0 ? no yes k = 0 ? no yes n is integer part k is fractional part nilfrac = 0 nilfrac = 1 calculate n and k n, k = bit rate m r f ref fig.8 flowchart for calculating n and k for the required bit rate. 2003 may 21 14 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW the following examples refer to the flowchart in fig.8. example 1 : an sdh or sonet link has a bit rate of 2488.32 mbits/s (stm16/oc48) that corresponds to octave 0 and an m division factor of 1. if the reference frequency f ref at pins cref and crefq is 77.76 mhz, the division factor r is required to be 4. the initial values for integer n and fractional part k are calculated using the equation: in this example, n = 128 and k = 0. since k is 0, fractional functionality is not required, so bit nilfrac in i 2 c-bus register fracn2 should be set to logic 1; see table 19. n = n 2 = 256 with no further correction required. the resulting values of r = 4, m = 1 and n = 256 are set by i 2 c-bus registers dcrcnf (table 22), divcnf (table 16), maindiv1 (table 17) and maindiv0 (table 18). example 2 : an sdh or sonet link has a bit rate of 2666.057143 mbits/s (15/14 2488.32 mbits/s) (stm16/oc48 link with fec) that corresponds to octave 0 and an m division factor of 1. if f ref at pins cref and crefq is 38.88 mhz, the division factor r is required to be 2. the values for n and k are calculated as follows: in this example, n = 137 and k = 0.1428571. fractional functionality is required, so bit nilfrac in i 2 c-bus register fracn2 should be set to logic 0. since k is less than 0.25, k is corrected to k = k + 0.5 = 0.6428571, and n is corrected to n = n 2 - 1 = 273. the resulting values of r = 2, m = 1, n = 273 and k = 10 1001 0010 0100 1001 0011 are set by i 2 c-bus registers dcrcnf (table 22), divcnf (table 16), maindiv1 (table 17), maindiv0 (table 18), fracn2 (table 19), fracn1 (table 20) and fracn0 (table 21). the fec bit rate is usually rounded up to 2666.06 mbits/s, which actually gives a different value for k than in this example. example 3 : a fibre channel link has a bit rate of 1062.50 mbits/s that corresponds to octave 1 and an m division factor of 2. if f ref at pins cref and crefq is 19.44 mhz, the division factor r is required to be 1. the values for n and k are calculated as follows: in this example, n = 109 and k = 0.3107. fractional functionality is required, so bit nilfrac in i 2 c-bus register fracn2 should be set to logic 0. since k is greater than 0.25 and less than 0.75, k does not need to be corrected. n is corrected ton=n 2 = 218. the resulting values of r = 1, m = 2, n = 218 and k = 01 0011 1110 0010 1000 0001 are set by i 2 c-bus registers dcrcnf (table 22), divcnf (table 16), maindiv1 (table 17), maindiv0 (table 18), fracn2 (table 19), fracn1 (table 20) and fracn0 (table 21). example 4 : a non standard transmission link has a bit rate of 3012 mbits/s that corresponds to octave 0 and an m division factor of 1. if f ref at pins cref and crefq is 20.50 mhz, the division factor r is required to be 1. the values for n and k are calculated as follows: in this example, n = 146 and k = 0.9268293. fractional functionality is required, so bit nilfrac in i 2 c-bus register fracn2 should be set to logic 0. since k is greater than 0.75, k is corrected to k = k - 0.5 = 0.4268293, and n is corrected to n = n 2 + 1 = 293. the resulting values of r = 1, m = 1, n = 293 and k = 01 1011 0101 0001 0010 1011 are set by i 2 c-bus registers dcrcnf (table 22), divcnf (table 16), maindiv1 (table 17), maindiv0 (table 18), fracn2 (table 19), fracn1 (table 20) and fracn0 (table 21). if the i 2 c-bus is not used, the clock synthesizer can be set up for the eight pre-programmed bit rates shown in table 3, by pins dr0, dr1 and dr2 using an external reference clock frequency of 19.44 mhz. n.k bit rate m r f ref --------------------------------------- - 2488.32 mbits 1 4 77.76 mhz -------------------------------------------------------- - 128 == = n.k bit rate m r f ref --------------------------------------- - 2666.05714283 mbits 1 2 38.88 mhz ---------------------------------------------------------------------------- - 137.1428571 == = n.k bit rate m r f ref --------------------------------------- - 1062.50 mbits 2 1 19.44 mhz -------------------------------------------------------- - 109.3106996 == = n.k bit rate m r f ref --------------------------------------- - 3012 mbits 1 1 20.50 mhz ------------------------------------------------ 146.9268293 == = 2003 may 21 15 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW prescaler outputs the frequency of prescaler outputs prsclo and prscloq is the vco frequency divided by a ratio of n.k. if the synthesizer is in-lock, the frequency of the prescaler output is equal to the reference frequency at cref and crefq divided by r which also corresponds to the recovered data rate. this provides an accurate reference that can be used by other phase locked loops in the application. if required, the polarity of the prescaler outputs can be inverted by setting bit prscloinv in i 2 c-bus register iocnf0 (address cbh) to logic 1. if no prescaler information is required, its output can be disabled by setting bit prscloen in the same register to logic 0. in addition, the prescaler output can be set for type of output, termination mode and signal amplitude. these parameter settings also apply to the parallel output clock poclk and poclkq and parity error output parerr and parerrq. for programming details, these parameter settings also apply to the parallel demultiplexer outputs. for programming details; see section configuring the parallel interface. programming the fwd the default window for frequency acquisition is 1000 ppm around the desired bit rate. the size of window determines the amount of variation in the frequency of the applied reference clock, and vco, that is tolerated by the fwd. the window size can be set to other predefined values between 250 and 2000 ppm by bits windowsize in i 2 c-bus register dcrcnf (address b6h). an additional feature allows the size of the frequency acquisition window to be set to 0 ppm, which effectively removes the dead zone from the fwd, converting it to a classical pll. the vco will then be directly phase-locked to the reference signal instead of the incoming bit stream. this is implemented by either applying a low level to pin winsize, or by setting bit winsize to logic 0 and bit i2cwinsize to logic 1 in i 2 c-bus register dcrcnf; see table 10. table 10 truth table for pin winsize accurate clock generation during loss of signal during a loss of signal, there is no data present for clock recovery to use. a frequency acquisition window size of zero will make the recovered clock frequency equal to the reference frequency, including its tolerance. setting bit autowin in i 2 c-bus register dcrcnf makes the window size dependent on the los status of the active limiter channel. if the optical input signal is lost, the fwd automatically selects the 0 ppm window size, so that the vco is directly phase-locked to the reference signal. this ensures that the output clock signal remains stable during loss of signal, and automatically reverts to normal dcr operation when the input signal returns. note that the accuracy of the reference frequency must be better than 20 ppm for the application to comply with itu-t recommendations. inwindow signal the status of the fwd circuit is indicated by the level on pin inwindow. a high level indicates that the vco is within the defined frequency acquisition window size, and a low level indicates that the vco is outside the defined window size. the status of the fwd circuit is also indicated by bit inwindow in i 2 c-bus registers interrupt and status. jitter performance the clock synthesizer is optimized for minimum jitter generation. for all sdh/sonet bit rates, the generated jitter complies with itu-t standard g.958 using a pure reference clock. to ensure negligible loss of performance when a reference clock is used, the reference signal should have a single sideband phase noise of better than - 140 dbc/hz, at frequencies of more than 12 khz from the carrier. if reference divider r is used, this negative value is allowed to increase at approximately 20 log (r). demultiplexer the demultiplexer converts the serial input bit stream to parallel formats of 1:16, 1:10, 1:8, and 1:4. the output data is available on a scalable bus, of which the output driver type can be either lvpecl or cml. in addition to the deserializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. a calculated parity of even is output at pins parity and parityq. a detected frame header pattern in the data stream results in a 1 clock cycle wide pulse on outputs fp and fpq. winsize window size (ppm) low 0 high 1000 2003 may 21 16 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW making pin enba high automatically aligns the parallel output into logical bytes or words. the same function is implemented by setting bit enba in i 2 c-bus register dmxcnf (address a8h). to support most commonly used transmission systems and protocols, the demultiplexing ratio can be set to 1:16, 1:10, 1:8, and 1:4, and the frame header pattern programmed to any 32 or 10-bit pattern; see section frame detection. if required, the demultiplexer output can be forced into a fixed logic 0 state by bit dmxmute in i 2 c-bus register dmxcnf. adjustable demultiplexing ratio for optimum layout connectivity, the physical positions of parallel data bus pins d00 to d15 and d00q to d15q on the chip are located either side of pin v ee (pin 63). the number of parallel data bus outputs that are used depends on the demultiplexing ratio selected by pins dmxr0 and dmxr1 or by bits dmxr in i 2 c-bus register dmxcnf (address a8 h). any unused parallel data bus outputs are disabled. the configuration settings and active outputs for each demultiplexing ratio are shown in table 11. in i 2 c-bus control mode, the default demultiplexing ratio is 16:1. to allow optimum layout connectivity, the pin designations of the parallel data bus bits can be reversed so that the default designated pin for d15 (msb) is exchanged with the default designated pin for d0 (lsb). this is implemented by bit busswap in i 2 c-bus register dmxcnf (address a8h). the highest supported speed for the parallel data bus is 400 mbits/s. therefore a demultiplexing ratio of 4:1 will support bit rates of up to 1.6 gbits/s. table 11 setting demultiplexing ratio pin dmxr1 pin dmxr0 bits dmxr (reg dmxcnf) demultiplexing ratio active outputs lsb to msb low low 00 1:4 d06 to d09 low high 01 1:8 d04 to d11 high low 10 1:10 d03 to d12 high high 11 1:16 d00 to d15 frame detection byte alignment is enabled if the enable byte alignment input (pin enba) is high, or if bit i2cenba and bit enba are both logic 1 in i 2 c-bus register dmxcnf (address a8h). whenever the incoming data has a 32-bit or 10-bit sequence that matches the programmed frame header pattern, the data is formatted into logical bytes or words, and a frame pulse is generated on differential outputs fp and fpq. any frame header pattern can be programmed in i 2 c-bus registers header0 to header3. any bit position can be programmed with a dont care to give a frame header pattern that is either much shorter than 32 or 10 bits, or has gaps. the dont care bits are produced by programming a pattern into i 2 c-bus registers headerx0 to headerx3 which is used to mask the programmed frame header pattern as shown in the example fig.9. the default frame header pattern is f6f62828h, corresponding to the middle section of the standard sdh/sonet frame header (the last two a1 bytes plus the first two a2 bytes). 2003 may 21 17 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth x 0 0 1 0 x 1 1 0 0 0 header3 headerx3 received data data stream headerx0 mgu548 header0 msb header lsb header bit32 1 0 1 1 1 01100010 00000011 011000xx bit1 1 0 0 0 0 1 0 0 fig.9 example of programming the frame header pattern. x = dont care msb = most significant byte. if enba is low, no active alignment takes place. however, if the frame header pattern occurs in the formatted data, a frame pulse will still be output on pins fp and fpq. for 10-bit oriented protocols, such as gigabit ethernet, the frame header detection operates on a 10-bit pattern sequence. these 10 bits should be programmed into i 2 c-bus registers header3 and the two msbs of header2; the remaining 22 bits are ignored. a dont care pattern overlay can be programmed in i 2 c-bus register headerx3 and the two msbs of headerx2. since some 10-bit oriented protocols use a dc balancing code, the detection pattern could appear in complementary form in the data stream. by setting bit cmpl in i 2 c-bus register dmxcnf (address a8h), the header detection scans the data stream for both the programmed pattern and its complement simultaneously. either occurrence produces a byte alignment and a corresponding frame pulse on pins fp and fpq. the default pattern (after power-up) is 0011111010 or k28.5 character plus alternating 010. this is the only pattern containing five consecutive bits of the same sign. receiver framing in sdh/sonet applications figure 10 shows a typical sdh/sonet reframe sequence involving byte alignment. frame and byte boundary detection is enabled on the rising edge of enba and remains enabled while enba is high. boundaries are recognized on receipt of the second a2 byte and fp goes high for one poclk cycle. in 1:16 mode, the first two a2 bytes in the frame header are the first data word to be reported with the correct alignment on the outgoing data bus (d00 to d15). in 1:8 mode the first a2 byte is the first aligned data byte (d04 to d11), while in 1:4 mode the most significant nibble of the first a2 byte is the first aligned data (d06 to d09). when interfacing with a section terminating device, enba must remain high for a full frame after the initial frame pulse. this is to allow the section terminating device to verify internally that frame and byte alignment are correct; see fig.11. byte boundary detection is disabled on the first fp pulse after enba has gone low. figure 12 shows frame and byte boundary detection activated on the rising edge of enba, and deactivated by the first fp pulse after enba has gone low. 2003 may 21 18 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mgu550 valid data invalid data serial clock enba serial data d00 to d15 (1:16) poclk (1:16) fp (1:16) d06 to d09 (1:4) poclk (1:4) fp (1:4) a1 a1 a2 28 28 1 : 16 1 : 4 a2 a2 2828 a2 a1 a2 a2 32 bits fig.10 frame and byte detection in sdh/sonet application. handbook, halfpage mgu340 enba fp boundary detection enabled fig.11 enba timing with section terminating device. handbook, halfpage mgu341 enba fp boundary detection enabled fig.12 alternate enba timing. 2003 may 21 19 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW parity generation outputs parity and parityq provide the even parity of the byte/word that is currently available on the parallel bus. odd parity can be output by setting bit parinv to logic 1 in i 2 c-bus register iocnf2 (address c9h). if no parity output is required, and/or to reduce output power, set bit paren, in the same register, to logic 0. con?guring the parallel interface there are several options for configuring the parallel interface which comprises the parallel data bus and associated outputs. the options for parallel data output d00 to d15 and d00q to d15q, parallel clock output poclk and poclkq, parity output parity and parityq, frame pulse output fp and fpq, and prescaler output prsclo and prscloq are: output driver type, termination mode, output amplitude, signal polarity, and selective enabling or disabling. the parallel data bus pin designations can also be reversed and/or muted. these options are set in i 2 c-bus registers iocnf3 (address c8h) and iocnf2 (address c9h), iocnf0 (address cbh) and dmxcnf (address a8h). i 2 c-bus register iocnf3, bit mfoutmode selects either the cml or lvpecl output driver. the default is lvpecl. bit mfoutterm sets the output termination mode to either standard lvpecl or floating termination, or in cml mode, to either dc or ac-coupled. in all cases, bits mfs adjust the amplitude. the default output amplitude is 800 mv (p-p) single-ended. in i 2 c-bus register iocnf2, setting bit pden to logic 0 disables the parallel interface output driver. this is not the same effect as setting bit dmxmute in i 2 c-bus register dmxcnf (address a8h), which forces the outputs to a logic 0 state. setting bit pdinv to logic 1 in i 2 c-bus register iocnf2 (address c9h) inverts the polarity of the parallel data. setting bit poclkinv to logic 1 in the same register inverts the clock output so that the clock edge is shifted by half a clock cycle, changing the rising edge to a falling edge. this function can be used to resolve a parallel data bus timing problem. the parallel bus clock is disabled by setting bit poclken to logic 0 in the same register. control bits in the same register and in register iocnf0 (address cbh) also apply the same options to the parity, frame pulse and prescaler outputs. loop mode i/os in line loopback mode, the internal data and clock routing switch routes the received serial data and recovered clock to outputs dout, doutq cout and coutq instead of to the demultiplexer. line loopback mode is activated by a low level on pin enloutq. line loopback mode is also selected by setting bit enloopout and bit i2cloopmode in i 2 c-bus register divcnf (address b0h). in diagnostic loopback mode, the demultiplexer selects the serial data and clock signals at loop mode input pins dloop, dloopq and cloop, cloopq instead of from the dcr. diagnostic loopback mode is activated by a low level on pin enlinq. diagnostic loopback mode is also selected by setting bit enloopin and bit i2cloopmode in i 2 c-bus register divcnf (address b0h). con?guring the rf i/os the polarity of specific rf serial data and clock i/o signals can be inverted using i 2 c-bus register iocnf1 (address cah). to allow easier connection to other ics, the pin designations for input data can be exchanged with the pin designations for input clock. the pin designations for output data and output clock can also be exchanged. the default pin designations for loop mode input data and clock are exchanged by setting bit cdinswap in i 2 c-bus register iocnf1 so that signals at pins cloop and cloopq are treated as data and signals at pins dloop and dloopq are treated as clock. the default pin designations for loop mode output data and clock are exchanged by setting bit cdoutswap in i 2 c-bus register iocnf1 so that signals at pins cout and coutq are treated as data and signals at pins dout and doutq are treated as clock. the amplitude of the rf serial output signals in cml drive mode, is adjustable (in 16 steps) between 60 mv (p-p) and 1000 mv (p-p), single-ended, controlled by bits rfs and rfswing in i 2 c-bus register iocnf0 (address cbh). the default amplitude is 80 mv (p-p), single-ended. the rf serial outputs are ac-coupled. 2003 may 21 20 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW cmos control inputs cmos control inputs ui, insel, winsize, dmxr0, dmxr1, enba, enloutq, enlinq and cs(dr0) have an internal pull-up resistor so that these pins go high when open circuit, and only go low when deliberately forced. this is also true for pins dr1 and dr2 in pre-programmed mode (pin ui is low). in i 2 c-bus control mode (pin ui is high), pins scl and sda comply with the i 2 c-bus interface standard. power supply connections four separate supply domains (v dd , v ccd , v cco and v cca ) provide isolation between the various functional blocks. each supply domain should be connected to a common v cc using a separate filter. all supply pins, including the exposed die pad, must be connected . the die pad connection to ground must have the lowest possible inductance. since the die pad is also used as the main ground return of the chip, this connection must also have a low dc impedance. the voltage supply levels should be in accordance with the values specified in chapters characteristics and limiting values. all external components should be surface mounted, with a preferable size of 0603 or smaller. the components must be mounted as close to the ic as possible. interrupt register the following events are recorded by setting the appropriate bit(s) in i 2 c-bus register interrupt (address 00 h): loss of signal on channel 1 loss of signal on channel 2 dcr frequency locked or unlocked limiter channel switching enabled or disabled high junction temperature. when register interrupt is polled by an i 2 c-bus read action, any set bits are reset. if a condition is still active, the corresponding bit remains set. status register the current status of the conditions that are recorded by register interrupt are indicated by setting the appropriate bit(s) in i 2 c-bus register status (address 01h). a bit is set only for the period that the condition is active and resets when the condition clears. register status is polled by an i 2 c-bus read action. interrupt generation an interrupt is generated if an interrupt condition sets a bit in i 2 c-bus register interrupt (address 00h) and if the bit is not masked by i 2 c-bus register intmask (address cch). only the high junction temperature interrupt bit is not masked by default. a generated interrupt is indicated by an active logic level at pin int. the active output level used is set by bit intpol in i 2 c-bus register intmask. the default is an active low level. bit intout sets the output mode at pin int to either open-drain or to standard cmos. the default is open-drain. an active low output in open-drain mode allows several receivers to be connected together, and requires only one 3.3 k w pull-up resistor. 2003 may 21 21 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. bit transfer refer to fig.13. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. fig.13 bit transfer. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl start and stop conditions refer to fig.14. both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p). fig.14 definition of start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition 2003 may 21 22 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW system con?guration refer to fig.15. a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. acknowledge refer to fig.16. only one data byte is transferred between the start and stop conditions during a write from the transmitter to the receiver. each byte of eight bits is followed by an acknowledge bit. the acknowledge bit is a high level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). a master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition; see fig.19. mba605 master transmitter / receiver slave receiver slave transmitter / receiver master transmitter master transmitter / receiver sda scl fig.15 system configuration. fig.16 acknowledgment on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 2003 may 21 23 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW i 2 c-bus protocol addressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the address byte is sent after the start condition. the master transmitter/receiver either reads from the read-registers or writes to the write-registers. it is not possible to read from and write to the same register. figure 17 shows how the slave and register address bytes are defined. read/write protocols the protocol for writing to a single register is shown in fig.18. the transmitter sends the address of the slave device, waits for an acknowledge from the slave, sends register address, waits for an acknowledge from the slave, sends data byte, waits for an acknowledge from the slave, followed by a stop condition. the protocol for reading one or more registers is shown in fig.19. the receiver sends the address of the slave device, waits for an acknowledge from the slave, receives data byte(s) from the slave (the TZA3012AHW starts sending data after asserting an acknowledge), after receiving the data, the receiver sends an acknowledge or, if finished, a not-acknowledge, followed by a stop condition. handbook, full pagewidth mdb070 msb lsb 1 msb lsb r/w slave address register address fig.17 slave and register addresses. handbook, full pagewidth s a1 aa data p acknowledge from slave r/w mdb386 0 register address slave address acknowledge from slave acknowledge from slave msb msb lsb one byte transferred fig.18 write protocol. 2003 may 21 24 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW i 2 c-bus registers the i 2 c-bus registers are accessed in i 2 c-bus control mode by setting pin ui high or leaving pin ui open circuit. address and read/write data are transferred serially via pin sda and clocked via pin scl when pin cs (chip select) is high. the i 2 c-bus registers are listed in table 12. handbook, full pagewidth s aa data r/w 1 slave address acknowledge from slave msb lsb first byte aa data p mdb387 acknowledge from master (1) msb lsb last byte acknowledge from master (1) acknowledge from master (1) fig.19 read protocol. (1) the master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. 2003 may 21 25 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 12 i 2 c-bus registers notes 1. addresses not shown must not be accessed. 2. x = dont care. address (hex) (1) name function default value read/ write 00 interrupt interrupt register; see table 13 - r 01 status status register; see table 14 - r a0 header3 programmable header, most signi?cant byte 1:10 ratio 1111 0110 0011 1110 w a1 header2 programmable header 1:10 ratio 1111 0110 10x xxxx w a2 header1 programmable header 0010 1000 w a3 header0 programmable header, least signi?cant byte 0010 1000 w a4 headerx3 programmable header, dont care, most signi?cant byte 1:10 ratio 0000 0000 0000 0000 w a5 headerx2 programmable header, dont care 1:10 ratio 0000 0000 00xx xxxx w a6 headerx1 programmable header, dont care 0000 0000 w a7 headerx0 programmable header, dont care, least signi?cant byte 0000 0000 w a8 dmxcnf demultiplexer con?guration register; see table 15 0000 1011 w b0 divcnf octave and loop mode con?guration register; see table 16 0000 0000 w b1 maindiv1 main divider division factor n; most signi?cant byte; range 128 to 511; see table 17 0000 0001 w b2 maindiv0 main divider division factor n; least signi?cant byte; see table 18 0000 0000 w b3 fracn2 fractional divider division factor k; see table 19 1000 0000 w b4 fracn1 fractional divider division factor k; see table 20 0000 0000 w b5 fracn0 fractional divider division factor k; see table 21 0000 0000 w b6 dcrcnf dcr con?guration register; see table 22 0000 1100 w bc limlos1th limiter 1 loss of signal threshold register; range 0 to 255 0000 0000 w bd limlos1cnf limiter 1 loss of signal con?guration register; see table 23 0000 1101 w be limlos2th limiter 2 loss of signal threshold register; range 0 to 255 0000 0000 w bf limlos2cnf limiter 2 loss of signal con?guration register; see table 24 0000 1101 w c0 limslice1 limiter 1 slice level register; range 0 to 255 0000 0000 w c1 limslice2 limiter 2 slice level register; range 0 to 255 0000 0000 w c2 limcnf limiter con?guration register; see table 25 0000 1000 w c8 iocnf3 parallel interface output con?guration register 3; see table 26 0000 1100 w c9 iocnf2 parallel interface output con?guration register 2; see table 27 1010 1010 w ca iocnf1 rf serial i/o con?guration register 1; see table 28 0000 0000 w cb iocnf0 rf serial output con?guration register 0; see table 29 0010 0011 w cc intmask interrupt masking register; see table 30 0101 0000 w 2003 may 21 26 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 13 register interrupt (address 00h) bit parameter 7 6 5 4 3 2 1 0 description name loss of signal on channel 1 los1 1 no signal present (loss of signal condition) 0 signal present loss of signal on channel 2 los2 1 no signal present (loss of signal condition) 0 signal present dcr frequency indication inwindow 1 frequency outside predefined window (unlocked) 0 frequency inside predefined window (locked) auto-switching between channels limsw 1 enabled (active limiter indicated in status register) 0 disabled (no auto-switching between channels) high junction temperature talarm 1 junction temperature 3 130 c 0 junction temperature <130 c 0 0 0 reserved 2003 may 21 27 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 14 register status (address 01h) bit parameter 7 6 5 4 3 2 1 0 description name loss of signal on channel 1 los1 1 no signal present (loss of signal condition) 0 signal present loss of signal on channel 2 los2 1 no signal present (loss of signal condition) 0 signal present dcr frequency indication inwindow 1 frequency inside predefined window (locked) 0 frequency outside predefined window (unlocked) active limiter indication limsel 1 limiter 1 active 0 limiter 2 active high junction temperature talarm 1 junction temperature 3 130 c 0 junction temperature <130 c 0 0 0 reserved 2003 may 21 28 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 15 register dmxcnf (address a8h); default value 0bh bit parameter 7 6 5 4 3 2 1 0 description name demultiplexing ratio dmxr 1 1 1:16 1 0 1:10 0 1 1:8 0 0 1:4 demultiplexing ratio programming i2cdmxr 1 via i 2 c-bus interface 0 via pins dmxr0 and dmxr1 frame header detection in 1:10 gigabit ethernet mode cmpl 1 simultaneously check for complementary header 0 check programmed header only parallel data bus bit designations busswap 1 d00 = msb, d15 = lsb (reversed) 0 d15 = msb, d00 = lsb (normal) demultiplexer mute parallel interface outputs dmxmute 1 mute; parallel interface outputs forced to logic 0 0 no mute enable/disable byte alignment enba 1 enabled 0 disabled enba control i2cenba 1 via i 2 c-bus interface 0 via pin enba 0 0 0 0 1 0 1 1 default value 2003 may 21 29 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 16 register divcnf (address b0h); default value 00h table 17 register maindiv1 (address b1h); default value 01h table 18 register maindiv0 (address b2h); default value 00h bit parameter 7 6 5 4 3 2 1 0 description name octave divider division factor m, octave selection div_m 0 0 0 m = 1, octave number 0 0 0 1 m = 2, octave number 1 0 1 0 m = 4, octave number 2 0 1 1 m = 8, octave number 3 1 0 0 m = 16, octave number 4 1 0 1 m = 32, octave number 5 1 1 0 m = 64, octave number 6 0 0 reserved enable/disable loop mode inputs enloopin 1 enabled 0 disabled enable/disable loop mode outputs enloopout 1 enabled 0 disabled loop mode control i2cloopmode 1 via i 2 c-bus interface 0 via pin enlinq and/or pin enloutq 0 0 0 0 0 0 0 0 default value bit parameter 7 6 5 4 3 2 1 0 description name ------- n8 main divider division factor n; n8 = msb div_n 0 0 0 0 0 0 0 1 default value bit parameter 7 6 5 4 3 2 1 0 description name n7 n6 n5 n4 n3 n2 n1 n0 main divider division factor n; n0 = lsb div_n 0 0 0 0 0 0 0 0 default value 2003 may 21 30 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 19 register fracn2 (address b3h); default value 80h note 1. x = dont care. table 20 register fracn1 (address b4h); default value 00h table 21 register fracn0 (address b5h); default value 00h bit parameter 7 6 5 4 3 2 1 0 description name nf x k21 k20 k19 k18 k17 k16 fractional divider division value k; k21 = msb div_k nilfrac control bit nilfrac 1 no fractional n functionality 0 fractional n functionality 1 0 0 0 0 0 0 0 default value bit parameter 7 6 5 4 3 2 1 0 description name k15 k14 k13 k12 k11 k10 k9 k8 fractional divider division value k div_k 0 0 0 0 0 0 0 0 default value bit parameter 7 6 5 4 3 2 1 0 description name k7 k6 k5 k4 k3 k2 k1 k0 fractional divider division value k; k0 = lsb div_k 0 0 0 0 0 0 0 0 default value 2003 may 21 31 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 22 register dcrcnf (address b6h); default value 0ch bit parameter 7 6 5 4 3 2 1 0 description name fwd window size; relative to bit rate windowsize 0 1 1 2000 ppm 1 0 0 1000 ppm 1 0 1 500 ppm 1 1 0 250 ppm fwd window size select; windowsize value or zero winsize 1 window size specified by windowsize; pll frequency allowed to vary around the reference frequency 0 window size = 0 ppm; pll frequency directly synthesized from reference frequency winsize control bit i2cwinsize 1 via i 2 c-bus interface 0 via pin winsize automatic window size select autowin 1 enabled 0 disabled reference divider division factor r; reference frequency refdiv 1 1 r = 8; 155.52 mhz 1 0 r = 4; 77.76 mhz 0 1 r = 2; 38.88 mhz 0 0 r = 1; 19.44 mhz 0 0 0 0 1 1 0 0 default value 2003 may 21 32 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 23 register limlos1cnf (address bdh); default value 0dh bit parameter 7 6 5 4 3 2 1 0 description name loss of signal detection on channel 1 los1 1 enabled 0 disabled loss of signal threshold level control bit on channel 1 i2creflvl1 1 via i 2 c-bus interface by internal dac; register limlos1th 0 via analog voltage on pin losth1 loss of signal detection hysteresis on channel 1 hys1 000 0db 001 1db 010 2db 011 3db 100 4db 101 5db 1 1 0 6 db 1 1 1 7 db slice level on channel 1 sl1 1 enabled 0 disabled slice level sign on channel 1 sl1sgn 1 positive 0 negative polarity of los on channel 1 los1pol 1 inverted 0 normal 0 0 0 0 1 1 0 1 default value 2003 may 21 33 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 24 register limlos2cnf (address bfh); default value 0dh bit parameter 7 6 5 4 3 2 1 0 description name loss of signal detection on channel 2 los2 1 enabled 0 disabled loss of signal threshold level control bit on channel 2 i2creflvl2 1 via i 2 c-bus interface by internal dac; register limlos2th 0 via analog voltage on pin losth2 loss of signal detection hysteresis on channel 2 hys2 000 0db 001 1db 010 2db 011 3db 100 4db 101 5db 110 6db 111 7db slice level on channel 2 sl2 1 enabled 0 disabled slice level sign on channel 2 sl2sgn 1 positive 0 negative polarity of los on channel 2 los2pol 1 inverted 0 normal 0 0 0 0 1 1 0 1 default value 2003 may 21 34 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 25 register limcnf (address c2h); default value 08h note 1. x = dont care. bit parameter 7 6 5 4 3 2 1 0 description name ampli?er octave selection ampoct 0 0 0 octave number 0; 1800 to 3200 mbits/s 0 0 1 octave number 1; 900 to 1800 mbits/s 0 1 0 octave number 2; 450 to 900 mbits/s 0 1 1 octave number 3; 225 to 450 mbits/s 1 x x octave number 4; 30 to 225 mbits/s channel selection insel 1 channel 1 selected; limiter 1 active 0 channel 2 selected; limiter 2 active channel selection control bit i2cinsel 1 via i 2 c-bus interface; bit insel 0 via pin insel single/dual limiter selection bothon 1 both limiters active 0 single limiter active, specified by bit insel 0 0 reserved 0 0 0 0 1 0 0 0 default value 2003 may 21 35 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 26 register iocnf3 (address c8h); default value 0ch bit parameter 7 6 5 4 3 2 1 0 description name parallel output signal amplitude mfs 0 0 0 0 60 mv (p-p) 0 0 0 1 minimum; 120 mv (p-p) 1 1 0 0 default; 800 mv (p-p) 1 1 1 1 maximum; 1000 mv (p-p) 0 0 reserved parallel output termination mfoutterm 1 lvpecl mode: floating; cml mode: ac-coupled 0 lvpecl mode: standard; cml mode: dc-coupled parallel output mode mfoutmode 1 current mode logic (cml) 0 low voltage positive emitter coupled logic (lvpecl) 0 0 0 0 1 1 0 0 default value 2003 may 21 36 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 27 register iocnf2 (address c9h); default value aah bit parameter 7 6 5 4 3 2 1 0 description name parallel data output polarity pdinv 1 inverted 0 normal parallel data output enable pden 1 enabled 0 disabled parallel clock output polarity poclkinv 1 inverted 0 normal parallel clock output enable poclken 1 enabled 0 disabled parity output polarity parinv 1 inverted 0 normal parity output enable paren 1 enabled 0 disabled frame pulse output polarity fpinv 1 inverted 0 normal frame pulse output enable fpen 1 enabled 0 disabled 1 0 1 0 1 0 1 0 default value 2003 may 21 37 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 28 register iocnf1 (address cah); default value 00h bit parameter 7 6 5 4 3 2 1 0 description name loop mode clock input polarity cininv 1 inverted 0 normal loop mode data input polarity dininv 1 inverted 0 normal loop mode clock and data inputs swap cdinswap 1 clock and data input pairs swapped 0 normal loop mode clock output polarity coutinv 1 inverted 0 normal loop mode data output polarity doutinv 1 inverted 0 normal loop mode clock and data outputs swap cdoutswap 1 clock and data output pairs swapped 0 normal 0 0 reserved 0 0 0 0 0 0 0 0 default value 2003 may 21 38 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 29 register iocnf0 (address cbh); default value 23h bit parameter 7 6 5 4 3 2 1 0 description name rf serial output signal amplitude rfs 0 0 0 0 minimum: 20mv (p-p); 60 mv (p-p) high swing 0 0 1 1 default: 80mv (p-p); 250 mv (p-p) high swing 1 1 1 1 maximum: 300mv (p-p); 1000 mv (p-p) high swing prescaler output polarity prscloinv 1 inverted 0 normal prescaler output enable prscloen 1 enabled 0 disabled rf serial output swing rfswing 1 high swing 0 low swing 0 reserved 0 0 1 0 0 0 1 1 default value 2003 may 21 39 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW table 30 register intmask (address cch); default value a0h note 1. signal is not processed by the interrupt controller. bit parameter 7 6 5 4 3 2 1 0 description name mask los1 signal mlos1 1 not masked 0 masked; note 1 mask los2 signal mlos2 1 not masked 0 masked; note 1 mask inwindow signal minwindow 1 not masked 0 masked; note 1 mask limsel signal mlimsel 1 not masked 0 masked; note 1 mask high junction temperature mtalarm 1 not masked 0 masked; note 1 0 reserved pin int polarity mode intpol 1 inverted; active low output 0 normal; active high output pin int output mode intout 1 standard cmos output 0 open-drain output 0 1 0 1 0 0 0 0 default value 2003 may 21 40 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW TZA3012AHW features in pre-programmed mode although the TZA3012AHW is primarily intended to be programmed via the i 2 c-bus (pin ui high), many of the TZA3012AHW functions can be accessed via the external chip pins in pre-programmed mode (pin ui low) as follows: choice of four pre-programmed sdh/sonet bit rates: stm1/oc3, stm4/oc12, stm16/oc48, stm16/oc48 + fec; pins dr0 to dr2 choice of four pre-programmed bit rates; fibre channel, double fibre channel, gigabit ethernet, 10-gigabit ethernet; pins dr0 to dr2 choice of four demultiplexing ratios; 1:16, 1:10, 1:8 or 1:4 pins dmuxr1 and dmuxr0 input channel selection (insel) received signal strength indicator, independently for channels 1 and 2 loss of signal detection threshold for each input channel individually (losth1 and losth2) automatic disable of unused logarithmic detector (losth1 and losth2) loop mode serial input and output configuration: pins enlinq and enloutq automatic byte alignment for sdh/sonet or gigabit ethernet (enba) frame detection for sdh/sonet (pattern is a1a1a2a2) or gigabit ethernet even parity generation lvpecl outputs on parallel interface with 800 mv (p-p), single-ended signal, (dc-coupled termination to v cc - 2v) cml serial rf outputs with typical 80 mv (p-p), single-ended signal, (ac-coupled load) in window detection (inwindow) fwd window size select, windowsize value ppm or 0 ppm (winsize) high junction temperature indication (pin int; open-drain) 18 to 21 mhz reference frequency supported. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter min. max. unit v cca , v ccd , v cco , v dd supply voltages - 0.5 + 3.6 v v n dc voltage on pins d00 to d15, d00q to d15q, poclk, poclkq, fp, fpq, parity, parityq, prsclo and prscloq v cc - 2.5 v cc + 0.5 v losth1, losth2 and rref - 0.5 v cc + 0.5 v rssi1 and rssi2 - 0.5 v cc + 0.5 v ui, insel, winsize, cs, sda, scl, dmxr0, dmxr1, enba, enloutq and enlinq - 0.5 v cc + 0.5 v los1, los2 and inwindow - 0.5 v cc + 0.5 v int - 0.5 v cc + 0.5 v i n input current on pins in1, in1q, in2 and in2q - 30 + 30 ma cref, crefq, cloop, cloopq, dloop and dloopq - 20 + 20 ma int - 2 + 2ma t amb ambient temperature - 40 + 85 c t j junction temperature -+ 125 c t stg storage temperature - 65 + 150 c 2003 may 21 41 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW thermal characteristics notes 1. in compliance with jedec standards jesd51-5 and jesd51-7. 2. four-layer printed-circuit board (pcb) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the pcb. characteristics v cc = 3.14 to 3.47 v; t amb = - 40 to + 85 c; r th(j-a) 16 k/w; all characteristics are specified for the default settings (note 1); all voltages are referenced to ground; positive currents flow into the device; unless otherwise specified. symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient notes 1 and 2 16 k/w symbol parameter conditions min typ max unit supplies i cca analog supply current 15 20 27 ma i ccd digital supply current see figs 20 and 22 270 350 450 ma i cco oscillator supply current 20 25 33 ma i dd digital supply current 0 0 1 ma i cc(tot) total supply current note 2 305 395 511 ma p tot total power dissipation note 2 0.96 1.3 1.77 w cmos input: pins ui, dr0, dr1, dr2, insel, winsize, dmxr0, dmxr1, enba, enloutq and enlinq v il low-level input voltage -- 0.2v cc v v ih high-level input voltage 0.8v cc -- v i il low-level input current v il =0v - 200 -- m a i ih high-level input current v ih =v cc -- 10 m a cmos output: pins los1, los2, inwindow and int v ol low-level output voltage i ol = 1 ma 0 - 0.2 v v oh high-level output voltage i oh = - 0.5 ma v cc - 0.2 - v cc v open-drain output: pin int v ol low-level output voltage i ol = 1 ma 0 - 0.2 v i oh high-level output current v oh =v cc -- 10 m a serial output: pins cout, coutq, dout and doutq v o(p-p) default output voltage swing (peak-to-peak value) single-ended with 50 w external load; enloutq = low; see figs 23 and 27; note 3 50 80 110 mv z o output impedance single-ended to v cc 80 100 120 w t r rise time 20% to 80% - 100 - ps t f fall time 80% to 20% - 100 - ps 2003 may 21 42 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW t d-c data-to-clock delay (cout, coutq and dout, doutq) between differential crossovers; see fig.29 80 140 200 ps d duty cycle cout and coutq between differential crossovers 40 50 60 % serial input: pins cloop, cloopq, dloop and dloopq v i(p-p) input voltage (peak-to-peak value) single-ended 50 - 1000 mv v i dc input voltage v cc - 1 - v cc + 0.25 v z i input impedance single-ended to v cc 40 50 60 w t d clock delay see fig.30 260 340 400 ps t su set-up time see fig.30 15 30 60 ps t h hold time see fig.30 15 30 60 ps d duty cycle signals cloop and cloopq between differential crossovers 40 50 60 % cml mode parallel output: pins d00 to d15, d00q to d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq v o(p-p) default output voltage swing (peak-to-peak value) single-ended with 50 w external load to v cc ; ac-coupled; see fig.27 or dc-coupled; see fig.28; note 4 650 800 1000 mv z o output impedance single-ended to v cc 70 95 110 w t r rise time 20% to 80% 200 250 350 ps t f fall time 80% to 20% 200 250 350 ps f pbr parallel bit rate -- 400 mbits/s lvpecl mode parallel output: pins d00 to d15, d00q to d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq v oh high-level output voltage 50 w termination to v cc - 2v; see fig.24 v cc - 1.2 v cc - 1.0 v cc - 0.9 v v ol low-level output voltage 50 w termination to v cc - 2v; see fig.24 v cc - 2.0 v cc - 1.9 v cc - 1.7 v v o(p-p) default output voltage swing (peak-to-peak value) lvpecl ?oating; fig.21; single-ended with 50 w external load to v cc ; ac-coupled; see fig.26 or dc-coupled; see fig.25; note 4 700 900 1150 mv t r rise time 20% to 80% 300 350 400 ps t f fall time 80% to 20% 300 350 400 ps f par parallel bit rate -- 400 mbits/s symbol parameter conditions min typ max unit 2003 may 21 43 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW parallel timing output: pins d00 to d15, d00q to d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq t d-c data-to-clock delay d00 to d15/poclk dmx 1:16, 1:10, 1:8; see fig.31; note 5 - 100 100 250 ps t d-c data-to-clock delay d06 to d09/poclk dmx 1:4; see fig.31; note 5 150 180 250 ps d duty cycle poclk 40 50 60 % skew channel to channel skew d00 and dn (between channels) dmx 1:16, 1:10, 1:8; note 5 -- 200 ps skew channel to channel skew d06 and d09 (between channels) dmx 1:4; note 5 -- 50 ps reference: pin rref v ref reference voltage 10 to 20 k w resistor to v ee 1.17 1.21 1.26 v i 2 c-bus pins scl and sda v il low-level input voltage -- 0.2v cc v v ih high-level input voltage 0.8v cc -- v v hys hysteresis of schmitt trigger inputs 0.05v cc -- v v ol sda low-level output voltage (open-drain) i ol = 3 ma 0 - 0.4 v i l leakage current - 10 -+ 10 m a c i input capacitance -- 10 pf i 2 c-bus timing f scl scl clock frequency -- 100 khz t low scl low time 1.3 -- m s t hd;sta hold time start condition 0.6 -- m s t high scl high time 0.6 -- m s t su;sta set-up time start condition 0.6 -- m s t hd;dat data hold time 0 - 0.9 m s t su;dat data set-up time 100 -- ns t su;sto set-up time stop condition 0.6 -- m s t r scl and sda rise time 20 - 300 ns t f scl and sda fall time 20 - 300 ns t buf bus free time between stop and start 1.3 -- m s c b capacitive load on each bus line -- 400 pf t sp pulse width of allowable spikes 0 - 50 ns symbol parameter conditions min typ max unit 2003 may 21 44 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW v nl noise margin at low-level 0.1v cc -- v v nh noise margin at high-level 0.2v cc -- v rf input: pins in1, inq1, in2 and in2q v i(p-p) input voltage swing (peak-to-peak value) single-ended; note 6 12 - 500 mv v sl typical slice level range note 7 - 50 -+ 50 mv z i input impedance differential 80 100 120 w a iso between channel isolation - 60 - db received signal strength indicator (rssi) v i(p-p) input voltage swing (peak-to-peak value) single-ended 5 - 500 mv s rssi rssi sensitivity see fig.4 15 17 20 mv/db v rssi output voltage v i(p-p) = 32 mv (p-p); prbs (2 31 - 1) 580 680 780 mv d v o(rssi) output voltage variation input 30 to 3200 mbits/s; prbs (2 31 - 1); v cc = 3.14 to 3.47 v; d t = 120 c - 50 -+ 50 mv output: pins rssi1 and rssi2 z o output impedance - 110 w i o(source) output source current -- 1ma i o(sink) output sink current -- 0.4 ma los detector hys hysteresis note 8 - 3 - db t a assert time d v i(p-p) =3db -- 5 m s t d de-assert time d v i(p-p) =3db -- 5 m s reference frequency input: pins cref and crefq v i(p-p) input voltage (peak-to-peak value) single-ended 50 - 1000 mv v i dc input voltage v cc - 1 - v cc + 0.25 v z i input impedance single-ended to v cc 40 50 60 w d f cref reference clock frequency accuracy sdh/sonet requirement - 20 -+ 20 ppm f cref reference clock frequency see table 7; r = 1, 2, 4 or 8 18 r 19.44 r21 r mhz pll characteristics t acq acquisition time 30 mbits/s -- 200 m s t acq(pc) acquisition time at power cycle 30 mbits/s -- 10 ms t acq(o) acquisition time octave change 30 mbits/s -- 10 m s tdr transitionless data run 30 mbits/s - 1000 - bits symbol parameter conditions min typ max unit 2003 may 21 45 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW notes 1. default settings: ui = low (pre-programmed mode; see table 1); dr0 = low, dr1 = high, dr2 = low (stm16/oc48); insel = high (limiter 1 active); winsize = high (1000 ppm); enba = high (automatic byte alignment); enloutq = high (dout, cout disabled); enlinq = high (dloop, cloop disabled); dmxr0 = high, dmxr1 = high (dmx ratio 1:16); cref and crefq = 19.44 mhz; losth2 not connected (los2 switched off); d00 to d15 and d00q to d15q, fp, fpq, parity, parityq, poclk, poclkq, prsclo and prscloq not connected. 2. the total supply current and power dissipation is dependent on the ic setups such as swing and loop modes and termination conditions. 3. the output swing is adjustable in 16 steps controlled by bits rfs in i 2 c-bus register cbh. 4. the output swing is adjustable in 16 steps controlled by bits mfs in i 2 c-bus register iocnf3 (address c8h). in standard lvpecl mode only swing = 12 (default) should be used. 5. with 50% duty cycle. 6. the rf input is protected against a differential overvoltage; the maximum input current is 30 ma. it is assumed that both inputs carry a complementary signal of the specified peak-to-peak value. 7. the slice level is adjustable in 256 steps controlled by i 2 c-bus registers limslice1 (address c0h) and limslice2 (address c1h). 8. the hysteresis is adjustable in 8 steps controlled by bits hys1 and hys2 in i 2 c-bus registers limlos1cnf (address bdh) and limlos2cnf (address bfh). 9. the j tol(p-p) min. value is 0.25ui for t amb = - 40 c to 0 c at f = 65 khz and 1 mhz. 10. the j tol(p-p) min. value is 0.25ui for t amb = - 40 c to 0 c at f = 250 khz and 5 mhz. 11. the j tol(p-p) min. value is 0.25ui for t amb = - 40 c to 0 c at f = 1 mhz and 20 mhz. jitter tolerance j tol(p-p) jitter tolerance (peak-to-peak value) stm1/oc3 mode (itu-t g.958); prbs (2 31 - 1); note 9 f = 6.5 khz 3 10 - ui f = 65 khz 0.3 1 - ui f = 1 mhz 0.3 0.5 - ui stm4/oc12 mode (itu-t g.958); prbs (2 31 - 1); note 10 f = 25 khz 3 10 - ui f = 250 khz 0.3 1 - ui f = 5 mhz 0.3 0.5 - ui stm16/oc48 mode (itu-t g.958); prbs (2 31 - 1); note 11 f = 100 khz 3 10 - ui f = 1 mhz 0.3 1 - ui f = 20 mhz 0.3 0.5 - ui symbol parameter conditions min typ max unit 2003 may 21 46 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl556 0 10 20 30 50 40 i ccd (ma) 0 15 510 value of address c8h, bit 3 to bit 0 lvpecl standard cml ac cml dc lvpecl floating fig.20 supply current per parallel output. handbook, full pagewidth mbl557 0 200 400 600 1000 800 v o(p-p) (mv) 0 15 510 value of address c8h, bit 3 to bit 0 lvpecl standard default lvpecl floating cml ac/dc fig.21 output voltage swing of parallel output. 2003 may 21 47 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl558 0 10 20 30 50 40 i ccd (ma) 0 15 510 value of address cbh, bit 3 to bit 0 cml ac low swing fig.22 supply current per serial output. serial outputs are off (default). handbook, full pagewidth mbl559 0 200 400 600 1000 800 v o(p-p) (mv) 0 15 510 value of address cbh, bit 3 to bit 0 (enloutq = low) (clock 2.4 ghz) cml ac low swing fig.23 output voltage swing of serial output. 2003 may 21 48 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl562 v cc out transmission lines optional ac coupling to high- impedance input 50 w 50 w 2 v v term 50 w 50 w outq i swing in swing control on-chip off-chip fig.24 standard pecl mode. handbook, full pagewidth mbl560 v cc out transmission lines to high- impedance input 50 w 50 w 100 w outq i swing in swing control on-chip off-chip fig.25 floating pecl mode (dc-coupled). 2003 may 21 49 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl561 v cc out transmission lines ac coupling to high- impedance input 50 w 50 w v bias 50 w 50 w outq i swing in swing control on-chip off-chip fig.26 floating lvpecl mode (ac-coupled). handbook, full pagewidth mbl563 v cc v bias out transmission lines recommended for serial outputs to high- impedance input 50 w 50 w 100 w 100 w 50 w 100 w 100 w 50 w outq i swing in swing control on-chip off-chip 120 w fig.27 cml mode (ac-coupled). 2003 may 21 50 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW handbook, full pagewidth mbl564 v cc out transmission lines to high- impedance input 50 w 50 w 50 w 100 w 100 w 50 w outq i swing in swing control on-chip off-chip fig.28 cml mode (dc-coupled). handbook, full pagewidth mgu345 t d-c cout dout the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential). fig.29 loop mode output timing. 2003 may 21 51 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW fig.30 loop mode input timing. the timing is measured from the crossover point of the clock input signal to the crossover point of the data input. mbl554 handbook, halfpage cloop dloop t d t su t h handbook, full pagewidth mgu343 poclk d00 to d15, fp, parity t d-c the timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signa ls are differential). fig.31 parallel bus output timing. 2003 may 21 52 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW package outline unit a max. a 1 a 2 a 3 b p h d h e l p z d (1) z e (1) cely w v q references outline version european projection issue date iec jedec jeita mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 1.15 0.85 7 0 0.08 0.08 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot638-1 01-03-30 03-04-07 d (1) e (1) 14.1 13.9 16.15 15.85 d h e h 7.1 6.1 7.1 6.1 1.15 0.85 b p b p e q e a 1 a l p detail x l (a 3 ) b 25 h d h e a 2 v m b d z d a c z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 10 mm scale htqfp100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad sot638-1 d h e h exposed die pad side 2003 may 21 53 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: below 220 c (snpb process) or below 245 c (pb-free process) C for all the bga packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. below 235 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 2003 may 21 54 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable 2003 may 21 55 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 may 21 56 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. 2003 may 21 57 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW notes 2003 may 21 58 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW notes 2003 may 21 59 philips semiconductors product speci?cation 30 mbits/s up to 3.2 gbits/s a-rate ? ?bre optic receiver TZA3012AHW notes ? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 403510/02/pp 60 date of release: 2003 may 21 document order number: 9397 750 10905 |
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