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general description the max1636 is a synchronous, buck, switch-mode, power-supply controller that generates the cpu supply voltage in battery-powered systems. it achieves ?% output voltage accuracy and offers the excellent load- transient response needed by upcoming generations of dynamic-clock cpus. up to 95% efficiency is achieved through synchronous rectification and maxim? proprietary idle mode con- trol scheme. efficiency is greater than 80% over a 1000:1 load-current range, extending battery life in sys- tem-suspend or standby modes. excellent dynamic response corrects output load transients caused by the latest dynamic-clock cpus within five 300khz clock cycles. strong, 1a, on-board gate drivers ensure fast, external n-channel mosfet switching. the max1636 features a logic-controlled and synchro- nizable, fixed-frequency, pulse-width-modulation (pwm) operating mode that reduces noise and rf interference in sensitive mobile communications and pen-entry appli- cations. holding skip high forces fixed-frequency mode for lowest noise under all load conditions. for a low-cost version that omits the +5v vl linear- regulator block and comes in a smaller 16-pin qsop package, refer to the max1637 data sheet. applications notebook computers subnotebook computers desktop computers bus-termination supplies features 1% dc accuracy (adjustable mode) output overvoltage crowbar protection output undervoltage shutdown adjustable switching frequency to 340khz low-dropout operation idle mode pulse-skipping operation 1.10v to 5.5v adjustable output voltage 2.5v/3.3v dual-mode fixed-output settings internal digital soft-start 1.1v 1% reference output 3a (typ) shutdown current open-drain power-good output ( r r e e s s e e t t ) 20-pin ssop package max1636 low-voltage, precision step-down controller for portable cpu power ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 skip lx dh bst shdn reset csl csh top view pgnd dl vl v+ sync ref cc ovp 12 11 9 10 v cc fb gnd gnd max1636 ssop 19-1268; rev 2; 2/98 evaluation kit manual follow s data sheet idle mode is a trademark of maxim integrated products. pin configuration typical operating circuit ordering information max1636 v+ shdn gnd v in dl pgnd lx dh vl v cc bst ovp csh csl fb reset to p cc skip gnd sync ref part max1636eap -40? to +85? temp. range pin-package 20 ssop for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
mv max1636 low-voltage, precision step-down controller for portable cpu power 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1, v+ = 15v, sync = vl = v cc , i vl = 0ma, i ref = 0ma, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v+ to gnd ...............................................................-0.3v to 36v gnd to pgnd........................................................................?v shdn to gnd. ......................................................... -0.3v to 36v lx, bst to gnd. ...................................................... -0.3v to 36v dh, bst to lx .............................................................-0.3v to 6v vl, v cc , csl, csh, fb, skip to gnd ...................... -0.3v to 6v dl to gnd.. ..................................................-0.3v to (vl + 0.3v) ref, reset , sync, cc, ovp to gnd. ..... -0.3v to (v cc + 0.3v) vl output current... ............................................................50ma vl short circuit to gnd..............................................momentary ref output current ............................................................20ma ref short circuit to gnd ....... ......................................indefinite continuous power dissipation (t a = +70?) ssop (derate 8.00mw/? above +70?) .....................640mw operating temperature range max1636eap. ..................................................-40? to +85? storage temperature range .............................-65? to +160? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? gate-driver supply rail csh - csl input source for vl regulator shdn to full current limit, five levels fb forced to ref positive direction shdn = gnd, ovp = gnd v cc = 3.3v, output not switching v cc = 3.3v, vl = 5v v cc = vl = 5v internal chip supply rail fb tied to v out , 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) fb tied to v cc , 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) v cc = 5v, output not switching fb tied to gnd, 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) negative direction conditions mv 20 30 40 idle mode switchover threshold clks 512 soft-start ramp time na -50 50 fb input current ? 310 shutdown supply current (v+) 1.5 power consumption 2.0 -145 -100 -55 v 4.2 5.5 input voltage range, vl v 4.5 30 input voltage range, v+ mv 80 100 120 current-limit threshold v ref 3.6 v v ref 5.5 output adjustment range v 3.15 5.5 input voltage range, v cc v 1.090 1.100 1.110 output voltage, adj mode v 2.486 2.55 2.614 output voltage, fixed 2.5v mode v 3.282 3.366 3.450 output voltage, fixed 3.3v mode units min typ max parameter mw smps controller
max1636 low-voltage, precision step-down controller for portable cpu power _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, sync = vl = v cc , i vl = 0ma, i ref = 0ma, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) % fb to dl delay, 22mv overdrive, c gate = 2000pf shdn = gnd, ovp = v cc fb, with respect to regulation point v cc = 5v, i(vl) = 0, v+ = 4.5v (includes pnp base current) v cc = 5v, i(vl) = 0 guaranteed by design sync = v cc sync = gnd sync = v cc i(vl) = 0 to 25ma, 5v < v+ < 30v i(vl) = 0 to 25ma, 6v < v+ < 30v rising edge, hysteresis = 25mv sync = gnd ref load = 0 to 50? sync = gnd ? 150 ? 1.25 % 4 7 10 khz 240 340 sync input frequency range ns 200 sync input rise/fall time ns 200 sync input pulse width low 200 maximum duty factor, dropout mode 98 99 93 96 ? 60 standby supply current (v+) ? 500 regulator supply current (v+) 60 91 94 170 200 230 270 300 330 khz v 4.5 5.0 5.3 4.7 5.0 5.3 vl output voltage v 3.15 vl/ v cc switchover threshold mv 10 ref load regulation hysteresis = 10? rising edge, hysteresis = 25mv v 3.45 3.60 3.75 vl undervoltage lockout threshold no ref load v 1.090 1.100 1.110 ref output voltage v cc = 3.3v to 5.5v mv 3 ref line regulation oscillator frequency % ns sync input pulse width high maximum duty factor overvoltage trip threshold thermal shutdown threshold overvoltage fault propagation delay % pin at gnd or v cc ; skip , ovp, sync shdn , skip , ovp, sync shdn , skip , ovp, sync falling edge (hysteresis = 1%) from shutdown or power-on-reset state % of nominal output v 0.4 reset output voltage low ? -1 1 v 0.8 v 2.4 logic input voltage high clks catastrophic output undervoltage lockout delay logic input voltage low logic input bias current clks 32768 reset delay time % -6 -3 reset trip threshold 6144 catastrophic output undervoltage lockout threshold 60 70 80 i sink = 4ma +5.5v stress voltage applied ? 1 reset output leakage current conditions units min typ max parameter shdn = gnd or v+ ? -3 3 shdn input bias current internal vl regulator and reference oscillator overvoltage protection inputs and outputs
max1636 low-voltage, precision step-down controller for portable cpu power 4 _______________________________________________________________________________________ gate-driver supply rail input source for vl regulator v cc = 3.3v, vl = 5v v cc = vl = 5v internal chip supply rail fb tied to v out , 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) fb tied to v cc , 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) fb tied to gnd, 0mv < (csh - csl) < 80mv, 4.5v < v+ < 30v (includes line and load regulation) conditions v 4.2 5.5 input voltage range, vl v 4.5 30 input voltage range, v+ v ref 3.6 v v ref 5.5 output adjustment range v 3.15 5.5 input voltage range, v cc v 1.086 1.114 output voltage, adj mode v 2.432 2.635 output voltage, fixed 2.5v mode v 3.195 3.497 output voltage, fixed 3.3v mode units min typ max parameter high or low, dh or dl dh or dl forced to 2v csh = csl = 5v, v+ = vl = v cc = gnd, either csh or csl input conditions ? 7 gate-driver on-resistance a 1 gate-driver sink/source current ? 10 current-sense input leakage current units min typ max parameter electrical characteristics (continued) (circuit of figure 1, v+ = 15v, sync = vl = v cc , i vl = 0ma, i ref = 0ma, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25?.) electrical characteristics (circuit of figure 1, v+ = 15v, sync = vl = v cc , i vl = 0ma, i ref = 0ma, t a =-40? to +85? , unless otherwise noted.) (note 1) v cc = 5v, i(vl) = 0 ? 60 regulator supply current (v+) v cc = 5v, i(vl) = 0, v+ = 4.5v (includes pnp base current) shdn = gnd, ovp = v cc ? 60 standby supply current (v+) i(vl) = 0 to 25ma, 6v < v+ < 30v v 4.7 5.3 i(vl) = 0 to 25ma, 5v < v+ < 30v vl output voltage rising edge, hysteresis = 25mv v 3.45 3.91 4.5 5.3 vl undervoltage lockout threshold 500 v cc = 5v, output not switching positive direction 2.0 mv 70 130 current-limit threshold v cc = 3.3v, output not switching 1.5 power consumption mw smps controller internal vl regulator and reference
max1636 low-voltage, precision step-down controller for portable cpu power _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v+ = 15v, sync = vl = v cc , i vl = 0ma, i ref = 0ma, t a = -40? to +85? , unless otherwise noted.) (note 1) fb, with respect to regulation point guaranteed by design sync = gnd sync = v cc % 3.5 10 oscillator frequency ns sync input pulse width high overvoltage trip threshold khz 240 340 sync input frequency range % ns 200 sync input rise/fall time ns 200 sync input pulse width low shdn , skip , ovp, sync shdn , skip , ovp, sync 200 falling edge (hysteresis = 1%) % of nominal output v 0.4 reset output voltage low v 0.8 v 170 230 2.4 270 330 logic input voltage high khz logic input voltage low % -7 -1.5 reset trip threshold catastrophic output undervoltage lockout threshold 60 80 i sink = 4ma high or low, dh or dl ? 7 gate-driver on-resistance conditions units min typ max parameter oscillator overvoltage protection inputs and outputs __________________________________________typical operating characteristics (circuit of figure 1, v in = 7v, t a = +25?, unless otherwise noted.) 100 50 1m 100m 1 10m 10 efficiency vs. load current (3.3v/3a circuit) 60 max1636 toc01 load current (a) efficiency (%) 70 80 90 v in = 22v v in = 30v v in = 7v v in = 15v 100 50 1m 100m 1 10m 10 efficiency vs. load current (5v/3a circuit) 60 max1636 toc02 load current (a) efficiency (%) 70 80 90 v in = 22v v in = 7v v in = 15v v in = 30v 100 50 1m 100m 1 10m 10 efficiency vs. load current (1.8v/1a circuit) 60 max1636 toc03 load current (a) efficiency (%) 70 80 90 v in = 15v v in = 7v v in = 22v note 1: specifications to -40? are guaranteed by design and not production tested.
50 100 75 150 125 225 200 175 250 150 250 200 300 350 400 450 500 max1636 toc11 f osc (khz) reset time delay (ms) reset time delay vs. osc frequency v out 50mv/div load current 0a 2a 4a load-transient response (3.3v/3a, pwm mode) max1636 toc12 100 s/div) 50 150 100 250 200 350 300 400 0 1.0 1.5 0.5 2.0 2.5 3.0 3.5 dropout voltage vs. load current max1636 toc10 load current (a) v in - v out (mv) v out forced to 4.95v max1636 low-voltage, precision step-down controller for portable cpu power 6 _______________________________________________________________________________________ 5 -5 1m 100m 1 10m 10 -3 max1636 toc07 load current (a) load regulation ? v out (mv) -1 1 3 -4 -2 0 2 4 load regulation vs. load current pwm mode v out = 5v _____________________________typical operating characteristics (continued) (circuit of figure 1, v in = 7v, t a = +25?, unless otherwise noted.) 100 50 1m 100m 1 10m 10 efficiency vs. load current (1.8v/4a circuit) 60 max1636 toc04 load current (a) efficiency (%) 70 80 90 v in = 7v v in = 22v v in = 15v 100 50 1m 100m 1 10m 10 efficiency vs. load current (1.8v/7a circuit) 60 max1636 toc05 load current (a) efficiency (%) 70 80 90 v in = 15v v in = 7v v in = 22v 1000 0.01 0152025 10 530 quiescent supply current vs. input voltage 0.10 max1636 toc06 input voltage (v) quiescent supply current (ma) 1 10 100 v out = 3.3v 0 10 5 15 30 35 25 20 40 0 10152025 5 3035404550 vl load-regulation error vs. vl load current max1636 toc08 vl load current (ma) load regulation ? v (mv) 0 0.3 0.2 0.1 0.4 0.5 0.6 040 30 10 20 50 60 70 80 90 100 ref load-regulation error vs. ref load current max1636 toc09 ref load current ( a) load regulation ? v (mv)
max1636 low-voltage, precision step-down controller for portable cpu power _______________________________________________________________________________________ 7 _____________________________typical operating characteristics (continued) (circuit of figure 1, v in = 7v, t a = +25?, unless otherwise noted.) v out 50mv/div 5a load current 0a 10a load-transient response (1.8v, pwm mode) max1636 toc13 100 s/div v out 20mv/div v lx inductor current 1a 0v 5v 0a switching waveforms (pwm mode) max1636 toc14 1 s/div v out 50mv/div v lx inductor current 1a 0v 5v 0a switching waveforms (pfm mode) max1636 toc15 20 s/div v out = 1.8v v out 1v/div v shdn 5v/div standby and startup response (v out = 1.8v, no load) max1636 toc17 1ms/div v out 20mv/div v lx inductor current 4a 0 5v 2a 0a switching waveforms (dropout operation) max1636 toc16 5 s/div v out = 5v v out 100mv/div v dl inductor current -5a 0 0 5v -10a overvoltage-protection waveforms (v in shorted to v out through a 0.5 ? resistor) max1636 toc18 10 s/div
max1636 low-voltage, precision step-down controller for portable cpu power 8 _______________________________________________________________________________________ pin description name function 1 csh current-sense input, high side 2 csl current-sense input, low side. also serves as a feedback input in fixed output modes. pin 3 reset timed reset output. low for at least 100ms after output voltage is valid, then goes high impedance (open drain). 4 shdn shutdown control input. puts chip in shutdown or standby mode, depending on ovp (table 5). 8 sync oscillator frequency select and synchronization input. tie to v cc for 300khz operation; tie to gnd for 200khz operation. 7 ref 1.100v reference output. capable of sourcing 50? for external loads; bypass with a 0.22? (min) capacitor. 6 cc compensation pin. connect a small capacitor to gnd to set the integration time constant. 5 ovp overvoltage protection enable/disable. tie to gnd to disable ovp; tie to v cc to enable ovp. 13 v+ 5v vl linear-regulator input. the vl linear regulator automatically shuts off if v+ is shorted to v l . bypass v+ to gnd with a 0.1? capacitor close to the ic. 12 v cc main supply voltage input. powers the pwm controller, logic, and reference. input range is +3.15v to +5.5v. 11 fb feedback input. tie to gnd for fixed 3.3v output; tie to v cc for fixed 2.5v output; tie to resistor divider for adjustable mode. 9, 10 gnd analog ground 15 dl low-side gate-driver output 14 vl 5v linear-regulator output. powers the dl low-side gate driver. bypass with a 2.2? (min) capacitor. 20 skip low-noise mode control. forces fixed-frequency pwm operation when high. 19 lx inductor connection 18 dh high-side gate-driver output 17 bst boost-capacitor connection 16 pgnd power ground standard application circuit the basic max1636 buck converter (figure 1) is easily adapted to meet a wide range of applications with inputs up to 30v by substituting components from table 1. these circuits represent a good set of trade- offs between cost, size, and efficiency, while staying within the worst-case specification limits for stress- related parameters, such as capacitor ripple current. do not change the circuits?switching frequency without first recalculating component values (particularly induc- tance value at maximum battery voltage). adding a schottky rectifier across the synchronous rectifier improves circuit efficiency by approximately 1%. this rectifier is otherwise not needed because the mosfet required typically incorporates a high-speed silicon diode from drain to source. use a schottky rectifier rated at a dc current equal to at least one-third of the load current.
max1636 low-voltage, precision step-down controller for portable cpu power _______________________________________________________________________________________ 9 table 1. component selection for standard applications component load current input voltage range 7v to 22v 7v to 22v 7v to 22v 4.75v to 30v 6v to 30v output voltage range 1.8v 1.8v 1.25v to 2v 3.3v 5v application cpu i/o cpu core cpu core frequency 300khz 300khz 300khz 300khz 300khz q1 high-side mosfet 1/2 si4902dy or 1/2 mmdf3no3hd international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy international rectifier irf7403 or siliconix si9804dy international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy q2 low-side mosfet 1/2 si4902dy or 1/2 mmdf3no3hd international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy fairchild fds6680 or siliconix si4420dy international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy international rectifier irf7413, fairchild nds8410a, or siliconix si4410dy c1 input capacitor 4.7?, 25v ceramic tokin c34y5u1e475z or marcon/united chemicon thcr40e1e475z 2 x 10?, 25v ceramic tokin c34y5u1e106z or marcon/united chemicon thcr50e1e106zt 4 x 10?, 25v ceramic tokin c34y5u1e106z or marcon/united chemicon thcr50e1e106zt 2 x 22?, 35v avx tpse226m035r0300 or sprague 593d226x0035e2w 2 x 22?, 35v avx tpse226m035r0300 or sprague 593d226x0035e2w c2 output capacitor 220?, 6.3v tantalum sprague 595d227x96r3c2 2 x 470?, 4v low-esr sprague 594d477x0004r2t 4 x 390?, 6.3v low- esr, sprague 594d397x06r3r2t, or 4 x 470?, 4v sprague 594d477x0004r2t 2x 220? sprague 594d 594d227x0010d2t 2x 220? sprague 594d 594d227x0010d2t r1 resistor 0.070 ? , 1% (1206) dale wsl-1206-r070f 0.015 ? , 1% (2512) dale wsl-2512-r015f 0.010 ? , 1% (2512) dale wsl-2512-r010f 0.020 ? , 1% (2010) dale wsl-2010-r020f 0.020 ? , 1% (2010) dale wsl-2010-r020f l1 inductor 15? sumida cd54-150 4.6? panasonic etqp1f4r6h, sumida cdrh127-4r7, coiltronics up2-4r7, or coilcraft do3316p-472 2.2? panasonic p1f2r0hl, sumida cdrh127-2r4, coiltronics up4-2r2, or coilcraft do5022p-222hc 10? sumida cdrh125-100, coiltronics up2-100, or coilcraft do3316-103 10? sumida cdrh125-100, coiltronics up2-100, or coilcraft do3316-103 1a 4a 7a (ev kit) 3a 3a
irc (1) 512-992-3377 (512) 992-7900 detailed description the max1636 is a bicmos, switch-mode, power-sup- ply controller designed primarily for buck-topology reg- ulators in battery-powered applications where high efficiency and low quiescent supply current are critical. light-load efficiency is enhanced by automatic idle mode operation, a variable-frequency, pulse-skipping mode that reduces transition and gate-charge losses. the step-down, power-switching circuit consists of two n-channel mosfets, a rectifier, and an lc output filter. the output voltage is the average ac voltage at the switching node, which is regulated by changing the duty cycle of the mosfet switches. the gate-drive sig- nal to the n-channel high-side mosfet, which must exceed the battery voltage, is provided by a flying- capacitor boost circuit that uses a 100nf capacitor between bst and lx. the max1636 contains 10 major circuit blocks (figure 2). the pulse-width-modulation (pwm) controller consists of a dual mode feedback network and multiplexer, a multi-input pwm comparator, high-side and low-side gate drivers, and logic. the max1636 contains fault- protection circuits that monitor the pwm output for undervoltage and overvoltage. bias generator blocks include the 5v (vl) linear regulator and the 1.1v preci- sion reference. the pwm uses a 200khz/300khz syn- chronizable oscillator. the circuit blocks are powered from an internal ic power rail that receives power from either vl or v cc . the synchronous-switch gate driver is powered directly from vl, while the high-side-switch gate driver is powered indirectly from vl via an external diode-capacitor boost circuit. max1636 low-voltage, precision step-down controller for portable cpu power 10 ______________________________________________________________________________________ (619) 661-6835 (81) 7-2070-1174 sanyo tokin (408) 432-8020 (847) 390-4373 (1) 408-434-0375 (1) 847-390-4428 tdk sprague (847) 956-0666 (81) 3-3607-5144 sumida (603) 224-1961 (714) 373-7939 (408) 988-8000 (1) 714-373-7183 panasonic (1) 603-224-1430 (1) 408-970-3950 siliconix (602) 303-5454 (1) 602-994-6430 motorola company central semiconductor matsuo fairchild (408) 721-2181 (1) 408-721-1635 (714) 969-2491 (512) 992-7900 (1) 714-960-6492 (1) 512-992-3377 irc dale (310) 322-3331 (1) 310-322-3332 international rectifier (ir) (605) 668-4131 (847) 639-6400 (561) 241-7876 (1) 847-639-1469 coilcraft (1) 605-665-1627 (1) 561-241-9339 coiltronics usa phone (516) 435-1110 (803) 946-0690 factory fax (country code) (1) 516-435-1824 (1) 803-626-3123 avx table 2. component suppliers figure 1. standard application circuit max1636 v+ 0.1 f power input 0.1 f 1 f 1nf c1 q1 cmpsh-3 q2 c2 l1 * r1 r2 r3 output 4.7 f shdn *see rectifier clamp diode section skip dl pgnd lx dh bst ovp vl v cc sync csh csl fb 10k v cc cc gnd gnd reset ref (847) 696-2000 (1) 847-696-9278 marcon/united chemi-con dual mode is a trademark of maxim integrated products.
max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 11 ref v cc ic power 200khz to 300khz osc pwm logic to vl input vl ref shdn v+ sync dl pgnd lx dh bst skip vl csh csl fb cc ref 0.2v gnd power good v ref -5% v ref +7% v ref -30% + 60khz lp filter shutdown control 1.1v ref. power switchover timer error integrator - + - + - ++ - + - + - reset ovp max1636 gm overvoltage fault under- voltage fault off slope compensation 5v linear reg. figure 2. functional diagram
pwm controller the heart of the current-mode pwm controller is a multi-input, open-loop comparator that sums four sig- nals: the output voltage error signal with respect to the reference voltage, the current-sense signal, the inte- grated voltage-feedback signal, and the slope- compensation ramp (figure 3). the pwm controller is a direct-summing type, lacking a traditional error amplifier and the phase shift associat- ed with it. this direct-summing configuration approach- es ideal cycle-by-cycle control over the output voltage (figure 4). when skip = low, idle mode circuitry automatically optimizes efficiency throughout the load-current range. idle mode dramatically improves light-load efficiency max1636 low-voltage, precision step-down controller for portable cpu power 12 ______________________________________________________________________________________ low light idle load current pulse-skipping, discontinuous inductor current mode description pwm high light pwm constant-frequency pwm, continuous inductor current pwm high heavy constant-frequency pwm, continuous inductor current low heavy constant-frequency pwm, continuous inductor current s s k k i i p p table 3. s s k k i i p p pwm table shoot- through control r q 30mv rq level shift 1x gm 2x osc level shift current limit synchronous rectifier control shdn ck -100mv csh csl cc ref fb bst dh lx vgg dl pgnd s s slope compensation skip counter dac soft-start figure 3. pwm controller functional diagram
max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 13 by reducing the effective frequency, subsequently reducing switching losses. it forces the peak inductor current to ramp to 30% of the full current limit, deliver- ing extra energy to the output and allowing subsequent cycles to be skipped. idle mode transitions seamlessly to fixed-frequency pwm operation as load current increases. with skip = high, the controller always operates in fixed-frequency pwm mode for lowest noise. each pulse from the oscillator sets the main pwm latch that turns on the high-side switch for a period determined by the duty factor (approximately v out / v in ). as the high-side switch turns off, the synchronous rectifier latch sets; 60ns later, the low-side switch turns on. the low-side switch stays on until the beginning of the next clock cycle. in pwm mode, the controller operates as a fixed-fre- quency, current-mode controller in which the duty fac- tor is set by the input/output voltage ratio. the current-mode feedback system regulates the peak inductor current value as a function of the output volt- age error signal. in continuous-conduction mode, the average inductor current is nearly the same as the peak current, so the circuit acts as a switch-mode transconductance amplifier. this pushes the second output lc filter pole, normally found in a duty-factor- controlled (voltage-mode) pwm, to a higher frequency. to preserve inner-loop stability and eliminate regenera- tive inductor current ?taircasing,?a slope-compensa- tion ramp is summed into the main pwm comparator to make the apparent duty factor less than 50%. the relative gains of the voltage-sense and current- sense inputs are weighted by the values of current sources that bias four differential input stages in the main pwm comparator (figure 4). the voltage sense into the pwm has been conditioned by an integrated component of the feedback voltage, yielding excellent dc output voltage accuracy. see the output voltage accuracy section for more information. synchronous rectifier driver (dl) synchronous rectification reduces conduction losses in the rectifier by shunting the normal schottky catch diode with a low-resistance mosfet switch. also, the synchronous rectifier ensures proper start-up of the boost gate-driver circuit. if the synchronous power mosfet is omitted for cost or other reasons, replace it with a small-signal mosfet, such as a 2n7002. if the circuit is operating in continuous-conduction mode, the dl drive waveform is simply the comple- ment of the dh high-side-drive waveform (with con- trolled dead time to prevent cross-conduction or ?hoot-through?. in discontinuous (light-load) mode, the synchronous switch is turned off as the inductor current falls through zero. fb ref csh csl cc ref slope compensation v cc i2 r1 r2 to pwm logic output driver uncompensated high-speed level translator and buffer i1 i3 i4 v bias figure 4. main pwm comparator functional diagram
max1636 ref and vl supplies and v cc input the 1.1v reference (ref) is accurate to ?% over tem- perature, making ref useful as a precision system ref- erence. bypass ref to gnd with a 0.22? (min) capacitor. ref can supply up to 50? for external loads. loading ref reduces the main output voltage slightly because of the reference load-regulation error. the 5v vl linear-regulator output can be tied to the system +5v supply in order to obtain gate-drive power from an efficient source. the two supply pins (v cc and vl) are independent of each other (no protection diodes or sequencing requirements), allowing you to choose the most efficient sources for chip biasing from among existing system supply voltages without having to worry about sequencing or latch-up problems (table 4). the v cc input runs the chip if the v cc voltage is greater than 3.15v. otherwise, the chip supply is pow- ered from vl via the internal v cc -vl switchover circuit. if a system supply between 3.3v and 5v is not avail- able, tie v cc directly to vl. in shutdown mode, the vl regulator and reference are completely turned off. in standby mode, the vl regula- tor and dl stay alive so that the overvoltage-protection circuit can operate (table 5). important: ensure that vl and v cc do not exceed 6v. measure vl with the main output fully loaded. if it is pumped above 5.5v, either excessive boost-diode capacitance or excessive ripple at v+ is the probable cause. use only small-signal diodes for the boost cir- cuit (10ma to 100ma schottky or 1n4148 are pre- ferred) and bypass vl to pgnd with a 4.7? capacitor directly at the package pins. shutdown and standby modes holding shdn low puts the ic into its 3? shutdown mode. shdn is a logic input with a threshold of about 1v (the vth of an internal n-channel mosfet). for automatic start-up, tie shdn to v+. standby operation is entered when shdn = low and ovp = high (table 5). in standby mode, the vl regula- tor stays active, and the dl output is forced high to provide overvoltage protection by clamping the output to gnd. however, dl is not forced high until the output sags below v ref , so that the output can be held high by external keep-alive supplies. reset power-good voltage monitor the power-good monitor generates a system-reset sig- nal. the reset output is an open drain that needs to be pulled up to the appropriate logic supply. at first power-up, reset is held low until output is in regula- tion. at this point, an internal timer begins counting oscillator pulses, and reset continues to be held low until 32,000 cycles have elapsed. after this timeout period (107ms at 300khz or 160ms at 200khz), the reset output is released. output undervoltage lockout the output undervoltage-lockout circuit is similar to foldback current limiting but employs a timer rather than a variable current limit. the smps has an under- voltage-protection circuit that is activated 6144 clock cycles after the smps is enabled. if the smps output is under 70% of the nominal value, output is latched off and does not restart until shdn is toggled or until v+ power is cycled below 1v. note that undervoltage pro- tection can make prototype troubleshooting difficult, since only 20ms or 30ms elapse before the smps is latched off. the output undervoltage lockout circuit protects against heavy overloads and shorts to the main smps output. the circuit trips if the output is less than 70% of the nominal output value any time after the timeout has expired upon start-up. when the comparator trips, the output is turned off (the smps stops switching). this state is similar to thermal shutdown and can be exited by a power-on reset or by a rising edge on shdn . the overvoltage crowbar is disabled in output undervoltage or thermal shutdown modes. low-voltage, precision step-down controller for portable cpu power 14 ______________________________________________________________________________________ available power sources v cc connects to v+ connects to vl connects to comment battery, 3.3v, and 5v 3.3v 5v 5v most efficient battery and 5v 5v 5v 5v battery and 3.3v 3.3v battery bypass capacitor only battery only vl battery bypass capacitor only least efficient table 4. powering the max1636
output overvoltage protection (ovp) the overvoltage crowbar protection circuit is intended to blow a fuse in series with the battery if the main smps output rises significantly higher than its preset level. in normal operation, the output is compared to the internal precision reference voltage. if the output goes 7% above nominal, the synchronous rectifier mosfet turns on 100% (the high-side mosfet is simultaneously forced off) in order to draw massive amounts of battery current to blow the fuse. this safety feature does not protect the system against a failure of the controller ic itself but is intended primarily to guard against a short across the high-side mosfet. a crow- bar event is latched and can only be reset by a rising edge on shdn (or by removal of the v+ supply volt- age). the overvoltage-detection decision is made rela- tive to the regulation point. the overvoltage comparators are kept inactive in standby mode. instead, the dl driver is simply left in the high state. however, dl does not turn on until the output has decayed to less than 1v. this prevents con- flicts in systems where the output is held up by an external source in suspend or backup mode. the ovp pin has an internal pulldown resistor that is only turned on during the reset phase. the ovp pin? state is then sampled and stored internally. a floating ovp pin implies no overvoltage protection. boost high-side gate-drive supply (bst) gate-drive voltage for the high-side n-channel switch is generated by a flying-capacitor boost circuit (figure 2). the capacitor between bst and lx is alternately charged from the vl supply and placed parallel to the high-side mosfet's gate-source terminals. on start-up, the synchronous rectifier (low-side mos- fet) forces lx to 0v and charges the boost capacitor to 5v. on the second half-cycle, the smps turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary enhancement voltage to turn on the high-side switch, an action that boosts the 5v gate-drive signal above the battery voltage. max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 15 mode s s h h d d n n ovp how entered status notes output uvlo high run high high all circuit blocks active normal operation don? care v out < 70% of nominal after 20?0ms timeout expires standby low high vl = on ref = off dl = high reset = high-z (high state) dl = high to enforce overvoltage protection vl = on ref = off dl = low reset = low cycling shdn or a power-on reset exits output uvlo. shutdown low low all circuit blocks inactive lowest possible quiescent consumption thermal shutdown high overvoltage (crowbar) high high v out > 7% too high vl = on ref = off dl = high reset = low cycling shdn or a power-on reset exits crowbar. high t j > +150? vl = on ref = off dl = high reset = low cycling shdn or a power-on reset exits thermal shutdown. thermal shutdown high low t j > +150? all circuit blocks inactive cycling shdn or a power-on reset exits thermal shutdown. table 5. operating modes
max1636 ringing at the high-side mosfet gate (dh) in discon- tinuous-conduction mode (light loads) is a natural oper- ating condition. it is caused by residual energy in the tank circuit, formed by the inductor and stray capaci- tance at the switching node, lx. the gate-drive nega- tive rail is referred to lx, so any ringing there is directly coupled to the gate-drive output. current-limiting and current-sense inputs (csh and csl) the current-limit circuit resets the main pwm latch and turns off the high-side mosfet switch whenever the voltage difference between csh and csl exceeds 100mv. this limiting is effective for both current flow directions, putting the threshold limit at ?00mv. the tolerance on the positive current limit is ?0%, so the external low-value sense resistor (r1) must be sized for 80mv/i peak , where i peak is the required peak inductor current to support the full load current. components must be designed to withstand continuous current stresses of 120mv/r1. for breadboarding or for very high current applications, it may be useful to wire the current-sense inputs with a twisted pair rather than pc traces (two pieces of wrapped wire twisted together are sufficient.) this reduces the noise picked up at csh and csl, which can cause unstable switching and reduced output cur- rent. oscillator frequency and synchronization (sync) the sync input controls the oscillator frequency. low selects 200khz; high selects 300khz. sync can also be used to synchronize with an external 5v cmos or ttl clock generator. sync has a guaranteed 240khz to 340khz capture range. a high-to-low transition on sync initiates a new cycle. operation at 300khz optimizes the application circuit for component size and cost. operation at 200khz pro- vides increased efficiency, lower dropout, and improved load-transient response at low input-output voltage differences (see the low-voltage operation section). output voltage accuracy (gnd, cc) output voltage error is guaranteed to be within ?% over all conditions of line, load, and temperature. the dc load regulation is typically better than 0.1% due to the integrator amplifier. transient response is optimized by providing a feedback signal that has a direct path from the output to the main summing pwm comparator. the integrated feedback signal is also summed into the pwm comparator, with the gain weighted so that the integrated signal has only enough gain to correct the dc inaccuracies. the integrator? response time is determined by the time constant set by the capacitor placed on the cc pin. the time constant should not be so fast that the integrator responds to the normal v out ripple or too slow to negate the integrator? effect. a 470pf to 1500pf cc capacitor is sufficient for 200khz to 300khz frequencies. figure 5 shows the output voltage response to a 0a to 3a load transient with and without the integrator. with the integrator, the output voltage returns to within 0.1% of its no-load value with only a small ac excursion. without the integrator, the typical load-transient response with the ac and dc output voltage changes. asymmetrical clamping at the integrator output pre- vents worsening of load transients during pulse- skipping mode. internal digital soft-start circuit soft-start allows a gradual increase of the internal cur- rent-limit level at start-up to reduce input surge cur- rents. the smps contains an internal digital soft-start circuit controlled by a counter, a digital-to-analog con- verter (dac), and a current-limit comparator. in shut- down or standby mode, the soft-start counter is reset to zero. when the smps is enabled, its counter starts counting oscillator pulses, and the dac begins incre- menting the comparison voltage applied to the current- limit comparator. the dac output increases from 0mv to 100mv in five equal steps as the count increases to 512 clocks. as a result, the main output capacitor charges up relatively slowly. the exact time of the out- put rise depends on output capacitance and load cur- rent, but it is typically 1ms with a 300khz oscillator. overload and dropout operation dropout (low input-output differential) operation is enhanced by stretching the clock pulse width to increase the maximum duty factor. the algorithm fol- lows: if the output voltage (v out ) drops out of regula- tion without the current limit having been reached, the smps skips an off-time period (extending the on-time). at the end of the cycle, if the output is still out of regula- tion, the smps skips another off-time period. this action can continue until three off-time periods are skipped, effectively dividing the clock frequency by as much as four. this behavior also slightly improves load- transient response. dividing the clock frequency by four raises the maximum duty factor to above 98%. the typical pwm minimum off-time is 300ns, regardless of the operating frequency. low-voltage, precision step-down controller for portable cpu power 16 ______________________________________________________________________________________
adjustable-output feedback (dual-mode fb) a fixed, preset output voltage of 2.5v and 3.3v is selected when fb is connected to v cc or ground. in this mode, internal resistors monitor the voltage on csl. for voltages other than the fixed-output options, adjust the output voltage through a resistor divider con- nected to fb (figure 2). calculate the output voltage with the following formula: v out = v ref (1 + r1 / r2) where v ref = 1.1v nominal. recommended normal val- ues for r2 range from 5k ? to 100k ? . to achieve a 1.1v nominal output, simply connect fb directly to csl. remote output voltage sensing is not possible in fixed output mode due to the combined nature of the volt- age-sense and current-sense inputs (csl). it is, howev- er, easy to do in adjustable mode by using the top of the external resistor divider as the remote sense point. low-noise operation (pwm mode) pwm mode ( skip = high) minimizes rf and audio interference in noise-sensitive applications such as hi-fi multimedia-equipped systems, cellular phones, rf communicating computers, and electromagnetic pen- entry systems. see the summary of operating modes in table 5. skip can be driven from an external logic signal. pwm mode forces a constant switching frequency, reducing interference due to switching noise by con- centrating the emissions at a known frequency outside the system audio or if bands. choose an oscillator fre- quency for which switching frequency harmonics do not overlap a sensitive frequency band. if necessary, synchronize the oscillator to a tight-tolerance external clock generator. to extend the output voltage-regula- tion range, constant operating frequency is not main- tained under overload or dropout conditions (see the overload and dropout operation section). pwm mode ( skip = high) forces two changes on the pwm controller. first, it disables the minimum-current comparator, ensuring fixed-frequency operation. second, it changes the detection threshold for reverse- current limit from 0mv to -100mv, allowing the inductor current to reverse at light loads. this results in fixed-fre- quency operation and continuous inductor-current flow. pwm mode eliminates discontinuous-mode inductor ringing and improves cross-regulation of transformer- coupled, multiple-output supplies. in most applications, tie skip to gnd to minimize qui- escent supply current. vl supply current with skip high is typically 20ma, depending on external mosfet gate capacitance and switching losses. max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 17 0 2 4 -50 50 i out (a) v out (mv) (100 s/div) cc = ref v out = 3.3v integrator defeated 0 2 4 -50 50 i out (a) v out (mv) (100 s/div) cc = 470pf v out = 3.3v integrator active figure 5a. load-transient response with integrator active figure 5b. load-transient response with integrator defeated low-voltage, precision step-down controller for portable cpu power
max1636 design procedure the five predesigned standard application circuits (figure 1 and table 1) contain ready-to-use solutions for common application needs. use the following design procedure to optimize these basic schematics for different voltage or current requirements. but before beginning a design, firmly establish the following: maximum input (battery) voltage, v in(max) . this value should include the worst-case conditions, such as no-load operation when a battery charger or ac adapter is connected but no battery is installed. v in(max) must not exceed 30v. minimum input (battery) voltage, v in(min) . this should be taken at full load under the lowest battery condi- tions. if v in(min) is less than 4.5v, use an external cir- cuit to externally hold vl above the vl undervoltage lockout threshold. if the minimum input-output differ- ence is less than 1.5v, the filter capacitance required to maintain good ac load regulation increases (see low-voltage operation section). inductor value the exact inductor value is not critical and can be freely adjusted to make trade-offs between size, cost, and efficiency. lower inductor values minimize size and cost but reduce efficiency due to higher peak-cur- rent levels. the smallest inductor is achieved by lower- ing the inductance until the circuit operates at the border between continuous and discontinuous mode. further reducing the inductor value below this crossover point results in discontinuous-conduction operation even at full load. this helps lower output filter capacitance requirements, but efficiency suffers due to high i 2 r losses. on the other hand, higher inductor val- ues mean greater efficiency, but resistive losses due to extra wire turns eventually exceed the benefit gained from lower peak-current levels. also, high inductor val- ues can affect load-transient response (see the v sag equation in the low-voltage operation section). the equations in this section are for continuous-conduction operation. three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant, lir, which is the ratio of inductor peak-to- peak ac current to dc load current. a higher lir value allows smaller inductance but results in higher losses and higher ripple. a good compromise between size and losses is a 30% ripple-current to load-current ratio (lir = 0.3), which corresponds to a peak inductor cur- rent 1.15 times higher than the dc load current. l = v out (v in(max) - v out ) / (v in(min) x f x i out x lir) where f = switching frequency, normally 200khz or 300khz, and i out = maximum dc load current. the peak current can be calculated by: i peak = i load + [v out (v in(max) - v out ) / (2 x f x l x v in(max) )] the inductor's dc resistance should be low enough that r dc x i peak < 100mv, as it is a key parameter for efficiency performance. if a standard, off-the-shelf inductor is not available, choose a core with an li 2 rat- ing greater than l x i peak 2 and wind it with the largest diameter wire that fits the winding area. for 300khz applications, ferrite-core material is strongly preferred; for 200khz applications, kool-mu (aluminum alloy) or even powdered iron is acceptable. if light-load efficien- cy is unimportant (in desktop pc applications, for example), then low-permeability iron-powder cores may be acceptable, even at 300khz. for high-current appli- cations, shielded-core geometries, such as toroidal or pot core, help keep noise, emi, and switching-wave- form jitter low. current-sense resistor value the current-sense resistor value is calculated accord- ing to the worst-case, low-current-limit threshold volt- age (from the electrical characteristics table) and the peak inductor current: r sense = 80mv / i peak use i peak from the second equation in the inductor value section. use the calculated value of r sense to size the mosfet switches and specify inductor satura- tion-current ratings according to the worst-case high- current-limit threshold voltage: i peak = 120mv / r sense low-inductance resistors, such as surface-mount metal film, are recommended. input capacitor value connect low-esr bulk capacitors directly to the drain on the high-side mosfet. the bulk input filter capaci- tor is usually selected according to input ripple current requirements and voltage rating, rather than capacitor value. electrolytic capacitors with low enough equiva- lent series resistance (esr) to meet the ripple-current requirement invariably have sufficient capacitance val- ues. aluminum electrolytic capacitors, such as sanyo os-con or nichicon pl, are superior to tantalum types, which risk power-up surge-current failure, espe- cially when connecting to robust ac adapters or low- impedance batteries. rms input ripple current (i rms ) is low-voltage, precision step-down controller for portable cpu power 18 ______________________________________________________________________________________ kool-mu is a registered trademark of magnetics, inc.
determined by the input voltage and load current, with the worst case occurring at v in = 2 x v out : therefore, when v in is 2 x v out : i rms = i load / 2 output filter capacitor value the output filter capacitor values are generally deter- mined by the esr and voltage-rating requirements rather than actual capacitance requirements for loop stability. in other words, the low-esr electrolytic capac- itor that meets the esr requirement usually has more output capacitance than is required for ac stability. use only specialized low-esr capacitors intended for switching-regulator applications, such as avx tps, sprague 595d, sanyo os-con, or nichicon pl series. to ensure stability, the capacitor must meet both mini- mum capacitance and maximum esr values as given in the following equations: c out > v ref (1 + v out / v in(min) ) / v out x r sense x f r esr < r sense x v out / v ref where r esr can be multiplied by 1.5, as discussed below. these equations are worst case, with 45 degrees of phase margin to ensure jitter-free, fixed-frequency operation, and provide a nicely damped output response for zero to full-load step changes. some cost- conscious designers may wish to bend these rules with less-expensive capacitors, particularly if the load lacks large step changes. this practice is tolerable if some bench testing over temperature is done to verify acceptable noise and transient response. no well-defined boundary exists between stable and unstable operation. as phase margin is reduced, the first symptom is timing jitter, which shows up as blurred edges in the switching waveforms where the scope does not quite sync up. technically speaking, this jitter (usually harmless) is unstable operation, since the duty factor varies slightly. as capacitors with higher esrs are used, the jitter becomes more pronounced, and the load-transient output voltage waveform starts looking ragged at the edges. eventually, the load-transient waveform has enough ringing on it that the peak noise levels exceed the allowable output voltage tolerance. note that even with zero phase margin and gross insta- bility, the output voltage noise never gets much worse than i peak x r esr (under constant loads). designers of rf communicators or other noise-sensi- tive analog equipment should be conservative and stay within the guidelines. designers of notebook computers and similar commercial-temperature-range digital sys- tems can multiply the r esr value by a factor of 1.5 without hurting stability or transient response. the output voltage ripple, which is usually dominated by the filter capacitor? esr, can be approximated as i ripple x r esr . there is also a capacitive term, so the full equation for ripple in continuous-conduction mode is v noise(p-p) = i ripple x [r esr + 1 / (2 x p x f x c out )]. in idle mode, the inductor current becomes discontinuous, with high peaks and widely spaced pulses, so the noise can actually be higher at light load (compared to full load). in idle mode, calculate the out- put ripple as follows: selecting other components mosfet switches the high-current n-channel mosfets must be logic- level types with guaranteed on-resistance specifica- tions at vgs = 4.5v. lower gate-threshold specifications are better (i.e., 2v max rather than 3v max). drain-source breakdown voltage ratings must at least equal the maximum input voltage, preferably with a 20% derating factor. the best mosfets have the lowest on-resistance per nanocoulomb of gate charge. multiplying r ds(on) by q g provides a good figure of merit for comparing various mosfets. newer mosfet process technologies with dense cell structures gener- ally perform best. the internal gate drivers tolerate >100nc total gate charge, but 70nc is a more practical upper limit to maintain best switching times. in high-current applications, mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the greatest heat contributor for both high-side and low-side mosfets. i 2 r losses are distributed between q1 and q2 according to duty fac- tor as shown in the equations below. generally, switch- ing losses affect only the upper mosfet, since the schottky rectifier usually clamps the switching node before the synchronous rectifier turns on. gate-charge losses are dissipated by the driver and do not heat the mosfet. calculate the temperature rise according to package thermal-resistance specifications to ensure v 0.02 x r r 0.0003 x l x 1/v 1/ v v r x c noise(p p) esr sense out in out sense 2 f ? =+ +? () [] () ii vvvv rms load out in out in = ? () / max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 19
max1636 low-voltage, precision step-down controller for portable cpu power 20 ______________________________________________________________________________________ that both mosfets are within their maximum junction temperature at high ambient temperature. the worst- case dissipation for the high-side mosfet occurs at both extremes of input voltage, and the worst-case dis- sipation for the low-side mosfet occurs at maximum input voltage. duty = (v out + v q2 ) / (v in - v q1 ) pd (upper fet) = i load 2 x r ds(on) x duty + v in x i load x f x [(v in x c rss ) / i gate + 20ns] pd (lower fet) = i load 2 x r ds(on) x (1 - duty) where on-state voltage drop v q = i load x r ds(on) , c rss = mosfet reverse transfer capacitance, i gate = dh driver peak output current capability (1a typ), and 20ns = dh driver inherent rise/fall time. the max1636? output undervoltage shutdown protects the synchro- nous rectifier under output short-circuit conditions. to reduce emi, add a 0.1? ceramic capacitor from the high-side switch drain to the low-side switch source. rectifier clamp diode the rectifier is a clamp across the low-side mosfet that catches the negative inductor swing during the 60ns dead time between turning one mosfet off and each low-side mosfet on. the latest generations of mosfets incorporate a high-speed silicon body diode, which serves as an adequate clamp diode if efficiency is not of primary importance. a schottky diode can be placed in parallel with the body diode to reduce the forward voltage drop, typically improving efficiency 1% to 2%. use a diode with a dc current rat- ing equal to one-third of the load current; for example, use an mbr0530 (500ma-rated) type for loads up to 1.5a, a 1n5819 type for loads up to 3a, or a 1n5822 type for loads up to 10a. the rectifier? rated reverse- breakdown voltage must be at least equal to the maxi- mum input voltage, preferably with a 20% derating factor. boost-supply diode a signal diode such as a 1n4148 works well in most applications. if the input voltage can go below +6v, use a small (20ma) schottky diode for slightly improved efficiency and dropout characteristics. do not use large power diodes, such as 1n5817 or 1n4001, since high junction capacitance can pump up vl to excessive voltages. low-voltage operation low input voltages and low input-output differential voltages each require extra care in their design. low absolute input voltages can cause the vl linear regula- tor to enter dropout and eventually shut itself off. low v in - v out differentials can cause the output voltage to sag when the load current changes abruptly. the sag? amplitude is a function of inductor value and maximum duty factor (d max , an electrical characteristics parameter, 98% guaranteed over temperature at f = 200khz) as follows: table 6 is a low-voltage troubleshooting guide. the cure for low-voltage sag is to increase the output capacitor? value. for example, at v in = +5.5v, v out = 5v, l = 10?, f = 200khz, and i step = 3a, a total capacitance of 660? keeps the sag less than 200mv. note that only the capacitance requirement increases; the esr requirements do not change. therefore, the added capacitance can be supplied by a low-cost bulk capacitor in parallel with the normal low-esr capacitor. __________applications information heavy-load efficiency considerations the major efficiency-loss mechanisms under loads are as follows, in the usual order of importance: p(i 2 r) = i 2 r losses p(tran) = transition losses p(gate) = gate-charge losses p(diode) = diode-conduction losses p(cap) = capacitor esr losses p(ic) = losses due to the ic? operating supply current inductor core losses are fairly low at heavy loads because the inductor? ac current component is small. therefore, they are not accounted for in this analysis. ferrite cores are preferred, especially at 300khz, but powdered cores, such as kool-mu, can also work well. efficiency = p out / p in x 100% = p out / (p out + p total ) x 100% p total = p(i 2 r) + p(tran) + p(gate) + p(diode) + p(cap) + p(ic) p = (i 2 r) = (i load ) 2 x (r dc + r ds(on) +r sense ) v ixl xc v xd v sag step f in min max out () ( ) () = ? 2 2
where r dc is the dc resistance of the coil, r ds(on) is the mosfet on-resistance, and r sense is the current- sense resistor value. the r ds(on) term assumes identi- cal mosfets for the high-side and low-side switches because they time-share the inductor current. if the mosfets are not identical, their losses can be estimat- ed by averaging the losses according to duty factor. pd(tran) = transition loss = v in x i load x f x 3/2 x [(v in c rss / i gate ) + 20ns] where c rss is the reverse transfer capacitance of the high-side mosfet (a data-sheet parameter), i gate is the dh gate-driver peak output current (1.5a typ), and 20ns is the rise/fall time of the dh driver (20ns typ). p(gate) = q g x f x vl where vl is the internal logic-supply voltage (+5v), and q g is the sum of the gate-charge values for low-side and high-side switches. for matched mosfets, q g is twice the data-sheet value of an individual mosfet. if v out is set to less than 4.5v, replace vl in this equa- tion with v batt . in this case, efficiency can be improved by connecting vl to an efficient 5v source, such as the system +5v supply. p(diode) = diode conduction losses = i load x v fwd x t d x f where t d is the diode-conduction time (120ns typ), and v fwd is the forward voltage of the diode. this power is dissipated in the mosfet body diode if no external schottky diode is used. p(cap) = input capacitor esr loss = i rms 2 x r esr where i rms is the input ripple current as calculated in the input capacitor value section. light-load efficiency considerations under light loads, the pwm operates in discontinuous mode, where the inductor current discharges to zero at some point during the switching cycle. this makes the inductor current? ac component high compared to the load current, which increases core losses and i 2 r loss- es in the output filter capacitors. for best light-load effi- ciency, use mosfets with moderate gate-charge levels and use ferrite, mpp, or other low-loss core mate- rial. avoid powdered-iron cores; even kool-mu (aluminum alloy) is not as good as ferrite. pc board layout considerations good pc board layout is required in order to achieve specified noise, efficiency, and stable performance. the pc board layout artist must be given explicit instructions, preferably a pencil sketch showing the placement of power-switching components and high- current routing. see the pc board layout in the max1636 evaluation kit manual for examples. a ground plane is essential for optimum performance. in most applications, the circuit will be located on a multi-layer board, and full use of the four or more copper layers is recommended. use the top layer for high-current max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 21 condition low v in -v out differential, <1v maximum duty-cycle limits exceeded. low v in -v out differential, <1.5v dropout voltage is too high (v out follows v in as v in decreases) reduce operation to 200khz. reduce mosfet on-resistance and coil dcr. symptom low v in -v out differential, <0.5v root cause normal function of internal low-dropout circuitry. unstable?itters between different duty factors and frequencies limited inductor-current slew rate per cycle. increase the minimum input voltage or ignore. low input voltage, <4.5v vl output is so low that it hits the vl uvlo threshold. low input voltage, <5v won? start under load or quits before battery is completely dead supply vl from an external source other than v in , such as the system +5v supply. vl linear regulator is going into dropout and isn? provid- ing good gate-drive levels. solution poor efficiency use a small 20ma schottky diode for boost diode. supply vl from an external source. sag or droop in v out under step-load change increase bulk output capacitance per formula (see low-voltage operation section). reduce inductor value. table 6. low-voltage troubleshooting chart
max1636 connections, the bottom layer for quiet connections (ref, cc, gnd), and the inner layers for an uninter- rupted ground plane. use the following step-by-step guide: 1) place the high-power components (c1, c2, q1, q2, d1, l1, and r1) first, with their grounds adjacent. minimize current-sense resistor trace lengths and ensure accurate current sensing with kelvin con- nections (figure 6). minimize ground trace lengths in the high-current paths. minimize other trace lengths in the high-current paths. use >5mm-wide traces. cin to high-side mosfet drain: 10mm max length rectifier diode cathode to low side mosfet: 5mm max length lx node (mosfets, rectifier cathode, induc- tor): 15mm max length ideally, surface-mount power components are butted up to one another with their ground terminals almost touching. these high-current grounds are then con- nected to each other with a wide, filled zone of top-layer copper so they do not go through vias. the resulting top-layer subground plane is connected to the normal inner-layer ground plane at the output ground terminals, which ensures that the ic? analog ground is sensing at the supply? output terminals without interfer- ence from ir drops and ground noise. other high-cur- rent paths should also be minimized, but focusing primarily on short ground and current-sense connec- tions eliminates about 90% of all pc board layout prob- lems (see the pc board layouts in the max1636 evaluation kit manual for examples). 2) place the ic and signal components. keep the main switching nodes (lx nodes) away from sensitive analog components (current-sense traces and ref capacitor). place the ic and analog components on the opposite side of the board from the power- switching node. important : the ic must be no fur- ther than 10mm from the current-sense resistors. keep the gate-drive traces (dh, dl, and bst) short- er than 20mm and route them away from csh, csl, and ref. place ceramic bypass capacitors close to the ic. the bulk capacitors can be placed further away. if using vl to power v cc , minimize noise by placing a 0.1? capacitor close to the v cc pin and placing the 4.7? capacitor further away, but closer than the boost diode (figure 7). 3) use a single-point star ground where the input ground trace, power ground (subground plane), and normal ground plane meet at the supply's output ground terminal. connect both ic ground pins and all ic bypass capacitors to the normal ground plane. low-voltage, precision step-down controller for portable cpu power 22 ______________________________________________________________________________________ max1636 sense resistor high-current path max1636 lx vl v cc gnd bst figure 6. kelvin connections for the current-sense resistors figure 7. capacitor placement transistor count: 3472 ___________________chip information
max1636 low-voltage, precision step-down controller for portable cpu power ______________________________________________________________________________________ 23 ssop.eps ________________________________________________________package information ssop.eps

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