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max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range ________________________________________________________________ maxim integrated products 1 19-2653; rev 0; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1157/max1159/max1175 14-bit, low-power, successive-approximation analog-to-digital converters (adcs) feature automatic power-down, factory-trimmed internal clock, and 14-bit wide parallel interface. the devices operate from a single +4.75v to +5.25v analog supply and feature a separate digital supply input for direct interface with +2.7v to +5.25v digital logic. the max1157 accepts an analog input voltage range from 0 to +10v while the max1159 accepts a bipolar analog input voltage range of ?0v. the max1175 accepts a bipolar analog input voltage range of ?v. all devices consume only 23mw at a sampling rate of 135ksps when using an external reference and 29mw when using the internal +4.096v reference. autoshutdown reduces supply current to 0.4ma at 10ksps. the max1157/max1159/max1175 are ideal for high-performance, battery-powered data-acquisition applications. excellent ac performance (thd = -100db) and dc accuracy (?lsb inl) make the max1157/ max1159/max1175 ideal for industrial process control, instrumentation, and medical applications. the max1157/max1159/max1175 are available in a 28-pin tssop package and are fully specified over the -40? to +85? extended temperature range and the 0? to +70? commercial temperature range. applications temperature sensing and monitoring industrial process control i/o modules data-acquisition systems precision instrumentation features analog input voltage range 10v, 5v, or 0 to 10v 14-bit wide parallel interface single +4.75v to +5.25v analog supply voltage interfaces with +2.7v to +5.25v digital logic 1lsb inl (max) 1lsb dnl (max) low supply current (max1159) 5.3ma (external reference) 6.2ma (internal reference) 5a autoshutdown mode small footprint 28-pin tssop package ordering information part temp range pin-package input voltage range inl (lsb) max1157 acui* 0 c to +70 c 28 tssop 0 to +10v 1 max1157bcui* 0 c to +70 c 28 tssop 0 to +10v 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 d5 d4 d3 d2 d1 d0 refadj n.c. n.c. dv dd dgnd cs reset ref agnd ain agnd av dd eoc r/c d13 d12 d11 d10 d9 d8 d7 d6 tssop top view max1157 max1159 max1175 pin configuration autoshutdown is a trademark of maxim integrated products, inc. ordering information continued at end of data sheet. * future product? ontact factory for availability.
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ain to agnd .....................................................-16.5v to +16.5v ref, refadj to agnd............................-0.3v to (av dd + 0.3v) cs , r/ c , reset to dgnd ........................................-0.3v to +6v d_, eoc to dgnd ...................................-0.3v to (dv dd + 0.3v) maximum continuous current into any pin ........................50ma continuous power dissipation (t a = +70 c) 28-pin tssop (derate 12.8mw/ c above +70 c) .....1026mw operating temperature range max11_ _cui......................................................0 c to +70 c max11_ _eui ...................................................-40 c to +85 c storage temperature range .............................-65 c to +150 c junction temperature ......................................................+150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (av dd = dv dd = +5v, external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units dc accuracy resolution res 14 bits differential nonlinearity dnl no missing codes over temperature -1 +1 lsb max11_ _a -1 +1 integral nonlinearity inl max11_ _b -2 +2 lsb rms noise, external reference 0.32 transition noise internal reference 0.34 lsb rms max1159 -10 0 +10 offset error max1157/max1175 -10 +10 mv gain error 0 0.2 %fsr offset drift 16 v/ c gain drift 1 ppm/ c ac accuracy (f in = 1khz, v ain = full range, 135ksps) signal-to-noise plus distortion sinad 81 85 db signal-to-noise ratio snr 82 85 db total harmonic distortion thd -100 -86 db spurious-free dynamic range sfdr 87 103 db analog input max1157 0 +10 max1159 -10 +10 input range v ain max1175 -5 +5 v max1157/max1175 normal operation 5.3 6.9 9.2 max1175 shutdown mode 3 normal operation 7.8 10 13.0 input resistance r ain max1159 shutdown mode 6 k ?
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +5v, external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units max1157, 0 v ain +10v -0.1 +2.0 normal operation -1.8 +1.2 max1159, -10v v ain +10v shutdown mode -1.8 +1.8 normal operation -1.8 +0.4 input current i ain max1175, -5v v ain +5v shutdown mode -1.8 +1.8 ma max1159, v ain = +10v, shutdown mode to operating mode 0.5 0.7 input current step at power-up i pu max1175, v ain = +5v, shutdown mode to operating mode 1 1.4 ma input capacitance c in 10 pf internal reference ref output voltage v ref 4.056 4.096 4.136 v ref output tempco 35 ppm/ c ref short-circuit current i ref-sc 10 ma external reference ref and refadj input voltage range 3.8 4.2 v refadj buffer disable threshold av dd - 0.4 av dd - 0.1 v normal mode, f sample = 135ksps 60 100 ref input current i ref shutdown mode (note 1) 0.1 10 a refadj input current i refadj refadj = av dd 16 a digital inputs/outputs output high voltage v oh i source = 0.5ma, dv dd = +2.7v to +5.25v, av dd = +5.25v dv dd - 0.4 v output low voltage v ol i sink = 1.6ma, dv dd = +2.7v to +5.25v, av dd = +5.25v 0.4 v input high voltage v ih 0.7 dv dd v input low voltage v il 0.3 dv dd v input leakage current digital input = dv dd or 0 -1 +1 a input hysteresis v hyst 0.2 v input capacitance c in 15 pf three-state output leakage i oz 10 a three-state output capacitance c oz 15 pf
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range 4 _______________________________________________________________________________________ note 1: maximum specification is limited by automated test equipment. note 2: to ensure best performance, finish reading the data and wait t br before starting a new acquisition. electrical characteristics (continued) (av dd = dv dd = +5v, external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) parameter symbol conditions min typ max units power supplies analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.70 5.25 v max1157 2.9 external reference, 135ksps max1159/max1175 4.0 5.3 max1157 3.8 analog supply current i avdd internal reference, 135ksps max1159/max1175 5.2 6.2 ma shutdown mode (note 1), digital input = dv dd or 0 0.5 5 a shutdown supply current i shdn standby mode 3.7 ma digital supply current i dvdd 0.75 ma power-supply rejection av dd = dv dd = +4.75v to +5.25v 1 lsb timing characteristics (figures 1 and 2) (av dd = +4.75v to +5.25v, dv dd = +2.7v to av dd , external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , c load = 20pf, t a = t min to t max .) parameter symbol conditions min typ max units maximum sampling rate f sample-max 135 ksps acquisition time t acq 2s conversion time t conv 4.7 s cs pulse width high t csh (note 2) 40 ns dv dd = +4.75v to +5.25v 40 cs pulse width low t csl (note 2) dv dd = +2.7v to +5.25v 60 ns r/ c to cs fall setup time t ds 0ns dv dd = +4.75v to +5.25v 40 r/ c to cs fall hold time t dh dv dd = +2.7v to +5.25v 60 ns dv dd = +4.75v to +5.25v 40 cs to output data valid t do dv dd = +2.7v to +5.25v 80 ns eoc fall to cs fall t dv 0ns dv dd = +4.75v to +5.25v 40 cs rise to eoc rise t eoc dv dd = +2.7v to +5.25v 80 ns dv dd = +4.75v to +5.25v 40 bus relinquish time t br dv dd = +2.7v to +5.25v 80 ns
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range _______________________________________________________________________________________ 5 inl vs. code max1157 toc01 code inl (lsb) 12288 16384 8192 4096 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 -2.5 0 dnl vs. code max1157 toc02 code dnl (lsb) -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 12288 16384 8192 4096 supply current (av dd + dv dd ) vs. temperature max1157 toc03 temperature ( c) supply current (ma) 60 40 -20 0 20 4.45 4.50 4.55 4.60 4.65 4.70 4.75 4.80 4.40 -40 80 5.25v 5.0v 4.75v f sample = 135ksps shutdown mode between conversions supply current (av dd + dv dd ) vs. sample rate max1157 toc04 sample rate (ksps) supply current (ma) 100 10 1 0.1 0.001 0.01 0.1 1 10 0.0001 0.01 1000 standby mode shutdown mode v ain = 0v gain error vs. temperature max1157 toc07 temperature ( c) gain error (%fsr) 60 40 -20 0 20 -0.15 -0.10 -0.05 0 0.05 0.10 0.15 0.20 -0.20 -40 80 shutdown current (av dd + dv dd ) vs. temperature max1157 toc05 temperature ( c) shutdown supply current (ma) 60 40 -20 0 20 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.5 4.0 5.0 0 -40 80 no conversions offset error vs. temperature max1157 toc06 temperature ( c) offset error (mv) 60 40 -20 0 20 -8 -6 -4 -2 0 2 4 8 6 10 -10 -40 80 max1159 internal reference vs. temperature max1157 toc08 temperature ( c) internal reference (v) 60 40 -20 0 20 4.066 4.076 4.086 4.096 4.106 4.116 4.126 4.136 4.056 -40 80 fft at 1khz max 1157 toc09 frequency (khz) magnitude (db) 40 20 -160 -140 -120 -100 -80 -60 -40 -20 0 -180 060 f sample = 135ksps typical operating characteristics (av dd = dv dd = +5v, external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , c load = 20pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) ( typical application circuit )
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range 6 _______________________________________________________________________________________ sinad vs. frequency max1157 toc10 frequency (khz) sinad (db) 10 10 20 30 40 50 60 70 80 90 100 0 1 100 spurious-free dynamic range vs. frequency max1157 toc11 frequency (khz) sfdr (db) 10 20 40 60 80 100 120 0 1 100 total harmonic distortion vs. frequency max1157 toc12 frequency (khz) thd (db) 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 1 100 typical operating characteristics (av dd = dv dd = +5v, external reference = +4.096v, c ref = 10f, c refadj = 0.1f, v refadj = av dd , c load = 20pf, t a = t min to t max , unless otherwise noted. typical values are at t a = +25 c.) ( typical application circuit ) pin description pin name function 1 d6 three-state digital data output 2 d7 three-state digital data output 3 d8 three-state digital data output 4 d9 three-state digital data output 5 d10 three-state digital data output 6 d11 three-state digital data output 7 d12 three-state digital data output 8 d13 three-state digital data output (msb) 9r/ c read/ convert input. power up and place the max1157/max1159/max1175 in acquisition mode by holding r/ c low during the first falling edge of cs . during the second falling edge of cs , the level on r/ c determines whether the reference and reference buffer power down or remain on after conversion. set r/ c high during the second falling edge of cs to power down the reference and buffer, or set r/ c low to leave the reference and buffer powered up. set r/ c high during the third falling edge of cs to put valid data on the bus. 10 eoc end of conversion. eoc drives low when conversion is complete. 11 av dd analog supply input. bypass with a 0.1f capacitor to agnd. 12 agnd analog ground. primary analog ground (star ground). 13 ain analog input 14 agnd analog ground. connect pin 14 to pin 12.
detailed description converter operation the max1157/max1159/max1175 use a successive- approximation (sar) conversion technique with an inherent track-and-hold (t/h) stage to convert an analog input into a 14-bit digital output. parallel outputs provide a high-speed interface to most microprocessors (ps). the functional diagram at the end of the data sheet shows a simplified internal architecture of the max1157/ max1159/ max1175. figure 3 shows a typical applica- tion circuit for the max1157/max1159/max1175. analog input input scaler the max1157/max1159/max1175 have an input scaler which allows conversion of true bipolar input voltages and input voltages greater than the power supply, while operating from a single +5v analog supply. the input scaler attenuates and shifts the analog input to match the input range of the internal dac. the max1157 has a unipolar input voltage range of 0 to +10v. the max1175 input voltage range is 5v while the max1159 input voltage range is 10v. figure 4 shows the equivalent input circuit of the max1157/ max1159/max1175. this circuit limits the current going into or out of ain to less than 1.8ma. max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range _______________________________________________________________________________________ 7 pin description (continued) pin name function 15 refadj reference buffer output. bypass refadj with a 0.1f capacitor to agnd for internal reference mode. connect refadj to av dd to select external reference mode. 16 ref reference input/output. bypass ref with a 10f capacitor to agnd. ref is the external reference input when in external reference mode. 17 reset reset input. logic high resets the device. 18 cs convert start. the first falling edge of cs powers up the device and enables acquisition when r/ c is low. the second falling edge of cs starts conversion. the third falling edge of cs loads the result onto the bus when r/ c is high. 19 dgnd digital ground 20 dv dd digital supply voltage. bypass with a 0.1f capacitor to dgnd. 21, 22 n.c. no connection. make no connection to these pins. 23 d0 three-state digital data output (lsb) 24 d1 three-state digital data output 25 d2 three-state digital data output 26 d3 three-state digital data output 27 d4 three-state digital data output 28 d5 three-state digital data output figure 1. load circuits 1ma dgnd high-z to v oh , v ol to v oh , and v oh to high-z c load = 20pf d0?13 a) 1ma dv dd dgnd high-z to v ol , v oh to v ol , and v ol to high-z c load = 20pf d0?13 b)
max1157/max1159/max1175 track and hold (t/h) in track mode, the internal hold capacitor acquires the analog signal (see figure 4). in hold mode, the t/h switches open and the capacitive dac samples the analog input. during the acquisition, the analog input (ain) charges capacitor c hold . the acquisition ends on the second falling edge of cs . at this instant, the t/h switches open. the retained charge on c hold rep- resents a sample of the input. in hold mode, the capac- itive dac adjusts during the remainder of the conversion time to restore node t/h out to zero within the limits of 14-bit resolution. force cs low to put valid data on the bus after conversion is complete. power-down modes select standby mode or shutdown mode with r/ c during the second falling edge of cs (see selecting standby or shutdown mode section). the max1157/max1159/ max1175 automatically enter either standby mode (refer- ence and buffer on), or shutdown (reference and buffer off) after each conversion depending on the status of r/ c during the second falling edge of cs . internal clock the max1157/max1159/max1175 generate an internal conversion clock to free the microprocessor from the bur- den of running the sar conversion clock. total conver- sion time after entering hold mode (second falling edge of cs ) to end-of-conversion ( eoc ) falling is 4.7s (max). applications information starting a conversion cs and r/ c control acquisition and conversion in the max1157/max1159/max1175 (see figure 2). the first falling edge of cs powers up the device and puts it in acquire mode if r/ c is low. the convert start cs is ignored if r/ c is high. the max1157/max1159/ max1175 need at least 6ms (c refadj = 0.1f, c ref = 10f) for the internal reference to wake up and settle before starting the conversion if powering up from shut- down. reset the max1157/max1159/max1175 by tog- gling reset with cs high. the next falling edge of cs begins acquisition. selecting standby or shutdown mode the max1157/max1159/max1175 have a selectable standby or low-power shutdown mode. in standby mode, the adc s internal reference and reference buffer do not power down between conversions, elimi- nating the need to wait for the reference to power up before performing the next conversion. shutdown mode powers down the reference and reference buffer after 14-bit, 135ksps, single-supply adcs with bipolar analog input range 8 _______________________________________________________________________________________ figure 2. max1157/max1159/max1175 timing diagram t csl t csh t acq t dh r/c cs eoc d0 d13 t ds t dv t eoc t do t br t conv high-z ref power- down control high-z data valid figure 3. typical application circuit for the max1157/max1159/ max1175 max1157 max1159 max1175 analog input ain av dd +5v analog +5v digital dv dd d0 d13 14-bit wide p data bus 10 f 0.1 f 0.1 f 0.1 f r/c cs agnd dgnd refadj ref eoc reset
completing a conversion. the reference and reference buffer require a minimum of 12ms (c refadj = 0.1f, c ref = 10f) to power up and settle from shutdown. the state of r/ c during the second falling edge of cs selects which power-down mode the max1157/ max1159/max1175 enters upon conversion comple- tion. holding r/ c low causes the max1157/max1159/ max1175 to enter standby mode. the reference and buffer are left on after the conversion completes. r/ c high causes the max1157/max1159/max1175 to enter shutdown mode and power down the reference and buffer after conversion (see figures 5 and 6). set the voltage at ref high during the second falling edge of cs to realize the lowest current operation. standby mode while in standby mode, the supply current is less than 3.7ma (typ). the next falling edge of cs with r/ c low causes the max1157/max1159/max1175 to exit stand- by mode and begin acquisition. the reference and ref- erence buffer remain active to allow quick turn-on time. max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range _______________________________________________________________________________________ 9 figure 4. equivalent input circuit max1157 r2 r3 161 ? 3.4k ? s3 power- down track track hold hold s1, s2 = t/h switch s3 = power down (max1159/max1175 only) s1 c hold 30pf s2 ain max1159/max1175 r2 r3 161 ? 3.4k ? s3 power- down track track hold hold ref r2 = 7.85k ? (max1159) or 3.92k ? (max1157/max1175) r3 = 5.45k ? (max1159) or 17.79k ? (max1157/max1175) s1 c hold 30pf s2 ain t/h out t/h out figure 5. selecting standby mode cs r/c eoc ref and buffer power acquisition conversion data out
max1157/max1159/max1175 shutdown mode in shutdown mode, the reference and reference buffer shut down between conversions. shutdown mode reduces supply current to 0.5a (typ) immediately after the conversion. the first falling edge of cs with r/ c low causes the reference and buffer to wake up and enter acquisition mode. to achieve 14-bit accuracy, allow 12ms (c refadj = 0.1f, c ref = 10f) for the internal reference to wake up. internal and external reference internal reference the internal reference of the max1157/max1159/ max1175 is internally buffered to provide +4.096v out- put at ref. bypass ref to agnd and refadj to agnd with 10f and 0.1f, respectively. sink or source current at refadj to make fine adjust- ments to the internal reference. the input impedance of refadj is nominally 5k ? . use the circuit of figure 7 to adjust the internal reference to 1.5%. external reference an external reference can be placed at either the input (refadj) or the output (ref) of the max1157/ max1159/max1175 s internal buffer amplifier. using the buffered refadj input makes buffering the external reference unnecessary. the internal buffer output must be bypassed at ref with a 10f capacitor. connect refadj to av dd to disable the internal buffer. directly drive ref using an external reference. during conversion, the external reference must be able to drive 100a of dc load current and have an output imped- ance of 10 ? or less. the input impedance of refadj is typically 5k ? . the dc input impedance of ref is a min- imum 40k ? . for optimal performance, buffer the reference through an op amp and bypass ref with a 10f capacitor. consider the max1157/max1159/max1175 s equivalent input noise (0.6lsb) when choosing a reference. reading the conversion result eoc flags the microprocessor when a conversion is complete. the falling edge of eoc signals that the data is valid and ready to be output to the bus. d0 d13 are the parallel outputs of the max1157/max1159/ max1175. these three-state outputs allow for direct connection to a microcontroller i/o bus. the outputs remain high-impedance during acquisition and conver- sion. data is loaded onto the bus with the third falling edge of cs with r/ c high (after t do ). bringing cs high forces the output bus back to high impedance. the max1157/max1159/max1175 then wait for the next falling edge of cs to start the next conversion cycle (see figure 2). 14-bit, 135ksps, single-supply adcs with bipolar analog input range 10 ______________________________________________________________________________________ figure 6. selecting shutdown mode cs r/c eoc ref and buffer power acquisition conversion data out figure 7. max1157/max1159/max1175 reference adjust circuit max1157 max1159 max1175 refadj +5v 68k ? 100k ? 150k ? 0.1 f
transfer function figures 8, 9, and 10 show the max1157/max1159/ max1175 s output transfer functions. the max1159 and max1175 outputs are coded in offset binary, while the max1157 is coded on standard binary. input buffer most applications require an input buffer amplifier to achieve 14-bit accuracy and prevent loading the source. switch the channels immediately after acquisi- tion, rather than near the end of or after a conversion when the input signal is multiplexed. this allows more time for the input buffer amplifier to respond to a large step-change in input signal. the input amplifier must have a high enough slew rate to complete the required output voltage change before the beginning of the acquisition time. figure 11 shows an example of this circuit using the max427. figures 12a and 12b show how the max1175 and max1159 analog input current varies depending on whether the chip is operating or powered down. the part is fully powered down between conversions if the voltage at r/ c is set high during the second falling edge of cs . the input current abruptly steps to the powered up value at the start of acquisition. this step in the input current can disrupt the adc input, depend- ing on the driving circuit s output impedance at high frequencies. if the driving circuit cannot fully settle by the end of acquisition time, the accuracy of the system can be compromised. to avoid this situation, increase the acquisition time, use a driving circuit that can settle within t acq , or leave the max1175/max1159 powered up by setting the voltage at r/ c low during the second falling edge of cs . layout, grounding, and bypassing for best performance, use printed circuit (pc) boards. do not run analog and digital lines parallel to each other, and do not lay out digital signal paths under- neath the adc package. use separate analog and dig- ital ground planes with only one point connecting the two ground systems (analog and digital) as close to the device as possible. route digital signals far away from sensitive analog and reference inputs. if digital lines must cross analog lines, do so at right angles to minimize coupling digital noise max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range ______________________________________________________________________________________ 11 figure 9. max1159 transfer function output code -8192 +8192 input voltage (lsb) input range = -10v to +10v 0 -8190 -8191 -8189 +8191 +8190 -1 +1 11 . . . 1111 11 . . . 1110 11 . . . 1101 10 . . . 0001 10 . . . 0000 01 . . . 1111 00 . . . 0011 00 . . . 0010 00 . . . 0001 00 . . . 0000 full-scale range (fsr) = +20v 1lsb = fsr x v ref 16384 x 4.096 full-scale transition figure 10. max1175 transfer function output code -8192 +8192 input voltage (lsb) input range = -5v to +5v 0 -8190 -8191 -8189 +8191 +8190 -1 +1 11 . . . 1111 11 . . . 1110 11 . . . 1101 10 . . . 0001 10 . . . 0000 01 . . . 1111 00 . . . 0011 00 . . . 0010 00 . . . 0001 00 . . . 0000 full-scale range (fsr) = +10v 1lsb = fsr x v ref 16384 x 4.096 full-scale transition figure 8. max1157 transfer function output code 16384 input voltage (lsb) input range = 0 to +10v 2 1 03 16383 16382 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 full-scale range (fsr) = +10v 1lsb = fsr x v ref 16384 x 4.096 full-scale transition
max1157/max1159/max1175 onto the analog lines. if the analog and digital sections share the same supply, isolate the digital and analog supply by connecting them with a low value (10 ? ) resistor or ferrite bead. the adc is sensitive to high-frequency noise on the av dd supply. bypass av dd to agnd with a 0.1f capacitor in parallel with a 1f to 10f low-esr capaci- tor with the smallest capacitor closest to the device. keep capacitor leads short to minimize stray inductance. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1157/max1159/ max1175 are measured using the endpoint method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step-width and the ideal value of 1lsb. a dnl error specification of 1lsb guarantees no missing codes and a monotonic transfer function. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization noise error only and results directly from the adc s res- olution (n bits): snr = ((6.02 ? n) + 1.76)db where n = 14 bits. in reality, there are other noise sources besides quanti- 14-bit, 135ksps, single-supply adcs with bipolar analog input range 12 ______________________________________________________________________________________ figure 12a. max1175 analog input current max1175 analog input current vs. analog input voltage analog input voltage (v) analog input current (ma) 2.5 0 -2.5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -2.0 -5.0 5.0 shutdown mode standby mode figure 12b. max1159 analog input current max1159 analog input current vs. analog input voltage analog input voltage (v) analog input current (ma) 5 0 -5 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 -10 10 shutdown mode standby mode figure 11. max1157/max1159/max1175 fast-settling input buffer max1157 max1159 max1175 max427 ref ** * ain analog input *max1157 only. **max1159/max1175 only.
zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency s rms amplitude to the rms equivalent of all the other adc output signals. effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc s error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest fre- quency component. chip information transistor count: 15,383 process: bicmos thd = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 log v+v+v+v v 2 2 3 2 4 2 5 2 1 e sinad - 1.76 nob = ? ? ? ? ? ? 602 . sinad db signal noise distortion rms rms ( ) log () = + ? ? ? ? ? ? 20 max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range ______________________________________________________________________________________ 13 ordering information (continued) part temp range pin-package input voltage range inl (lsb) max1157aeui* -40 c to +85 c 28 tssop 0 to +10v 1 MAX1157BEUI* -40 c to +85 c 28 tssop 0 to +10v 2 max1159 acui 0 c to +70 c 28 tssop 10v 1 max1159bcui 0 c to +70 c 28 tssop 10v 2 max1159aeui* -40 c to +85 c 28 tssop 10v 1 max1159beui* -40 c to +85 c 28 tssop 10v 2 max1175 acui* 0 c to +70 c 28 tssop 5v 1 max1175bcui* 0 c to +70 c 28 tssop 5v 2 max1175aeui* -40 c to +85 c 28 tssop 5v 1 max1175beui* -40 c to +85 c 28 tssop 5v 2 * future product? ontact factory for availability.
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range 14 ______________________________________________________________________________________ max1157 max1159 max1175 ain 14 bits 5k ? refadj av dd dv dd agnd dgnd capacitive dac 14 bits d0 d13 agnd ref reset r/c cs eoc output registers input scaler clock reference successive- approximation register and control logic functional diagram
max1157/max1159/max1175 14-bit, 135ksps, single-supply adcs with bipolar analog input range maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) tssop4.40mm.eps

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