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1 of 22 march 8, 2007 dsc 5695/1 ? 2007 integrated device technology, inc. features true dual-ported memory cells ? allows simultaneous access of the same memory location high per-port throughput performance ? industrial: 800 mbps low-power operation ? active: 15 ma (typ.) ? standby: 2 ua (typ.) multiplexed address and data i/os counter enable and repeat features full synchronous operation on both ports separate upper-byte and lower-by te controls for multiplexed bus and bus matching compatibility lvttl-compatible, single 1.8v (+/- 100mv) power supply industrial temperature range (-40c to +85c) available in a 100-ball fpbga (fine pitch bga) green parts available, see ordering information block diagram notes: 1. this block diagram depicts operation with the address and data signals mux?d on the right port but not on the left port. if each port is set to operate with the address and data signals mux?d, then both sides of the block diagram will be the same as the right port pictured above. 16k x 16 memory array control logic special function logic zz control logic address/data i/o control i/o 0r ? i/o 15r ads r ub r lb r cnten r cntrpt r ce r oe r r/w r int r clk r sf 0 ? sf 7 zz r sfen clk r address/data i/o control i/o 0l ? i/o 15l ads l ub l lb l cnten l cntrpt l clk l a 0l ? a 13l ce l oe l r/w l int l clk l zz l data 0l ? data 15l addr 0l ? addr 13l data 0r ? data 15r addr 0r ? addr 13r advanced datasheet idt70p9268l mobile multimedia interface (m 2 i) very low power 1.8v 16k x 16 synchronous dual-port static ram
2 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range device description the 70p9268l is a very low power 16k x 16 synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with ve ry short cycle times. the 70p9268 supports two modes of operatio n. the first features one port with multiplexed address and data signals. the second features both ports with multiplexed address and data s ignals. please refer to the pinout below for more information on how to select the operation mode. pin configuration idt70p9268 by100 100-ball fpbga notes: 1. the device setup shown above features multiplexed address and data signals on the right port and non-multiplexed address and data signals on the left port. 2. for multiplexed address and data signal operation on the left port, this pin should be set to v dd . for non-multiplexed address and data signal operation on the left port, this pin should be set to v ss . 3. for multiplexed address and data signal operation on the left port, these pins should be set to v ss . a1 v ss a2 i/o 0 r a3 v dd a4 i/o 4 r a5 i/o 7 r a6 v dd a7 i/o 10 r a8 v dd a9 i/o 15 r a10 sfen b1 r/ w r b2 clk r b3 i/o 1 r b4 v ss b5 i/o 5 r b6 v ss b7 i/o 11 r b8 v ss b9 i/o 14 r b10 oe r c1 ads r c2 cnten r c3 cntrpt r c4 i/o 2 r c5 i/o 6 r c6 i/o 8 r c7 i/o 12 r c8 zz r c9 sf 7 c10 v ss d1 ce r d2 int r d3 ub r d4 lb r d5 i/o 3 r d6 i/o 9 r d7 i/o 13 r d8 sf 6 d9 sf 5 d10 sf 4 e1 int l e2 v ss e3 v dd e4 ub l e5 cntrpt l e6 sf 0 e7 msel (2) e8 v dd e9 v ss e10 v dd f1 ce l f2 lb l f3 cnten l f4 clk l f5 v ss f6 a 13 l (3) f7 sf 2 f8 v ss f9 v ss f10 sf 1 g1 ads l g2 a 0 l (3) g3 a 3 l (3) g4 v dd g5 i/o 8 l g6 i/o 12 l g7 a 7 l (3) g8 zz l g9 oe l g10 sf 3 h1 r/ w l h2 a 2 l (3) h3 i/o 0 l h4 v ss h5 i/o 4 l h6 i/o 11 l h7 i/o 13 l h8 a 9 l (3) h9 a 12 l (3) h10 nc j1 a 1 l (3) j2 a 5 l (3) j3 i/o 1 l j4 i/o 6 l j5 i/o 7 l j6 i/o 9 l j7 v dd j8 i/o 15 l j9 a 10 l (3) j10 a 11 l (3) k1 a 4 l (3) k2 a 6 l (3) k3 i/o 2 l k4 i/o 3 l k5 i/o 5 l k6 v dd k7 i/o 10 l k8 v ss k9 i/o 14 l k10 a 8 l (3)
3 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range pin names (70p9268) notes: 1. the device setup shown above features multiplexed address and data signals on both ports. 2. for non-multiplexed address and data signal operation on the left port, set pin e7 = v ss . left port right port names ce l ce r chip enable (input) r/w l r/w r read/write enable (input) oe l oe r output enable (input) a 0l ? a 15l n/a address (input) i/o 0l ? i/o 15l n/a data (input/output) n/a i/o+a 0r ? i/o+a 15r multiplexed address and data (input/output) clk l clk r clock (input) ub l ub r upper byte enable (input) lb l lb r lower byte enable (input) ads l ads r address strobe enable (input) cnten l cnten r counter enable (input) cntrpt l cntrpt r counter repeat (input) int l int r interrupt flag (output) zz l zz r sleep mode enable (input) sfen special function enable (input) sf 0-7 special function i/o (input/output) m sel left port mode select v dd power (1.8v) v ss ground (0v)
4 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range truth table i - read/write and enable control (multiplexed port) truth table ii - read/write and enable control (non-multiplexed port) truth table iii - address counter control recommended operating temperature and supply voltage oe clk ce ub lb r/w ads zz upper byte lower byte cycle address mode x h x x x x l high z high z x x deslected x l h h x x l high z high z x x both bytes deselected x l l h l l l -- -- n a n x x x x l h l d in high z n+1 -- w rite to upper byte x l h l l l l -- -- n a n x x x x l h l high z d in n+1 -- w rite to lower byte x l l l l l l -- -- n a n x x x x l h l d in d in n+1 -- write to both bytes h l l h h l l -- -- n a n l x x x h h l d out high z n+2 -- read upper byte only h l h l h l l -- -- n a n l x x x h h l high z d out n+2 -- read lower byte only h l l l h l l -- -- n a n l x x x h h l d out d out n+2 -- read both bytes h l l l x h l high z high z x x outputs disabled x x x x x x x h high z high z x x sleep mode ? power down oe clk ce ub lb r/w zz upper byte i/o lower byte i/o mode x h x x x l high z high z deselected x l h h x l high z high z both bytes deselected x l l h l l d in high z write to upper byte only x l h l l l high z d in write to lower byte only x l l l l l d in d in w rite to both bytes l l l h h l d out high z read upper byte only l l h l h l high z d out read lower byte only l l l l h l d out d out read both bytes h l l l x l high z high z outputs disabled x x x x x x h high z high z sleep mode ? power down external address previous internal address internal address used clk ads cnten cntrpt mode a n x a n l x h external address used x a n a n + 1 h l h counter enabled ? internal address generation x a n + 1 a n + 1 h h h external address blocked ? counter disabled (a n + 1 reused) x x a n x x l counter reset to last external address loaded grade am bient tem perature gnd vdd in du strial -40 c to +85 c 0v 1.8v +/- 100m v
5 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range recommended dc operating conditions absolute maximum ratings capacitance dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8v +/- 100mv) symbol parameter min. typ. max. unit v dd supply voltage 1.7 1.8 1.9 v v ss ground 0 0 0 v v ih input high voltage 1.2 -- v dd + 0.2 v v il input low voltage -0.2 -- 0.4 v symbol rating industrial unit v dd voltage on input, output and i/o terminals with respect to v ss -0.5v to v dd +0.3v v v term terminal voltage with respect to gnd -0.5v to +2.9v v t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c t jn junction temperature +150 c i out dc output current 20 ma symbol parameter conditions max. unit c in input capacitance vin = 0v 9 pf c out output capacitance vout = 0v 11 pf symbol parameter test conditions min. max. unit |i li | input leakage current v in = v ss to v dd -- 1 ua |i lo | output leakage current ce x = v ih or oe x = v ih or v out = v ss to v dd -- 1 ua v ol output low voltage i ol = 0.1ma, v dd = min -- 0.2 v v oh output high voltage i oh = -0.1m a, v dd = min v dd ? 0.2v -- v v olsf output low voltage i ol = 4ma, v dd = min -- 0.4 v
6 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8v +/- 100mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using ?ac test conditions? at input levels of gnd to 1.8v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port ?a? may be either left or right port. port ?b? is the opposite from port ?a?. ac test conditions input pulse levels v ss to v dd input rise/fall times 3ns max. input timing reference levels v dd /2 output reference levels v dd /2 output load figure 1 1.8v r1 13500 ? r2 13500 ? 70p9268 symbol parameter test conditions typ. max. i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) 15 ma 25 ma i sb 1 standby current (both ports ? ttl inputs) ce l = ce r = v ih , outputs disabled, f = f max (1) 2 ma 4 ma i sb 2 standby current (one port ? ttl inputs) ce ? a ? = v il and ce ? b ? = v ih , active port outputs disabled, f = f max (1) 3 ma 5 ma i sb 3 full standby current (both ports cmos inputs) both ports outputs disabled ce l and ce r > v dd ? 0.2v, v in > v dd ? 0.2v, or v in < 0.2v, f = 0 (2) 2 ua 8 ua i sb 4 full standby current (one port ? cmos inputs) ce ? a ? < 0.2v and ce ? b ? > v dd ? 0.2v, v in > v dd ? 0.2v or v in < 0.2v, active port outputs disabled, f = f max (1) 3 ma 5 ma i zz sleep mode current zz l and zz r > v dd ? 0.2v 2 ua 8 ua r1 r2 30pf (1) 1.8v figure 1. ac output test level (5pf for t lz , t hz , t wz , t ow )
7 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range ac electrical characteristics over the operating temperature range (read and write cycle timing for multiplexed port) (v dd = 1.8v +/- 100mv) 70p9268l ind. only symbol parameter min. max. t cyc clock cycle time 20 -- t ch clock high time 8 -- t cl clock low time 8 -- t r clock rise time -- 3 t f clock fall time -- 3 t sa address setup time 5 -- t ha address hold time 1 -- t sc chip enable setup time 5 -- t hc chip enable hold time 1 -- t sw r/w setup time 5 -- t hw r/w hold time 1 -- t sd input data setup time 5 -- t hd input data hold time 1 -- t sad ads setup time 5 -- t had ads hold time 1 -- t scn cnten setup time 5 -- t hcn cnten hold time 1 -- t srst cntrst setup time 5 -- t hrst cntrst hold time 1 -- t oe output enable to data valid -- 10 t olz output enable to high z 2 -- t ohz output enable to low z -- 10 t cd clock to data valid -- 12 t dc data output hold after clock high 2 -- t ckhz clock high to output high z 2 9 t cklz clock high to output low z 2 -- t ins interrupt flag set time 12 -- t inr interrupt flag reset time 12 -- t co clock to clock offset 5 --
8 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range ac electrical characteristics over the operating temperature range (read and write cycle timing for non-multiplexed port) (v dd = 1.8v +/- 100mv) 70p9268l ind. only symbol parameter min. max. t cyc clock cycle time 20 -- t ch clock high time 8 -- t cl clock low time 8 -- t r clock rise time -- 3 t f clock fall time -- 3 t sa address setup time 5 -- t ha address hold time 1 -- t sc chip enable setup time 5 -- t hc chip enable hold time 1 -- t sw r/w setup time 5 -- t hw r/w hold time 1 -- t sd input data setup time 5 -- t hd input data hold time 1 -- t sad ads setup time 5 -- t had ads hold time 1 -- t scn cnten setup time 5 -- t hcn cnten hold time 1 -- t srst cntrst setup time 5 -- t hrst cntrst hold time 1 -- t olz output enable to low z 2 -- t ohz output enable to high z -- 10 t cd clock to data valid -- 12 t dc data output hold after clock high 2 -- t ckhz clock high to output high z 2 10 t cklz clock high to output low z 2 -- t ins interrupt flag set time 12 -- t inr interrupt flag reset time 12 -- t co clock to clock offset 5 --
9 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform for mux?d port single read cycle timing waveform for mux?d port burst read cycle addr / data ads ub / lb ce clk tch tcl tcyc tsc tsb tsad thad tsa tha an dn oe tohz thc thb tsw r/w tolz toe tclz tcd tckhz addr / data ads clk tch tcl tcyc tsad thad tsa tha an dn cnten tscn thcn dn+1 tcklz tcd tckhz
10 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform for mux?d port single write cycle timing waveform for mux?d port burst write cycle addr / data ads r/w ce clk tch tcl tcyc tsc tsw tsad thad tsa tha tsd thd an dn an+1 dn+1 addr / data ads r/w ce clk tch tcl tcyc tsc tsw tsad thad tsa tha tsd thd an dn dn+1 dn+2 cnten tscn
11 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of mux?d port write to non-mux?d port read notes: 1. ce , ub / lb n = v il ; cnten and repeat = v ih . 2. oe = v il for port, which is being read from. oe = v ih for mux?d port, which is being written to. 3. if t co < minimum specified, then data from non-mux?d port read is not valid until following non-mux?d port clock cycle (ie, time from w rite to valid read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from non-mux?d port read is available on first non-mux?d port clock cycle (ie, time from write to valid r ead on opposite port will be t co + t cyc2 + t cd2 ). addr / data a r/w a clk a tch tcl tcyc ads a t sw thw tsa tha match valid tsa tha tsd thd tco tsw thw tcd tsa tha match no match valid tch tcl tcyc r/w b clk b address b data b tdc
12 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of non-mux?d port write to mux?d port read data in?a? r/w a clk a tch tcl tcyc address a t sw thw tsa tha match tsa tha tsw thw tcd tsa tha match r/w b clk b addr/data b valid tsd thd valid tdc no match tco
13 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of non-mux?d port read-to-write-to-read notes: 1. output ub / lb state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. clk dn+2 tsa tha an read an+1 an+2 an+2 an+3 an+4 qn+3 nop (4) write read tsc thc tsd thd qn tch tcl tcyc tsb thb tsw thw tsw thw tcd tckhz tckhz ce ub/lb r/w address data in data out (1)
14 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of non-mux?d port read-to-write-to-read (oe controlled) notes: 1. output ub / lb state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. address data out clk dn+2 tsa tha an read an+1 an+2 an+3 an+4 an+5 qn+4 write read tsc thc tsd thd qn tch tcl tcyc tsb thb tsw thw tsw thw tcd tckhz ce ub/lb r/w data in dn+3 tohz (1) oe
15 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of non-mux?d port write with counter advance notes: 1. ce , ub / lb , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce , ub / lb = v il . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. clk dn+1 dn dn+2 dn+1 ads tsad thad tsa tha an tsa tha an an+1 an+2 an+3 an+4 tscn thcn dn+3 write external address write with counter write counter hold address internal address cnten data in dn+4
16 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform of non-mux?d port operation with counter repeat notes: 1. ce , ub / lb = v il . 2. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 3 . no dead cycle exists during cntrpt operation. a read or write cycle may be coincidental with the counter cntrpt cycle: address loaded by last valid ads load will be accessed. 4. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. clk data 1 data 0 data 3 data 2 ads tsad thad tsa tha an tsa tha an tscn thcn write to ads addr ess an advance counter write to an+1 address internal address cnten data in r/w an+1 an+2 an+2 an an+1 an+2 tsw thw tsrpt thrpt data 1 data 0 advance counter write to an+2 hold counter write to an+2 repeat read last ads address an advance counter read an+1 advance counter read an+1 cntrpt data out
17 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform for x8 to x16 bus matching clk a ce a ub a addr a / data a dn an lb a r/w a dn+1 an ce b r/w b addr b / data b dn, dn+1 an ads a ads b tsad thad tsa tha tsad thad tsb thb
18 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform - interrupt timing clk addr / data tsad thad 3ffe tsa tha data tsd thd tins clk tinr r/w ce r/w ads int ce tsoe thoe addr / data 3ffe data oe ads tsad thad
19 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range timing waveform - entering sleep mode timing waveform - exiting sleep mode addr / data clk r/w ce zz i zz sleep mode set cycles no new reads or writes allowed normal operation sleep mode data data addr / data clk ce r/w zz i zz no new reads or writes allowed an sleep mode recovery cycles normal operation sleep mode dn tsad thad tsa tha tcd tsc tsw ads
20 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range functional description the 70p9268l provides a true synchronous multiplexed and non-multiple xed dual-port static ram interface. registered inputs prov ide minimal set- up and hold times on address, data, and all critical control input s. all internal registers are clocked on the rising edge of t he clock signal. counter enable and counter repeat inputs are provided to fac ilitate burst reads and writes to the memory. synchronous interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left p ort interrupt flag (int l ) is asserted when the right port writes to memory loca tion 3ffe (hex), where a write is defined as ce r = r/ w r = v il . the left port clears the interrupt through access of address location 3ffe when ce l = v il , r/ w l = v ih . likewise, the right port interrupt flag (int r ) is asserted when the left port writes to memory location 3fff (hex) and to clear the interrupt flag (int r ), the right port must read the memory location 3fff. the message (16 bits) at 3ffe or 3fff is user-defined since it is an addressable sram location. if the interrupt function is not used, address, location s 3ffe and 3fff are not used as mail boxes, but as part of the random access memory. truth table iv - interrupt flag advanced input read and output drive registers the idt70p9268l is equipped with 8 special function (sf x ) pins that can be programmed to function as either input read register (irr) or output drive register (odr) pins. irr pins allow the user to capture the status of external binary state devices and report that statu s to a processor, asic, fpga, etc. via a standard read access from either port. odr pins a llow the user to monitor and control the state of external bi nary state devices via standard reads and writes from either port. the functionality of t he sf pins are determined by the status of the pin direction register (pdr). refer to truth table v for information on programming t he pdr and operating the special function pins. truth table v - input read and output drive registers notes: 1. if i/on = h, sfn is programmed as an output and i/on will be used to read and write to this odr location during subsequent tran sactions when i/o 8 = l. if i/on= l, sfn is programmed as an input and i/on will be used to read this irr location during subsequent reads where i/o 8 = l. 2. for n = 0 - 7 . if pdrn = 0, i/on = irrn (the registered value of sfn). if pdrn = 1, i/on = odrn (the value last written to odrn). 3. for n = 8 - 15 , i/on = pdrn- 8 . 4. for i/o 0 - i/o 7 , the value written to i/on will be input to each odrn location (where pdrn = 1) with a ?1? corresponding to ?on? and a ?0? cor responding to ?off?. left port right port clk l r/w l ce l add l int l clk r r/w r ce r add r int r function ? l l 3fff x ? x x x l set right intr flag ? x x x x ? h l 3fff h reset right intr flag ? x x x l ? l l 3ffe x set left intl flag ? h l 3ffe h ? x x x x reset left intl flag sfen addr r/w i/o0 ? i/o7 i/o8 i/o9 ? i/o15 function l 0 l note 1 h x program pin direction register l 0 h note 2 note 3 note 3 reading the status of sfn and pdrn l 0 l note 4 l x write to output drive register
21 of 22 march 8, 2007 idt70p9268l advanced datasheet very low power 16k x 16 synchronous mobile multimedia interface (m 2 i) dual port static ram industrial temperature range special function i/o operation the pdr determines whether the sf x pins will operate as irr or odr. the pdr is pr ogrammed by writing to address x0000 with sfen = v il and i/o 8 = h. writing a ?0? to i/o x will set sf x to be an irr pin. writing a ?1? to i/o x will set sf x to be an odr pin. the status of the special function pins and the pdr can be read as a standard memory access to address x0000 from either port a nd the data is output via the standard i/os (truth table v). during special function reads i/o 0 - i/o 7 output the status of the special function pins with i/on corre- sponding to sfn. i/o 8 - i/o 15 outputs the status of the pin direction register with i/on = pdrn- 8 . for sf pins set to odr operation, the status of these pins is determined by using standard write accesses from either port to a ddress x0000 with sfen = v il and i/o 8 = l. a written ?1? will correspond to ?on? for the connec ted binary state device and a written ?0? will correspond to ?off?. sleep mode the idt70p9268 is equipped with an optional sleep or low-power m ode on both ports. the sleep mode pin on both ports is asynchro nous and active high. during normal operation, the zz-pin is pulled low. when zz is pulled high, the port will enter sleep mode where it will m eet lowest possible power conditions. the sleep mode timing di agram shows the modes of operation: normal operation, no read/write allowed and sleep mode. for normal operation all inputs must meet setup and hold times pr ior to sleep and after recovering from sleep. clocks must also meet cycle high and low times during these periods. three cycles prior to asserting zz (zz x = v ih ) and three cycles after de-asserting zz (zz x = v il ), the device must be disabled via the chip enable pins. if a write or a read operation occurs during these periods, the memory array may be corrupte d. validity of data out from the ram cannot be guaranteed immediately after zz is assert ed (prior to being in sleep). when exiting sleep mode, the devi ce must be in read mode (r/ w x = v ih ) when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. during sleep mode the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep current (i zz ). all outputs will remain in high-z state while in sleep mode. all inputs are allowed to toggle. the ram will not be selected and will not perform any reads or writes. i/o function 0 ? 7 w ith sfen = l, i/o 8 = h, the value written to address 0 on i/on will determine the status of pdrn (1 = output, 0 = input). w ith sfen = l, i/o 8 = l, the value written to address 0 on i/on will be input to the corresponding odrn location (1 = on, 0 = off). 8 with sfen = l, writing a ?0? to address 0 on this i/o causes the values of i/o 0 ? i/o 7 to be input to their corresponding odr locations. with sfen = l, writing a ?1? to address 0 on this i/o causes the values of i/o 0 ? i/o 7 to be input to their corresponding pdr locations, which in turn determine whether sf 0 ? sf 7 are individually programmed to be inputs (irr) or outputs (odr). 9 ? 15 with sfen = l, reads to address 0 will output the status of the pdr, where i/on = pdrn- 8
22 of 22 march 8, 2007 idt70p9268l advanced datasheet corporate headquarters 6024 silver creek valley road san jose, ca 95138 for sales: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com for tech support: 408-284-2794 dualporthelp@idt.com the idt logo is a registered trademark of integrated device technology, inc. very low power 16k x 16 dual port synchronous static ram industrial temperature range ordering information advanced datasheet: definition "advanced" datasheets contain descriptions for products that are in early release. ?advanced? datasheets are informational onl y. advanced speci- fications are subject to change without notice. revision history 02/06/07: initial release xxxxx aa device type package process/ temperature range blank i commercial (0c to+70c) industrial (-40c to+85c) bz 70p9268 100-pin fpbga (by-100) 16kx16 low-power dual-port ram a g green 999 speed 50 speed in megahertz

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