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rev: 1.12 4/2007 1/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h18/32/36at/b-180/166/150/100 256k x 18, 128k x 32, 128k x 36 4mb sync burst srams 180 mhz?100 mhz 3.3 v v dd 3.3 v and 2.5 v i/o tqfp, bga commercial temp industrial temp features ? ft pin for user-configurable flow through or pipelined operation ? single cycle deselect (scd) operation ? 3.3 v +10%/?5% core power supply ? 2.5 v or 3.3 v i/o supply ? lbo pin for linear or interleaved burst mode ? internal input resistors on mode pins allow floating mode pins ? default to interleaved pipelined mode ? byte write ( bw ) and/or global write ( gw ) operation ? common data inputs and data outputs ? clock control, registered, address, data, and control ? internal self-timed write cycle ? automatic power-down for portable applications ? jedec standard 100-lead tqfp or 119-bump bga package ? rohs-compliant 100-lead tqfp and 119-bump bga packages available functional description applications the gs840h18/32/36a is a 4,718,592-bit (4,194,304-bit for x32 version) high performance synchronous sram with a 2- bit burst address counter. although of a type originally developed for level 2 cache applications supporting high performance cpus, the device now finds application in synchronous sram applications ranging from dsp main store to networking chip set support. the gs840h18/32/36a is available in a jedec standard 100-lead tqfp or 119-bump bga package. controls addresses, data i/os, chip enables ( e 1 , e 2 , e 3 ), address burst control inputs ( adsp , adsc , adv ), and write control inputs ( bx , bw , gw ) are synchronous and are controlled by a positive-edge-triggered clock input (ck). output enable ( g ) and power down control (zz) ar e asynchronous inputs. burst cycles can be initiated with either adsp or adsc inputs. in burst mode, subsequent burst addresses are generated internally and are controlled by adv . the burst address counter may be configured to count in either linear or interleave order with the linear burst order ( lbo ) input. the burst function need not be used . new addresses can be loaded on every cycle with no degradation of chip performance. flow through/pipeline reads the function of the data output register can be controlled by the user via the ft mode pin/bump (pin 14 in the tqfp and bump 5r in the bga). holding the ft mode pin/bump low places the ram in flow through mode, causing output data to bypass the data output register. holding ft high places the ram in pipelined mode, activating the rising-edge-triggered data output register. scd pipelined reads the gs840h18/32/36a is an scd (single cycle deselect) pipelined synchronous sram. dcd (dual cycle deselect) versions are also available. scd srams pipeline deselect commands one stage less than read commands. scd rams begin turning off their outputs immediately after the deselect command has been captured in the input registers. byte write and global write byte write operation is performed by using byte write enable ( bw ) input combined with one or more individual byte write signals ( bx ). in addition, global write ( gw ) is available for writing all bytes at one time, regardless of the byte write control inputs. sleep mode low power (sleep mode) is attained through the assertion (high) of the zz signal, or by stopping the clock (ck). memory data is retained during sleep mode. core and interface voltages the gs840h18/32/36a operates on a 3.3 v power supply and all inputs/outputs are 3.3 v- and 2.5 v-compatible. separate output power (v ddq ) pins are used to de-couple output noise from the internal circuit. parameter synopsis ?180 ?166 ?150 ?100 pipeline 3-1-1-1 tcycle t i 5.5 ns 3.0 ns 335 ma 6.0 ns 3.5 ns 310 ma 6.6 ns 3.8 ns 280 ma 10 ns 4.5 ns 190 ma flow through 2-1-1-1 t tcycle i 8 ns 9 ns 210 ma 8.5 ns 10 ns 190 ma 10 ns 12 ns 165 ma 12 ns 15 ns 135 ma kq dd kq dd
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq b dq b v ss v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b v ss v ddq v ddq v ss dq a dq a v ss vddq dq a dq a v ss nc vdd zz dq a dq a vddq v ss dq a dq a v ss vddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 nc nc b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 256k x 18 top view dqp a a nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 2/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h18a 100-pin tqfp pinout (package t) note: pins marked with nc can be tied to either v dd or v ss . these pins can also be left floating.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 128k x 32 top view dq b nc dq b dq b dq b dq a dq a dq a dq a nc dq c dq c dq c dq d dq d dq d nc dq c nc 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 3/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h32a 100-pin tqfp pinout (package t) note: pins marked with nc can be tied to either v dd or v ss . these pins can also be left floating.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ddq v ss dq c dq c v ss v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d v ss v ddq v ddq v ss dq b dq b v ss v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ss dq a dq a v ss v ddq lbo a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a a e 1 e 2 b d b c b b b a e 3 ck gw bw v dd v ss g adsc adsp adv a a a 128k x 36 top view dq b dqp b dq b dq b dq b dq a dq a dq a dq a dqp a dq c dq c dq c dq d dq d dq d dqp d dq c dqp c 10099989796959493929190898887868584838281 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ft gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 4/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h36a 100-pin tqfp pinout (package t) note: pins marked with nc can be tied to either v dd or v ss . these pins can also be left floating.
tqfp pin description symbol type description a 0 , a 1 i address field lsbs and addr ess counter preset inputs a i address inputs b a in byte write signal for data inputs dq a ; active low b b in byte write signal for data inputs dq b ; active low b c in byte write signal for data inputs dq c ; active low b d in byte write signal for data inputs dq d ; active low bw i byte write?writes all enabled bytes; active low ck i clock input signal; active high gw i global write enable?writes all bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low dq a i/o byte a data input and output pins dq b i/o byte b data input and output pins dq i/o byte c data input and output pins dq d i/o byte d data input and output pins dqp a i/o 9th data i/o pin; byte a dqp b i/o 9th data i/o pin; byte b dqp c i/o 9th data i/o pin; byte c dqp d i/o 9th data i/o pin; byte d zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply nc - no connect gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 5/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
1234567 a v ddq a a adsp aav ddq b nc e 2 aadsc ae 3 nc c nc a a v dd aanc d dq b nc v ss nc v ss dqp a nc e nc dq b v ss e 1 v ss nc dq a f v ddq nc v ss g v ss dq a v ddq g nc d q b b b adv nc nc dq a h dq b n c v ss gw v ss dq a nc j v ddq v dd nc v dd nc v dd v ddq k nc dq b v ss ck v ss nc dq a l dq b nc nc nc b a dq a nc m v ddq dq b v ss bw v ss nc v ddq n dq b nc v ss a 1 v ss dq a nc p nc dqp b v ss a 0 v ss nc dq a r nc a lbo v dd ft anc t nc a a nc a a zz u v ddq nc nc nc nc nc v ddq gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 6/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h18a pad out?119-bump bga?top view (package b)
1234567 a v ddq a a adsp aav ddq b nc e 2 aadsc ae 3 nc c nc a a v dd aanc d dq c nc v ss nc v ss nc dq b e dq c dq c v ss e 1 v ss dq b dq b f v ddq dq c v ss g v ss dq b v ddq g dq c d q c b c adv b b dq b dq b h dq c dq c v ss gw v ss dq b dq b j v ddq v dd nc v dd nc v dd v ddq k dq d dq d v ss ck v ss dq a dq a l dq d dq d b d nc b a dq a dq a m v ddq dq d v ss bw v ss dq a v ddq n dq d dq d v ss a 1 v ss dq a dq a p dq d nc v ss a 0 v ss nc dq a r nc a lbo v dd ft anc t nc nc a a a nc zz u v ddq nc nc nc nc nc v ddq gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 7/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h32a pad out?119-bump bga?top view (package b)
1234567 a v ddq a a adsp aav ddq b nc e 2 aadsc ae 3 nc c nc a a v dd aanc d dq c dqp c v ss nc v ss dqp b dq b e dq c dq c v ss e 1 v ss dq b dq b f v ddq dq c v ss g v ss dq b v ddq g dq c2 d q c b c adv b b dq b dq b2 h dq c dq c v ss gw v ss dq b dq b j v ddq v dd nc v dd nc v dd v ddq k dq d dq d v ss ck v ss dq a dq a l dq d dq d b d nc b a dq a dq a m v ddq dq d v ss bw v ss dq a v ddq n dq d dq d v ss a 1 v ss dq a dq a p dq d dqp d v ss a 0 v ss dqp a dq a r nc a lbo v dd ft anc t nc nc a a a nc zz u v ddq nc nc nc nc nc v ddq gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 8/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h36a pad out?119-bump bga?top view (package b)
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 9/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. bga pin description symbol type description a 0 , a 1 i address field lsbs and address counter preset inputs a i address inputs b a in byte write signal for data inputs dq a ; active low b b in byte write signal for data inputs dq b ; active low b c in byte write signal for data inputs dq c ; active low b d in byte write signal for data inputs dq d ; active low ck i clock input signal; active high bw i byte write?writes all enabled bytes; active low gw i global write enable?writes all bytes; active low e 1 , e 3 i chip enable; active low e 2 i chip enable; active high g i output enable; active low adv i burst address counter advance enable; active low adsp , adsc i address strobe (processor, cache controller); active low dq a i/o byte a data input and output pins dq b i/o byte b data input and output pins dq i/o byte c data input and output pins dq d i/o byte d data input and output pins dqp a i/o 9th data i/o pin; byte a dqp b i/o 9th data i/o pin; byte b dqp c i/o 9th data i/o pin; byte c dqp d i/o 9th data i/o pin; byte d zz i sleep mode control; active high ft i flow through or pipeline mode; active low lbo i linear burst order mode; active low v dd i core power supply v ss i i/o and core ground v ddq i output driver power supply nc - no connect
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 10/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. a1 a0 a0 a1 d0 d1 q1 q0 counter load dq dq register register dq register dq register dq register dq register dq register dq register d q register d q register a0?an lbo adv ck adsc adsp gw bw b a b b b c b d e 1 g zz power down control memory array 36 36 4 a qd e 3 e 2 dqxn?dqxn note: only x36 version shown for simplicity. 1 ft gs840h18/32/36a block diagram
mode pin functions mode name pin name state function burst order control lbo l linear burst h or nc interleaved burst output register control ft l flow through h or nc pipeline power down control zz l or nc active h standby, i dd = i sb gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 11/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: there are pull-up devices on lbo and ft pins and a pull down device on the zz pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. note: the burst counter wraps to initial state on the 5th clock. note: the burst counter wraps to initial state on the 5th clock. linear burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 interleaved burst sequence a[1:0] a[1:0] a[1:0] a[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 burst counter sequences
byte write truth table function gw bw b a b b b c b d notes read h h x x x x 1 read h l h h h h 1 write byte a h l l h h h 2, 3 write byte b h l h l h h 2, 3 write byte c h l h h l h 2, 3, 4 write byte d h l h h h l 2, 3, 4 write all bytes h l l l l l 2, 3, 4 write all bytes l x x x x x gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 12/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. all byte outputs are active in read cycles regar dless of the state of byte write enable inputs. 2. byte write enable inputs b a , b b , b c and/or b d may be used in any combination with bw to write single or multiple bytes. 3. all byte i/os remain high-z during all write operations regardless of the state of byte write enable inputs. 4. bytes ? c ? and ? d ? are only available on the x32 and x36 versions.
synchronous truth table operation address used state diagram key 5 e 1 e 2 adsp adsc adv w 3 dq 4 deselect cycle, power down none x h x x l x x high-z deselect cycle, power down none x l f l x x x high-z deselect cycle, power down none x l f h l x x high-z read cycle, begin burst external r l t l x x x q read cycle, begin burst external r l t h l x f q write cycle, begin burst external w l t h l x t d read cycle, continue burst next cr x x h h l f q read cycle, continue burst next cr h x x h l f q write cycle, continue burst next cw x x h h l t d write cycle, continue burst next cw h x x h l t d read cycle, suspend burst current x x h h h f q read cycle, suspend burst current h x x h h f q write cycle, suspend burst current x x h h h t d write cycle, suspend burst current h x x h h t d notes: 1. x = don?t care, h = high, l = low. 2. e = t (true) if e 2 = 1 and e 3 = 0; e = f (false) if e 2 = 0 or e 3 = 1. 3. w = t (true) and f (false) is defined in the byte write truth table preceding. 4. g is an asynchronous input. g can be driven high at any time to disable active output drivers. g low can only enable active drivers (shown as ?q? in the truth table above). 5. all input combinations shown above are tested and supported. in put combinations shown in gray boxes need not be used to accom plish basic synchronous or synchronous burst oper ations and may be avoided for simplicity. 6. tying adsp high and adsc low allows simple non-burst synchronous operations. see bold items above. 7. tying adsp high and adv low while using adsc to load new addresses allows simple burst operations. see italic items above. gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 13/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
first write first read burst write burst read deselect r w cr cw x x wr r wr x x x simple synchronous operation simple burst synchronous operation cr r cw cr cr notes: 1. the diagram shows only supported (tested) synchr onous state transitions. the diagram presumes g is tied low. 2. the upper portion of the diagram assu mes active use of only the enable (e 1, e 2, e 3 ) and write (b a , b b , b c , b d , bw and gw ) control inputs and that adsp is tied high and adsc is tied low. 3. the upper and lower portions of the diagram together a ssume active use of only the enable, write and adsc control inputs and assumes adsp is tied high and adv is tied low. gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 14/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram
first write first read burst write burst read deselect r w cr cw x x wr r w r x x x cr r cw cr cr w cw w cw notes: 1. the diagram shows supported (tes ted) synchronous state transit ions plus supported transitions that depend upon the use of g . 2. use of ?dummy reads ? (read cycles with g high) may be used to make the transition from read cycles to write cycles without passing through a deselect cycle. dummy read cycles increment the address counter just like normal read cycles. 3. transitions shown in grey tone assume g has been pulsed high long enough to turn the ram?s drivers off and for incoming data to meet data input set up time. gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 15/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. simplified state diagram with g
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ? 0.5 to 4.6 v v ddq voltage in v ddq pins ? 0.5 to 4.6 v v i/o voltage on i/o pins ? 0.5 to v ddq +0.5 ( 4.6 v max.) v v in voltage on other input pins ? 0.5 to v dd +0.5 ( 4.6 v max.) v i in input current on any pin +/ ? 20 ma i out output current on any i/o pin +/ ? 20 ma p d package power dissipation 1.5 w t stg storage temperature ? 55 to 125 o c t bias temperature under bias ? 55 to 125 o c gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 16/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: permanent damage to the device may occur if the absolute maximum ratings are exceeded. operation should be restricted to recomm ended operating conditions. exposure to conditions exceeding the absolute maximum ra tings, for an extended period of time, may affect reliability of this component. power supply voltage ranges parameter symbol min. typ. max. unit notes 3.3 v supply voltage v dd 3.0 3.3 3.6 v 3.3 v v ddq i/o supply voltage v ddq3 3.0 3.3 3.6 v 2.5 v v ddq i/o supply voltage v ddq2 2.3 2.5 2.7 v notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc.
logic levels parameter symbol min. typ. max. unit notes v dd input high voltage v ih 2.0 ? v dd + 0.3 v 1 v dd input low voltage v il ? 0.3 ? 0.8 v 1 v ddq3 i/o input high voltage v ihq3 2.0 ? v ddq + 0.3 v 1,3 v ddq3 i/o input low voltage v ilq3 ? 0.3 ? 0.8 v 1,3 v ddq2 i/o input high voltage v ihq2 0.6*v dd ? v ddq + 0.3 v 1,3 v ddq2 i/o input low voltage v ilq2 ? 0.3 ? 0.3*v dd v 1,3 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 3. v ihq (max) is voltage on v ddq pins plus 0.3 v. gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 17/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. recommended operating temperatures parameter symbol min. typ. max. unit notes ambient temperature (com mercial range versions) t a 0 25 70 c 2 ambient temperature (industrial range versions) t a ? 40 25 85 c 2 notes: 1. the part numbers of industrial temperatur e range versions end the character ?i?. un less otherwise noted, all performance spe cifica - tions quoted are evaluated for worst case in the temperature range marked on the device. 2. input under/overshoot voltage must be ? 2 v > vi < v ddn +2 v not to exceed 4.6 v maximum, with a pulse width not to exceed 20% tkc. 50% tkc v ss ? 2.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 50% tkc v dd + 2.0 v 50% v dd v il
capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf input/output capacitance c i/o v out = 0 v 6 7 pf gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 18/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. note: these parameters are sample tested. ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v dd /2 output reference level v ddq /2 output load fig. 1 notes: 1. include scope and jig capacitance. 2. test conditions as specified with output loading as shown in fig. 1 unless otherwise noted. 3. device is deselected as defined by the truth table. dq v ddq/2 50 ? 30pf * output load 1 * distributed test jig capacitance (t a = 25 = 2.5 v)
dc electrical characteristics parameter symbol test conditions min max input leakage current (except mode pins) i il v in = 0 to v dd ? 1 ua 1 ua zz input current i in1 v dd v in v ih 0 v v in v ih ? 1 ua ? 1 ua 1 ua 100 ua ft , scd, zq input current i in2 v dd v in v il 0 v v in v il ? 100 ua ? 1 ua 1 ua 1 ua output leakage current i ol output disable, v out = 0 to v dd ? 1 ua 1 ua output high voltage v oh2 i oh = ? 8 ma, v ddq = 2.375 v 1.7 v ? output high voltage v oh3 i oh = ? 8 ma, v ddq = 3.135 v 2.4 v ? output low voltage v ol i ol = 8 ma ? 0.4 v operating currents parameter test conditions symbol -180 -166 -150 -100 unit 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c 0 to 70c ?40 to 85c operating current device selected; all other inputs v ih o r v il output open idd pipeline 335 345 310 320 280 290 190 200 ma idd flow through 210 220 190 200 165 175 135 145 ma standby current zz v dd ? 0.2 v isb pipeline 20 30 20 30 20 30 20 30 ma isb flow through 20 30 20 30 20 30 20 30 ma deselect current device deselected; all other inputs v ih or v il idd pipeline 55 65 50 60 50 60 40 50 ma idd flow through 40 50 40 50 35 45 35 45 ma gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 19/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com.
ac electrical characteristics parameter symbol -180 -166 -150 -100 unit min max min max min max min max pipeline clock cycle time tkc 5.5 ? 6.0 ? 6.7 ? 10 ? ns clock to output valid tkq ? 3.0 ? 3.5 ? 3.8 ? 4.5 ns clock to output invalid tkqx 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in low-z tlz 1 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns flow through clock cycle time tkc 9.0 ? 10.0 ? 12.0 ? 15.0 ? ns clock to output valid tkq ? 8.0 ? 8.5 ? 10.0 ? 12.0 ns clock to output invalid tkqx 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock to output in low-z tlz 1 3.0 ? 3.0 ? 3.0 ? 3.0 ? ns clock high time tkh 1.3 ? 1.3 ? 1.3 ? 1.3 ? ns clock low time tkl 1.5 ? 1.5 ? 1.5 ? 1.5 ? ns clock to output in high-z thz 1 1.5 3.2 1.5 3.5 1.5 3.8 1.5 5 ns g to output valid toe ? 3.2 ? 3.5 ? 3.8 ? 5 ns g to output in low-z tolz 1 0 ? 0 ? 0 ? 0 ? ns g to output in high-z tohz 1 ? 3.2 ? 3.5 ? 3.8 ? 5 ns setup time ts 1.5 ? 1.5 ? 1.5 ? 2.0 ? ns hold time th 0.5 ? 0.5 ? 0.5 ? 0.5 ? ns zz setup time tzzs 2 5 ? 5 ? 5 ? 5 ? ns zz hold time tzzh 2 1 ? 1 ? 1 ? 1 ? ns zz recovery tzzr 20 ? 20 ? 20 ? 20 ? ns gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 20/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. notes: 1. these parameters are sampled and are not 100% tested 2. zz is an asynchronous signal. however, in order to be recognized on any given clock cycl e, zz must meet the specified setup a nd hold times as specified above.
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 21/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. pipeline mode timing begin read a cont cont deselect write b read c read c+1 read c+2 read c+3 cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts ts th ts th ts th ts burst readburst read single write tkctkc tkltkl tkh single write single read tkh single read q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) abc deselected with e1 e1 masks adsp e2 and e3 only sampled with adsp and adsc adsc initiated read ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 22/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. flow through mode timing begin read a cont cont write b read c read c+1 read c+2 read c+3 read c cont deselect thz tkqx tkq tlz th ts tohz toe th ts th ts th ts th ts th ts th ts th ts th ts th ts th ts tkctkc tkltkl tkhtkh abc q(a) d(b) q(c) q(c+1) q(c+2) q(c+3) q(c) e2 and e3 only sampled with adsc adsc initiated read deselected with e1 fixed high ck adsp adsc adv a0?an gw bw ba ?bd e1 e2 e3 g dqa?dqd
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 23/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. sleep mode timing diagram tzzr tzzh tzzs hold setup tkltkl tkhtkh tkctkc ck adsp adsc zz application tips single and dual cycle deselect scd devices force the use of ?dummy read cycles? (read cycles that are launched no rmally but that are ended with the output drivers inactive) in a fully synchronous en vironment. dummy read cycles waste perfor mance but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of rams. dcd srams do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple ba nk application (wait states need not be inserted at bank addre ss boundary crossings), but greater care must be exercised to av oid excessive bus contention.
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 24/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. gs840h18/32/36a output dr iver characteristics -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 v out (pull down) vddq - v out (pull up) i out (ma) 3.6v pd hd 3.3v pd hd 3.1v pd hd 3.1v pu hd 3.3v pu hd 3.6v pu hd pull up drivers pull down drivers vddq vout i out vss
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 25/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. tqfp package drawing (package t) d1 d e1 e pin 1 b e c l l1 a2 a1 y notes: 1. all dimensions are in millimeters (mm). 2. package width and length do not include mold protrusion. symbol description min. nom. max a1 standoff 0.05 0.10 0.15 a2 body thickness 1.35 1.40 1.45 b lead width 0.20 0.30 0.40 c lead thickness 0.09 ? 0.20 d terminal dimension 21.9 22.0 22.1 d1 package body 19.9 20.0 20.1 e terminal dimension 15.9 16.0 16.1 e1 package body 13.9 14.0 14.1 e lead pitch ? 0.65 ? l foot length 0.45 0.60 0.75 l1 lead length ? 1.00 ? y coplanarity 0.10 lead angle 0 ? 7
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 26/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. package dimensions?119-bump fpbga (package b, variation 1 ) 7 6 5 4 3 2 1 a1 bottom view 1.27 7.62 1.27 20.32 140.20 220.20 b a 0.20(4x) ?0.10 ?0.30 c c a b s s ?0.60~0.90 (119x) c seating plane 0.15 c 0.50~0.70 2.06.0.13 0.900.10 0.15 c a b c d e f g h j k l m n p r t u 0.560.05 s s a b c d e f g h j k l m n p r t u 0.70 ref 12.00 1 2 3 4 5 6 7 220.20 19.50 pin #1 corner ?1.00(3x) ref 30 typ. 0.15 c
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 27/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. ordering information for gs i synchronous burst rams org part number 1 type package speed 2 (mhz/ns) t a 3 status 256k x 18 gs840h18at-180 pipeline/flow through tqfp 180/8 c 256k x 18 gs840h18at-166 pipeline/flow through tqfp 166/8.5 c 256k x 18 gs840h18at-150 pipeline/flow through tqfp 150/10 c 256k x 18 gs840h18at-100 pipeline/flow through tqfp 100/12 c 128k x 32 gs840h32at-180 pipeline/flow through tqfp 180/8 c 128k x 32 gs840h32at-166 pipeline/flow through tqfp 166/8.5 c 128k x 32 gs840h32at-150 pipeline/flow through tqfp 150/10 c 128k x 32 gs840h32at-100 pipeline/flow through tqfp 100/12 c 128k x 36 gs840h36at-180 pipeline/flow through tqfp 180/8 c 128k x 36 gs840h36at-166 pipeline/flow through tqfp 166/8.5 c 128k x 36 gs840h36at-150 pipeline/flow through tqfp 150/10 c 128k x 36 gs840h36at-100 pipeline/flow through tqfp 100/12 c 256k x 18 gs840h18at-180i pipeline/flow through tqfp 180/8 i 256k x 18 gs840h18at-166i pipeline/flow through tqfp 166/8.5 i 256k x 18 gs840h18at-150i pipeline/flow through tqfp 150/10 c 256k x 18 gs840h18at-100i pipeline/flow through tqfp 100/12 c 128k x 32 gs840h32at-180i pipeline/flow through tqfp 180/8 i 128k x 32 gs840h32at-166i pipeline/flow through tqfp 166/8.5 i 128k x 32 gs840h32at-150i pipeline/flow through tqfp 150/10 c 128k x 32 gs840h32at-100i pipeline/flow through tqfp 100/12 c 128k x 36 gs840h36at-180i pipeline/flow through tqfp 180/8 i 128k x 36 gs840h36at-166i pipeline/flow through tqfp 166/8.5 i 128k x 36 gs840h36at-150i pipeline/flow through tqfp 150/10 c 128k x 36 gs840h36at-100i pipeline/flow through tqfp 100/12 c 256k x 18 gs840h18agt-180 pipeline/flow through rohs-compliant tqfp 180/8 c 256k x 18 gs840h18agt-166 pipeline/flow through rohs-compliant tqfp 166/8.5 c 256k x 18 gs840h18agt-150 pipeline/flow through rohs-compliant tqfp 150/10 c 256k x 18 gs840h18agt-100 pipeline/flow through rohs-compliant tqfp 100/12 c 128k x 32 gs840h32agt-180 pipeline/flow through rohs-compliant tqfp 180/8 c 128k x 32 gs840h32agt-166 pipeline/flow through rohs-compliant tqfp 166/8.5 c notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs840h32at -8t. 2. the speed column indicates the cycle frequency (mhz) of the dev ice in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site ( www.gsitechnology.com ) for a complete listing of current offerings.
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 28/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 128k x 32 gs840h32agt-150 pipeline/flow through rohs-compliant tqfp 150/10 c 128k x 32 gs840h32agt-100 pipeline/flow through rohs-compliant tqfp 100/12 c 128k x 36 gs840h36agt-180 pipeline/flow through rohs-compliant tqfp 180/8 c 128k x 36 gs840h36agt-166 pipeline/flow through rohs-compliant tqfp 166/8.5 c 128k x 36 gs840h36agt-150 pipeline/flow through rohs-compliant tqfp 150/10 c 128k x 36 gs840h36agt-100 pipeline/flow through rohs-compliant tqfp 100/12 c 256k x 18 gs840h18agt-180i pipeline/flow through rohs-compliant tqfp 180/8 i 256k x 18 gs840h18agt-166i pipeline/flow through rohs-compliant tqfp 166/8.5 i 256k x 18 gs840h18agt-150i pipeline/flow through rohs-compliant tqfp 150/10 c 256k x 18 gs840h18agt-100i pipeline/flow through rohs-compliant tqfp 100/12 c 128k x 32 gs840h32agt-180i pipeline/flow through rohs-compliant tqfp 180/8 i 128k x 32 gs840h32agt-166i pipeline/flow through rohs-compliant tqfp 166/8.5 i 128k x 32 gs840h32agt-150i pipeline/flow through rohs-compliant tqfp 150/10 c 128k x 32 gs840h32agt-100i pipeline/flow through rohs-compliant tqfp 100/12 c 128k x 36 gs840h36agt-180i pipeline/flow through rohs-compliant tqfp 180/8 i 128k x 36 gs840h36agt-166i pipeline/flow through rohs-compliant tqfp 166/8.5 i 128k x 36 gs840h36agt-150i pipeline/flow through rohs-compliant tqfp 150/10 c 128k x 36 gs840h36agt-100i pipeline/flow through rohs-compliant tqfp 100/12 c 256k x 18 gs840h18ab-180 pipeline/flow through 119 bga (var. 1) 180/8 c 256k x 18 gs840h18ab-166 pipeline/flow through 119 bga (var. 1) 166/8.5 c 256k x 18 gs840h18ab-150 pipeline/flow through 119 bga (var. 1) 150/10 c 256k x 18 GS840H18AB-100 pipeline/flow through 119 bga (var. 1) 100/12 c 128k x 32 gs840h32ab-180 pipeline/flow through 119 bga (var. 1) 180/8 c 128k x 32 gs840h32ab-166 pipeline/flow through 119 bga (var. 1) 166/8.5 c 128k x 32 gs840h32ab-150 pipeline/flow through 119 bga (var. 1) 150/10 c 128k x 32 gs840h32ab-100 pipeline/flow through 119 bga (var. 1) 100/12 c 128k x 36 gs840h36ab-180 pipeline/flow through 119 bga (var. 1) 180/8 c 128k x 36 gs840h36ab-166 pipeline/flow through 119 bga (var. 1) 166/8.5 c 128k x 36 gs840h36ab-150 pipeline/flow through 119 bga (var. 1) 150/10 c 128k x 36 gs840h36ab-100 pipeline/flow through 119 bga (var. 1) 100/12 c 256k x 18 gs840h18ab-180i pipeline/flow through 119 bga (var. 1) 180/8 i ordering information for gsi sync hronous burst rams (continued) org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs840h32at -8t. 2. the speed column indicates the cycle frequency (mhz) of the dev ice in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 29/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 256k x 18 gs840h18ab-166i pipeline/flow through 119 bga (var. 1) 166/8.5 i 256k x 18 gs840h18ab-150i pipeline/flow through 119 bga (var. 1) 150/10 c 256k x 18 GS840H18AB-100i pipeline/flow through 119 bga (var. 1) 100/12 c 128k x 32 gs840h32ab-180i pipeline/flow through 119 bga (var. 1) 180/8 i 128k x 32 gs840h32ab-166i pipeline/flow through 119 bga (var. 1) 166/8.5 i 128k x 32 gs840h32ab-150i pipeline/flow through 119 bga (var. 1) 150/10 c 128k x 32 gs840h32ab-100i pipeline/flow through 119 bga (var. 1) 100/12 c 128k x 36 gs840h36ab-180i pipeline/flow through 119 bga (var. 1) 180/8 i 128k x 36 gs840h36ab-166i pipeline/flow through 119 bga (var. 1) 166/8.5 i 128k x 36 gs840h36ab-150i pipeline/flow through 119 bga (var. 1) 150/10 c 128k x 36 gs840h36ab-100i pipeline/flow through 119 bga (var. 1) 100/12 c 128k x 36 gs840h36agb-180 pipeline/flow through rohs-compliant 119 bga (var. 1) 180/8 c 128k x 36 gs840h36agb-166 pipeline/flow through rohs-compliant 119 bga (var. 1) 166/8.5 c 128k x 36 gs840h36agb-150 pipeline/flow through rohs-compliant 119 bga (var. 1) 150/10 c 128k x 36 gs840h36agb-100 pipeline/flow through rohs-compliant 119 bga (var. 1) 100/12 c 128k x 36 gs840h36agb-180i pipeline/flow through rohs-compliant 119 bga (var. 1) 180/8 i 128k x 36 gs840h36agb-166i pipeline/flow through rohs-compliant 119 bga (var. 1) 166/8.5 i 128k x 36 gs840h36agb-150i pipeline/flow through rohs-compliant 119 bga (var. 1) 150/10 c 128k x 36 gs840h36agb-100i pipeline/flow through rohs-compliant 119 bga (var. 1) 100/12 c ordering information for gsi sync hronous burst rams (continued) org part number 1 type package speed 2 (mhz/ns) t a 3 status notes: 1. customers requiring delivery in tape and reel should add the c haracter ?t? to the end of the part number. example: gs840h32at -8t. 2. the speed column indicates the cycle frequency (mhz) of the dev ice in pipelined mode and the latency (ns) in flow through mo de. each device is pipeline/flow through mode-selectable by the user. 3. t a = c = commercial temperature range. t a = i = industrial temperature range. 4. gsi offers other versions this type of device in many differ ent configurations and with a vari ety of different features, on ly some of which are covered in this data sheet. see the gsi technology web site (www.gsitechnology.com ) for a complete listing of current offerings.
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 30/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 4mb burst datashee t revision history rev. code: old; new types of changes format or content page /revisions;reason gs84018/32/36 rev 1.02c 5/ 1999; gs84018/32/36 8/1999d format/typos ? document/continued changing to new format. content ? gs84018/32/36 8/ 1999;gs84018/32/36 9/ 1999e format/typos ? took ?e? out of 840he...in core and interface voltages. ? pin outs/new small caps format. ? timing diagrams/new format. ? block diagrams/new small caps format. content ? pin outs/x32 & x36 tqfp/changed pin 72 from dqa3 to dqb3. ? pin description/rearranged address inputs to match order on tqfp pinout. ? tqfp package diagram/corrected dimension d max from 20.1 to 22.1. gs84018/32/36 9/ 1999e;gs84018/32/36 ? gs84018/32/3610-11/ 1999;gs84018/32/362/ 2000g format ? new gsi logo ? took ?pin? out of heading for consistency. gs84018/32/362/2000g; 840h18a_r1_04 content ? corrected all part order numbers 840h18a_r1_04; 840h18a_r1_05 content ? updated pin description table 840h18a_r1_05; 840h18a_r1_06 content ? updated bga pin description table to meet jedec standard 840h18a_r1_06; 840h18a_r1_07 content/format ? updated table on page 1 ? updated operating currents table on page 18 ? updated ac electrical char acteristics table on page 19 ? added 150 mhz and 100 mhz ? updated format to comply with technical publications standards 840h18a_r1_07; 840e18_r1_08 content ? reduced i dd by 20 ma in table on page 1 and operating currents table 840h18a_r1_08; 840h18_r1_09 content ? removed 200 mhz references from entire datasheet 840h18a_r1_09; 840h18a_r1_10 content ? updated format ? matched current numbers to nbt parts ? removed preliminary banner
gs840h18/32/36at/b-180/166/150/100 rev: 1.12 4/2007 31/31 ? 1999, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. 840h18a_r1_10; 840h18a_r1_11 content ? added pb-free tqfp information ? added variation number to 119 bga information 840h18a_r1_11; 840h18a_r1_12 content ? added note to tqfp pinouts (pg. 2, 3, 4) ? updated power supply voltage ranges table (pg. 16) ? updated logic level tables (pg. 17) ? changed pb-free to rohs-c ompliant (entire document) ? added rohs-compliant 119 bga (pg. 1, 27, 28, 29, 30) 4mb burst datashee t revision history

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