AN548/0792 the imsa110 back-end post processor application note summary page 1. introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. description of the backend post processor . . . . . . . . . . . . . . . . . . . . . . 1 2.1 input block (shifter, cascade adder and rectifier) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 statistics monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 data conditioning unit (data transformation unit and data normaliser) . . . . . . . . 3 2.3.1 data transformation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3.2 data normaliser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 output unit (output adder and output multiplexers) . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.1 output adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.2 output multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. uses of the backend post processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.1 local area averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3.2 histogram equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 edge detection and enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3.1 edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3.2 edge enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 feature recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.5 changing conditions compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.6 binary image processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.7 multilevel thresholding - image contouring . . . . . . . . . . . . . . . . . . . . . . 8 3.8 dynamic range compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 i. introduction the imsa110 consists of a high performance con- figurable array of multiply-accumulators (420 mops), three programmable length 1120 stage shift registers and a versatile backend post proc- essing unit. all these features are controlled from a microprocessor interface. the comprehensive on- chip facilities ensure that a single device is capable of dealing with many tasks commonly found in the fields of signal and image processing. the backend post processing unit gives the imsa110 a high degree of flexiblility, especially for image processing applications. this document de- scribes by example some of the uses of the back- end post processor. unless specified otherwise all the examples con- sidered will be based around image processing applications with 8 bits per pixel being used to represent the image data. 2. description of the back-end post processor figure 1 shows the functional blocks and intercon- nections which are present within the backend post processor of the imsa110. 1/10
shifter -2 to 14 shifter [8:0] cascade adder rectifier prescaler byte select min/max register comparator gt/lt over/undershoot count over/undershoot buffer min/max buffer lsr 64 x 32 bit ram 8 6 usr 32 y bus [26:22] [21:0] 32 data transformation unit 22 22 22 mux 22 22 22 22 from mac array negative overflow positive overflow cascade input pads 1 rounding 22 control statistics monitor 5 22 22 1 1 x bus 8 from bcr mux zero data 22 mux 22 1 rounding output adder 22 22 8 8 6 [21:14] [7:0] mux mux 88 [13:8] [21:14] [7:0] 22 clock cycle cascade output pads 1 2 3 4 5 6 over/under select (isbs) 2 data normaliser AN548-01.eps figure 1 : detailed block diagram of the back-end post processing unit the imsa110 back-end post processor 2/10
this diagram can be broken down into 4 main sections, the input block, statistics monitior, data conditioning unit and output block. a brief descrip- tion of each of these major sections is given below, for full details reference should be made to the data sheet. 2.1 input block (shifter, cascade adder and rectifier) data from the mac array encounters the shifter when it enters the input block. the shifter is capable of up to 8 arithmetic shifts in either direction. when shifting left it is possible for an overflow to occur. such an overflow is not detected by the device, hence it is left to the user to ensure that uninten- tional overflows do not occur. when shifting right rounding is applied to improve the accuracy of the device. the magnitude and direction of the shift are controlled by bcr0[5..1] as described in the data sheet. the output data from the shifter is fed into the cascade adder. here it is added to both the round- ing bit generated by the shifter and the data applied to either the cascade input bus or zero depending on the setting of bcr0[0]. should the result of the 22 bit signed addition be greater than 2 21 -1 then a positive overflow is generated. similarly if the result is less than -2 22 a negative overflow is generated. the output from the cascade adder can be option- ally full or half wave rectified depending on the setting of bcr0[7..6]. the output of the rectifier drives the x bus. note that when full wave rectifi- cation is being used and the output of the cascade adder is -2 21 then the output from the rectifier remains as -2 21 . 2.2 statistics monitor the statistics monitior allows the x bus to be moni- tored for certain conditions. four different modes of operation are possible and these are tabulated below: mode bcr1[1] bcr1[0] max register 0 1 min register 0 0 overshoot counter 1 1 undershoot counter 1 0 when configured to be in max register mode and the x bus exceeds the current threshold in the mmr (max/min register), then the mmr is loaded with the value on the x bus and the counter (ouc) is incremented. if the threshold is not exceeded then no action is taken. thus assuming the mmr was initially set to -2 21 its value at some later time is the maximum value which has appeared on the x bus in that period, and the ouc has been incre- mented by the number of times the threshold has been updated. if configured to be in min register mode the thresh- old is updated and the counter incremented when- ever the x bus is less than the current threshold. note that when operating in max/min register mode if a positive or negative overflow occurs then the threshold is not updated since this could leave a misleading value in the mmr. as an overshoot counter the statistics monitor op- erates by incrementing the ouc every time the value on the x bus exceeds the threshold in the mmr or if a positive overflow occurs. the ouc is unsigned and will not wrap around, thus behaving as a saturating counter. similarly when configured to be in undershoot counter mode the ouc is incremented every time the value on the x bus is less than the current threshold. when overflows occur this is recorded in bits 22 and 23 of the mmr. positive overflows cause bit 22 to be set while negative overflows cause bit 23 to be set. these bits may be cleared by writing to the mmb copy location. direct access to the mmr and ouc via the micro- processor interface is not possible. instead the reading and writing of these registers is performed by making use of the mmb, cmm, oub and cou registers. full details may be found in the data sheet. 2.3 data conditioning unit (data transformation unit and data normaliser) 2.3.1. data transforma tion unit the data transformation unit contains a prescaler, an under/over select detector, a look up table and a byte selector. it may be used on its own to provide arbitrary data mappings of an 8 bit segment of the x bus, or in conjunction with the data normaliser to implement sophisticated dynamic range compres- sion functions. the prescaler allows an 8 bit field to be selected from anywhere within the 22 bits of the x bus. this 8 bit field is used as an address to the lut. the way in which the address is treated is defined in scr[6]. if this bit is set to zero then the address is signed and runs from -128 to 127. alternatively if this bit is set to one then the address is unsigned and runs from 0 to 255. the over/under select detector monitors the operaton of the prescaler to the imsa110 back-end post processor 3/10
ensure that all the significant bits and the sign of the x bus are included within the 8 bit field. if this is not the case then an overselect or underselect signal is generated depending on whether the x bus is positive or negative respectively. the lut consists of sixty four 32 bit words. in addition there are a further two 32 bit locations known as the upper and lower saturation registers (usr, lsr). the most significant 6 bits of the address field are used to select one of the 32 bit registers in the lut. this 32 bit output is known as the y bus. the least significant 2 bits of the address field are then used to control a byte select on the output. thus the lut may be used to provide arbitrary 8bit - 8bit data transformations. positive overflows on the x bus or overselects in the prescaler cause the lut to access the usr overriding the address supplied by the prescaler. similarly negative overflows and underselects cause the lut to access the lsr. when such conditions occur the byte select control is also overridden thus causing the most significant byte (byte 3) of the appropriate saturation register to appear on the byte wide output of the data trans- formation unit. the lut is programmed via the memory interface. the addressing for the lut corresponds directly to the 8 bit field, assuming that the byte selector is being used. to enable access to the lut, usr and lsr from the microprocessor interface the lut access control bit acr[1] must be set to zero. this forces the y bus to zero and causes the normaliser to be controlled by bcr3[7..3] regardless of the setting of the dynamic normalisation bit. once the lut has been programmed the lut access control bit may be reset to one thus allowing the lut to be used in the data transformation unit. 2.3.2 data normaliser the data normaliser contains a shifter followed by a zero data unit. the shifter is capable of right shifts of up to 14 bits and left shifts of up to 2 bits. any amount of shift outside this range invokes the zero data unit which zeros the output of the data normal- iser. the amount of shift is specified by one of two 5 bit sources. these are either bcr3[7..3] or bits 26 to 22 of the y bus. the source currently selected is determined by the setting of bcr3[2]. 2.4 output unit (output adder and output multiplexers) 2.4.1 output adder the output adder takes one of its inputs from the data normaliser (including the rounding bit). the other input is either the least significant 22 bits of the y bus or zero depending on the setting of bcr3[1] 2.4.2 output multiplexers the output multiplexers allow the selected byte from the lut to be optionally selected to drive either the most or least significant 8 bits of the cascade output pins. this feature is controlled by the setting of bcr2[5..6]. any cascade output pins not being driven by the selected byte are driven by the appropriate bits of the output adder. 1 1 1 1 1 1 1 1 1 1 9 AN548-02.eps figure 2 : local averaging filter kernel 3. using the backend of the ims a110s 3.1 local area averaging local averaging is the one of the simplest image filtering operations. a typical local averaging filter may be seen in figure 2. although this filter looks very simple to implement on imsa110s there is one slight problem and that is how to achieve the divide by nine operation. the operation is necessary to ensure that the output image data requires the same number of bits to represent it as the input data. the imsa110 is capable of dividing by integer powers of two. using this capability the 1 9 could be replaced with 1 16 . although this would adequately restrict the magnitude of the output data a signifi- cant loss of dynamic r ange could occur. a better solution is to gener ate an approximation to 1 9 in the form shown below. where x represents the coeffi- cient and y the number of righ shift below : x 2 y ? 1 9 it may be simply shown that the closest approxima- tion which may be used with ims a110s is: x = 57 y = 9 the imsa110 back-end post processor 4/10
by using these values the local averaging kernel to be programmed into the imsa110 is as shown below: 1 9 2 57 57 57 57 57 57 57 57 57 AN548-03.eps figure 3 : modified local averaging filter kernel the division by 2 9 cant be performed by the shifter in the input block since it is only capable of right shifting up to 8 places. the shifter in the normaliser however is capable of right shifting the required nine places. to configure an imsa110 so that it performs the local averaging operation used in the above exam- ple the following values would have to be pro- grammed into the coefficient and control registers: coeff register 0123456 cr0a 57 57 57 0000 cr0b 57 57 57 0000 cr0c 57 57 57 0000 registers data msb .. lsb scr 0 x x 1 1 1 x 0 acr 000000x0 bcr0 x x 000001 bcr1 000000xx bcr2 0 0 0 xxxxx bcr3 01001000 x : indicates dont care. exactly the same technique may be applied to other filter kernels which require an awkward divi- sion. for example the edge enhancement opera- tion shown in figure 4 requires a division by 5 operation. a modified version of the kernel which may be easily implemented is shown below. 1 5 0 0 0 0 - 1 - 1 - 1 - 1 5 AN548-04.eps figure 4 : edge enhancement filter kernel 1 2 0 00 0 64 - 13 - 13 - 13 - 13 6 AN548-05.eps figure 5 : modified edge enhancement filter kernel 3.2 histogram equalization histogram equalization is one example of the wider field of histogram modification [1]. all such opera- tions manipulate the grey levels within an image to generate a new image with a modified grey level histogram. the histogram equalization technique attempts to manipulate the grey levels within an image so that an even spread is obtained across the entire range of intensities. details of the tech- nique are widely available in the technical press [1] so an in depth discussion will not be provided here. there are two distinct stages in performing a histo- gram equalization the second of which imsa110s are capable of performing. the first stage is the calculation of the transfer function which maps the original image onto the histogram equalized image. the main computational cost involved in this stage is the determination of the original histogram. the second stage requires the implementation of the transfer function to map the grey levels in the input image to the equalized grey levels in the output image. the transfer function is implemented by making use of the arbitrary 8bit-8bit mapping ability of the lut present within the imsa110. the offset of each location in the lut may be regarded as one of the original grey levels and the value programmed into that location is the transformed grey level after equalization. for example suppose that it was desired to use an imsa110 to perform a histogram equalization on 8 -bit image data applied to the cascade input port with the mac coefficients programmed to zero. the table below shows the values which would have to be programmed into the main control registers. the output data would appear on the lower 8 bits of the cascade output port. the imsa110 back-end post processor 5/10
register data msb .. lsb scr 0 1 x 1 xxxx acr 0 0 0000ax bcr0 xxxxxxx0 bcr1 0 0 0000xx bcr2 0 1 000000 bcr3 1 0 000000 lut n dddddddd x : indicates dont care. a : set to 0 to prog ram lut, set to 1 to allow imsa110 lut ac- cess. d : program with the mapping n t d[7..0]. by modifying the transfer function programmed into the lut many other operations are possible includ- ing thresholding and image contouring which are described in sections 3.3 and 3.7 respectively. 3.3 edge detection and enhancement 3.3.1 edge detection edge detection is a very important image process- ing operation since it is often the first stage in feature recognition. for example consider the hori- zontal edge detector shown in figure 6. this filter is actually the y component of the s?bel operator. the output (h(x,y)) from the filter when convolved with an image is a measure of the change of intensity in the y direction at each point. 1 1 1 4 y g = - 1 - 1 - 2 000 2 AN548-06.eps figure 6 : y component of the s?bel operator the output at any given point may be positive or negative depending on the direction of the intensity gradient vector at that location. often when using such a filter to detect vertical edges only the mag- nitude of the gradient vector is of interest (i.e. its direction is irrelevant). the results may be modified to simply indicate the magnitude by processing the output as shown below. f[x,y] = | h ( x , y ) | the modulus operation is an ideal example of the use of full wave rectification. the tables below show the configuration of the coefficient and control reg- isters necessary to calculate |h ( x,y ) |. coeff register 0123456 cr0a -1 -2 -1 0000 cr0b 0000000 cr0c 1210000 registers data msb .. lsb scr 0xx101x0 acr 000000x0 bcr0 10000101 bcr1 000000xx bcr2 0 0 0 xxxxx bcr3 00000000 x : indicates dont care. typically once an edge detection operator has been convolved with an image it is necessary to make some sort of decision based on the magni- tude as to whether an edge exists at each point of the output. the method usually used is known as thresholding [1]. the threshold operation involves mapping all points with a grey level greater than a given thresh- old to one value (typically 255), and all other points to another value (typically 0). the lookup table as described in section 3.2 provides the ability to perform just such an arbitrary mapping. by modify- ing the control registers presented above it is pos- sible to do not only the edge detection operation and the full wave rectification, but also to apply an arbitrary threshold all within a single device. the updated table of control registers is shown below: registers data msb .. lsb scr 01x101x0 acr 000000a0 bcr0 10000101 bcr1 000000xx bcr2 01000000 bcr3 10000000 lut n dddddddd x : indicates dont care. a : set to 0 to program lut, set to 1 to allow ims a110 lut ac- cess. d : set to 0 for n less t han or equal to the threshold, set to 1 other- wise. 3.3.2 edge enhancement edge enhancement is often applied to images to either counteract blurring or to produce a sharper looking image which is sometimes aesthetically more pleasing. one filter kernel which gives an edge enhancement may be seen in figure 5. when this filter is convolved with an image it is poss ible to generate not only valid positive image data but also negative values under some circumstances. one solution would be to apply full wave rectifica- the imsa110 back-end post processor 6/10
tion to the result however it is generally more acceptable if half wave rectification is applied. to implement such a filter on an imsa110 the coefficient and control registers would have to be set up as shown in the following tables. coeff register 0123456 cr0a 0 -13 00000 cr0b -13 64 -13 0000 cr0c 0 -13 00000 registers data msb .. lsb scr 0xx101x0 acr 00000000 bcr0 0 1 001101 bcr1 0 0 0000xx bcr2 0 0 0 xxxxx bcr3 0 0 000000 x : indicates dont care. 3.4 feature recognition by using the statistics monitor it is possible to get the imsa110 to see if a given pattern was present within an image. to enable this process to take place a number of things have to be done: the mac coefficients must be configured as a pattern detector for the pattern which is b eing searched for. if the pattern is large a number of devices can be cascaded [2] to achieve the re- quired window size. the statistics monitor must be configured so that it is in max register mode. the mmr must be programmed with -2 21 at the start of the search period (typically at the start of a frame). as one or more images are processed the mmr register is continually updated to indicate the high- est mac output which has occured so far. when the pattern detector encounters the pattern that it is designed to search for the mac output should generate a very large output which exceeds a given threshold. this output will be recorded in the mmr. by examining the mmr at the end of the search period (typically at the end of the frame) it is possi- ble to see if the threshold has been exceeded. if this is the case then it is possible to say that the pattern pr obably occurred somewhere within the data that was processed. the setting of the thresh- old to achieve reliable operation requires system teaching using known sets of data. in a similar fashion it is possible to perform feature recognition with the statistics monitor configured as an overshoot counter. in this mode of operation the detection of the desired pattern is indicated by an increase in the value of the ouc (care must be taken to ensure that it does not saturate). the method of setting the threshold at which the over- shoot counter is incremented is identical to the description given in the previous paragraph. at first sight it may appear that this method enables the number of occurences of a given pattern to be counted. unfortunately this is unlikely to be the case for the following reason. when the pattern being searched for is encoun- tered it is possible for the ouc to be incremented more than once. this is caused by a combination of uncertainty about the pattern and the properties of pattern detectors as decribed below: in a typical pattern matching application the pat- tern is rarely perfect. degradations from the ideal may be caused by additive noise, distortion of the object, changing lighting conditions etc. to take this into account the threshold is normally set to a value which is low enough to increment the ouc for all likely occurences of the pattern. due to the nature of pattern detectors a large output is not only generated when the detector is coincident with the pattern but quite large out- puts can also be generated when it is just off centre. the combination of these two problems means that each occurence of the pattern could increment the ouc one or more times thus damaging any indica- tion the change in ouc could give about the num- ber of occurences of a pattern. 3.5 changing conditions compensation the front end of many automated image process- ing systems will experience slowly changing input conditions. these may occur due to changing light levels, drifting component tolerances etc. the in- clusion of the max/min register modes of the sta- tistics monitor allows the system to automatically compensate for these changes. for example con- sider a system which uses daylight to illuminate the field of view. as the day proceeds the output from the camera will change. by spending periods of time monitoring both the maximum and minimum levels in the data stream it is possible to adapt the system to take these changes into account. the imsa110 back-end post processor 7/10
3.6 binary image procesing a binary image is one which contains only two grey levels. typically a binary image is the result of a thresholding operation as described in section 3.3. by making use of the mac and the backend it is possible to implement a wide variety of different operations some of which are summarised below: isolated pixel removal removal of all pixels which have no identical neighbour. line linking bridging of small gaps between pixels. encoding according to connectivity coding of pixels depending on their connectivity with re- spect to surrounding pixels. binary thinning including staircase elimination [3] [4] [5] [6] [7] feature growth opposite of the above. conways game of life the oldest computer game known to man. as an example of the techniques involved isolated pixel removal will be examined in more detail. consider a pixel with its 8 surrounding neighbours as shown in figure 7. it is assumed that active and inactive pixels are represented by 1 and 0 respec- tively. p 0 AN548-07.eps figure 7 : a pixel and its 8 closed neighbours 1 1 1 1 1 1 1 1 9 AN548-08.eps figure 8 : filter kernel for isolated pixel removal if the central pixel is in the opposite state to all its surrounding neighbours then the value of the cen- tral pixel must be toggled. in order to perform the transformation it is necessary to develop a filter kernel which will give a unique output for each of these two condition. one such kernel is shown in figure 8 below: by programming the mac with this kernel the outputs generated when the binary image is ap- plied will range from 0 to 17 inclusive. the two particular cases of special interest are 8 and 9 which correspond to a 0 surrounded by 1s and a 1 surrounded by 0s respectively. to convert from the output of the mac to a binary image in the original format use may be made of the lut. the complete mapping for the lut and the setting of the main control registers for this example are tabulated below: coeff register 0123456 cr0a 1110000 cr0b 1910000 cr0c 1110000 registers data msb .. lsb scr 01x111x0 acr 000000a0 bcr0 x x 000001 bcr1 000000xx bcr2 01000000 bcr3 10000000 lut 0-7 00000000 lut 8 00000001 lut 9 00000000 lut 10-17 00000001 x : indicates dont care. a : set to 0 to program lut, set to 1 to allow ims a110 lut ac- cess. 3.7 multilevel thresholding - image contouring often it is desired to highlight a number of areas within a single image. providing that each of the areas occupies a different region of the grey scale then this can be achieved by multi level threshold- ing (sometimes known as image contouring). typi- cally such a technique is often used in medical work. for example consider an x-ray taken of a patient which may well contain three very distinct regions: clear regions: representing bone. intermediate regions: representing major body organs. dark regions: representing regions where the x-rays met little resistance. by using the lut to provide arbitrary 8bit-8bit data mappings as descibed in sections 3.2 and 3.3 it is possible to assign each of these three regions a separate value. as a further enhancement external hardware could be used to colour each of the three regions. such colouring can greatly simplify the comprehension of some types of image. the imsa110 back-end post processor 8/10
3.8 dynamic range compression consider image data which requires 12 bits to represent each pixel. if it is desired to display such an image on a system which uses only 8 bits per pixel then some form of range compression is required. one solution is to discard the lower 4 bits of each pixel. this would leave the 8 most signifi- cant bits for display. if however, the image was dark the lower 4 bits would contain a large proportion of the image data. to throw away the lower 4 bits in such a situation would almost certainly be unac- ceptable. a better solution in this case would be to use the nonlinear tranformation shown in figure 9. using this transformation values between 0 and 63 are unchanged; values between 64 and 1023 are mapped into the range 64 to 183 and values be- tween 256 and 4095 are mapped into the range 184 to 232. the imsa110 is capable of performing just such a nonlinear transformation by making use of both the data transformation unit and the data normaliser. the mode of operation which is required is known as dynamic normalisation, this is selected by set- ting bcr3[2] (enable dynamic normalisation). in this mode the prescaler selects a 6-bit field any- where within the x bus. this is used as an address to the lut. bits 22 to 26 of the output of the lut are used to control the normaliser block so that the input to the normaliser is dynamically scaled. the output of the normaliser is then added, in the output adder, to the least significant 22 bits of the output of the lut. the operation can be viewed as : output =( input scale )+ offset where the scale is provided by bits 22 to 26 and the offset is provided by bits 0 to 21 of the lut. to define the transformation function shown in figure 9 it is necessary to carefully calculate the values to be placed in the lut. the first stage in this calculation is deciding which slice of the x bus the prescaler is going to select. in this example it will be set so that bits 4 through to 11 are selected. this means that bits 6 to 11 are used as the address for the lookup table. bearing this in mind it may be seen that in the first segment of the transfer func- tion the lut address is zero. since in this segment the scale is 1 (0 right shifts) and the offset is 0 the following four bytes of data must be programmed into the first 32 bit location of the lut. byte 3 byte 2 byte 1 byte 0 lut 000000000 the second segment of the transfer function occurs between lut addresses 1 to 15. in this segment the gradient is 1/8 (3 right shifts). to ensure that the first and second segment line up correctly it is important to set the offset of the second segment to the correct value. it may be easily shown that in this case the offset is 56. thus the data to be programmed into the 15 lut locations from addresses 1 to 15 is: byte 3 byte 2 byte 1 byte 0 lut 1 00 c0 00 38 lut n 00 c0 00 38 lut 15 00 c0 00 38 1 64 184 232 1 64 1024 4095 0 log input scale log output scale AN548-09.eps figure 9 : typical dynamic range compression function the imsa110 back-end post processor 9/10
in exactly the same manner the lut data for the third and final segment of the transfer function may be shown to be: byte 3 byte 2 byte 1 byte 0 lut 16 01 80 00 a8 lut n 01 80 00 a8 lut 63 01 80 00 a8 the settings of the other main control registers to perform the example transform on data applied to the cascade input port are: coeff register 0123456 cr0a 0000000 cr0b 0000000 cr0c 0000000 registers data msb .. lsb scr 01x1xxx0 acr 000000a0 bcr0 xxxxxxx0 bcr1 0 00000xx bcr2 0 0000100 bcr3 x x x x x 1 1 0 x : indicates dont care. a : set to 0 to program the lut, set to 1 to allow ims a110 lut access. 4. summary this document has attempted to describe by exam- ple some of the many ways in which the backend post processor of the imsa110 may be used. it has only been possible to scratch the surface of a handful of applications but hopefully the examples discussed should have provided an insight into both the flexibility and capability of this section of the device. 5. references [1] r. c. gonzalez, p.wintz digital image processing, addison wesley. [2] r. whitton cascading ims a110s, inmos. [3] r. stefanelli, a. rosenfeld some parallel thinning algorithms for digital pictures. comm acm 18, 2. [4] h.e. lu, p.s.p. wang a comment on fast parallel algorithms for thinning digital patterns. comm acm 29, 3. [5] c.m. holt, a. stewart, m. clint, r.h. perrott an improved parallel thinning algorithm. comm acm 30, 2. [6] r.w. hall fast parallel thinning algorithms: parallel speed and connectivity preservation. comm acm 32, 1. [7] z. guo, r.w. hall parallel thinning with two subiteration algorithms. comm acm 32, 3. information furnished is believed to be accurate and rel iable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - it aly - ja pan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. the imsa110 back-end post processor 10/10
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