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12 -bit monitor and c ontrol system with multichannel adc, dacs, temperature sensor , and current sense ad7294 rev. f information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notic e. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2008C 2010 analog devices, inc. all rights reserved. features 12- bit sar adc with 3 s conversion time 4 uncommitted analog inputs differential/single - ended v ref , 2 v ref i nput ranges 2 high - side current sense inputs 5 v to 59.4 v operating range 0.5 % max gain er ror 200 mv input range 2 external diode temperature sensor inputs ?55c to +150 c measurement range 2c accuracy series resistance cancellation 1 internal temperature sensor 2c accuracy built - in monitoring features min imum /max imum recorder for each channel programmable alert thresholds programma ble hysteresis four 12- bit monotonic 15 v dacs 5 v span, 0 v to 10 v offset 8 s settling time 10 ma sink and source capability power - on resets (por) to 0 v internal 2.5 v reference 2- wire fast mode i 2 c interface temperature range: ?40 c to +105c package type: 64 - lead tqfp or 56 - lead lfcsp applications cellular base station s gsm, edge, umts, cdma , td - scdma, w - cdma, wimax point - to - multipoint and other rf transmission systems 12 v, 24 v, 48 v automotive applications industrial controls general description the ad7294 contains all the functions required for general - purpose monitoring and control of current, voltage, and temperature integrated into a single - chip solution. the part includes low voltage (200 mv) analog input sense amplifiers for current monito ring across shunt resistors, temperature sense inputs, and four uncommitted analog input channels multiplexed into a sar analog - to - digital converter ( adc ) with a 3 s conver - sion time . a high accuracy internal reference is provided to drive both the digita l- to - anal og converter (dac) and adc. four 12 - bit dacs provide the outputs for voltage control. the ad7294 also includes limit registers for alarm functions. the part is designed on analog devices, inc., high voltage dmos process f or high voltage compli ance , 59.4 v on the current sense inputs, and up to a 15 v dac output voltage. the ad7294 is a highly integrated solution that offers all the functionality neces sary for precise control of the power amplifier in cellular bas e station applications. in these typ es of applications , t he dacs pro vide 12- bit resolution to control the bias currents of t he power transistors. t hermal diode - based temperature sensors are incorporated to com pensate for temperature effects. the adc monitors the high - side current and tempera ture. all this function - ality is provided in a 64 - lead tqfp or a 56 - lead lfcsp operating over a temperature r ange of ?40c to +105c.
ad7294 rev. f | page 2 of 48 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 3 functional block diagram .............................................................. 4 specifications ..................................................................................... 5 dac specifications ....................................................................... 5 adc specifications ...................................................................... 6 general specifications ................................................................. 8 timing characteristics ................................................................ 9 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 14 terminology .................................................................................... 19 dac terminology ...................................................................... 19 adc terminology ...................................................................... 19 theory of operation ...................................................................... 20 adc overview ........................................................................... 20 adc transfer functions ........................................................... 20 analog inputs .............................................................................. 20 current sensor ............................................................................ 22 analog comparator loop ......................................................... 23 temperature sensor ................................................................... 24 dac operation ........................................................................... 25 adc and dac reference .......................................................... 26 v drive feature .............................................................................. 26 register setting ............................................................................... 27 address pointer register ........................................................... 27 command register (0x00) ........................................................ 28 result register (0x01) ................................................................ 28 t sense 1, t sense 2 result registers (0x02 and 0x03) ....................... 29 t sense int result register (0x04) .............................................. 29 dac a , dac b , dac c , dac d , registers (0x01 to 0x04) ............... 30 alert status register a (0x05), register b (0x06), and register c (0x07) ........................................................................ 30 channel sequence register (0x08) .......................................... 30 configuration register (0x09) .................................................. 31 power - down register (0x0a) ................................................... 32 data high /data low registers: 0x0b, 0x0c (v in 0); 0x 0e , 0x 0f (v in 1); 0x 11 , 0x 12 (v in 2); 0x 14 , 0x 15 (v in 3) .............................. 32 hysteresis registers: 0x0d (v in 0), 0x 10 (v in 1), 0x13 (v in 2), 0x16 (v in 3) .................................................................................. 32 t sense offset registers (0x26 and 0x27) ................................... 33 i 2 c interface .................................................................................... 34 general i 2 c timing .................................................................... 34 serial bus address byte ............................................................. 35 interface protocol ....................................................................... 35 modes of operation ....................................................................... 39 command mode ........................................................................ 39 autocycle mode .......................................................................... 40 alerts and limits theory .............................................................. 41 alert_flag bit .............................................................................. 41 alert status registers ................................................................. 41 data high and data low monitoring features ............................ 41 hysteresis ..................................................................................... 42 applications information .............................................................. 43 base station power amplifier monitor and control ............. 43 gain control of power amplifier ............................................. 44 layout and configuration ............................................................. 45 power supply bypassing and grounding ................................ 45 outline dimensions ....................................................................... 46 ordering guide .......................................................................... 47
ad7294 rev. f | page 3 of 48 revision history 11/10rev. e to rev. f change to table 2, dynamic performance, spurious-free dynamic range (sfdr) ................................................................... 6 10/10rev. d to rev. e change to reflow temperature, table 5 ...................................... 10 5/10rev. c to rev. d added 56-lead lfcsp ...................................................... universal change to features section and general description section ... 1 changes to table 2 ............................................................................ 6 changes to table 6 .......................................................................... 10 added figure 4 ................................................................................ 11 changes to table 7 .......................................................................... 12 changes to command register section ....................................... 28 changes to autocycle mode section ............................................ 40 updated outline dimensions ........................................................ 47 changes to ordering guide ........................................................... 48 7/09rev. b to rev. c changes to table 4 endnotes ........................................................... 8 4/09rev. a to rev. b changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 7 changes to table 23 ........................................................................ 29 3/09rev. 0 to rev. a changes to configuration register (0x09) section .................... 29 changes to table 23 and table 24 ................................................. 29 changes to table 27 ........................................................................ 30 changes to autocycle mode section ............................................ 38 change to alert status registers section ..................................... 39 changes to data high and data low monitoring features section .............................................................................................. 39 1/08revision 0: initial version
ad7294 rev. f | page 4 of 48 functional block dia gram 05747-001 limit registers mux control logic i 2 c interface protocol temp sensor high side current sense high side current sense ref out / ref in dac t1 t2 to load rs1(+) rs2(+) rs2(?) rs1(?) d1+ d2+ d1? d2? av dd (1 to 6) agnd (1 to 7) dac out v+ ab/cd ad7294 ref out / ref in adc v pp (1 to 2) alert/ busy dcap v ref 10.41 i sense 1 overrange i sense 2 overrange r sense 12-bit adc as0 as1 as2 scl sda dv dd dgnd (1 to 2) v in 0 v in 1 v in 2 v in 3 12-bit dac 100k? 200k? 100k? 200k? 12-bit dac 100k? 200k? 100k? 200k? 12-bit dac 100k? 200k? 100k? 200k? 12-bit dac 100k? 200k? 100k? 200k? offset in a v out b offset in b v out c offset in c v out d offset in d v out a 2.5v ref figure 1 .
ad7294 rev. f | page 5 of 48 specifications dac specifications av dd = dv dd = 4.5 v to 5.5 v, agnd = dgnd = 0 v, i nternal 2.5 v reference ; v drive = 2.7 v to 5.5 v ; t a = ?40c to +105c, unless otherwise noted. dac out v+ ab and dac ou tv+ cd = 4.5 v to 16.5 v, offset in x is f loating, therefore, the dac output span = 0 v to 5 v. table 1. parameter min typ max unit test conditions/comments accuracy resolution 12 bits relative accuracy (inl) 1 3 lsb differential nonlinearity (dnl) 0.3 1 lsb guaranteed monotonic zero - scale error 2.5 8 mv full - scale error of dac and output amplifier 15.5 1 mv dac out v+ = 5.0 v full - scale error of dac 2 mv dac out v+ = 15.0 v offset error 8.575 mv measured in the linear region, t a = ?40c to +105c 2 mv measured in the linear region, t a = 25c offset error temperature coefficient 5 ppm /c gain error 0.025 0.155 % fsr gain temperature coefficient 5 ppm /c dac output characteristics output voltage s pan 0 2 v ref v 0 v to 5 v for a 2.5 v reference output voltage offset 0 10 v the output voltage span can be positioned in the 0 v to 15 v range ; if the offset in x is left floating , the offset pin = 2/3 v ref , giving an output of 0 v to 2 v ref o ffset input pin range 0 5 v out = 3 v offset ? 2 v ref + v dac , dac high - z = 0 v 1.667 5 v out = offset in x, dac high - z = v drive dc input impedance 2 75 k? 100 k ? to v ref , and 200 k ? to agnd, s ee figu re 47 output voltage settling time 2 8 s 1/4 to 3/4 change within 1/2 lsb , m easured from last scl edge slew rate 2 1.1 v/s short - circuit current 2 40 ma full - scale current shorted to ground load current 2 10 ma source and/or sink within 200 mv of supply capacitive load stability 2 10 nf r l = dc output impedance 2 1 ? reference reference output voltage 2.49 2.5 2.51 v 0.4 % max imum @ 25c, av dd = dv dd = 4.5 v to 5.5 v reference input voltage range 0 av dd ? 2 v input current 100 125 a v ref = 2.5 v input capacitance 2 20 pf v ref output impedance 2 25 ? reference temperature coefficient 10 25 ppm/c 1 this value indicates that the dac output amplifiers can output voltages 15.5 mv below the dac outv+ supply. if higher dac out v+ supply voltages are used, the full - scale error of the dac is typically 2 mv with no load. 2 samples are tested during initial release to ensure compliance; they are not subject to production testing.
ad7294 rev. f | page 6 of 48 adc specifications av dd = dv dd = 4.5 v to 5.5 v, agnd = dgnd = 0 v, v ref = 2.5 v internal or external; v drive = 2.7 v to 5.5 v; v pp = av dd to 59.4 v; t a = ?40c to +105c, unless otherwise noted. table 2. parameter min typ max unit test conditions/comments dc accuracy resolution 12 bits integral nonlinearity (inl) 1 0.5 1 lsb differential mode 0.5 1.5 lsb single-ended or pseudo differential mode differential nonlinearity (dnl) 1 0.5 0.99 lsb differential, single-ended, and pseudo differential modes single-ended mode offset error 1 7 lsb offset error match 0.4 lsb gain error 0.5 2.5 lsb gain error match 0.4 lsb differential mode positive gain error 3 lsb positive gain error match 0.5 lsb zero code error 3 10 lsb zero code error match 0.5 lsb negative gain error 3 lsb negative gain error match 0.5 lsb conversion rate conversion time 2 3 s autocycle update rate 2 50 s throughput rate 22.22 ksps f scl = 400 khz analog input 3 single-ended input range 0 v ref v 0 v to v ref mode 0 2 v ref v 0 v to 2 v ref mode pseudo differential input range: v in+ ? v in? 4 0 v ref 0 v to v ref mode 0 2 v ref 0 v to 2 v ref mode fully differential input range: v in+ ? v in? ?v ref +v ref 0 v to v ref mode ?2 v ref +2 v ref 0 v to 2 v ref mode input capacitance 2 30 pf dc input leakage current 1 a dynamic performance signal-to-noise ratio (snr) 1 72.5 73 db f in = 10 khz sine wave; differential mode 71 72 db f in = 10 khz sine wave; single-ended and pseudo differential modes signal-to-noise + distortion (sinad) ratio 1 71 71.5 db f in = 10 khz sine wave; differential mode 69 72.5 db f in = 10 khz sine wave; single-ended and pseudo differential modes total harmonic distortion (thd) 1 ?81 C74 db f in = 10 khz sine wave; differential mode ?79 C72 db f in = 10 khz sine wave; single-ended and pseudo differential modes spurious-free dynamic range (sfdr) 1 ?81 ?74 db f in = 10 khz sine wave; differential mode ?79 ?72 f in = 10 khz sine wave; single-ended and pseudo differential modes channel-to-channel isolation 2 ?90 db f in = 10 khz to 40 khz
ad7294 rev. f | page 7 of 48 parameter min typ max unit test conditions/comments temperature sensor internal operating range ?40 +105 c accuracy 2 c internal temperature sensor, t a = ?3 0c to +90c 2.5 c internal temperature sensor, t a = ?40c to +105c resolution 0.25 c lsb size update rate 5 ms temperature sensor external external transistor is 2n3906 operating range ?55 +150 c limited by external diode accuracy 2 c t a = t diode = ?40c to +105 c resolution 0.25 c lsb size low level output current source 2 8 a medium level output current source 2 32 a high level output current source 2 128 a maximum series resistance (r s ) for external diode 2 100 ? for < 0.5c additional error, c p = 0, s ee figure 30 maximum parallel capacitance (c p ) for external diode 2 1 nf r s = 0, s ee figure 29 current sense v pp = av dd to 59.4 v v pp supply range av dd 59.4 v gain 12.4375 12.5 12.5625 gain of 12.5 gives a gain error = 0.5% max imum ; delivers 200 mv range with +2.5 v reference rs(+)/rs( ?) input bias current 25 32 a cmrr/psrr 2 80 db inputs shorted to v pp offset error 50 340 v offset drift 1 v/c amplifier peak - to - peak noise 2 400 v referre d to input v pp supply current 0.18 0.25 ma v pp = 59.4 v reference reference output voltage 2.49 2.51 v 0.2% max imum at 25 c only reference input voltage range 0.1 4.1 v for fou r uncommitted adcs 1 av dd ? 2 for current sense dc l eakage current 2 a v ref output impedance 2 25 ? input capacitance 2 20 pf reference temperature coefficient 10 25 ppm/c 1 see the terminology section for more details. 2 sampled du ring initial release to ensure compliance, not subject to production testing. 3 v in+ or v in ? must remain within gnd/v dd . 4 v in ? = 0 v for specified performance. for full input range on v in ? , see figure 39 .
ad7294 rev. f | page 8 of 48 general specifications av dd = dv dd = 4.5 v to 5.5 v, agn d = dgnd = 0 v, v ref = 2.5 v i nternal or e xternal ; v drive = 2.7 v to 5.5 v; v pp = av dd to 59.4 v; dac out v+ ab and dac outv+ cd = 4 .5 v to 16.5 v; offset in x is f loating, therefore, dac output span = 0 v to 5 v; t a = ?40c to +105c, unl ess otherwise note d. table 3. parameter min typ max unit test conditions/comments logic inputs input high voltage, v ih 0.7 v drive v sda, scl only input low voltage, v il 0.3 v drive v sda, scl only input leakage current, i in 1 a input hysteresis, v hyst 0.05 v drive v input capacitance, c in 8 pf glitch rejection 50 ns input filtering suppresses noise spikes of less than 50 ns i 2 c? address pins maximum external capacitance if floating 30 pf tristate input dac h ig h-z p in leakage 10 a input with pull - down resistor, v in = 5.5 v 1 a input with pull - down resistor, v in = 0 v logic outputs sda, alert sda and alert/busy are open - drain outputs output low voltage, v ol 0.4 v i sink = 3 ma 0.6 v i sink = 6 ma floating - state leakage current 1 a floating - state output capacitance 8 pf i sense overrange i sense overrange is a push - pull output output high voltage, v oh v drive ? 0.2 v i source = 200 a for push - pull outputs output low voltage, v ol 0.2 v i sink = 200 a for push - pull outputs overrange set point v fs v fs 1.2 mv v fs = v ref adc/12.5 power requirements v pp av dd 59.4 v av dd 4.5 5.5 v v(+) 4.5 16.5 v dv dd 4.5 5.5 v t ie dv dd to av dd v drive 2.7 5.5 v i dd dynamic 5.3 6.5 ma av dd + dv dd + v drive , dac o utputs unloaded dac out v+ x , i dd 0.6 1.2 ma @ mid scale output voltage, dac o utputs unloaded power dissipation 70 105 mw power - down i dd 0.5 1 a for each av dd and v drive di dd 1 16.5 a dac out v+ x , i dd 35 60 a power dissipation 2.5 mw
ad7294 rev. f | page 9 of 48 timing characteristi cs i 2 c serial interface av dd = dv dd = 4.5 v to 5.5 v, agnd = dgnd = 0 v, v ref = 2.5 v internal or exte rn al ; v drive = 2.7 v to 5.5 v ; v pp = av dd to 59.4 v; dac out v+ ab and dac outv+ cd = 4.5 v to 16.5 v; offset in x is f loating, therefore, dac output span = 0 v to 5 v; t a = ?40c to +105c, unless otherwise noted. table 4. parameter 1 limit at t min , t max unit description f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data set up time t 6 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , set up time for repeated start t 8 0.6 s min t su,sto , stop condition set up time t 9 1.3 s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 300 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 2 ns min t f , fall time of scl and sda when transmitting c b 400 pf max capacitive load for each bus line 1 see figure 2 . 2 c b is the total capacitance in pf of one bus line. t r and t f are measu red between 0.3 dv dd and 0.7 dv dd . timing and circuit diagra ms start condition repeated start condition stop condition t 9 t 3 t 1 t 11 t 4 t 10 t 4 t 5 t 7 t 6 t 8 t 2 sda scl 05747-002 figure 2 . i 2 c- compatible serial interface timing diagram c l 50pf t o output pin v oh (min) or v ol (max) 200 a 200 a i ol i oh 05747-003 figure 3 . load circuit for digital output
ad7294 rev. f | page 10 of 48 absolute maximum rat ings t a = 25 c, unless otherwise noted. 1 table 5. para meter rating v pp x to agnd ?0.3 v to +70 v av dd x to agnd ?0.3 v to +7 v dac outv+ ab to agnd ?0.3 v to +17 v dac outv+ cd to agnd ?0.3 v to +17 v dv dd to dgnd ?0.3 v to +7 v v drive to opgnd ?0.3 v to +7 v digital inputs to opgnd ?0.3 v to v drive + 0.3 v sda/scl to opgnd ?0.3 v to + 7 v digital outputs to opgnd ?0.3 v to v drive + 0.3 v rs(+)/rs( ?) to v pp x v pp ? 0.3 v to v pp + 0.3 v ref out /ref in adc to agnd ?0.3 v to av dd + 0.3 v ref out /ref in dac to agnd ?0.3 v to av dd + 0.3 v opgnd to agnd ?0.3 v to +0.3 v opgnd to dgnd ?0 .3 v to +0.3 v agnd to dgnd ?0.3 v to +0.3 v v out x to agnd ?0.3 v to dac outv(+) + 0.3 v analog inputs to agnd ?0.3 v to av dd + 0.3 v operating temperature range b version ?40c to +105c storage temperature range ?65c to +150c junction temperatu re (t j max) 150c esd human body model 1 kv reflow soldering peak temperature 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device a t these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. to conform with ipc 2221 industrial st andards, it is advis able to use conformal coating on the high voltage pins. thermal resistance table 6 . thermal resistance package type ja jc unit 64- lead tqfp 54 16 c/w 56- lead lfcsp 21 2 c/w esd caution 1 transient currents of up to 100 ma do not cause scr latch - up.
ad7294 rev. f | page 11 of 48 pin configuration and function descripti ons v in 0 v in 1 v in 2 v in 3 agnd3 av dd 3 ref out /ref in dac nc dac high-z dgnd i sense 2 overrange i sense 1 overrange dv dd dgnd v drive opgnd scl sda as0 as1 as2 alert/busy agnd5 nc 39 38 37 41 40 36 35 34 33 42 43 44 45 46 47 48 10 11 12 8 9 13 14 15 16 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 nc v pp 2 v pp 1 rs1(?) rs1(+) nc av dd 5 av dd 6 agnd6 agnd7 dcap ref out /ref in adc nc rs2(?) rs2(+) nc av dd 1 agnd1 agnd2 av dd 2 d2? d2+ d1+ d1? pin 1 indicator nc = no connect ad7294 tqfp top view (not to scale) dac out gnd cd nc nc offset in a offset in b offset in c offset in d v out a dac out gnd ab dac outv+ ab v out b v out c v out d agnd 4 av dd 4 dac outv+ cd 05747-005 figure 4 . tqfp pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4 4 3 ad7294 lfcs p top view (not to scale) dgnd i sense 2 overrange i sense 1 overrange dv dd dgnd v drive opgnd scl sda as0 as1 as2 alert/busy agnd5 dac out gnd cd offset in b offset in c offset in d v out a dac out gnd ab offset in a dac outv+ ab v out b v out c v out d agnd4 av dd 4 dac outv+ cd agnd3 av dd 3 ref out /ref in dac nc rs2(?) rs2(+) av dd 1 agnd1 agnd2 av dd 2 d1(?) d1(+) d2(+) d2(?) v in 0 v in 1 v in 2 v in 3 v pp 2 v pp 1 rs1(?) rs1(+) nc av dd 5 agnd6 agnd7 dcap ref out /ref in adc pin 1 indicator 05747-004 notes 1. nc = no connec t. 2. connect the exposed p ad t o the ground plane of the pcb using mu l tiple vias. figure 5. lfcsp pin configuration
ad7294 rev. f | page 12 of 48 table 7 . pin function descriptions tqfp pin no. lfcsp pin no. mnemonic description 2, 61 1, 54 rs2( ?), rs1(?) connection for external shunt resistor. 3, 60 2, 53 rs2(+), rs1(+) connection for external shunt resistor. 1, 4, 16, 17, 32, 33, 59, 64 3, 52 nc no connection. do not connect these pins. 5, 8, 14, 25, 56, 57 4, 7, 13, 22, 50 av dd 1 to av dd 6 for tqfp; av dd 1 to av dd 4 for lfcsp analog supply pins. the operating range is 4.5 v to 5.5 v. these pins provide the supply voltage for all the analog circuitry on the ad7294. connect the av dd and dv dd pins together to ensure that all supply pins are at the same potential. this supply should be decoupled to agnd with one 10 f tantalum capacitor and a 0.1 f ceramic capacitor for each av dd pin. 6, 7, 13, 24, 34, 55, 58 5, 6 12, 21, 29, 49, 51 agnd1 to agnd7 analog ground. ground reference point for all analog circuitry on the ad7294. refer all analog input signals and any external reference signal to this agnd voltage. connect all seven of these agnd pins to the agnd plane of the system. note that agnd5 is a dac ground reference point and should be used as a star ground for circuitry being driven by the dac outputs. ideally, the agnd and dgnd voltages should be at the same potential and must not be more than 0.3 v apart, even on a transient basis. 9, 12 8, 11 d2( ?), d1(?) temperature sensor analog input. these pins are connected to the external temperature sensing transistor. see figure 45 and figure 46. 10, 11 9, 10 d2(+), d1(+) temperature sensor analog inp ut. these pins are connected to the external temperature sensing transistor. see figure 45 and figure 46. 15 14 ref out /ref in dac dac reference output/input pin. the ref out /ref in dac pin is common to all four dac channels. on power - up, the default configuration of this pin is external reference (ref in ). enable the internal reference by writing to the power - down register; see table 27 . decoupling capacitors (220 nf recommended) a re connected to this pin to decouple the reference buffer. provided the output is buffered, the on - chip reference can be taken from this pin and applied externally to the rest of a system. a maximum external reference voltage of av dd ? 2 v can be supplied to the ref out portion of the ref out /ref in dac pin. 18, 23, 26, 31 15, 20 23,28 offset in a to offset in d dac analog offset input pins. these pins set the desired output range for each dac channel. the dacs have an output voltage span of 5 v, which can be shifted from 0 v to 5 v to a maximum output voltage of 10 v to 15 v by supplying an offset voltage to these pins. these pins can be left floating, in which case decouple them to agnd with a 100 nf capacitor. 19, 22, 27, 30 16, 19, 24, 27 v out a to v out d buffered analog dac outputs for channel a to channel d. each dac analog output is driven from an output amplifier that can be offset using the offset in x pin. the dac has a maximum output voltage span of 5 v that can be level shifted to a maximum output voltage level of 15 v. each output is capable of sourcing and sinking 10 ma and driving a 10 nf load. 20, 29 17, 26 dac out gnd ab, dac out gnd cd analog ground. analog ground pins for the dac output amplifiers on v out a and v out b, and v out c and v out d, r espectively. 21, 28 18, 25 dac outv+ ab, dac outv+ cd analog supply. analog supply pins for the dac output amplifiers on v out a and v out b, and v out c and v out d, respectively. the operating range is 4.5 v to 16.5 v. 35 30 alert/busy digital output. selecta ble as an alert or busy output function in the configuration register. this is an open - drain output. an external pull - up resistor is required. when configured as an alert, this pin acts as an out - of - range indicator and becomes active when the conversion result violates the data high or data low register values. see the alert status registers section. when configured as a busy output, this pin becomes active when a conversion is in progress. 38, 37, 36 33, 32, 3 1 as0, as1, as2 digital logic input. together, the logic state of these inputs selects a unique i 2 c address for the ad7294. see table 34 for details. 39 34 sda digital input/output. serial bus bidirectional data; external pull - up resisto r required.
ad7294 rev. f | page 13 of 48 tqfp pin no. lfcsp pin no. mnemonic description 40 35 scl serial i 2 c bus clock. the data transfer rate in i 2 c mode is compatible with both 100 khz and 400 khz operating modes. open - drain input; e xternal pull - up resistor required. 41 36 opgnd dedicated ground pin for i 2 c interface. 42 37 v drive logic power supply. the voltage supplied at this pin determines at what voltage the interface operates. decouple this pin to dgnd. the voltage range on this pin is 2.7 v to 5.5 v and may be different to the voltage level at av dd and dv dd , but shoul d never exceed either by more than 0.3 v. to set the input and output thresholds, connect this pin to the supply to which the i 2 c bus is pulled. 43, 47 38, 42 dgnd digital ground. this pin is the ground for all digital circuitry. 44 39 dv dd logic power supply. the operating range is 4.5 v to 5.5 v. these pins provide the supply voltage for all the digital circuitry on the ad7294. connect the av dd and dv dd pins together to ensure that all supply pins are at the same potential. decouple this supply to dgnd with a10 f tantalum capacitor and a 0.1 f ceramic capacitor. 46, 45 41, 40 i sense 1 overrange, i sense 2 overrange fault comparator outputs. these pins connect to the high - side current sense amplifiers. 48 not applicable dac high -z hig h impedance control on dac outputs. when this pin is set to a high logic level, it sets the dac outputs to the voltage level on the offset in x pins. this pin has an internal 1 m ? pul l - down resistor. 49, 50, 51, 52 43, 44, 45, 46 v in 3 to v in 0 uncommitted adc analog inputs. these pins are programmable as four single - ended channels or two true differential analog input channel pairs. see table 1 and table 13 for more details. 53 47 ref out /ref in adc adc reference inpu t/output pin. the ref out /ref in adc pin provides the reference source for the adc. upon power - up, the default configuration of this pin is external reference (ref in ). enable the internal reference by writing to the power - down register ; see table 27 . connect decoupling capacitors (220 nf recommended) to this pin to decouple the reference buffer. provided the output is buffered, the on - chip reference can be taken from this pin and applied externally to the rest of a system. a maximum external reference voltage of 2.5 v can be supplied to the ref out portion of the ref out /ref in adc pin. 54 48 dcap external decoupling capacitor input for internal temperature sensor. decouple this pin to agnd using a 0.1 f capacitor. in normal operation, the voltage is typically 3.7 v. 62, 63 55, 56 v pp 1, v pp 2 current sensor supply pins. power supply pins for the high - side current sense amplifiers. operating range is from av dd to 59.4 v. decouple this supply to agnd. see the current sense filtering section. ep exposed pad the exposed pad is located on the underside of the package. connect the exposed pad to the ground plane of the pcb using multiple vias.
ad7294 rev. f | page 14 of 48 typical performance characteri stics 20 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10000 8000 6000 4000 2000 amplitude (db) frequency (khz) 8192 point fft av dd = dv dd = 5v v drive = 5v, v ref range f sample = 22.22ksps f in = 10khz, f sclk = 400khz single ended snr = 71db, thd = ?82db 05747-088 figure 5 . signal - to - noise ratio single - ended , v ref range 05747-089 20 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10000 8000 6000 4000 2000 amplitude (db) frequency (khz) 8192 point fft av dd = dv dd = 5v v drive = 5v, 2v ref range f sample = 22.22ksps f in = 10khz, f sclk = 400khz single ended snr = 72db, thd = ?80db figure 6 . signal - to - noise ratio single - ended , 2 v ref range 05747-087 20 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10000 8000 6000 4000 2000 amplitude (db) frequency (khz) 8192 point fft av dd = dv dd = 5v v drive = 5v, v ref range f sample = 22.22ksps f in = 10khz, f sclk = 400khz differential snr = 72db, thd = ?86db figure 7 . signal - to - noise ratio differential, v ref range 05747-086 20 0 ?20 ?40 ?60 ?80 ?100 ?120 0 10000 8000 6000 4000 2000 amplitude (db) frequency (khz) 8192 point fft av dd = dv dd = 5v v drive = 5v, 2v ref range f sample = 22.22ksps f in = 10khz, f sclk = 400khz differential snr = 73db, thd = ?82db figure 8 . signal - to - noise ratio differential, 2 v ref range 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?1.0 ?0.8 ?0.2 ?0.6 inl (lsb) code 05747-077 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 t a = 25c v drive = 5v, v ref range v ref = 2.5v v dd = 5v single-ended figure 9 . adc inl single - ended, v ref range 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0.6 dnl (lsb) code t a = 25c v drive = 5v, v ref range v ref = 2.5v v dd = 5v single-ended 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 05747-072 figure 10 . adc dnl single - ended, v ref range
ad7294 rev. f | page 15 of 48 1.0 0.8 0.4 0.6 0.2 0 ?0.4 ?1.0 ?0.8 ?0.2 ?0.6 inl (lsb) code 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 t a = 25c v drive = 5v, 2v ref range v ref = 2.5v v dd = 5v single-ended 05747-078 figur e 11 . adc inl single -ended, 2 v ref rang e 05747-073 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0.6 dnl (lsb) code t a = 25c v drive = 5v, 2v ref range v ref = 5v v dd = 5v single-ended 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 figure 12 . adc dnl single- ended , 2 v ref range 05747-075 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0.6 inl (lsb) code t a = 25c v drive = 5v, v ref range v ref = 2.5v v dd = 5v differential 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 figure 13 . adc inl differential, v ref range 05747-076 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0. 6 inl (lsb) code t a = 25c v drive = 5v, v ref range v ref = 5v v dd = 5v differential 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 figure 14 . adc inl differential, v ref range t a = 25c v ref = 2.5v v dd = 5v differential 05747-070 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0.6 dnl (lsb) code t a = 25c v drive = 5v, 2v ref range v ref = 2.5v v dd = 5v differential 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 figure 15 . adc d nl differential, 2 v ref range 05747-071 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.8 0.4 0.6 dnl (lsb) code t a = 25c v drive = 5v, 2v ref range v ref = 5v v dd = 5v differential 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 figure 16 . adc dnl differential, 2 v ref range
ad7294 rev. f | page 16 of 48 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 0 6 5 4 3 2 1 inl (lsb) reference voltage (v) min inl max inl t a = 25c v drive = 5v, v ref range v dd = 5v single-ended i 2 c mode 400khz 05747-093 figure 17 . adc inl vs. reference volta ge 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 0 6 5 4 3 2 1 dnl (lsb) reference voltage (v) min dnl max dnl t a = 25c v drive = 5v, v ref range v dd = 5v single-ended i 2 c mode 400khz 05747-094 figure 18 . adc dnl vs. reference voltage 05747-079 2.0 1.0 1.5 0.5 0 ?1.0 ?2.0 ?0.5 ?1.5 inl (lsb) code 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 av dd = dv dd = 5v v drive = 5v, internal ref, offset in a/b/c/d = floating figure 19 . dac inl 05747-080 0.6 0.4 0.2 0 ?0.4 ?0.6 ?0.2 dnl (lsb) code 256 512 0 768 1024 1280 1536 1792 2048 2304 2560 2816 3072 3328 3584 3840 4096 av dd = dv dd = 5v v drive = 5v, internal ref, offset in a/b/c/d = floating figure 20 . dac dnl 05747-097 20 ?20 ?15 ?10 ?5 0 5 10 15 output (v) time (s) 0 1 2 3 4 5 6 7 8 9 10 figure 21 . 0.1 hz to 10 hz dac output noise (cod e 800) 5.0 0 0.5 1.0 1.5 2.5 3.5 4.5 2.0 3.0 4.0 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 6 7 8 9 10 dac output (v) time (s) 64pf 1nf 10nf 05747-084 figure 22 . settling time for a ? to ? output voltage step
ad7294 rev. f | page 17 of 48 0.8 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0.6 0 0.4 0 201816141210 8642 (%) time (s) 64pf 1nf 10nf 05747-085 figure 23 . zoomed in settling for a ? to ? output voltage step 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 40353025201510 5 v out (v) sink current (ma) dac a dac b dac c dac d 05747-090 av dd = dv dd = 5v offset in = flo a ting dac out v = 15v v drive = 5 v , interna l ref figure 24 . dac sinking current at input code = x0 00, (v out = 0 v) 0 ?0.1 ?0.2 ?0.3 ?0.4 ?0.5 ?0.6 ?0.7 ?0.8 ?0.9 ?1.0 0 40353025201510 5 v out ? (v+) source current (ma) dac a dac b dac c dac d 05747-091 av dd = dv dd = 5v offset in = flo a ting dac out v = 15v v drive = 5 v , interna l ref figure 25 . dac sourcing current at input code = x000, (v out = 0 v) 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 ?50 50 20 4030 10 0 ?10?20?30?40 change in output voltage (mv) load current (ma) dac a dac b dac c dac d 05747-092 av dd = dv dd = 5v offset in = flo a ting dac out v = 15v v drive = 5 v , interna l ref figure 26 . dac output voltage vs. load current, input code = x800 55 50 45 40 35 30 25 20 ?5 0 5 10 15 20 temperature reading (c) time (seconds) 05747-064 figure 27 . respon se of the ad7294 to thermal s hock using 2n3906 ( 2n3906 p laced in a s tirred oil ba th ) 55 50 45 40 35 30 25 ?5 0 6055504540353025201510 5 temperature (c) time (seconds) external internal ad7294 in socket on 200mm 100mm 2-layer fr-4 pcb 05747-066 figure 28 . response to therm al shock from room temperature into 50c stirred oil (both the ad7294 and the 2n3906 are p laced in a stirred oil ba th )
ad7294 rev. f | page 18 of 48 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 ?1.2 ?1.4 ?1.6 ?1.8 ?2.0 0 0.5 1.0 1.5 2.0 2.5 error (c) capacitance from d+ to d? (nf) 05747-065 figure 29 . temperature error vs. capacitor between d+ and d ? 15 10 5 0 ?5 ?10 ?15 ?20 0 2000 4000 6000 8000 10000 12000 error (c) series resistance ( ?) 05747-062 figure 30 . temperature error vs. series resistance for 15 typical parts 05747-096 5 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 amplitude (db) frequency (hz) 1k 10k 100k 1m 10m 100m figure 31 . frequency response of the high - side current sensor on the ad7 294 ?50 ?95 ?90 ?85 ?80 ?75 ?70 ?65 ?60 ?55 1k 10k 100k 1m 10m psrr (db) frequency (hz) 05747-102 figure 32 . i sense power s upply rejection rati o vs. supply ripple frequency w ithout v pp supply decoupling capac itors for a 500 mv ripple ?50 ?110 ?100 ?90 ?80 ?70 ?60 1 100m 10m 1m 100k 10k 1k 100 10 cmrr (db) ripple frequency (hz) 05747-103 figure 33 . i sense common - mode rejection ratio vs. ripple frequency for a 400 mv peak - to - peak rip ple
ad7294 rev. f | page 19 of 48 terminology dac terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensur es monotonicity. this dac is guaranteed mono - tonic by design. zero code error zero code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero code error is always positive in the ad7294 because the output o f the dac cannot go below 0 v. zero code error is expressed in mv. full - scale error full - scale error is a measure of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output shoul d be v dd ? 1 lsb. full - scale error is expressed in mv. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full - scale range. total unadjusted er ror total unadjusted error (tue) is a measure of the output error, taking all of the various errors into account. zero code error drift zero code error drift is a measure of the change in zero code error with a change in temperature. it is expressed in v /c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full - scale range)/c. adc terminology signal -to - noise and distortion ratio (sinad) the measured ratio of signal - to - no ise and distortion at the output of the adc . the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dep endent on the number of quantization l evels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal - to - noise and distortion ratio for an ideal n - bit converter with a sine wave input is given by signal - to -( noise + distortion ) = (6.02 n + 1.76) db thus, the sinad is 74 db for a n ideal 12- bit converter. total harmonic distortion (thd) the ratio of the rms sum of harmonics to the fundamental. for the ad7294, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 )db( v vvvvv thd ++++ = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through sixth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the f undamental. typically, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity the difference between the m easured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error the deviation of the first code transition (00000) to (00001) from the ideal that is, agnd + 1 lsb. offset error match the difference in offset error between any t wo channels. gain error the deviation of the last code transition (111110) to (111111) from the ideal (that is, ref in ? 1 lsb) after the offset error has been adjusted out. gain error match the difference in gain error between any two channels.
ad7294 rev. f | page 20 of 48 theory o f operation adc overview the ad7294 provides the user with a 9 - channel multiplexer, an on - chip track - and - hold, and a s ucce ssive approximation adc based around a capacitive dac. the analog input range for the part can be selected as a 0 v to v ref input or a 2 v ref input, confi gured with either single - ended or differential analog inputs. the ad7294 has an on - chip 2.5 v re fer ence that can be disabled when an external reference is preferred. if the internal adc reference is to be used elsewhere in a system, the output must first be buffered. the various monitored and uncommitted input signals are multi - plexed into the adc. the ad7294 has four uncommitted analog input channels , v in 0 to v in 3. these four channels allow single- ended, differential, and pseudo differential mode measurements of various system signals. adc transfer functions the designed code transitions occur at s uccessive integer lsb values (1 lsb, 2 lsb, and so on). in single - ended mode, the lsb size is v ref /4096 when the 0 v to v ref range is used and 2 v ref /4096 when the 0 v to 2 v ref range is used. the ideal transfer characteristic for the adc when output ting straight binary coding is shown in figure 34. 000...000 11 1... 11 1 1lsb = v ref /4096 1lsb v ref ? 1lsb analog input adc code 0v 000...001 000...010 11 1... 1 10 11 1...000 01 1... 11 1 note 1. v ref is either v ref or 2 v ref . 05747-016 figure 34 . single - ended transfer characteristic in differential mode, the lsb size is 2 v ref /4096 when the 0 v to v ref range is used , and 4 v ref /409 6 when the 0 v to 2 v ref range is used. t he ideal transfer cha racteristic for the adc when outputting twos complement coding is shown in figure 35 (with the 2 v ref range). 100...000 01 1... 11 1 1lsb = 2 v ref /4096 +v ref ? 1lsb ?v ref + 1lsb v ref ? 1lsb analog input adc code 100...001 100...010 01 1... 1 10 000...001 000...000 11 1... 11 1 05747-017 figure 35 . differential tra nsfer characteristic with v ref v ref input range for v in 0 to v in 3 in single - ended mode, the output code is straight binary, where v in = 0 v, d out = x000, v in = v ref ? 1 lsb , and d out = x fff in differential mode, the code is twos complement, where v in+ ? v in? = 0 v, and d out = x 00 v in+ ? v in? = v ref ? 1 lsb , and d out = x7ff v in+ ? v in? = ?v ref , and d out = x800 channel 5 and channel 6 ( c urrent s ensor inputs) are twos complement, where v in+ ? v in? = 0 m v, and d out = x 000 v in+ ? v in? = v ref /12.5 ? 1 lsb, d out = x7ff v in+ ? v in? = ?v ref /12.5, d out = x800 channel 7 to channel 9 ( t emperature s ensor inputs) are twos complement with the lsb equal to 0.25 c, where t in = 0 c, and d out = x 000 t in = + 255.75 c, and d out = x7ff t in = ? 256 c, and d out = x800 analog inputs the ad7294 has a total of four analog inputs. depending on the configuration register setup, they can be configured as two single- ended inputs, two pseudo differential channels , or two fully differential channels. see the register setting section for further details. single - ended mode the ad7294 can have four single - ended analog input channels. in applications where the signal source has high impedance, it is recommended to buffer the analog input before applying it to the adc. th e analog input range can be programmed to be either 0 v to v ref or 0 v to 2 v ref . in 2 v ref mode, the input is effectively divided by 2 before the conversion takes place. note that the voltage with respect to gnd on the adc analog input pins cannot exc eed av dd . if the analog input signal to be sampled is bipolar, the internal reference of the adc can be used to externally bias up this
ad7294 rev. f | page 21 of 48 signal so that it is correctly formatted for the adc. figure 36 shows a typical connection dia gram when operating the adc in single - ended mode. v in 0v +1.25v ?1.25v ref out adc v in 0 ad7294 1 v in 3 r r 3r r 0v +2.5v 0.47f 1 additional pins omitted for clarity. 05747-018 figure 36 . single - ended mode connection diagram differential mode the ad7294 can have two differential analog input pairs. differential signals have some benefits over single - ended signals, including noise immunity based on the common - mode rejection of the device and improvements in distortion performance. figure 37 defines the fully differential analog input of the ad7294. v in+ ad7294 1 v in? v ref p-p v ref p-p common-mode volt age 1 additiona l pins omitted for clarit y. 05747-019 figure 37 . differential input definition the amplitude of the differential signal is the difference between the signals applied to v in+ and v in? i n each differential pair ( v in+ ? v in ? ). the resulti ng converted data is stored in two s complement format in the re sult re gister. simultaneously drive v in 0 and v in 1 by two signals , each of amplitude v ref (or 2 v ref , depending on the range chosen) , that are 180 out of phase. assuming the 0 v to v ref range is selected, the amplitude of the differential signal is , ther efore , ?v ref to +v ref peak - to - peak (2 v ref ), regardless of the common mode (v cm ). the common mode is the average of the two signals ( v in + + v in )/2 the common mode is , therefore , the voltage on which the two inputs are centered. this results in the span of eac h input being v cm v ref /2. this voltage has to be set up externally, and its range varies with the reference value, v ref . as the value of v ref increases, the common - mode range decreases. when driving the inputs with an amplifier, the actual common -m ode ra nge is determined by the output voltage swing of the amplifier . the common mode must be in this range to guarantee the functionality of the ad7294. when a conversion takes place, the common mode is rejected, resulting in a virtually noise - free signal of a mplitude ?v ref to +v ref , corresponding to the digital output codes of ?2048 to +2047 in two s complement format . if the 2 v ref range is used, the input signal amplitude extends from ?2 v ref (v in+ = 0 v, v in? = v ref ) to +2 v ref (v in? = 0 v, v in+ = v ref ). driving differential inputs the differential modes available on v in 0 to v in 3 in table 13 require that v in+ and v in ? be driven simultaneously with two equal signals that are 180 out of phase. the common mode on which the analog input is centered must be set up externally. the common - mode range is determined by v ref , the power supply, and the particular amplifier used to drive the analog inputs. differential modes of operation with either an ac or dc input provide the best thd pe rformance over a wide frequency range. because not all ap plications have a signal precon ditioned for differential operation, there is often a need to perform a single- ended - to - differential conversion. using an op amp pair an op amp pair can be used to dire ctly couple a differential signal to one of the analog input pairs of the ad7294. the circuit con - figurations illustrated in figure 38 show how a dual op amp can be used to convert a single - ended bipolar signal into a differen ti al unipolar input signal. the voltage applied to point a sets up the common - mode voltage. as shown in figure 38, point a connect s to t he referenc e, but any value in the common - mode range can be the input at point a to set up the common mode. the ad8022 is a suitable dual op amp that can be used in this configuration to provide differential drive to the ad7294. c are is required when choosing the op amp because the selection depends on the required power supply and system performan ce objectives. the driver circuits in figure 38 are optimized for dc coupling applications requiring best distortion performance. the differential op amp driver circuit shown in figure 38 is con figured to convert and level shift a single - ended, ground referenced (bipolar) signal to a differential signal centered at the v ref level of the adc.
ad7294 rev. f | page 22 of 48 20k? 220k? 2 v ref p-p 27? 27? v+ v? v+ v? gnd 2.5v 3.75v 1.25v 2.5v 3.75v 1.25v ref out adc v in+ ad7294 1 v in? 440? 220? 0.47f 1 additional pins omitted for clarity. 220? 220? 10k? a 05747-023 figure 38 . dual op amp circuit to convert a single - ended bipolar signal in to a differential unipolar signa l pseudo differential mode the four uncommitted analog input channels can be configured as two pseudo differential pairs. uncommitted input, v in 0 and v in 1, are a pseudo differential pair, as are v in 2 and v in 3 . in this mode, v in+ is conne cted to the signal source, which can have a maximum amplitude of v ref (or 2 v ref , depending on the range chosen) to make use of the full dynamic range of the part. a dc input is applied to v in? . the voltage applied to this input provides an offset from ground or a pseudo ground for the v in+ input. which channel is v in+ is determined by the adc channel allocation. the differential mode must be selected to operate in the pseudo differential mode. the resulting converted pseudo differen - tial data is stored i n twos complement format in the result register. the governing equation for the pseudo differential mode, for v in 0 is v out = 2( v in+ ? v in ? ) ? v ref_adc where v in+ is the single - ended signal and v in ? is a dc voltage. the benefit of pseudo differential inputs is that they separate the analog input signal ground from the adc ground, allowing dc common - mode voltages to be cancelled. the t ypical voltage range for v in? while in pseudo differential mode is shown in figure 39; figure 40 shows a connection diagram for pseudo differential mode. 2.0 1.5 1.0 0.5 ?0.5 0 0 6 5 4 3 2 1 v in? (v) v ref (v) 05747-095 av dd = dv dd = 5v v drive = 5v figure 39 . v in ? input range vs. v ref in pseudo differential m ode dc input voltage v ref p-p ref out /ref in adc v in+ ad7294 1 v in? 0.47 f 1 additional pins omitted for clarity. 05747-026 figure 40 . pseudo d ifferential mode connection diagram current sensor t wo bidirectional high - side current sense amplifiers are provided that can accurately amplify differential current s hunt voltages in the presence of high common - mode voltages from av dd up to 59.4 v. each amplifier can accept a 200 mv differential input. both current sense amplifiers have a fixed gain of 12.5 and uti lize an internal 2.5 v reference . an analog comparato r is also provided with each amplifier for fault detection. the threshold is defined as 1.2 full -s cale voltage range w hen this limit is reached, the output is latched onto a dedicated pin. this output remains high until the latch is cleared by writing t o the appropriate register. ad7294 av dd to 54.5v rs(+) r sense i load rs(?) r1 40k? r2 40k? r3 100k? r4 100k? q1 q2 v out to mux a1 a1 a2 v pp 05747-029 figure 41 . high - side current sense the ad7294 current sense comprise s two main blocks : a differential and an instrumentation amplifier. a load current flowing through the external shunt resistor produces a voltage at the input terminals of the ad7294. resistors r1 and r2 connect the input terminals to the differential amplifier (a1). a1 nulls the voltage appearing across its own input terminals by adjusting the current through r1 and r2 with transistor q1 and transistor q2. common - mode feedback maintains the sum of these currents at approximately 50 a. when the input signal to the ad7294 is zero, the currents in r1 and r2 are equal. when the differential signal is nonzero, the current increases through one of the resistors and decreases in the other. the current differ - ence is proportional to the siz e and polarity of the input signal. the differential currents through q1 and q2 are converted into a differential v oltage by r3 and r4. a2 is configured as an instru - mentation amplifier, buffering this voltage and providing additional
ad7294 rev. f | page 23 of 48 gain. therefore , for an input voltage of 200 mv at the pins, an output span of 2.5 v is generated. the current sensors on the ad7294 are design ed to remove any flicker noise and offset present in the sensed signal. this is achieved by implementing a chopping technique that is transpa - rent to the user . the v sense signal is first converted by the ad7294, the analog inputs to the amplifiers are then swapped , and the differential voltage is once again converted by the ad7294. the two conversion results enable the digital remova l of any offset or noise. switches on the amplifier inputs enable this chopping technique to be implemented . this process requires 6 s in total to return a final result. choosing r sense the resistor values used in conjunction with the current sense amplifiers on the ad7294 are determined by the specific appli - cation requirements in terms of voltage, current , and power. small resistors minimi z e power dissipation, have low inductance t o prevent any induced voltage spikes, and have good tolerance, which reduce current variations. the final values chose n are a compromise between low power dissipation and good accuracy. l ow value resisto rs have less power dissipated in them, but highe r value resistors may be required to utili z e the full input range of the adc, thus achieving maximum snr performance. when the sense current is known, the voltage range of the ad7294 current sensor (200 mv) is divided by the maximum sense current to yield a suitable shunt value. if the power dissi - pation in the shunt resistor is too large, the shunt resistor can be reduced , in which ca se, less of the adc input range is used. using less of the adc input range re sults i n conversion results, which are more susceptible to noise and offset errors because offset error s are fixed and are thus more significant when smaller input ranges are used. r sense must be able to dissipate the i 2 r losses. if the power dissi - pation rating of the resistor is exceeded, its value may drift or the resistor may be damaged resulting in an open circuit. this can result in a differential voltage across the terminals of the ad7294 in excess of the absolute maximum ratings. additional protect ion is afforded to the current sensors on the ad7294 by the recommended current limiting resistors, rf1 and rf2, as illustrated in figure 42. the ad7294 can handle a maximum continuous current of 30 ma; thus , an rf2 of 1 k ? provide s adequate protection for the ad7294. if i sense has a large high frequency component, take care to choose a resistor with low inductance. low inductance metal film resistors are best suited for these applications. current sense filtering in some a pplications, it may be desirable to use external filtering to reduce the input bandwidth of the amplifier ( see figure 42) . the ?3 db differential bandw idth of this filter is equal to bw dm = 1/ (4 rc ) note that the maximum series resistance on the rs(+) and rs( ?) inputs (as shown in figure 41) is limited to a maximum of 1 k due to back -to- back esd protection diodes from rs (+) and rs (?) to v pp . also, note that if rf1 and rf2 ar e in series with r1 and r2 ( shown in figure 41 ), it affect s the gain of the amplifier. any mismatch between rf1 and rf2 can introd uce offset error. 05747-098 rf1 rf2 cf ad7294 v pp r sense i load rsx(?) rsx(+) 10nf v pp figure 42 . current sense filtering ( rs x can be either rs1 or rs2 ) for certain r f applications , the optimum value for rf1 and rf2 is 1 k w hereas cf1 can range from 1 f to 10 f. cf2 is a decoupling capacitor for the v pp supply. its value is application dependant , but for initial evaluation , values in the range of 1 nf to 100 nf are recommended . kelvin sense resistor connection when usin g a low value sense resistor for high current measurement, the problem of parasitic series resistance can arise. the lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. avoid t his pr oblem by using a kelvin sense connection. this type of connection separates the current path through the resistor and the voltage drop across the resistor. figure 43 shows the correct way to connect the sense resistor between th e rs (+) and rs (?) pins of the ad7294. sense resistor current flow from supply current flow to load kelvin sense traces ad7294 rsx(+) rsx(?) 05747-031 figure 43 . kelvin sense connections ( rsx can be either rs1 or rs2 ) analog comparator lo op the ad7294 contains two setpoint comparators that are used for independent analog control. this circ uitry enables users to quickly detect if the sensed voltage across the shunt ha s
ad7294 rev. f | page 24 of 48 increased about the preset (v ref 1.2) /12.5. if this occurs , the i sense overrange pin is set to a high logic level enabling appropriate action to be taken to prevent any dam age to the external circuitry. the setpoint threshold level is fixed internally in the ad7294 , and the current sense amplifier saturates above this level . the comparator also triggers if a voltage of less than av dd is applied to the r sense or v pp p in . temperature sensor the ad7294 contains one local and two remote temperature sensors. the temperature sensor s continuously monitor the three temperature inputs and new readin gs are automatically available eve ry 5 ms. the on - chip, band gap temperature sen sor mea sur es the temper - ature of the system. diodes are used in conjunction with the two remote temperature sensors to mon itor the temperature of othe r critical board components. limit registers temp sensor t1 t2 alert d2+ d2? d1+ d1? ad7294 cap remote sensing transistors 16 i i i-bias mux mux v dd bias diode to adc 4 i f c = 65khz lpf 05747-032 figure 44 . internal and remote temperature sensors the te mperature sensor module on the ad7294 is based on the three current principle ( see figure 44) , where three currents are passed th rough a diode and the forward voltage drop is measure d at each diode, allowing the temperature to be calculated free of errors caused by series resistance. each input integrates, in turn , over a period of several hundred microseconds. this takes place continuously in the background, leaving the user free to perform conversions on the other channels. when integration is complet e, a signal passe s to the control logic to initiate a conversion automatically . if the adc is in command mode, the temperature conversion is performed as soon as the next conversion is completed. in autocycle mode, the conversion is inserted into an appropriate place in the current sequence; see the register setting section for further details. if the adc is idle, the conversion takes place immediately. three registers store the result of the last conversion o n each temperature channel; these can be read at any time. in addition, in command mode, one or both of the two external channel registers can be read out as part of the output sequence. remote sensing diode the ad7294 is designed to work with discrete tra nsistors, 2n3904 and 2n3906. if an alternative transistor is used, the ad7294 operate s as specified provided the following conditions are adhered to. ideality factor the ideality factor, n f , of the transistor is a measure of the deviation of the thermal diode from ideal behavior. the ad7294 is trimmed for an n f value of 1.008. use the following equation to calculate the error introduced at a temperature t (c) when using a transistor whose n f does not equal 1.008: t = (n f ? 1.008) (273.15 k + t ) to f a c t or this in, the user can write the ?t value to the offset register. the ad7294 automatically adds it to, or subtracts it from, the temperature measurement. base emitter voltage the ad7294 operate s as specified provide d that the base - emitter voltage is greater than 0.25 v at 8 a at the highest operating temperature , and less than 0.95 v at 128 a for the lowest operating temperature. base resistance the base resistance should be less than 100 ?. h fe variation a transistor with small variation in h fe (app roximately 50 to 150) should be used. small variation in h fe indicates tight control of the v be characteristics. for rf applications, the use of high q capacitors functioning as a filter protect s the integrity of the measurement . these capacitors, such as johanson technology 10 pf high q capacitors: reference code 500r07s100jv4t , should be connected between the base and the emitter, as close to the external device as possible. however, large capacitances affect the accuracy of the temperature meas ure - ment; thus , the recommended maximum capacitor value is 100 p f. in most cases, a capacitor is not required ; the selection of any capacitor is dependent on the noise frequency level . 05747-099 2n3904 npn ad7294 d+ d? 10pf figure 45 . measuring temperature using an npn transis tor 05747-100 10pf 2n3906 pnp ad7294 d+ d? figure 46 . measuring temperature using a pnp transistor
ad7294 rev. f | page 25 of 48 series resistance cancellation the ad7294 has been designed to automaticall y cancel out the effect of parasitic , base , and collector resistance on the tempera - ture read ing. this gives a more accurate result, without the need for any user characterization of the parasitic resis tance. the ad7294 can compensate for up to 100 in a process that is transparent to the user. dac operation the ad7294 contains four 12 - bit dacs that provide digital control with 12 bits of resolution with a 2.5 v internal reference. the dac core is a thin film 12 - bit string dac with a 5 v output s pan and an output buffer that can drive the high voltage output stage. the dac has a span of 0 v to 5 v with a 2.5 v reference input. the output range of the dac, which is controlled by the offset input, can be positioned from 0 v to 15 v. figure 47 is a block diagram of the dac architecture. 05747-101 12-bit dac i 2 c data inputs a1 r1 100k? r2 200k? 5v 15v v dac ref out / ref in dac external reference capacitor r1 100k? r2 200k? a2 offset in x dac out v+ xx (power down register = 0) agnd dac high-z figure 47 . dac architecture resistor string the resistor string structure is shown in figure 48 . it consists of a string of 2 n resistors, each of v alue r. the code loaded to the dac register determines at which node on the string the volta ge is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. this architecture is inherently monotonic, voltage out, and low glitch. it is also linear because all of the resistors are of equal value. r r r r r to output amplifier 05747-028 figure 48 . resistor string structure output amplifier referring to figure 47 , the purpose of a1 is to buffer the dac output range from 0 v to v ref . the second amplifi er, a2, is configured such that when an offset is applied to offset in x, its output voltage is three times the offset voltage minus twice the dac voltage. v out = 3 v offset ? 2 v dac the dac word is digitally inverted on - chip such that v out = 3 v offset + 2( v dac ? v ref ) and v da c = u n 2 d v ref where: v dac is the output of the dac before digital inversion. d is the decimal equivalent of the binary code that is loaded t o the dac register. n is the bit resolution of the dac. an example of the offset function is given in table 8 . table 8 . offset voltage function example offset voltage v out with 0x000 v out with 0x fff 1.67 v 0 v 5 v ? 1 lsb 3.33 v 5 v 10 v ? 1 lsb 5.00 v 10 v 15 v ? 1 lsb the user has the option of leaving the offset pin open, in which case the voltage on the noninverting input of o p amp a2 is set by the resistor divider, giving v out = 2 v dac
ad7294 rev. f | page 26 of 48 this generates the 5 v output span from a 2.5 v reference. digitally inverting the dac allows the circuit to operate as a generic dac when no offset is applied. if the offset pin is not being driven , it is best practice to place a 100 nf capacitor between the pin and ground to improve both the settling time and the noise performance of the dac . note that a significant amount of power can be dissipated in the dac outputs. a thermal shutdown circuit set s the dac outputs to high impedance if a die temperature of >150 c is measured by the internal temperature sensor. this also set s the over tem - perature alert bit in alert register c, see the alerts and limits theory section . n ote that this feature is disabled when the temperature sensor p ower s down. high impe dance input pin when the high impedance pin ( dac h igh - z pin) is taken high by the user ( see figure 47) , the voltage on the offset pin appears on the dac output voltage pin. essentially , the internal amplifier a2 acts as a voltage follower. this feature allows a fast change in the output when a fault occurs. adc and dac reference the ad7294 has two independent internal high performance 2.5 v r eferences , one for the adcs and the other for the four on - chip dacs . if the application r equires an external reference, it can be applied to the ref out /ref in dac pin and/or to the ref out /ref in adc pin. the internal reference should be buffered before being used by external circuitry. decouple both the ref out / ref in dac pin and the ref out /ref in adc pin to agnd using a 220 nf capacitor. on power - up , the ad7294 is configured for use with an external reference. to enable the internal r eferences , write a zero to both the d4 and d5 bits in the power - down register ( see the reg ister setting section for more details ). both the adc and dac reference s require a minimum of 60 s to power up and settle to a 12- bit perfor mance when a 220 nf decoupling capacitor is used. the ad7294 can also operate with an external reference. suitable reference sources for the ad729 4 include ad780 , ad1582 , adr431 , ref193 , and adr391 . in addition, choo sing a referen ce with an output trim adjustment, such as the adr441 , allows a system designer to trim system errors by setting a reference voltage to a voltage other than the nominal. long - term drift is a meas ure of how much the reference drifts ove r time. a reference with a low long - term drift specification ensures that the overall solution remains stable during its entire lifetime. if an external reference is used, select a low temperature coefficient specifi cation to reduce the temperature dependence of the system output voltage on ambient conditions. v drive feature the ad7294 also has a v drive feature to control the voltage at which the i 2 c interface operates. t he v drive pin is connected to the supply to wh ich the i 2 c bus is pulled. this pin sets the input and output threshold levels for the digital logic pins and the i sense overrange pins . the v drive feature allows the ad7294 to easily interface to both 3 v and 5 v processors. for example, if the ad7294 is operated with a v dd of 5 v, the v drive pin can be powered from a 3 v supply, allowing a large dynamic range with low voltage digital processors. thus, the ad7294 can be used with the 2 v ref input range with a v dd of 5 v, yet remains cap able of interfacin g to 3 v digital parts. decouple t his pin to dgnd with a 10 0 nf and a 1 f capacitor.
ad7294 rev. f | page 27 of 48 register setting the ad7294 contains internal registers (see figure 49 ) that store conversion results, high and low conversion limits, and in formation to configure and control the device. address pointer register serial bus interface sda scl data command register result register dac registers t sense result registers 3 t sense offset registers 2 alert registers 3 configuration register power-down register hysteresis register data high / data low registers 18 channel sequence register 05747-039 figure 49 . ad7294 register structure each data register has an address to which the address pointer register points when communicating with it. the command register is the only reg ister that is a write - only register; the rest are read/write registers. address point er register the address pointer register is an 8 - bit register, in which the 6 lsbs are used as pointer bits to store an address that points to one of the ad7294 data registers, see table 9 . table 9 . ad7294 register address address in hex registers (r is read/w is write) 00 command r egister (w) 01 result r egister (r)/dac a v alue (w) 02 t sense 1 r esult (r)/dac b v alue (w) 03 t sense 2 r esult (r)/dac c v alue (w) 04 t sense int r esult (r)/dac d v alue (w) 05 alert register a (r/w) 06 alert register b (r/w) 07 alert register c (r/w) 08 channel sequence register (r/w) 09 configuration r egister (r/w) 0a power - down reg ister (r/w) 0b data low r egister v in 0 (r/w) 0c data high r egister v in 0 (r/w) 0d hysteresis r egister v in 0 (r/w) 0e data low register v in 1 (r/w) 0f data high register v in 1 (r/w) 10 hysteresis r egister v in 1 (r/w) 11 data low r egister , v in 2 (r/w) 12 data high r egister v in 2 (r/w) 13 hysteresis r egister v in 2 (r/w) 14 data low r egister v in 3 (r/w) 15 data high r egister v in 3 (r/w) 16 hysteresis r egister v in 3 (r/w) 17 data low r egister i sense 1 (r/w) 18 data high r egister i sense 1 (r/w) 19 hysteresis r egister i sense 1 (r/w) 1a data low r egister i sense 2 (r/w) 1b data high r egister i sense 2 (r/w) 1c hysteresis r egister i sense 2 (r/w) 1d data low r egister t sense 1 (r/w) 1e data high r egister t sense 1 (r/w) 1f hysteresis r egister t sense 1 (r/w) 20 data low r egister t sense 2 (r/w) 21 data high r egister t sense 2 (r/w) 22 hysteresis r egister t sense 2 (r/w) 23 data low r egister t sense int (r/w) 24 data high r egister t sense int (r/w) 25 hysteresis r egister t sense int (r/w) 26 t sense 1 offset regis ter (r/w) 27 t sense 2 offset regi ster (r/w) 40 factory test mode 41 factory test mode
ad7294 rev. f | page 28 of 48 command register (0 x00) writing in the command register puts the part into command mode. wh en in command mode, the part cycles through the selected channels from lsb (d 0 ) to msb (d7) on each subse - quent read (see table 10) . a channel is selected for conversion if a one is written to the desired bit in the c ommand r egister. on p ower - up , all bits in the c ommand r egister are set to zero. if the external t sense channels are selected in the co mm and register byte , it is not actually requesting a conversion. the result of the last automatic conversion is output as part of the sequence (s ee the modes of operation s ection ). if a command mode conversion is required while t he autocycle mode is active, it is necessary to disable the autocycle mode before proceeding to the command mode ( see the autocycle mode section for more details). result register (0 x01) the r esult register is a 16 - bit read - onl y register. the conversion results for the four uncommitted adc inputs and the two i sense channels are stored in the result register for re ading. bit d14 to bit d12 are the channel allocation bits, each of which ide ntifies the adc channel that correspond s to the subsequent result (s ee the adc channel allocation s ection for more details) . bit d11 to bit d0 contain the most recent adc result. d15 is reserved as an a lert _f lag bit. table 11 list s the contents of the first byte that is read from the ad7294 results register ; table 12 list s the contents of the second byte read. table 10 . command register 1 msb lsb bits d7 d6 d5 d4 d3 d2 d1 d0 channel r ead out last result from t sense 2 read out last result from t sense 1 i sense 2 i sense 1 v in 3 (s.e.) or v in 3 ? v in 2 (diff) v in 2 (s.e.) or v in 2 ? v in 3 (diff) v in 1 (s.e.) or v in 1 ? v in 0 (diff) v in 0 (s.e.) or v in 0 ? v in 1 (diff) 1 s.e. indicates single - ended and diff indicates differential. table 11. result register (first read) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 alert_flag ch id2 ch id1 ch id0 b11 b10 b9 b8 table 12. result register (second read) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0
ad7294 rev. f | page 29 of 48 adc channel allocation the three channel address bits indicate which channel the result in the result register represents. table 13 details the channel id bits (s.e. indicates single - ended and diff indicates differential). table 13 . adc channel allocation function channel id ch id2 ch id1 ch id0 v in 0 (s.e.) or v in 0 ? v in 1 (diff) 0 0 0 v in 1 (s.e.) or v in 1 ? v in 0 (diff) 0 0 1 v in 2 (s.e.) or v in 2 ? v in 3 (diff) 0 1 0 v in 3 (s.e.) or v in 3 ? v in 2 (diff) 0 1 1 i sense 1 1 0 0 i sense 2 1 0 1 t sense 1 1 1 0 t sense 2 1 1 1 t sense 1 , t sense 2 result registers (0x 02 and 0 x 03) register t sense 1 and register t sense 2 are 16 - bit read only register s . the msb, d15 is the alert _flag bit wh ereas bit d14 to bit d12 contain the three ad c channel allocation bits . d11 is reserved for flagging diode open circuits. the temperature re ading from the adc is stored in an 11 - bit twos co mplement format, d10 to d0 ( see tabl e 14 and table 15 ). conversions take place approx - imately every 5 ms. table 14 . t sense register (first read) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 alert_flag ch id2 ch id1 ch id0 b11 b10 b9 b8 table 15 . regis ter (second read) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 t sense int result register (0x 04) the t sense int register is a 16 - bit read - only register used to store the adc data generated from the internal temperature sen sor. similar to the t sense 1 and t sense 2 result registers, this register stores the temperatu re readings from the adc in a n 11- bit twos complement format , d10 to d0, and uses the msb a s a general alert flag. b it s[ d14 : d11 ] are not used and are set to zero . conversions take place approximately every 5 ms. the temperature data format in table 16 also applies to the internal temperature sensor data. temperature value format the temperature reading from the adc is stored in a n 11- bit twos complement format, d10 to d0, to accommodate both positive an d negative temperature measure ments. the temper - ature data format is provided in table 16 . table 16 . t sense data format input d10 (msb) d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) value (c) ?256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25
ad7294 rev. f | page 30 of 48 dac a , dac b , dac c , dac d , register s (0 x 01 to 0 x 04 ) writing to these register addresses sets the dac a , dac b , dac c , and dac d output voltage code s, respectively . bits[d11:d0] in the write result registe r are t he data bits sent to dac a . bit d15 to bit d12 are ignored. table 17 . dac register (first write) 1 msb lsb d15 d14 d13 d12 d11 d10 d9 d8 x x x x b11 b10 b9 b8 1 x is dont care. table 18. dac register (second write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 alert status registe r a (0x 05), register b (0x 06) , and register c ( 0x 07) the alert status registers ( a, b , and c ) are 8 - bit re ad/write registers that provide information on an alert event. if a conversion results in activating the alert /busy pin or the a lert_ f lag bit in the result register or t sense registers, the alert status register can be read to gain further information. to cl e a r the full con tent of any one of the alert registe rs , write a code of ff (all one s) to the relevant registers. alternatively, the user can write to the respective alert bit in the selected alert register to clear the a lert associated with that bit. the entire contents o f all the alert status registers can be cleared by writing a 1 to bit d1 and bit d2 in the configuration register, as shown in table 24. however, this operation then enables the alert /busy pin for subsequent conversions. see the alerts and limits theory section for more details. channel sequence reg ister (0x 08) the channel sequence register is an 8 - bit read/write register that allows the user to sequence the adc conversions to be per - formed in autocycle mode. tabl e 22 shows the content of the channel sequence register. see the modes of operation s ection for more information. table 19 . alert status register a alert bit d7 d6 d5 d4 d3 d2 d1 d0 function v in 3 high alert v in 3 low alert v in 2 high alert v in 2 low alert v in 1 high alert v in 1 low alert v in 0 high alert v in 0 low alert table 20 . alert status register b alert bit d7 d6 d5 d4 d3 d2 d1 d0 function reserved reserved i sense 2 overrange i sense 1 overrange i sense 2 high alert i sense 2 low alert i sense 1 high alert i sense 1 low alert table 21 . alert status register c alert bit d7 d6 d5 d4 d3 d2 d1 d0 function open - diode flag ove rt emp alert t sense int high alert t sense int low alert t sense 2 high alert t sense 2 low alert t sense 1 high alert t sense 1 low alert table 22 . channel sequence register channel bit d7 d6 d5 d4 d3 d2 d1 d0 function reserved reserve d i sense 2 i sense 1 v in 3 v in 2 v in 1 v in 0
ad7294 rev. f | page 31 of 48 configuration regist er (0 x09) the configuration register is a 16 - bit read/write register that sets the operating modes of the ad7294. the bit functions of the configuration register are outlined in table 23 and table 24. on power - up, the configuration register is reset to 0x0000. sample delay and bit trial delay it is recommended that no i 2 c bus activity occur when a con - version is taking place; however, this may not be possible, for example, when operating in autocycle mode. bit d14 and bit d13 in the configuration register are used to delay critical sample intervals and bit trials from occurring while there is activity on the i 2 c bus. on power - up , bit d14 (nois e- delayed sampling), bit d13 (noise - delayed bit trials), and bit d3 (i 2 c filters ) are enabled (set to 0). this configuration is appropriate for low frequency applications because the bit trial s are prevented from occurring when there is activity on the i 2 c bus, thus ensuring good dc linearity perfor - mance. for high frequency input signals, it may be desirable to have a know n sampling point , thus the noise - delayed sampling can be disabled by writing a 1 to bit d14 in the configura tion register. this ensures that the sampling instance is fixed relative to sda, resulting in improved snr performance. if noise - delay samplings extend longer than 1 s, the current conversion terminates. this termination can occur if there are edges on sda that are outside the i 2 c s pecification. when noise - delayed sampling is enabled, the rise and fall times must meet the i 2 c- specified standard. when d13 is enabled , the conversion time may vary. the default configuration for bit d3 (enabled) is recommended for normal operation becau se it ensures that the i 2 c requirements for t of (minimum)and t sp are met. the i 2 c filters reject glitches shorter than 50 ns. if this function is disabled, the conversion results are more susceptible to noise from the i 2 c bus. table 23 . configuration register bit function description d15 to d8 channel bit d15 d14 d13 d12 d11 d10 d9 d8 function reserved n oise - delayed sampling. use to delay critical sample intervals from occurring when there is activity on the i 2 c bus. n oise - de layed bit trials. use to delay critical bit trials from occurring when there is activity on the i 2 c bus. a uto cycle mode p seudo differential mode for v in 3/v in 4 p seudo differential mode for v in 1/v in 2 d ifferential mode for v in 3/v in 4 d ifferential mode for v in 1/v in 2 setting enabled = 0 enabled = 0 enabled = 1 enabled = 1 enabled = 1 enabled = 1 enabled = 1 disabled = 1 disabled = 1 disabled = 0 disabled = 0 disabled = 0 disabled = 0 disabled = 0 table 24 . configuration register bit function description d7 to d0 channel bit d7 d6 d5 d4 d3 d2 d1 d0 function 2v ref range for v in 4 2v ref range for v in 3 2v ref range for v in 2 2v ref range for v in 1 i 2 c filters alert pin busy pin (d2 = 0) , clear alerts (d2 = 1) select alert pin polarity (activ e high/ active low) setting enabled = 1 disabled = 0 enabled = 1 disabled = 0 enabled = 1 disabled = 0 enabled = 1 disabled = 0 enabled = 0 disabled = 1 enabled d2 = 1 d1 = 0 disabled d2 = 0 enabled d1 = 1 + d0 = 0 disabled d1 = 0 active high = 1 active l ow = 0 table 25. a lert /busy function description d2 d1 alert/busy p in functions 0 0 pin does not provide any interrupt signal. 0 1 configures p in as a busy output . 1 0 configures pin as an alert output. 1 1 resets the alert/bu sy output pin, the alert_flag bit in the conversion result register, and the entire alert status register (if any is active). 1, 1 is written to bits [ d2 : d1 ] in the configuration register to reset the alert/busy pin, the alert_f lag bit, and the alert status register. following this write , the contents of the configuration register read 1 , 0 for bit d2 and bit d1, respectively, if read back. table 26 . adc input mode example d11 d10 d9 d8 description 0 0 0 0 all channels single - ended 0 0 0 1 differential m ode on v in 1/v in 2 0 1 0 1 pseudo differential mod e on v in 1/v in 2
ad7294 rev. f | page 32 of 48 power - down register ( 0x0a) the power - down register is an 8 - bit read/write register that power s down various sections on the ad7294 device. on power - up , the default value for the power - down register is 0x30. the content of the power - down register is provided in table 27 . table 27 . power - down register description bit function d7 power down the full chip d6 reserved d5 power down the adc reference buffer (to allow external reference, 1 at power - up) d4 power down the dac reference buffer (to allow external reference, 1 at power - up) d3 power down the temperature sensor d2 power d own i sense 1 d1 power d own i sense 2 d0 d ac outputs set to high impedance (set automatically if die temperature >150c) in normal o peration, the two msbs of the i 2 c slave address are se t to 11 by an internal rom. however, in full power - down mode ( p ower down by setting b it d7 = 1), this rom is s witched off and the slave address msbs become 00. therefore, to exit the full - power - down state , it is necessary to w rite to the ad7294 using this modified slave address. after writing 0 to power down bit d7, the slave address msbs return to their original 11 value . data high /data low registers: 0x 0b, 0x 0c (v in 0 ); 0x 0e , 0x 0f (v in 1); 0 x 11 , 0 x 12 (v in 2); 0 x 14, 0x 15 (v in 3) the data high and data low registers for a channel are 16 - bit, read/write registers ( see tabl e 29 and table 30) . general alert is flagged by the msb, d15. d14 to d12 are not used in the register and are set to 0 s. the remaining 12 bits set the high and low li mits for th e relevant channel. for single - end e d mode , the default value s for v in 0 to v in 3, are 000 and fff in binary format. for differen - tial mode on v in 0 to v in 3 , the default values for data high and data low are 7ff and 800, two s complement format. note that if the part is configured in either single- en ded or differential mode and the mode is changed , th e user must re program the limits in the data high and data low registers . channel 7 to channel 9 (t sense 1, t sense 2, and t sense int) default to 3ff and 400 for the data high and data low limits because they are in two s complement 11 - bit format. tab le 28 . default v alues for data high and data low r egisters adc channel single - ended differential data low data high data low data high v in 0 000 fff 800 7ff v in 1 000 fff 800 7ff v in 2 000 fff 800 7ff v in 3 000 fff 800 7ff i sense 1 n/ a n/a 800 7ff i sense 2 n/a n/a 800 7ff t sense 1 n/a n/a 400 3ff t sense 2 n/a n/a 400 3ff t sense int n/a n/a 400 3ff table 29 . ad7294 data high / low register (first r ead /w rite ) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 alert_flag 0 0 0 b11 b10 b9 b8 table 30. ad7294 data high / low register (second r ead /w rite ) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 hysteresis registers : 0x 0d (v in 0) , 0x 10 (v in 1), 0x 13 (v in 2), 0 x16 (v in 3) each hysteresis register is a 16 - bit read/write register wherein only the 12 lsbs of the register are used ; the msb signal s the alert event. if fff is written to the hysteresis register , the hyste - resis register enters the minimum/max imum mode, see the alerts and limits theory section for further details. table 31. hysteresis register (first read/write) msb lsb d15 d14 d13 d12 d11 d10 d9 d8 alert_flag 0 0 0 b11 b10 b9 b8 table 32 . hysteresis register (second read/write) msb lsb d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0
ad7294 rev. f | page 33 of 48 t sense offset registers ( 0x 26 and 0x 27) the ad7294 has temperature offset , 8- bit twos complement regis - ters f or both remote c hannel t sense 1 and remote channel t sense 2. it allows the user to add or subtract an offset to the temperature. the offset registers for t sense 1 and t sense 2 are 8 - bit read/write registers that store data in a twos complement format. this data is subtracted from the temperature readings taken by t sense 1 and t sense 2 temperature sensors. the offset is implemented before the values are stored in the t sense result register. the offset registers can be used to compensate for transistors with different ideality factors because the t sense results are based on the 2n3906 transistor ideality factor. d ifferent transistors with different ideality factor s result in different offsets within the region of interest , which can be compensated for by using this register. table 33 . t sense offset data format input msb d7 d6 d5 d4 d3 d2 d1 lsb d0 value (c) ?32 +16 +8 +4 +2 +1 +0.5 +0.25
ad7294 rev. f | page 34 of 48 i 2 c interface general i 2 c timing figure 50 shows the timing diagram for general read and w rite operations using an i 2 c- compliant interface . the i 2 c bus uses open - drain drivers ; therefore, when no device is driving the bus, both scl and sda are high. this is known as idle state. when the bus is idle, the master initiates a data transfer by esta blishing a start condition , defined as a high - to - low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that a data stream follows. the master device is responsible for generating the clock. data is sent over the serial bus in groups of nine bits eight bits of data from the transmitter followed by an acknowledge bit ( ack ) from the receiver. data transitions on the sda line must occur during the low period of the clock signal and remain stable during the h igh period. the receiver should pull the sda line low during the acknowledge bit to signal that the preceding byte has been received correctly. if this is not the case , cancel the transaction. the first byte that the master sends must consist of a 7 - bit s lave address , followed by a data direction bit. each device on the bus has a unique slave address; therefore, the first byte sets up communica tion with a single slave device for the duration of the trans a ctio n. the transaction can be used either to write t o a slave device (data direction bit = 0) or to read data from it (data direction bit = 1). in the case of a read transaction, it is often necessary first to write to the slave device (in a separate write transaction) to tell it from which register to rea d. reading and writing cannot be combined in one transaction. when the transaction is complete, the master can keep control of the bus, initiating a new transaction by generating another start b it (high - to - low transition on sda while sc l is high). this is known as a r epeated start (sr). alternatively , the bus can be relinquished by releasing the scl line followed by the sda line. this low - to - high transition on sda while scl is high is known as a stop bit (p), and it leaves the i 2 c bus in its idle state (no current is consumed by the bus ). the example in figure 50 s hows a simple write transaction with an ad7294 as the slave device. in this example , the ad7294 register pointer is being set up ready for a future read transaction. p7 p6 p5 p4 p3 p2 p1 p0 start cond by master ack. by ad7294 slave address byte ack. by ad7294 scl sda register address stop by master user programmable 5 lsbs r/w a6 a5 a4 a3 a2 a1 a0 05747-040 figure 50 . general i 2 c timing
ad7294 rev. f | page 35 of 48 serial bus address b yte the first byte the user writes to the device is the slave address byte . similar to all i 2 c- compatible devices , the ad7294 has a 7- bit serial address. the 5 lsbs are user - pr ogrammable by the 3 three - state input pins , as shown in table 34. in table 34, h means tie the pin to v drive , l means tie the pin to dgnd, and nc refers to a pin left floating. note that in this final c ase , the stray capacitance on the pin must be less than 30 pf to allow correct detection of the floating state; therefore , any pcb trace must be kept as short as possible. table 34 . slave address control using three - state input pins as2 as1 as0 slave address (a6 to a0) l l l 0x61 l l h 0x62 l l nc 0x63 l h l 0x64 l h h 0x65 l h nc 0x66 l nc l 0x67 l nc h 0x68 l nc nc 0x69 h l l 0x6a h l h 0x6b h l nc 0x6c h h l 0x6d h h h 0x6e h h nc 0x6f h nc l 0x7 0 h nc h 0x71 h nc nc 0x72 nc l l 0x73 nc l h 0x74 nc l nc 0x75 nc h l 0x76 nc h h 0x77 nc h nc 0x78 nc nc l 0x79 nc nc h 0x7a nc nc nc 0x7b interface protocol the ad7294 uses the following i 2 c protocols . writing a single byte of data to an 8 - bit register the al ert registers ( 0x05, 0x06, 0x 07), power - down register ( 0x 0a), channel sequence register ( 0x 08), temperature offset registers ( 0x26, 0x 27), and the command register ( 0x 00) are 8- bit registers; therefore, only one byte of data can be written to each. in this operation, the master device sends a byte of data to the slave device , see figure 51 . to write data to the register, the command sequence is as follows: 1. the master device asserts a start condition. 2. the master sends the 7 - bit slav e address followed by a zero for the direction bit, indicating a write operation. 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. 5. the slave asserts an acknowledge on sda. 6. the master sends a data byte. 7. the sla ve asserts an acknowledge on sda. 8. the master asserts a stop condition to end the transaction.
ad7294 rev. f | page 36 of 48 sda 1 1 9 9 p0p1p2p3p4p5p6p7 r/w a4 a3 a2 a1 a0 a6 scl a5 1 9 sda (continued) scl (continued) start by master ack. by ad7294 ack. by ad7294 frame 1 slave address byte frame 2 address pointer register byte s slave address 0 a reg pointer a data a p frame 3 data byte ack. by ad7294 stop by master d0d1d2d3d4d5d6d7 from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknow ledge a = not acknowledge 05747-061 figure 51 . single byte write sequence
ad7294 rev. f | page 37 of 48 writing two bytes of data to a 16 - bit register the limit and hysteresis registers (0x0b to 0x25), the result registers (0x01 to 0x04), and the configuration register (0x09) are 16 - bit registers; therefore, two bytes of data are required to write a value to any one of these registers. writing two bytes of data to one of these registers consists of the following sequence : 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. the slave asserts an acknowledge on sda. 5. the master sends the first data byte (most significant). 6. the slave asserts an acknowledge on sda. 7. the master sends the second data byte (least significant). 8. the slave asserts an acknowledge on sda. 9. the master asserts a stop condition on sda to end the transaction. writing to multiple registers writing to multiple address registers consists of the following: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device (ad7294) asserts an acknowledge on sda. 4. the master sends a register address, for example the alert status register a register address. the slave asserts an acknowledge on sda. 5. the master sends the data byte. 6. the slave asserts an acknowledge on sda. 7. the master sends a second register address, for example the configuration register. the slave asserts an acknowledge on sda. 8. the master sends the first data byte. 9. the slave asserts an acknowledge on sda. 10. the master sends the s econd data byte. 11. the slave asserts an acknowledge on sda. 12. the master asserts a stop condition on sda to end the transaction. the previous examples detail writing to two register s only (the alert status register a and the configuration register). however, t he ad7294 can read from multiple register s i n one write operation as shown in figure 53. 05747-059 s slave address 0 a reg pointer a data<15:8> a p data<7:0> a from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 52 . writing two bytes of data to a 16 - bit register 05747-054 s slave address 0 a point to config reg (0x09) a data<15:8> a p data<7:0> a point to pd reg (0x0a) data<7:0> a a .. . .. . from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 53 . writing to m ul tiple r egisters
ad7294 rev. f | page 38 of 48 reading data from an 8 - bit register reading the contents from any of the 8 - bit registers is a single byte read operation, as shown in figure 55 . in this protocol, the first part of the transaction writes to the r egister pointer. when the register address has been set up, any number of reads can be performed from that particular register without having to write to the address pointer register again. when the required number of reads is completed, the master should not acknowledge the final byte. this tells the slave to stop transmitting, allowing a stop condition to be asserted by the master. further reads from this register c an be performed in a future transaction witho ut having to re write to the register pointer. if a read from a different address is required, the relevant register address has to be written to the address pointer register, and again , any number of reads from this register can then be performed. in the next example , the maste r device receives two b yte s from a slave device as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. t he master receives a data byte. 5. t he master asserts an acknowledge on sda . 6. the master rec eives another 8 - bit data byte. 7. the master asserts a no acknowledge (nack) on sda to inform the slave that the data transfer is complete. 8. the master asserts a stop condition on sda, and the transaction ends. reading two bytes of data from a 16 - bit register in this example , the master device reads three lots of two - byte data from a slave device , but as many lots consisting of two - bytes can be read as required . t his protocol assumes that the particula r re gister address has been set up by a single byte write operation to the address pointer register ( see the previous read example ). 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the read bit (high). 3. t he addressed slave device asserts an acknowledge on sda. 4. the master receives a data byte. 5. the master asserts an acknowledge on sda. 6. the master receives a second data byte. 7. the master asserts an acknowledge on sda. 8. the master receives a data byte. 9. the ma ster asserts an acknowledge on sda. 10. the master receives a second data byte. 11. the master asserts an acknowledge on sda. 12. the master receives a data byte. 13. the master asserts an acknowledge on sda. 14. the master receives a second data byte. 15. the master asserts a n o acknowledge on sda to notify the slave t hat the data transfer is complete. 16. the master asserts a stop condition on sda to end the transaction. 05747-060 s a p .. . .. . 1 a a a a a a slave address data<7:0> data<7:0> data<7:0> data<15:8> data<15:8> data<15:8> from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 54 . reading three lots of two bytes of data from the conversion result regis ter 05747-055 s 0 a a a p reg pointer ... ... sr 1 a a slave address slave address data<7:0> data<7:0> from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 55 . reading two single bytes of data from a selected register
ad7294 rev. f | page 39 of 48 modes o f operation there are two different methods of initia ting a conversion on the ad7294: command mode and autocycle mode. command mode in command mode , the ad7294 adc convert s on - demand on either a single channel or a sequence of channels. to enter this mode, the required combination of channels is written into the command register (0x00). the first conversion take s place at the end of this write operation, in time for the result to be read out in the next read operation. while this result is being read out, the next conversion in the sequence takes place, and so on. to exit the command mode, the master should not acknowl edge the final byte of data. thi s stop s the ad7294 transmitting, allowing the master to assert a stop condition on the bus. it is therefore important that , after writing to the command register , a r epea ted start (sr) signal be used rather than a stop (p) followed by a start (s) when swit ching to read mode; otherwise , the command mode exit s after the first conversion. after writing to the command register, the register pointer is returned to its previous value. if a new pointer value is required (typically the adc result register 0x01) , it can be written immediately following the command byte. this extra write operation does not affect the conversion sequence because the second conversion triggers only at the start of the first read operation. the maximum throughput that can be achieved using this mode with a 400 khz i 2 c clock is (400 k hz /18) = 22.2 ksps. figure 56 shows the command mode convert ing on a sequence of channels including v in 0, v in 1, and i sense 1. 1. the master device asserts a start condition on sda. 2. the ma ster sends the 7 - bit slave address followed by the write bit (low). 3. the addressed slave device (ad7294) asserts an acknowledge on sda. 4. the master sends the command register addres s 0x00. the slave asserts an acknowledge on sda. 5. the master sends the data b y te 0x13 which selects the v in 0, v in 1, and i sense 1 channels. 6. the slave asserts an acknowledge on sda. 7. the master sends the result register address ( 0x01 ) . the s lave asserts an acknowledge on sda. 8. the master sends the 7 - bit slave address followed by the writ e bit (high). 9. the slave (ad7294) asserts an acknowledge on sda. 10. the master receives a data byte, which contains the alert_fla g bit, the channel id bits , and the four ms bs of the converted result for c hannel v in 0 . the master then asserts a n acknowledge on s da. 11. the master receives the second data byte, which contains the eight lsbs of the converted result for c hannel v in 0. the master then asserts on acknowledge on sda. 12. point 10 and point 11 repeat for channel v in 1 and channel i sense 1. 13. once the master has received the results from all the selected channels, the slave again converts and outputs the result for the first channel in the selected sequence. point 10 to point 12 are repeated. 14. the m aster asserts a no acknowledge on sda and a st op condition on sda to end the conversion and exit command mode. the ad7294 automatically exit s command mode if no read occurs in a 5 ms period. to change the conversion sequence, rewrite a new sequence to the command mode. 05747-056 s a p .. . .. . 0 a a command = 0x13 a v in 0<11:8> a point to result reg (0x01) sr 1 a * a ch id (000) alert? .. . a ch id (001) alert? a .. . a i sense 1<11:8> * * * * a a .. . .. . a v in 0<7:0> .. . ....... . a * = position of a conversion start slave address point to command reg (0x00) v in 1<7:0> v in 0<7:0> v in 1<11:8> v in 0<11:8> slave address i sense 1<7:0> i sense 1<7:0> alert? ch id (100) alert? ch id (000) from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge figure 56 . command mode operation
ad7294 rev. f | page 40 of 48 autocycle mode the ad7294 can be configured to convert continuously on a programmable sequence of channels making it the ideal mode of operation for system monitoring . these conversions take place in the background approxim ately every 50 s, and are transparent to the master. t ypically, t his mode is used to automatically monitor a selection of channels with either the limit registers programmed to signal an out - of - range condition via the alert function or the min imum/ max imum recorders tracking the variation over time of a particular channel. reads and writes can be performed at any time (the adc result register 0x01 contains the most recent conversion result). on power up , this mode is dis abled. to e nable t his mode , write to b it d1 2 in the configuration register (0x09) and select the desired channels for conversion in the channel sequence register (0x08) . if a command mode conversion is required while the autocycle mode is active, it is necessary to disable the autocycle mode before proceeding to the command mode. this is achieved either by clear - ing bit d12 of the configuration register or by writing 0x00 to the channel sequence register. when the command mode conversion is complete, the user must exit command mode by issuing a stop condition before reenabling autocycle mode. when switching out of autocycle mode to command mode, the temperature sensor must be given sufficient time to settle and complete a new temperature integration cycle. therefore, temperature sensor conve rsion s performed within the first 500 ms after switching from a utocycle mode to command mode may result in false temperature high and low alarms being triggered. it is recommended to disable temperature sensor alarms for the first 500 ms after mode switching b y writing 0x400 to the data low t sense x register and 0x3ff to the data high r egister t sense x . the temperature sensor alerts should be reconfigured to the desire d alarm level once the 500 ms has elapsed. alternatively, temperature alerts trigger ed during the first 500 ms after mode switching should be ignored.
ad7294 rev. f | page 41 of 48 alerts and limits th eory alert_flag bit the alert_f lag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. if a n alert occurs and the alert_f lag bit is set , the master can read the alert status register to obtain more information on where the alert occurred. alert status r egisters the alert status registers are 8 - bit read/write register s that provide information o n an alert event. if a conversion results in activa - tion of the alert /busy pin or the alert_flag bit in the result register or t sense registers, the alert status register can be read to get more information (s ee figure 57 for the alert register structure ). 05747-057 alert register a alert register b alert register c d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 v in 3 high alert v in 3 low alert v in 2 high alert v in 2 low alert v in 1 high alert v in 1 low alert v in 0 high alert v in 0 low alert reserved reserved i sense 2 overrange* i sense 2 high alert i sense 1 overrange* i sense 2 low alert i sense 1 low alert i sense 1 high alert open diode flag* over temp alert* t sense int high alert t sense 2 high alert t sense int low alert t sense 2 low alert t sense 1 low alert t sense 1 high alert alert flag or alert/busy configuration register d2 = 1, d1 = 0 * these bits are always active, all other bits can be programmed to be active or not as required. figure 57 . alert register structure register a ( see table 19 ) consists of four channels with two status bits per channel, one corresponding to each of the data high and data lo w limits. it stores the alert event data for v in 3 to v in 0, which are the standard voltage inputs. when the content of this register is read , any bit with a status of 1 indicates a violation of its associated limit ; t hat is, it identifies the channel and wh ether the violation occurred on the upper or lower limit. if a second alert event occurs on another channel before the content of the alert register has been read , the bit corresponding to the second alert event is also set. register b ( see table 20 ) consists of three channels also with two status bits per channel, representing the specified data high and data low limits. b its [ d3 : d0 ] correspond to the high and low limit alerts for the current sense inputs. bit d4 and bit d5 represe nt the i sense 1 overrange and i sense 2 overrange of v ref /10.41. during power - up, it is possible for the fault outputs to be trig - ger ed, depending on which supply comes up first. clearing these bits as par t of the initialization routine is recommended on po wer - up by writing a 1 to both d4 and d5. internal circuitry in the ad7294 can alert if either the d1 or the d2 input pins for the external temperature sensor are open circuit. the most significant bit of register c (s ee table 21 ) alert s the user when an open diode flag occurs on the external tempera ture sensors. if the internal temperature sensor detect s an ad7294 die temperature greater than 150 c, the overtem - perature alert bit, bit d6 in register c , is set and the dac outputs are set to a high impedance sate. the remaining six bits in r egister 6 store alert event data for t sense 1, t sense 2, and t sense int with two status bits per channel , one corresponding to each of the data high and data low limits. to clear the full content of any one of the a lert r egisters , write a code of ff (all ones) to the relevant registers. alternatively, the user can write to the respective alert bit in the selected alert register to clear the alert associated with that bit. the entire contents of all th e alert status registers ca n be cleared by writing a 1 to bit d1 and b it d2 in the configuration register, as shown in table 24 . however, this operation then enables the a lert/ busy pin for subsequent conversions. data high and data low monitoring features the ad7294 signals an alert (in either hardware via the alert /busy pin , software via the alert_f lag bi t, or both, depending on the configuration) if the result moves outside the upper or lower limit set by the user. the data high register stores the upper limit that activates the alert /busy output pin and/or the alert_flag bit in the conver - sion result register. if the conversion result is greater than the value in the data high register, an alert occurs. the data low register store s the lower limit that activates the alert/busy output pin and/or the alert_flag bit in the conversion result register. if the conversion result is less than the value in the data low register, an alert occurs. an al ert associated with either the data high o r data low register is cleared automatically once the monitored signal is back in range ; that is, the conversion res ult is between the limits. the content of the alert register is updated after each conversion. a conversion is performed every 50 s in autoc ycle mode, so the content of the alert register may change every 50 s. i f the alert pin signal s an alert event and the content of the alert register is not read before the next conversion is complete, the content of the register may be changed if the signal being moni - tored returns between the prespecified limits. in these circum - stances, the alert pin no longer signals the occurrence of an alert event.
ad7294 rev. f | page 42 of 48 the h ysteresis register can be used to avoid fl icker on the alert/ busy pin. if the h ysteresis functio n is enabled, the conversion result must return to a value of at least n lsb below the data high register value, or n lsb above the data low register value for the alert /busy o utput pin and alert_flag bit to be reset. the value of n is taken from the 12 - bit hysteresis register associated with that channel. by setting the hysteresis register to a code close to the maximum outpu t code for the adc , that is, 0x77d , data high or data low alerts do not clear automatically by the ad7294 . bit d11 of t he t sense data high or data low limit registers is the diode open - circuit flag . if t his bit is set to 0 , it indicates the presence of an open circuit between the d x + and d x? pins. an alert trigger ed on either i sense overrange pin remains until it is cleared by the user writing to the alert register. the content s of the data high and data low registers are reset t o their default values on power - up ( see table 28 ). hysteresis the hysteresis value determines the reset point for the alert/busy pin and/or alert_flag bit if a violation of the limits occurs. the hysteresis register stores the hysteresis value, n, when using the limit registers. each pair of limit registers has a dedicated hysteresis register. for example, if a hysteresis value of 8 lsb s is required on the upper and lower limits of v in 0, the 16- bit word 0000 0000 0000 1000 should be written to the hysteresis register of v in 0 (see table 9 ). on power - up, the hysteresis registers contain a value of 8 lsb s for non tem pera - ture result registers and 8 c, or 32 lsb s , for the t sense registers. if a different hysteresis value is required, that value must be written to the hyste resis register for the channel in question. the advantage of having hysteresis registers associated with each of the limit regis ters is that it prevents chatter on the al ert bits as sociated with each adc channel. figure 58 shows the limit checking operation. using the limit registers to store min imum /max imum conversion results if fff i s wr itten to the hysteresis register for a particular channel , the data high and data low registers for that channel no longer act as limit registers as previously described, but act as storage registers for the maximum and mini mum conversion results. this function is useful when an aler t signal is not required in an application , but it is still required to monitor the minimum and maximum conversion va lues over time. note that on power - up, the contents of the data high register for each channel are set to maximum code , whereas the contents of the data low registers are set to minimum code by default. high limit low limit high limit ? hysteresis low limit + hysteresis time input signal alert signal 05747-067 figure 58 . limit checking
ad7294 rev. f | page 43 of 48 a pplications information the ad7294 contains all the functions required for general - purpose monitoring and control of current, voltage, and temperature . with its 59.4 v maximum common - mode range, the device is useful in industrial and automotive applica tions where current sensing in the presence of a high common -m ode voltage is required. for example , the part is ideally suited f or monitoring and controlling a power amplifier in a cellular base station . base s tation p ower amplifier monitor and control the ad7294 is used in a power amplifier signal chain to achieve the optimal bias condition for the ldmos transistor. the main factors influencing the bias conditions are tempera - ture, supply voltage, gate voltage drift, and general processing parameters. the overall p erformance of a power amplifier configuration is determined by the inherent tradeoffs required in e fficiency, gain, and linearity. the high level of integration offered by the ad7294 allows the use of a single chip to d ynamically control the drain bias current to maintain a constant value over temperature and time , thus significantly improving the overall performance of the power amplifier. the ad7294 incorporates the functionality of eight discrete components bringing considerable board area savin gs over alternative solutions. the circuit in figure 59 is a typical system connection diagram for the ad7294. the device monitor s and control s the overall performance of two final stage amplifier s. the gain co ntrol and phase adju stment of the driver stage are incorporated in the application and are carried out by the two available uncommitted outputs of the ad7294. both high - side current senses measure the amount of current on the respective final stage amplifiers. the comparator outputs, i sense 1 overrange and i sense 2 overrange pins, are the controlling signals for switches on the rf inputs of the ldmos power fets. if the high - side current sense reads a value above a specified limit compared with the setpoint, the rf in signal is s witched off by the comparator. by measuring the transmitted power (tx) and the received power (rx), the device can dynamically change the drivers and pa signal to optimize performance. this application requires a logarithmic detector/controller, such as a nalog devices ad8317 or ad8362 . comparators and registers mux temp sensor high side current sense high side current sense t1 t2 v out a v out b v out c filter filter rf choke rf out ldmos rs1(+) rs2( + ) rs2(?) rs1(?) rs2(?) d1+ d2+ d2? d1? set-point 240mv i sense 1 overrange i sense 2 overrange gain control r sense r sense v dd ldmos rf out 12-bit adc v in 0 v in 1 v in 2 v in 3 12-bit dac 12-bit dac 12-bit dac 12-bit dac v out d gain control rf choke tx power monitor rx power monitor tx power rf cutoff rx power ad7294* rf in rf in *additional pins omitted for clarity. ref ref 05747-036 figure 59 . typical hpa monitor and control application
ad7294 rev. f | page 44 of 48 gain control o f p ower a mplifier in gain con trol mode, a setpoint voltage, proportional in db to the desired output power, is applied to a power detector such as the ad8362 . a sample of the output power from the power amplifier ( pa ), through a directiona l coupler and attenuator (or by other means), is fed to the input of the ad8362 . the v out is connecte d to the gain control termina l of the pa, see figure 60 . based on the defined relationship between vout and the rf input signal, the ad8362 adjust s the voltage on vout (vout is now an error amplifier output) until the level at the rf input corresponds to the applied vset. the a d7294 complet es a feedback loop that track s the output of the ad8362 and adjust s the vset input of the ad8362 accordingly. vout of the ad8362 is applied to the gain control terminal of the power amplifier. f or this output power control loop to be stable, a ground referenced capacitor must be connected to the clpf pin. this capacitor integrates the error signal (which is actually a cur rent) that is present when the loop is not balanced. in a system where a variable gain am plifier (vga) or variable voltage atte nuator (vva) feeds the power amp , only one ad8362 is required. in such a case , the gain on one of the parts (vva, pa) is fixed an d v out feeds the control input of the other. c5 1nf c7 0.1nf c6 0.1nf 1:4 t2 ad8362 ad7294 c lpf envelope of transmitted signal directional coupler a ttenu at or power amplifier rf in v in v out vout vset inlo inhi 05747-037 figure 60 . setpoint controller operation
ad7294 rev. f | page 45 of 48 layout and configura tion power supply bypassi ng and grounding for optimum performance, carefully consider the power supply and ground ret urn layout on any pcb where the ad7294 is used. the pcb containing the ad7294 should have separate analog and digital sect ions, each having its own area of the board. the ad7294 should be located in the analog section on any pcb. decouple t he power suppl y to the ad7294 to ground with 10 f and 0.1 f capacitors. place t he capacitors as physically close as possible to the device, with the 0.1 f capacitor ideally right up against the device. it is important that the 0.1 f capacitor ha ve low effective series resistance (esr) and low effective series inductance (esl ); common ceramic types of capacitors are suitable. the 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the 10 f capacitors are the tantalum bead type. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. shield c locks and other components with fast switching digital sig nals from other parts of the board by a digital ground. avoid crossover of digital and analog signals , if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the b oard. the best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side; however, this is not always possible with a 2 - layer board. la yout considerations for external temperature sensors power a mplifier boards can be electrically noisy environments , and care must be taken to protect the an alog inputs from noise, particu larly when measuring the very small voltages from a remote diode sens or. take t he following precautions: ? place the remote sensing diode as close as possible to the ad7294. if the worst noise sources are avoided, this distance can be 4 inches to 8 inches. ? route the d+ and d ? tracks close together, in parallel, with grounded guard tracks on each side. provide a ground plane under the tracks, if possible. ? use wide tracks to minimize inductance and reduce noise pickup. a 10 mil track minimum width and spacing is recommended , as shown in figure 61. agnd d1+ d1? agnd 0.25mm 0.25mm 0.25mm 0.25mm 0.25mm 0.25mm 0.25mm 05747-049 figure 61 . arrangement of signal tracks ? try to minimize the number of copper/solder joints because they can cause thermocouple effects. where copper/solder joints are used, make sure that they are in both the d x + and d x ? path and are at the same temperature. ? place a 10 pf capacitor between the base and emitter of the discrete diode , as close as possible to the diode. ? if the distance to the rem ote sensor is more than 20 cm , the use of twisted - pair cable is recommended. b ecause the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. when using long cables, the filter capacitor can be reduced or removed.
ad7294 rev. f | page 46 of 48 outline dimensions compliant t o jedec s t andards ms-026-abd 1.20 max 33 48 64 1 17 16 32 49 0.40 bsc lead pitch 0.75 0.60 0.45 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 0.23 0.18 0.13 top view (pins down) pin 1 view a 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarit y se a ting plane 0 min 7 3.5 0 0.15 0.05 view a ro ta ted 90 ccw 012108- a figure 62 . 64- lead thin plastic quad flat package [tqfp] (su- 64- 1) dimensions shown in millimeters compliant t o jedec s t andards mo-220-vlld-2 030509- a pin 1 indic at or top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 6.25 6.10 sq 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 6.50 ref sea ting plane 0.60 max 0.60 max pin 1 indic at or coplanarit y 0.08 0.05 max 0.02 nom 0.25 min exposed p ad (bot t om view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 63 . 56 - lead lead frame chip sc ale package [ lfcsp_vq] 8 mm 8 mm body, very thin quad (cp - 56 - 1) dimensions shown in millime ters
ad7294 rev. f | page 47 of 48 ordering guide model 1 temperature range package description package option AD7294BSUZ ?40c to +105c 64- lead thin plastic quad flat package [tqfp] su-64-1 AD7294BSUZrl ?40c to +105c 64- lead thin plastic quad flat package [tqfp] su-64-1 ad7294 bc pz ?40c to +105c 56- lead lead frame chip scale pac ka ge [lfcsp _ vq] cp-56-1 ad7294bcpzrl ?40c to +105c 56- lead lead frame chip scale package [lfcsp_ vq] cp-56-1 eval -ad7294ebz evaluation board 1 z = rohs compliant part.
ad7294 rev. f | page 48 of 48 notes i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2008C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05747-0-11/10(f)

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