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single channel, 12-/16-bit, serial input, current source and voltage output dacs ad5412/ad5422 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009-2010 analog devices, inc. all rights reserved. features 12-/16-bit resolution and monotonicity current output ranges: 4 ma to 20 ma, 0 ma to 20 ma, 0 ma to 24 ma 0.01 % fsr typical total unadjusted error (tue) 3 ppm/c output drift voltage output ranges: 0 v to 5 v, 0 v to 10 v, 5 v, 10 v 10% overrange 0.01 % fsr typical total unadjusted error (tue) 2 ppm/c output drift flexible serial digital interface on-chip output fault detection on-chip reference: 10 ppm/c maximum asynchronous clear function power supply range av dd : 10.8 v to 40 v av ss : ?26.4 v to ?3 v/0 v output loop compliance: av dd C 2.5 v temperature range: ?40c to +85c tssop and lfcsp packages applications process control actuator control plc general description the ad5412/ad5422 are low-cost, precision, fully integrated 12-/16-bit digital-to-analog converters (dac) offering a pro- grammable current source and programmable voltage output designed to meet the requirements of industrial process control applications. the output current range is programmable at 4 ma to 20 ma, 0 ma to 20 ma, or an overrange function of 0 ma to 24 ma. voltage output is provided from a separate pin that can be configured to provide 0 v to 5 v, 0 v to 10 v, 5 v, or 10 v output ranges; an overrange of 10% is available on all ranges. analog outputs are short and open-circuit protected and can drive capacitive loads of 1 f. the device operates with an av dd power supply range from 10.8 v to 40 v. output loop compliance is 0 v to av dd C 2.5 v. the flexible serial interface is spi- and microwire?- compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. the device also includes a power-on-reset function, ensuring that the device powers up in a known state. the part also includes an asynchronous clear pin (clear) that sets the outputs to zero-scale/midscale voltage output or the low end of the selected current range. the total output error is typically 0.01% in current mode and 0.01% in voltage mode. table 1. pin-compatible devices part number description ad5410 single channel, 12-bit, serial input current source dac ad5420 single channel, 16-bit, serial input current source dac
ad5412/ad5422 rev. c | page 2 of 40 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 ac performance characteristics ................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configurations and function descriptions ......................... 11 typical performance characteristics ........................................... 13 general ......................................................................................... 13 voltage output ............................................................................ 15 current output ........................................................................... 20 terminology .................................................................................... 24 theory of operation ...................................................................... 26 architecture ................................................................................. 26 serial interface ............................................................................ 27 power-on state ........................................................................... 28 data register ............................................................................... 29 control register .......................................................................... 29 reset register .............................................................................. 30 status register ............................................................................. 30 ad5412/ad5422 features ............................................................ 31 fault alert .................................................................................... 31 voltage output short circuit protection ................................ 31 voltage output overrange ........................................................ 31 voltage output force-sense ..................................................... 31 asynchronous clear (clear) ................................................. 31 internal reference ...................................................................... 31 external current setting resistor ............................................ 31 digital power supply .................................................................. 32 external boost function ........................................................... 32 external compensation capacitor ........................................... 32 digital slew rate control .......................................................... 32 i out filtering capacitors (lfcsp package) ............................. 33 applications information .............................................................. 35 driving inductive loads ............................................................ 35 transient voltage protection .................................................... 35 galvanically isolated interface ................................................. 35 microprocessor interfacing ....................................................... 35 layout guidelines....................................................................... 35 thermal and supply considerations ....................................... 36 industrial analog output module ........................................... 37 outline dimensions ....................................................................... 38 ordering guide .......................................................................... 39 revision history 3/10rev. b to rev. c changes to avss to gnd parameter in table 5 ........................ 10 2/10rev. a to rev. b changes to thermal and supply considerations section and table 25 ............................................................................................ 36 8/09rev. 0 to rev. a changes to table 2 ............................................................................ 4 changes to table 3 ............................................................................ 7 changes to introduction to table 4 ................................................ 8 changes to introduction to table 5 and to table 5 .................... 10 changes to pin configurations and function descriptions section, added figure 6, renumbered subsequent figures ..... 11 changes to theory of operation section.................................... 26 changes to architecture section .................................................. 26 changes to ad5412/ad5422 features section ......................... 31 added iout filtering capacitors (lfcsp package)section, including figure 69 to figure 72 and table 24 ........................... 33 changes to thermal and supply considerations section ......... 36 updated outline dimensions ....................................................... 38 changes to ordering guide .......................................................... 39 5/09revision 0: initial version
ad5412/ad5422 rev. c | page 3 of 40 functional block diagram input shift register and control logic power-on reset vref ad5412/ad5422 12-/16-bit dac 12/16 latch sclk sdin sdo refout refin range scaling gnd c comp ?v sense v out +v sense r set r set i out boost fault clear clear s elect dv cc select dv cc av ss av dd r2 06996-001 r3 figure 1.
ad5412/ad5422 rev. c | page 4 of 40 specifications av dd = 10.8 v to 26.4 v, av ss = ?26.4 v to ?3 v/0 v, av dd + |av ss | < 52.8 v, gnd = 0 v, refin = 5 v external; dv cc = 2.7 v to 5.5 v. v out : r load = 1 k, c l = 200 pf, i out : r load = 350 ; all specifications t min to t max , unless otherwise noted. table 2. parameter 1 min typ max unit test conditions/comments voltage output output voltage ranges 0 5 v 0 10 v ?5 +5 v ?10 +10 v accuracy output unloaded resolution 16 bits ad5422 12 bits ad5412 total unadjusted error (tue) b version ?0.1 +0.1 % fsr ?0.05 0.01 +0.05 % fsr t a = 25c a version ?0.3 +0.3 % fsr ?0.1 0.05 +0.1 % fsr t a = 25c relative accuracy (inl) 2 ?0.008 +0.008 % fsr ad5422 ?0.032 +0.032 % fsr ad5412 differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic bipolar zero error ?6 +6 mv bipolar output range ?1.5 0.2 +1.5 mv t a = 25c, bipolar output range bipolar zero error temperature coefficient (tc) 3 3 ppm fsr/c bipolar output range zero-scale error ?5 +5 mv ?3.5 0.3 +3.5 mv t a = 25c zero-scale error temperature coefficient (tc) 3 2 ppm fsr/c offset error ?4 +4 mv unipolar output range ?1.5 0.2 +1.5 mv t a = 25c, unipolar output range offset error temperature coefficient (tc) 3 2 ppm fsr/c unipolar output range gain error ?0.07 +0.07 % fsr ?0.05 0.004 +0.05 % fsr t a = 25c gain error temperature coefficient (tc) 3 1 ppm fsr/c full-scale error ?0.07 +0.07 % fsr ?0.05 0.001 +0.05 % fsr t a = 25c full-scale error temperature coefficient (tc) 3 1 ppm fsr/c output characteristics 3 headroom 0.5 0.8 v output unloaded output voltage drift vs. time 90 ppm fsr drift after 1000 hours, t a = 125c short-circuit current 20 ma load 1 k capacitive load stability t a = 25c r load = 20 nf r load = 1 k 5 nf r load = 1 f external compensation capacitor of 4 nf connected dc output impedance 0.3 power-on time 10 s
ad5412/ad5422 rev. c | page 5 of 40 parameter 1 min typ max unit test conditions/comments dc psrr 90 130 v/v 3 12 v/v output unloaded current output output current ranges 0 24 ma 0 20 ma 4 20 ma accuracy (internal r set ) resolution 16 bits ad5422 12 bits ad5412 total unadjusted error (tue) b version ?0.3 +0.3 % fsr ?0.13 0.08 +0.13 % fsr t a = 25c a version ?0.5 +0.5 % fsr ?0.3 0.15 +0.3 % fsr t a = 25c relative accuracy (inl) 4 ?0.024 +0.024 % fsr ad5422 ?0.032 +0.032 % fsr ad5412 differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.27 +0.27 % fsr ?0.12 0.08 +0.12 % fsr t a = 25c offset error temperature coefficient (tc) 3 16 ppm fsr/c gain error ?0.18 +0.18 % fsr ad5422 ?0.03 0.006 +0.03 % fsr ad5422, t a = 25c ?0.22 +0.22 % fsr ad5412 ?0.06 0.006 +0.06 % fsr ad5412, t a = 25c gain temperature coefficient (tc) 3 10 ppm fsr/c full-scale error ?0.2 +0.2 % fsr ?0.1 0.08 +0.1 % fsr t a = 25c full-scale temperature coefficient (tc) 3 6 ppm fsr/c accuracy (external r set ) resolution 16 bits ad5422 12 bits ad5412 total unadjusted error (tue) b version ?0.15 +0.15 % fsr ?0.06 0.01 +0.06 % fsr t a = 25c a version ?0.3 +0.3 % fsr ?0.1 0.02 +0.1 % fsr t a = 25c relative accuracy (inl) 4 ?0.012 +0.012 % fsr ad5422 ?0.032 +0.032 % fsr ad5412 differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.1 +0.1 % fsr ?0.03 0.006 +0.03 t a = 25c offset error temperature coefficient (tc) 3 3 a/c gain error ?0.08 +0.08 % fsr ?0.05 0.003 +0.05 % fsr t a = 25c gain temperature coefficient (tc) 3 4 ppm fsr/c full-scale error ?0.15 +0.15 % fsr ?0.06 0.01 +0.06 % fsr t a = 25c full-scale temperature coefficient (tc) 3 7 ppm fsr/c
ad5412/ad5422 rev. c | page 6 of 40 parameter 1 min typ max unit test conditions/comments output characteristics 3 current loop compliance voltage 0 av dd ? 2.5 v output current drift vs. time drift after 1000 hours, t a = 125c 50 ppm fsr internal r set 20 ppm fsr external r set resistive load 1200 inductive load 50 mh t a = 25 c dc psrr 1 a/v output impedance 50 m output current leakage when output is disabled 60 pa reference input/output reference input 3 reference input voltage 4.95 5 5.05 v for specified performance dc input impedance 27 40 k reference output output voltage 4.995 5 5.005 t a = 25c reference temperature coefficient (tc) 3 , 5 1.8 10 ppm/c output noise (0.1 hz to 10 hz) 3 10 v p-p noise spectral density 3 100 nv/hz at 10 khz output voltage drift vs. time 3 50 ppm drift after 1000 hours, t a = 125c capacitive load 3 600 nf load current 3 5 ma short-circuit current 3 7 ma load regulation 3 95 ppm/ma digital inputs 3 jedec compliant input high voltage, v ih 2 v input low voltage, v il 0.8 v input current ?1 +1 a per pin pin capacitance 10 pf per pin digital outputs 3 sdo output low voltage, v ol 0.4 v sinking 200 a output high voltage, v oh dv cc ? 0.5 v sourcing 200 a high impedance leakage current ?1 +1 a high impedance output capacitance 5 pf fault output low voltage, v ol 0.4 v 10 k pull-up resistor to dv cc output low voltage, v ol 0.6 v at 2.5 ma output high voltage, v oh 3.6 v 10 k pull-up resistor to dv cc power requirements av dd 10.8 40 v av ss ?26.4 0 v |av ss | + av dd 10.8 52.8 v dv cc input voltage 2.7 5.5 v internal supply disabled output voltage 4.5 v dv cc , which can be overdriven up to 5.5 v output load current 3 5 ma short-circuit current 3 20 ma
ad5412/ad5422 rev. c | page 7 of 40 parameter 1 min typ max unit test conditions/comments ai dd outputs unloaded 2.5 3 ma outputs disabled 3.4 4 ma current output enabled 3.9 4.4 ma voltage output enabled ai ss outputs unloaded 0.24 0.3 ma outputs disabled 0.5 0.6 ma current output enabled 1.1 1.4 ma voltage output enabled di cc 1 ma v ih = dv cc , v il = gnd power dissipation 128 mw av dd = 40 v, av ss = 0 v, outputs unloaded 120 mw av dd = +24 v, av ss = ?24 v, outputs unloaded 1 temperature range: ?40c to +85c; typical at +25c. 2 when the ad5412/ad5422 is powered with av ss = 0 v, inl for the 0 v to 5 v and 0 v to 10 v ranges is measured beginning from code 256 for the ad5422 and code 16 for the ad5412. 3 guaranteed by design and characterization; not production tested. 4 for 0 ma to 20 ma and 0 ma to 24 ma ranges, inl is measured beginning from co de 256 for the ad5422 and code 16 for the ad5412. 5 the on-chip reference is production tr immed and tested at 25c and 85c. it is characterized from ?40c to +85c. ac performance characteristics av dd = 10.8 v to 26.4 v, av ss = ?26.4 v to ?3 v/0 v, av dd + |av ss | < 52.8 v, gnd = 0 v, refin = +5 v external; dv cc = 2.7 v to 5.5 v. v out : r load = 1 k, c l = 200 pf, i out : r load = 350 ; all specifications t min to t max , unless otherwise noted. table 3. parameter 1 min typ max unit test conditions/comments dynamic performance voltage output output voltage settling time 25 s 10 v step to 0.03 % fsr 32 s 20 v step to 0.03 % fsr 18 s 5 v step to 0.03 % fsr 8 s 512 lsb step to 0.03 % fsr (16-bit lsb) slew rate 0.8 v/s power-on glitch energy 10 nv-sec digital-to-analog glitch energy 10 nv-sec glitch impulse peak amplitude 20 mv digital feedthrough 1 nv-sec output noise (0.1 hz to 10 hz bandwidth) 0.1 lsb p-p 16-bit lsb output noise (100 khz bandwidth) 200 v rms 1/f corner frequency 1 khz output noise spectral density 150 nv/hz meas ured at 10 khz, midscale output, 10 v range ac psrr ?75 db 200 mv 50 hz/60 hz sine wave superimposed on power supply voltage current output output current settling time 10 s 16 ma step to 0.1% fsr 40 s 16 ma step to 0.1% fsr, l = 1 mh ac psrr ?75 db 200 mv 50 hz/60 hz sine wave superimposed on power supply voltage 1 guaranteed by characterization, not production tested.
ad5412/ad5422 rev. c | page 8 of 40 timing characteristics av dd = 10.8 v to 26.4 v, av ss = ?26.4 v to ?3 v/0 v, av dd + |av ss | < 52.8v, gnd = 0 v, refin = +5 v external; dv cc = 2.7 v to 5.5 v. v out : r load = 1 k, c l = 200 pf, i out : r load = 300 ; all specifications t min to t max , unless otherwise noted. table 4. parameter 1 , 2 , 3 limit at t min , t max unit description write mode t 1 33 ns min sclk cycle time t 2 13 ns min sclk low time t 3 13 ns min sclk high time t 4 13 ns min latch delay time t 5 40 ns min latch high time t 5 5 s min latch high time (after a write to the control register) t 6 5 ns min data setup time t 7 5 ns min data hold time t 8 40 ns min latch low time t 9 20 ns min clear pulse width t 10 5 s max clear activation time readback mode t 11 90 ns min sclk cycle time t 12 40 ns min sclk low time t 13 40 ns min sclk high time t 14 13 ns min latch delay time t 15 40 ns min latch high time t 16 5 ns min data setup time t 17 5 ns min data hold time t 18 40 ns min latch low time t 19 35 ns max serial output delay time (c l sdo 4 = 15 pf) t 20 35 ns max latch rising edge to sdo tristate (c l sdo 4 = 15 pf) daisy-chain mode t 21 90 ns min sclk cycle time t 22 40 ns min sclk low time t 23 40 ns min sclk high time t 24 13 ns min latch delay time t 25 40 ns min latch high time t 26 5 ns min data setup time t 27 5 ns min data hold time t 28 40 ns min latch low time t 29 35 ns max serial output delay time (c l sdo 4 = 15 pf) 1 guaranteed by characterization; not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 c l sdo = capacitive load on sdo output.
ad5412/ad5422 rev. c | page 9 of 40 db23 sclk latch sdin 24 21 db0 t 2 t 3 t 1 t 4 t 8 t 7 t 6 t 9 t 10 t 5 clear i out /v out 06996-002 figure 2. write mode timing diagram db23 sclk latch sdin 24 21 db0 sdo db23 selected register data clocked out nop condition undefined data input word specifies register to be read 12 24 db0 db15 db0 xxxx 89 23 22 first 8 bits are don?t care bits t 20 t 19 t 17 t 12 t 13 t 14 t 11 t 15 t 16 t 18 06996-003 figure 3. readback mode timing diagram db23 db23 sclk sdin 24 21 db0 db0 db0 sdo db23 input word for dac n input word for dac n ? 1 undefined input word for dac n 25 48 26 latch db23 db0 t 20 t 28 t 27 t 26 t 29 t 22 t 23 t 21 t 24 t 25 06996-004 figure 4. daisy-chain mode timing diagram
ad5412/ad5422 rev. c | page 10 of 40 absolute maximum ratings t a = 25c, unless otherwise noted. transient currents of up to 80 ma do not cause scr latch-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 5. parameter rating av dd to gnd ?0.3 v to +48 v av ss to gnd +0.3 v to ?28 v av dd to av ss ?0.3 v to +60 v dv cc to gnd ?0.3 v to +7 v digital inputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) refin/refout to gnd ?0.3 v to +7 v v out to gnd av ss to av dd i out to gnd ?0.3 v to av dd operating temperature range (t a ) industrial 1 ?40c to +85c storage temperature range ?65c to +150c junction temperature (t j max) 125c 24-lead tssop package ja thermal impedance 42c/w 40-lead lfcsp package ja thermal impedance 28c/w power dissipation (t j max C t a )/ ja lead temperature jedec industry standard soldering j-std-020 esd (human body model) 2 kv esd caution 1 power dissipated on chip must be derated to keep the junction temperature below 125c, assuming that the maximum power dissipatio n condition is sourcing 24 ma into gnd from i out with a 4 ma on-chip current.
ad5412/ad5422 rev. c | page 11 of 40 pin configurations and function descriptions 1 2 3 4 5 6 7 8 9 10 12 11 dv cc fault gnd latch clear clear select av ss sclk sdin gnd gnd sdo 20 21 22 23 24 19 18 17 16 15 14 13 ?v sense +v sense v out nc notes 1. nc = no connec t 2. the paddle can be connected to 0v if the output voltage range is unipolar. the paddle can be left electrically unconnected provided that a supply connection is made at the av ss pin. it is recommended that the paddle be thermally connected to a copper plane for enhanced therm a l performance. i out boost c comp dv cc select r set refout refin av dd ad5412/ ad5422 top view (not to scale) 06996-005 notes 1. nc = no conne c t. 2 . the exposed paddle can be connected to 0v if the output voltage range is unipolar. the exposed paddle can be left electrically unconnected provided that a supply connection is made at the av ss pin. it is recommended that the paddle be thermally connected to a copper plane for enhanced therm a l performance. pin 1 indicator 1 nc 2 fault 3 gnd 4 c lear select 5 clear 6 latch 7 sclk 8 sdin 9 sdo 10 nc 23 dv cc select 24 c comp 25 nc 26 i out 27 boost 28 cap1 29 cap2 30 nc 22 nc 21 nc 11 n c 12 gnd 13 gnd 15 gnd 17 r efout 16 r set 18 refin 19 nc 20 nc 14 av ss 33 +v se nse 34 ?v sense 35 n c 36 av dd 37 av ss 38 nc 39 dv cc 40 nc 32 v out 31 nc top view (not to scale) ad5412/ad5422 06996-006 figure 5. tssop pin configuration figure 6. lfcsp pin configuration table 6. pin function descriptions pin no. mnemonic description tssop lfcsp 1 14, 37 av ss negative analog supply pin. voltage ranges from C3 v to C24 v. this pin can be connected to 0 v if the output voltage range is unipolar. 2 39 dv cc digital supply pin. voltage ranges from 2.7 v to 5.5 v. 3 2 fault fault alert. this pin is asserted low when an open circuit is detected in current mode or an overtemperature is detected. open drain outp ut must be connected to a pull-up resistor. 4, 12 3, 15 gnd these pins must be connected to 0 v. 18 1, 10, 11, 19, 20, 21, 22, 25, 30, 31, 35, 38, 40 nc no connection. do not connect to these pins. 5 4 clear select selects the voltage output clear value, either zero-scale or midscale code (see table 21 ). 6 5 clear active high input. asserting this pin sets the current output to the bottom of the selected range or sets the voltage output to the user selected value (zero-scale or midscale). 7 6 latch positive edge sensitive latch. a rising latch edge parallel loads the input shift register data into the dac register, also updating the output. 8 7 sclk serial clock input. data is cloc ked into the shift register on the rising edge of sclk. this operates at clock speeds of up to 30 mhz. 9 8 sdin serial data input. data must be valid on the rising edge of sclk. 10 9 sdo serial data output. used to cl ock data from the serial register in daisy-chain or readback mode. data is valid on the rising edge of sclk (see figure 3 and figure 4 ). 11 12, 13 gnd ground reference pin. 13 16 r set an external, precision, low drift 15 k current setting resistor can be connected to this pin to improve the i out temperature drift performance. see the ad5412/ad5422 features section. 14 17 refout internal reference voltage output. refout = 5 v 2 mv. 15 18 refin external reference voltage input. reference input range is 4 v to 5 v. refin = 5 v for a specified performance.
ad5412/ad5422 rev. c | page 12 of 40 pin no. mnemonic description tssop lfcsp 16 23 dv cc select when connected to gnd, this pin disables the internal supply, and an external supply must be connected to the dv cc pin. leave this pin unconnected to enable the internal supply. see the ad5412/ad5422 features section. 17 24 c comp optional compensation capacitor connectio n for the voltage output buffer. connecting a 4 nf capacitor between this pin and the v out pin allows the voltage output to drive up to 1 f. it should be noted that the addition of this capacitor reduces the bandwidth of the output amplifier, increasing the settling time. 19 26 i out current output pin. 20 27 boost optional external transistor connection. connecting an external transistor reduces the power dissipated in the ad5412/ad5422. see the ad5412/ad5422 features section. n/a 28, 29 cap1, cap2 connection for optional output filtering capacitor. see the ad5412/ad5422 features section. 21 32 v out buffered analog output voltage. the output amplifier is capable of directly driving a 1 k, 2000 pf load. 22 33 +v sense sense connection for the positive voltage output load connection. 23 34 ?v sense sense connection for the negative voltage output load connection. 24 36 av dd positive analog supply pin. voltage ranges from 10.8 v to 60 v. 25 (epad) 41 (epad) exposed paddle negative analog supply pin. voltage ranges from C3 v to C24 v. this paddle can be connected to 0 v if the output voltage range is unipolar. the paddle can be left electrically unconnected provided that a supply connection is made at the av ss pin. it is recommended that the paddle be thermally connected to a copper plane for enhanced thermal performance.
ad5412/ad5422 rev. c | page 13 of 40 typical performance characteristics general 0 100 200 300 400 500 600 700 800 900 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 di cc ( a ) logic voltage (v) dv cc = 5v t a = 25c dv cc = 3v 0 6996-022 figure 7. di cc vs. logic input voltage ?2 ?1 0 1 2 3 4 5 10 12 14 16 18 20 22 24 26 28 ai dd /ai ss (ma) av dd /|av ss | (v) ai dd ai ss t a = 25c v out = 0v output unloaded 06996-108 figure 8. ai dd /ai ss vs. av dd /|av ss | 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 10 15 20 25 30 35 40 a i dd ( m a ) av dd (v) t a = 25c i out = 0ma 06996-023 figure 9. ai dd vs. av dd 0 1 2 3 4 5 6 7 8 9 ?21 ?19 ?17 ?15 ?13 ?11 ?9 ?7 ?5 ?3 ?1 1 dv cc output v oltage (v) load current (ma) t a = 25c 0 6996-024 figure 10. dv cc output voltage vs. load current ch1 2.00v ch3 5.00v m200s ch3 2.1v 1 3 av dd reference output 06996-025 figure 11. refout turn-on transient ch1 2v m2.00s line 1.8v 1 0 6996-026 figure 12. refout output noise (0 .1 hz to 10 hz bandwidth)
ad5412/ad5422 rev. c | page 14 of 40 ch1 20v m2.00s line 0v 1 0 6996-027 figure 13. refout output no ise (100 khz bandwidth) 4.997 ?40 ?20 0 20 temperature (c) 40 60 80 4.998 4.999 5.000 5.001 5.002 5.003 reference output voltage (v) 50 devices shown av dd = 24v 06996-029 figure 14. reference voltage vs. temperature 0 5 10 15 20 25 30 35 40 45 1 0 2345678910 population ( % ) temperature coefficient (ppm/c) av dd = 24v 0 6996-030 figure 15. reference temperature coefficient histogram 4.9955 4.9960 4.9965 4.9970 4.9975 4.9980 4.9985 4.9990 4.9995 5.0000 5.0005 0123456789 reference output voltage (v) load current (ma) t a = 25c av dd = 24v 0 6996-031 figure 16. reference voltage vs. load current
ad5412/ad5422 rev. c | page 15 of 40 voltage output ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0.0005 0 0.0010 0.0015 0.0020 0.0025 0 10,000 20,000 30,000 40,000 50,000 60,000 inl error (% fsr) code 06996-117 10v range 5v range +5v range +10v range av dd = +24v av ss = ?24v t a = 25c figure 17. integral nonlinearity error vs. dac code, dual supply ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 0 10,000 20,000 30,000 40,000 50,000 60,000 inl error (% fsr) code +5v range +10v range av dd = 24v av ss = 0v t a = 25c 06996-118 figure 18. integral nonlinearity error vs. dac code , single supply ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0 0.4 0.6 0.8 1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 dnl error (lsb) code 06996-119 10v range 5v range +10v range +5v range av dd = +24v av ss = ?24v t a = 25c figure 19. differential nonlinearity error vs. dac code, dual supply ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 dnl error (lsb) code av dd = 24v av ss = 0v t a = 25c 06996-120 +5v range +10v range figure 20. differential nonlinearity error vs. dac code, single supply ?0.009 ?0.007 ?0.003 ?0.005 ?0.001 0.001 0.003 0.005 0 10,000 20,000 30,000 40,000 50,000 60,000 total unadjsuted error (% fsr) code 06996-221 10v range 5v range +5v range +10v range av dd = +24v av ss = ?24v t a = 25c figure 21. total unadjusted error vs. dac code, dual supply ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 0.030 0 10,000 20,000 30,000 40,000 50,000 60,000 total unadjusted error (% fsr) code av dd = 24v av ss = 0v t a = 25c 06996-122 +5v range +10v range figure 22. total unadjusted error vs. dac code, single supply
ad5412/ad5422 rev. c | page 16 of 40 ?0.0015 ?0.0010 ?0.0005 0.0005 0 0.0010 0.0015 ?40 ?20 0 20 40 60 80 inl error (% fsr) temperature (c) +5v range max inl +10v range max inl 5v range max inl 10v range max inl +5v range min inl +10v range min inl 5v range min inl 10v range min inl 06996-121 av dd = +24v av ss = ?24v figure 23. integral nonlinearity error vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) av dd = +24v av ss = ?24v all ranges 06996-124 figure 24. differential nonlinearity error vs. temperature ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 ?40 ?20 0 20 40 60 80 total unadjsuted error (% fsr) temperature (c) av dd = +24v av ss = ?24v output unloaded +5v range +10v range 5v range 10v range 0 6996-101 figure 25. total unadjusted error vs. temperature ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0.004 0.006 0.008 0.010 0.012 ?40 ?20 0 20 40 60 80 full-scale error (% fsr) temperature (c) av dd = +24v av ss = ?24v output unloaded +5v range +10v range 5v range 10v range 06996-100 figure 26. full-scale error vs. temperature ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?40?20 0 20406080 offset error ( m v) temperature (c) +5v range +10v range av dd = +24v av ss = ?24v output unloaded 0 6996-129 figure 27. offset error vs. temperature ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 ?40?20 0 20406080 bipolar zero error ( m v) temperature (c) +5v range +10v range av dd =+24v av ss = ?24v output unloaded 0 6996-130 figure 28. bipolar zero error vs. temperature
ad5412/ad5422 rev. c | page 17 of 40 ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0.004 0.006 0.008 0.010 0.012 0.014 ?40 ?20 0 20 40 60 80 gain error (% fsr) temperature (c) +5v range +10v range 5v range 10v range avdd = +24v avss = ?24v output unloaded 0 6996-131 figure 29. gain error vs. temperature ?1.2 ?0.7 ?0.2 0.3 0.8 1.3 ?40 ?20 0 20 40 60 80 zero-scale error (mv) temperature (c) av dd =+24v av ss = ?24v output unloaded +5v range +10v range 5v range 10v range 06996-102 figure 30. zero-scale error vs. temperature ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 10 12 14 16 18 20 22 24 26 28 inl error (% fsr) av dd /|av ss | (v) t a =25c 10v range 06996-231 figure 31. integral nonlinearity error vs. av dd /|av ss | ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0.2 0 0.4 0.6 0.8 1.0 10 12 14 16 18 20 22 24 26 28 dnl error (lsb) av dd /|av ss | (v) t a = 25c 10v range 06996-232 figure 32. differential nonlinearity error vs. av dd /|av ss | 0 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 0.0040 0.0045 0.0050 10 12 14 16 18 20 22 24 26 28 total unadjusted error (% fsr) av dd /|av ss |(v) t a = 25c 10v range 06996-033 figure 33. total unadjusted error vs. av dd /|av ss | ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 ?20 ?15 ?10 ?5 0 5 10 15 20 change in output voltage (v) source/sink current (ma) av dd = +15v t a =25c 10v range av ss = ?15v 06996-132 figure 34. source and sink capability of output amplifier, full-scale code loaded
ad5412/ad5422 rev. c | page 18 of 40 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 ?20 ?15 ?10 ?5 0 5 10 15 20 change in output voltage (v) source/sink current (ma) av dd = +15v av ss = ?15v t a = 25c 10v range 06996-035 figure 35. source and sink capability of output amplifier, zero-scale loaded ?12 ?8 ?4 0 4 8 12 ?10 ?5 0 5 10 15 20 25 30 output voltage (v) time (s) 10v range t a = 25c output unloaded 06996-136 av ss = ?24v av dd = +24v figure 36. full-scale positive step ?12 ?8 ?4 0 4 8 12 ?10 ?5 0 5 10 15 20 25 30 output voltage (v) time (s) av ss = ?24v 10v range t a = 25c output unloaded av dd = +24v 06996-137 figure 37. full-scale negative step ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 ?1 1 3 5 7 9 11 13 15 output voltage (mv) time (s) 0x8000 to 0x7fff 0x7fff to 0x8000 av dd = +24v t a = 25c 10v range av ss = ?24v 06996-036 figure 38. digital-to-analog glitch
ad5412/ad5422 rev. c | page 19 of 40 0 5 10 15 20 25 30 35 0 2 4 6 8 10 12 14 16 18 20 v out (mv) time (s) av dd =+15v t a = 25c av ss = ?15v 06996-039 06996-037 ch1 5.0v m 5.00ms line 1.8v 1 av dd = +24v av ss = ?24v t a = 25c figure 39. peak-to-peak noise (0.1 hz to 10 hz bandwidth) figure 41. v out vs. time on power-up 06996-038 ch1 50.0v m 5.00ms line 0v 1 av dd = +24v av ss = ?24v t a = 25c figure 40. peak-to-peak noise (100 khz bandwidth)
ad5412/ad5422 rev. c | page 20 of 40 current output ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0 10,000 20,000 30,000 40,000 50,000 60,000 inl error (% fsr) code av dd = 24v av ss = ?24v/0v t a = 25c r load = 250 ? 06996-106 external r set internal r set external r set , boost transistor internal r set , boost transistor figure 42. integral nonlinearity vs. code ?1.0 ?0.8 ?0.6 ?0.2 ?0.4 0 0.2 0.4 0.6 0.8 1.0 0 10,000 20,000 30,000 40,000 50,000 60,000 dnl error (lsb) code 06996-007 av dd = 24v av ss = ?24v/0v t a = 25c r load = 250 ? external r set internal r set external r set , boost transistor internal r set , boost transistor figure 43. differential nonlinearity vs. code ?0.15 ?0.13 ?0.11 ?0.09 ?0.07 ?0.05 ?0.03 0.01 0.05 ?0.01 0.03 0 10,000 20,000 30,000 40,000 50,000 60,000 total unadjusted error (% fsr) code external r set internal r set external r set , boost transistor internal r set , boost transistor 06996-008 av dd = 24v av ss = ?24v/0v t a = 25c r load = 250 ? figure 44. total unadjusted error vs. code ?0.010 ?0.008 ?0.006 ?0.004 0 ?0.002 0.002 0.004 ?40 ?20 0 20 40 60 80 inl error (% fsr) temperature (c) 0ma to 24ma range av dd = 24v av ss = ?24v/0v 0 6996-009 figure 45. integral nonlinearity vs. temperature, internal r set ?0.003 ?0.002 ?0.001 0 0.002 0.001 0.003 ?40 ?20 0 20 40 60 80 inl error (% fsr) temperature (c) 0ma to 24ma range av dd = 24v av ss = ?24v/0v 0 6996-109 figure 46. integral nonlinearity vs. temperature, external r set ?1.0 ?0.8 ?0.6 ?0.4 0 ?0.2 0.4 0.8 0.2 0.6 1.0 ?40 ?20 0 20 40 60 80 dnl error (lsb) temperature (c) av dd = 24v av ss = ?24v/0v all ranges internal and external r set 0 6996-010 figure 47. differential nonlinearity vs. temperature
ad5412/ad5422 rev. c | page 21 of 40 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 ?40 ?20 0 20 40 60 80 total unadjusted error (% fsr) temperature (c) av dd = 24v av ss = ?24v/0v 4ma to 20ma internal r set 0ma to 20ma internal r set 0ma to 24ma internal r set 4ma to 20ma external r set 0ma to 20ma external r set 0ma to 24ma external r set 06996-013 figure 48. total unadjusted error vs. temperature ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 ?40?20 0 20406080 offset error (% fsr) temperature (c) 4ma to 20ma internal r set 0ma to 20ma internal r set 0ma to 24ma internal r set 4ma to 20ma external r set 0ma to 20ma external r set 0ma to 24ma external r set av dd = 24v av ss = ?24v/0v 06996-017 figure 49. offset error vs. temperature ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 ?40 ?20 0 20 40 60 80 gain error (% fsr) temperature (c) av dd = 24v av ss = ?24v/0v 4ma to 20ma internal r set 0ma to 20ma internal r set 0ma to 24ma internal r set 4ma to 20ma external r set 0ma to 20ma external r set 0ma to 24ma external r set 06996-018 figure 50. gain error vs. temperature ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 10 15 20 25 30 35 40 inl error (% fsr) av dd (v) t a = 25c 0ma to 24ma range av ss = 0v 0 6996-011 figure 51. integral nonlinearity error vs. av dd , external r set ?0.015 ?0.020 ?0.010 ?0.005 0.005 0.015 0 0.010 0.020 10 15 20 25 30 35 40 inl error (% fsr) av dd (v) t a = 25c 0ma to 24ma range av ss = 0v 06996-014 figure 52. integral nonlinearity error vs. av dd , internal r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 10 15 20 25 30 35 40 dnl erro r (lsb) av dd (v) t a = 25c 0ma to 24ma rang av ss = 0v 0 6996-012 figure 53. differential nonlinearity error vs. av dd , external r set
ad5412/ad5422 rev. c | page 22 of 40 ?0.8 ?1.0 ?0.6 ?0.4 0 0.8 ?0.2 0.4 0.6 0.2 1.0 10 15 20 25 30 35 40 dnl error (lsb) av dd (v) t a = 25c 0ma to 24ma range av ss = 0v 0 6996-015 figure 54. differential nonlinearity error vs. av dd , internal r set ?0.010 ?0.015 ?0.005 0 0.010 0.005 0.020 0.015 0.025 10 15 20 25 30 35 40 total unadjusted error (% fsr) av dd (v) t a = 25c 0ma to 24ma range av ss = 0v 0 6996-016 figure 55. total unadjusted error vs. av dd , external r set ?0.15 ?0.13 ?0.11 ?0.09 ?0.07 ?0.05 ?0.03 ?0.01 0.01 0.03 0.05 10 15 20 25 30 35 40 total unadjusted error (% fsr) av dd (v) 06996-032 t a = 25c 0ma to 24ma range av ss = 0v figure 56. total unadjusted error vs. av dd , internal r set 0 0.5 1.0 1.5 2.0 2.5 ?40 ?20 0 20 40 60 80 headroom voltage (v) temperature (c) av dd = 15v av ss = 0v i out = 24ma r load = 500 ? 06996-019 figure 57. compliance voltage headroom vs. temperature 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 100 200 300 400 500 600 output cur r ent ( a ) time (s) av dd = 24v av ss = 0v t a = 25c r load = 250 ? 06996-020 figure 58. output current vs. time on power-up ?50 ?40 ?30 ?20 ?10 0 10 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 output current (a) time (s) av dd = 24v av ss = 0v t a = 25c r load = 250 ? 06996-021 figure 59. output current vs . time on output enable
ad5412/ad5422 rev. c | page 23 of 40 ?10 0 10 20 30 40 50 60 70 0 5 10 15 20 25 30 35 40 45 leakage current (pa) compliance voltage (v) t a = 25c av dd = 40v av ss = 0v output disabled 06996-028 figure 60. output leakage current vs. compliance voltage ?30 ?20 ?10 0 10 20 30 02468101214161820 output current (a) time (s) av dd = 24v av ss = 0v t a = 25c r load = 250 ? 0x8000 to 0x7fff 0x7fff to 0x8000 06996-049 figure 61. digital to analog glitch 0 5 10 15 20 25 ?1012345678 output current (ma) time (s) t a = 25c av dd = 24v av ss = 0v r load = 300 ? 06996-134 figure 62. 4 ma to 20 ma output current step
ad5412/ad5422 rev. c | page 24 of 40 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or inl, is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 17 . differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monoton- icity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 19 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5412/ad5 422 are monotonic over their full operating temperature range. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos comple- ment coding). a plot of bipolar zero error vs. temperature can be seen in figure 28 . bipolar zero temperature coefficient (tc) bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register. ideally, the output should be full-scale ? 1 lsb. full-scale error is expressed in percent of full-scale range (% fsr). negative full-scale error/zero-scale error negative full-scale error is the error in the dac output voltage when 0x0000 (straight binary coding) or 0x8000 (twos comple- ment coding) is loaded to the dac register. ideally, the output voltage should be negative full-scale ? 1 lsb. a plot of zero- scale error vs. temperature can be seen in figure 30 . zero-scale temperature coefficient (tc) zero-scale tc is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage- output dac is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is expressed in v/s. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed in % fsr. a plot of gain error vs. temperature can be seen in figure 29 . gain error temperature coefficient (tc) gain error tc is a measure of the change in gain error with changes in temperature. gain error tc is expressed in ppm fsr/c. tot a l un a dju s te d e r ror ( t u e ) tue is a measure of the output error taking all the various errors into account, namely inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed in % fsr. current loop voltage compliance the maximum voltage at the i out pin for which the output current is equal to the programmed value. power-on glitch energy power-on glitch energy is the impulse injected into the analog output when the ad5412/ad5422 is powered on. it is specified as the area of the glitch in nv-sec. see figure 41 and figure 58 . digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state, but the output voltage remains constant. it is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 38 and figure 61 . glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in millivolt and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 38 and figure 61 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus.
ad5412/ad5422 rev. c | page 25 of 40 power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the power supply voltage. volt age reference tc voltage reference tc is a measure of the change in the reference output voltage with a change in temperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given temperature range expressed in ppm/c, as follows: 6 10 ? ? ? ? ? ? ? = temprange v vv tc refnom refmin refmax where: v refmax is the maximum reference output measured over the total temperature range. v refmin is the minimum reference output measured over the total temperature range. v refnom is the nominal reference output voltage, 5 v. tempr ang e is the specified temperature range, ?40c to +85c. load regulation load regulation is the change in reference output voltage due to a specified change in load current. it is expressed in ppm/ma.
ad5412/ad5422 rev. c | page 26 of 40 theory of operation the ad5412/ad5422 are precision digital-to-current loop and voltage output converters designed to meet the requirements of industrial process control applications. they provide a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. current ranges are 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma; the voltage ranges available are 0 v to 5 v, 5 v, 0 v to 10 v, and 10 v; a 10% overrange is available on all voltage output ranges. the current and voltage outputs are available on separate pins, and only one is active at any time. the desired output configuration is user selectable via the control register. architecture the dac core architecture of the ad5412/ad5422 consists of two matched dac sections. a simplified circuit diagram is shown in figure 63 . the four msbs of the 12-/16-bit data-word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either ground or the reference buffer output. the remaining 8/12 bits of the data- word drive the s0 to s7/s11 switches of an 8-/12-bit voltage mode r-2r ladder network. 8-12 bit r-2r ladder four msbs decoded into 15 equal segments 2r 2r s0 s1 s7/s11 e1 e2 e15 v out 2r 2r 2r 2r 2r 06996-057 figure 63. dac ladder structure the voltage output from the dac core is either converted to a current (see figure 64 ) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see figure 65 ). the current and voltage are output on separate pins and cannot be output simultaneously. 12-/16-bit dac a1 a v dd i out a2 t1 t2 r set r2 r3 06996-058 figure 64. voltage-to-curre nt conversion circuitry 06996-059 12-/16-bit dac range scaling v cm refin +v sense v out ?v sense r1 r load ?1v to +3v ad5412/ad5422 figure 65. voltage output voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 1 k in parallel with 1 f (with an external compen- sation capacitor) to gnd. the source and sink capabilities of the output amplifier can be seen in figure 35 . the slew rate is 1 v/s with a full-scale settling time of 25 s maximum (10 v step). figure 65 shows the voltage output driving a load, r load , on top of a common-mode voltage (v cm ) of ?1 v to +3 v. in output module applications where a cable could possibly become disconnected from +v sense , resulting in the amplifier loop being broken and possibly resulting in large destructive voltages on v out , include an optional resistor (r1) between +v sense and v out , as shown in figure 65 , of a value between 2 k and 5 k to ensure the amplifier loop is kept closed. if remote sensing of the load is not required, connect +v sense directly to v out and connect ?v sense directly to gnd. when changing ranges on the voltage output, a glitch may occur. for this reason, it is recommended that the output be disabled by setting the outen bit of the control register to logic low before changing the output voltage range; this prevents a glitch from occurring. driving large capacitive loads the voltage output amplifier is capable of driving capacitive loads of up to 1 f with the addition of a nonpolarized 4 nf compensation capacitor between the c comp and v out pins. without the compensation capacitor, up to 20 nf capacitive loads can be driven.
ad5412/ad5422 rev. c | page 27 of 40 serial interface the ad5412/ad5422 are controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz. it is compatible with spi, qspi?, microwire, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk. data is clocked in on the rising edge of sclk. the input register consists of eight address bits and 16 data bits, as shown in table 7 . the 24-bit word is uncondi- tionally latched on the rising edge of the latch pin. data continues to be clocked in irrespective of the state of latch. on the rising edge of latch, the data that is present in the input register is latched; in other words, the last 24 bits to be clocked in before the rising edge of latch is the data that is latched. the timing diagram for this operation is shown in figure 2 . table 7. input shift register format msb lsb d23 to d16 d15 to d0 address byte data-word table 8. address byte functions address word function 00000000 no operation (nop) 00000001 data register 00000010 readback register value as per read address (see table 9 ) 01010101 control register 01010110 reset register standalone operation the serial interface works with both a continuous and noncon- tinuous serial clock. a continuous sclk source can be used only if latch is taken high after the correct number of data bits have been clocked in. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and latch must be taken high after the final clock to latch the data. the rising edge of sclk that clocks in the msb of the data-word marks the beginning of the write cycle. exactly 24 rising clock edges must be applied to sclk before latch is brought high. if latch is brought high before the 24 th rising sclk edge, the data written is invalid. if more than 24 rising sclk edges are applied before latch is brought high, the input data is also invalid. controller data in data out serial clock control out ad5412/ ad5422 1 sdo sdin sclk latch ad5412/ ad5422 1 sdo sdin sclk latch ad5412/ ad5422 1 sdo sdin sclk latch 1 additional pins omitted for clarity. 06996-060 figure 66. daisy chaining the ad5412/ad5422 daisy-chain operation for systems that contain several devices, the sdo pin can be used to daisy-chain the devices together as shown in figure 66 . this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. daisy-chain mode is enabled by setting the dcen bit of the control register to 1. the first rising edge of sclk that clocks in the msb of the data-word marks the beginning of the write cycle. sclk is continuously applied to the input shift register. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is valid on the rising edge of sclk, having been clocked out on the previous falling sclk edge. by connecting the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n, where n is the total number of ad5412/ ad5422 devices in the chain. when the serial transfer to all devices is complete, latch is taken high. this latches the input data in each device in the daisy chain. the serial clock can be a continuous or a gated clock. a continuous sclk source can be used only if latch is taken high after the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and latch must be taken high after the final clock to latch the data (see figure 4 for a timing diagram).
ad5412/ad5422 rev. c | page 28 of 40 readback operation re adback mode is invoked by setting the address byte and read address when writing to the input register (see table 9 and table 11 ). the next write to the ad5412/ad5422 should be a nop command, which clocks out the data from the previously addressed register as shown in figure 3 . by default the sdo pin is disabled after having addressed the ad5412/ad5422 for a read operation; a rising edge on latch enables the sdo pin in anticipation of data being clocked out. after the data has been clocked out on sdo, a rising edge on latch disables (tristate) the sdo pin. to read back the data register, for example, implement the following sequence: 1. write 0x020001 to the input register. this configures the part for read mode with the data register selected. 2. follow this with a second write: a nop condition, which is 0x000000. during this write, the data from the register is clocked out on the sdo line. table 9. read address decoding read address function 00 read status register 01 read data register 10 read control register power-on state during power-on of the ad5412/ad5422, the power-on-reset circuit ensures that all registers are loaded with zero-code. as such, both outputs are disabled; that is, the v out and i out pins are in tristate. the +v sense pin is internally connected to ground through a 40 k resistor. therefore, if the v out and +v sense pins are connected together, v out is effectively clamped to ground through a 40 k resistor. also upon power-on, internal calibration registers are read, and the data is applied to internal calibration circuitry. for a reliable read operation, there must be sufficient voltage on the av dd supply when the read event is triggered by the dv cc power supply powering up. powering up the dv cc supply after the av dd supply ensures this. if dv cc and av dd are powered up simultaneously or the internal dv cc is enabled, the supplies should be powered up at a rate greater than, typically, 500 v/sec or 24 v/50 ms. if this cannot be achieved, issue a reset command to the ad5412/ad5422 after power-on; this performs a power-on-reset event, reading the calibration registers and ensures specified operation of the ad5412/ad5422. voltage output for a unipolar voltage output range, the output voltage can be expressed as ? ? ? ? ? ? = 2 for a bipolar voltage output range, the output voltage can be expressed as 2 2 refin n refin out vgain d gain vv ? ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac. v refin is the reference voltage applied at the refin pin. gain is an internal gain whose value depends on the output range selected by the user as shown in tabl e 10 . table 10. internal gain value output range gain value +5 v 1 +10 v 2 5 v 2 10 v 4 current output for the 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma current output ranges, the output current is respectively expressed as d i n out ? ? ? ? ? ? = 2 ma20 d i n out ? ? ? ? ? ? = 2 ma24 ma4 2 ma16 + ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac. table 11. input shift register contents for a read operation msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d2 d1 d0 0 0 0 0 0 0 1 0 x 1 read address 1 x = dont care.
ad5412/ad5422 rev. c | page 29 of 40 data register the data register is addressed by setting the address word of the input shift register to 0x01. the data to be written to the d ata register is entered in the d15 to d4 positions for the ad5412 and the d15 to d0 positions for the ad5422, as shown in table 12 and table 13 . table 12. programming the ad5412 data register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 12-bit data-word x x x x table 13. programming the ad5422 data register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 16-bit data-word control register the control register is addressed by setting the address word of the input shift register to 0x55. the data to be written to th e control register is entered in the d15 to d0 positions, as shown in tabl e 14 . the control register functions are shown in table 15 . table 14. programming the control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clrsel ovrrng rext outen sr clock sr step sren dcen r2 r1 r0 table 15. control register functions option description clrsel see table 21 for a description of the clrsel operation. ovrrng setting this bit increases the voltage output range by 10% (see the ad5412/ad5422 features section). rext setting this bit selects the exte rnal current setting resistor (see the ad5412/ad5422 features section). outen output enable. this bit must be set to enable the outputs. the range bits select which output is functional. sr clock digital slew rate control (see the ad5412/ad5422 features section). sr step digital slew rate control (see the ad5412/ad5422 features section). sren digital slew rate control enable. dcen daisy chain enable. r2, r1, r0 output range select (see table 16 ). table 16. output range options r2 r1 r0 output range selected 0 0 0 0 v to 5 v voltage range 0 0 1 0 v to 10 v voltage range 0 1 0 5 v voltage range 0 1 1 10 v voltage range 1 0 1 4 ma to 20 ma current range 1 1 0 0 ma to 20 ma current range 1 1 1 0 ma to 24 ma current range
ad5412/ad5422 rev. c | page 30 of 40 reset register the reset register is addressed by setting the address word of the input shift register to 0x56. the data to be written to the reset register is entered in the d0 position as shown in table 1 7 . the reset register options are shown in table 17 and table 18 . table 17. programming the reset register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved reset table 18. reset register functions option description reset setting this bit performs a reset operation, restoring the ad5412/ad5422 to its power-on state. status register the status register is a read-only register. the status register functionality is shown in tabl e 19 and table 20 . table 19. decoding the status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reserved i out fault slew active over temp table 20. status register functions option description i out fault this bit is set if a fault is detected on the i out pin. slew active this bit is set while the output value is slewing (slew rate control enabled). over temp this bit is set if the ad5412/ad5422 core temperature exceeds ~150c.
ad5412/ad5422 rev. c | page 31 of 40 ad5412/ad5422 features fault alert the ad5412/ad5422 are equipped with a fault pin, which is an open-drain output allowing several ad5412/ad5422 devices to be connected together to one pull-up resistor for global fault detection. the fault pin is forced active by one of the following fault scenarios: ? the voltage at i out attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the i out current is controlled by a pmos transistor and internal amplifier, as shown in figure 64 . the internal circuitry that develops the fault output avoids using a comparator with window limits because this would require an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than ~1 v of remaining drive capability (when the gate of the output pmos transistor nearly reaches ground). thus, the fault output activates slightly before the compliance limit is reached. because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active. ? if the core temperature of the ad5412/ad5422 exceeds approximately 150c. the i out fault and over temp bits of the status register are used in conjunction with the fault pin to inform the user which one of the fault conditions caused the fault pin to be asserted (see and ). table 19 table 20 voltage output short circuit protection under normal operation, the voltage output sinks/sources 10 ma. the maximum current that the voltage output delivers is ~20 ma; this is the short-circuit current. voltage output overrange an overrange facility is provided on the voltage output. when enabled via the control register, the selected output range is overranged by, typically, 10%. voltage output force-sense the +v sense and ?v sense pins are provided to facilitate remote sensing of the load connected to the voltage output. if the load is connected at the end of a long or high impedance cable, sensing the voltage at the load allows the output amplifier to compensate and ensure that the correct voltage is applied across the load. this function is limited only by the available power supply headroom. asynchronous clear (clear) the clear pin is an active high clear that allows the voltage output to be cleared to either zero-scale code or midscale code, user selectable via the clear select pin, or the clrsel bit of the control register, as described in table 21 . (the clear select feature is a logical or function of the clear select pin and the clrsel bit.) the current output clears to the bottom of its programmed range. it is necessary for clear to be high for a minimum amount of time to complete the operation (see figure 2 ). when the clear signal is returned low, the output remains at the cleared value. the preclear value can be restored by pulsing the latch signal low without clocking any data. a new value cannot be programmed until the clear pin is returned low. table 21. clrsel options clrsel output value unipolar output range bipolar output range 0 0 v 0 v 1 midscale negative full scale in addition to defining the output value for a clear operation, the clrsel bit and clear select pin also define the default output value. during selection of a new voltage range, the output value is as defined in table 21 . to avoid glitches on the output, it is recommended that, before changing voltage ranges, the user disable the output by setting the outen bit of the control register to logic low. when outen is set to logic high, the output goes to the default value as defined by clrsel and clear select. internal reference the ad5412/ad5422 contain an integrated 5 v voltage reference with initial accuracy of 5 mv maximum and a temperature drift coefficient of 10 ppm/c maximum. the reference voltage is buffered and externally available for use elsewhere within the system. see figure 16 for a load regulation graph of the integrated reference. external current setting resistor r set is an internal sense resistor as part of the voltage-to-current conversion circuitry (see figure 64 ). the stability of the output current over temperature is dependent on the stability of the value of r set . as a method of improving the stability of the output current over temperature, an external precision 15 k low drift resistor can be connected to the r set pin of the ad5412/ad5422 to be used instead of the internal resistor (r set ). the external resistor is selected via the control register (see table 14 ).
ad5412/ad5422 rev. c | page 32 of 40 digital power supply by default, the dv cc pin accepts a power supply of 2.7 v to 5.5 v. alternatively, via the dv cc select pin, an internal 4.5 v power supply can be output on the dv cc pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. this facility offers the advantage of not having to bring a digital supply across an isolation barrier. the internal power supply is enabled by leaving the dv cc select pin unconnected. to disable the internal supply, tie dv cc select to 0 v. dv cc is capable of supplying up to 5 ma of current (for a load regulation graph, see figure 10 ). external boost function the addition of an external boost transistor, as shown in figure 67 , reduces the power dissipated in the ad5412/ad5422 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). a discrete npn transistor with a breakdown voltage, bv ceo , greater than 40 v can be used. the external boost capability has been developed for users who may wish to use the ad5412/ad5422 at the extremes of the supply voltage, load current, and temperature range. the boost transistor can also be used to reduce the amount of temperature-induced drift in the part. this minimizes the temperature-induced drift of the on-chip voltage reference, which improves on drift and linearity. boost mjd31c or pbss8110z r load 0.022f 1k? ad5412/ ad5422 i out 06996-061 figure 67. external boost configuration external compensation capacitor the voltage output can ordinarily drive capacitive loads of up to 20 nf; if there is a requirement to drive greater capacitive loads, of up to 1 f, an external compensation capacitor can be con- nected between the c comp and v out pins. the addition of the capacitor keeps the output voltage stable but also reduces the bandwidth and increases the settling time of the voltage output. digital slew rate control the slew rate control feature of the ad5412/ad5422 allows the user to control the rate at which the output voltage or current changes. with the slew rate control feature disabled, the output changes at a rate limited by the output drive circuitry and the attached load. see figure 62 for current output step and figure 36 for voltage output step. to reduce the slew rate, enable the slew rate control feature. with the feature enabled via the sren bit of the control register (see table 14 ), the output, instead of slewing directly between two values, steps digitally at a rate defined by two parameters accessible via the control register, as shown in table 14 . the parameters are set by the sr clock and sr step bits. sr clock defines the rate at which the digital slew is updated; sr step defines by how much the output value changes at each update. both parameters together define the rate of change of the output voltage or current. tabl e 22 and table 23 outline the range of values for both the sr clock and sr step parameters. figure 68 shows the output current changing for ramp times of 10 ms, 50 ms, and 100 ms. table 22. slew rate step size options sr step ad5412 step size (lsb) ad5422 step size (lsb) 000 1/16 1 001 1/8 2 010 1/4 4 011 1/2 8 100 1 16 101 2 32 110 4 64 111 8 128 table 23. slew rate update clock options sr clock update clock frequency (hz) 0000 257,730 0001 198,410 0010 152,440 0011 131,580 0100 115,740 0101 69,440 0110 37,590 0111 25,770 1000 20,160 1001 16,030 1010 10,290 1011 8280 1100 6900 1101 5530 1110 4240 1111 3300 the time it takes for the output to slew over a given output range can be expressed as follows: sizelsb frequency clock update sizestep change output timeslew u u (1) where: slew time is expressed in seconds. output change is expressed in amps for i out or volts for v out . when the slew rate control feature is enabled, all output changes change at the programmed slew rate; if the clear pin is asserted, the output slews to the zero-scale value at the programmed slew rate. the output can be halted at its current value with a write to the control register. to avoid halting the output slew, the slew active bit (see tabl e 19 ) can be read to check that the slew has completed before writing to any of the
ad5412/ad5422 rev. c | page 33 of 40 ad5410/ad5420 registers. the update clock frequency for any given value is the same for all output ranges. the step size, however, varies across output ranges for a given value of step size because the lsb size is different for each output range. table 24 shows the range of programmable slew times for a full- scale change on any of the output ranges. the values in table 24 were obtained using equation 1. the digital slew rate control feature results in a staircase formation on the current output, as shown in figure 72. this figure also shows how the staircase can be removed by connecting capacitors to the cap1 and cap2 pins, as described in the i out filtering capacitors (lfcsp package) section. 0 5 10 15 20 25 ?10 0 10 20 30 40 50 60 70 80 90 100 110 output current (ma) time (ms) t a = 25c av dd = 24v r load = 300 ? 06996-139 10ms ramp, sr clock = 0x1, sr step = 0x5 50ms ramp, sr clock = 0xa, sr step = 0x7 100ms ramp, sr clock = 0x8, sr step = 0x5 figure 68. output current slewing under control of the digital slew rate control feature i out filtering capacitors (lfcsp package) capacitors can be placed between cap1 and av dd , and cap2 and av dd , as shown in figure 69. cap1 av dd c1 c2 a v dd ad5412/ ad5422 cap2 gnd 06996-062 i out figure 69. i out filtering capacitors the cap1 and cap2 pins are available only on the lfcsp package. the capacitors form a filter on the current output circuitry, as shown in figure 70, reducing the bandwidth and the slew rate of the output current. figure 71 shows the effect the capacitors have on the slew rate of the output current. to achieve significant reductions in the rate of change, very large capacitor values are required, which may not be suitable in some applications. in this case, the digital slew rate control feature can be used. the capacitors can be used in conjunction with the digital slew rate control feature as a means of smoothing out the steps caused by the digital code increments, as shown in figure 72. dac i out boost cap1 cap2 c1 r1 c2 av dd 4k? 12.5k ? 40? 06996-063 figure 70. i out filter circuitry 0 5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 10 15 20 25 output current (ma) time (ms) t a = 25c av dd =24v r load =300 ? 06996-142 no capacitor 10nf on cap1 10nf on cap2 47nf on cap1 47nf on cap2 figure 71. slew controlled 4 ma to 20 ma output current step using external capacitors on the cap1 and cap2 pins 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 ?1012345678 output current (ma) time (ms) t a = 25c av dd = 24v r load = 300 ? no external caps 10nf on cap1 10nf on cap2 06996-043 figure 72. smoothing out the steps caused by the digital slew rate control feature
ad5412/ad5422 rev. c | page 34 of 40 table 24. programmable slew time values in seco nds for a full-scale change on any output range update clock frequency (hz) step size (lsb) 1 2 4 8 16 32 64 128 257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020 198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026 152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007 0.0034 131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008 0.0039 115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009 0.0044 69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015 0.007 37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03 0.014 25,770 2.5 1.3 0.64 0.32 0.16 0.08 0.04 0.020 20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05 0.025 16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06 0.03 10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10 0.05 8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12 0.06 6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15 0.07 5530 12 5.9 3.0 1.5 0.74 0.37 0.19 0.09 4240 15 7.7 3.9 1.9 0.97 0.48 0.24 0.12 3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16
ad5412/ad5422 rev. c | page 35 of 40 applications information encode serial clock in controller adum1400 1 serial data out sync out control out decode to sclk to sdin to latch to clear v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 06996-065 1 additional pins omitted for clarity. driving inductive loads when driving inductive or poorly defined loads, connect a 0.01 f capacitor between i out and gnd. this ensures stability with loads above 50 mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling. the digital slew rate control feature may also prove useful in this situation. transient voltage protection the ad5412/ad5422 contain esd protection diodes that prevent damage from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to protect the ad5412/ad5422 from excessively high voltage transients, external power diodes and a surge current limiting resistor are required, as shown in figure 73 . the constraint on the resistor value is that, during normal operation, the output level at i out must remain within its voltage compliance limit of av dd C 2.5 v, and the two protection diodes and resistor must have appropriate power ratings. further protection can be provided with transient voltage suppressors or transorbs; these are available as both unidirectional suppressors (protect against positive high voltage transients) and bidirectional suppressors (protect against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. it is recommended that all field connected nodes be protected. figure 74. isolated interface microprocessor interfacing microprocessor interfacing to the ad5412/ad5422 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the ad5412/ad5422 require a 24-bit data- word with data valid on the rising edge of sclk. for all interfaces, the dac output update is initiated on the rising edge of latch. the contents of the registers can be read using the readback function. layout guidelines av dd i out r load r p a v dd ad5412/ ad5422 gnd 06996-064 in any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. design the printed circuit board (pcb) on which the ad5412/ad5422 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5412/ad5422 is in a system where multiple devices require an analog ground-to-digital ground connection, make the connection at one point only. establish the star ground point as close as possible to the device. figure 73. output transient voltage protection the ad5412/ad5422 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. the i coupler? products from analog devices, inc., provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5412/ad5422 makes the parts ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 74 shows a 4-channel isolated interface to the ad5412/ ad5422 using an adum1400 . for further information, visit http://www.analog.com/icouplers .
ad5412/ad5422 rev. c | page 36 of 40 the power supply lines of the ad5412/ad5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with a digital ground to avoid radiating noise to other parts of the board. never run these near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (this is not required on a multilayer board that has a separate ground plane, but separating the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the pcb should run at right angles to each other. this reduces the effects of feed through the board. a microstrip technique is by far the best but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to the ground plane, and signal traces are placed on the solder side. thermal and supply considerations the ad5412/ad5422 are designed to operate at a maximum junction temperature of 125c. it is important that the devices not be operated under conditions that cause the junction temperature to exceed this value. excessive junction tempera- ture can occur if the ad5412/ad5422 are operated from the maximum av dd while driving the maximum current (24 ma) directly to ground. in this case, control the ambient temperature or reduce av dd . the conditions depend on the device package. at the maximum ambient temperature of 85c, the 24-lead tssop package can dissipate 950 mw, and the 40-lead lfcsp package can dissipate 1.42 w. to ensure that the junction temperature does not exceed 125c while driving the maximum current of 24 ma directly into ground (also adding an on-chip current of 3 ma), reduce av dd from the maximum rating to ensure that the package is not required to dissipate more power than previously stated (see table 25 , figure 75 , and figure 76 ). 0 0.5 1.0 1.5 2.0 2.5 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) power dissipation (w) lfcsp tssop 06996-066 figure 75. maximum power dissipation vs. ambient temperature 25 27 29 31 33 35 37 39 41 43 45 25 35 45 55 65 75 85 ambient temperature (c) supply voltage (v) 06996-067 tssop lfcsp figure 76. maximum supply voltage vs. ambient temperature table 25. thermal and supply co nsiderations for each package considerations tssop lfcsp maximum allowed power dissipation when operating at an ambient temperature of 85c mw950 42 85125 = ? = ? ja a j tmaxt w42.1 28 85125 = ? = ? ja a j tmaxt maximum allowed ambient temperature when operating from a supply of 40 v and driving 24 ma directly to ground c7842)028.040(125 = ? =? jad j pmaxt c9428)028.040(125 = ?= ? jad j pmaxt maximum allowed supply voltage when operating at an ambient temperature of 85c and driving 24 ma directly to ground v34 42028.0 85125 = ? = ? ja dd a j ai tmaxt v51 28028.0 85125 = ? = ? ja dd a j ai tmaxt
ad5412/ad5422 rev. c | page 37 of 40 industrial analog output module many industrial control applications have requirements for accurately controlled current and voltage output signals. the ad5412/ad5422 are ideal for such applications. figure 77 shows the ad5412/ad5422 in a circuit design for an output module, specifically for use in an industrial control application. the design provides for a current or voltage output. the module is powered from a field supply of 24 v. this supplies av dd directly. an inverting buck regulator generates the negative supply for av ss . for transient overvoltage protection, transient voltage suppressors (tvs) are placed on all field accessible connections. a 24 v volt tvs is placed on each i out , v out , +v sense , and ?v sense connection, and a 36 v tvs is placed on the field supply input. for added protection, clamping diodes are connected from the i out , v out , +v sense , and ?v sense pins to the av dd and av ss power supply pins. if remote voltage load sensing is not required, the +v sense pin can be directly connected to the v out pin and the Cv sense pin can be connected to gnd. isolation between the ad5412/ad5422 and the backplane circuitry is provided with adum1400 and adum1200 i coupler digital isolators; further information on i coupler products is available at www.analog.com/icouplers . the internally generated digital power supply of the ad5412/ ad5422 powers the field side of the digital isolaters, removing the need to generate a digital power supply on the field side of the isolation barrier. the ad5412/ad5422 digital supply output supplies up to 5 ma, which is more than enough to supply the 2.8 ma requirements of the adum1400 and adum1200 operating at a logic signal frequency of up to 1 mhz. to reduce the number of isolators required, nonessen- tial signals such as clear can be connected to gnd. fault and sdo can be left unconnected, reducing the isolation requirements to just three signals. latch sclk sdin sdo dv cc av ss av dd +v sense ?v sense i out v out +v sense ?v sense i out +v out c comp gnd clear fault refout refin clear select dv cc select ad5412/ ad5422 1 24v smaj24ca 4nf 24v field supply 36v 10f 0.1f 0.1f 10f 0.1f ?15v inverting buck regulator ? 15 v v dd2 v dd2 gnd 1 gnd 1 v ia v ia nc gnd 1 v ic v id v ib v ib v oa v oa v oc v od v ob v ob gnd 2 v e2 gnd 2 gnd 2 adum1400 10k? field ground adum1200 v dd1 v dd1 microcontroller digital outputs digital inputs 0.1f 0.1f backplane interface backplane supply smaj36ca 4.7k ? 18 ? 100? + + 06996-068 1 additional pins omitted for clarity. figure 77. ad5412/ad5422 in an industrial analog output module application
ad5412/ad5422 rev. c | page 38 of 40 outline dimensions compliant to jedec standards mo-153-adt 061708-a 24 13 12 1 6.40 bsc 0.15 0.05 0.10 coplanarity top view exposed pad (pins up) bottom view 4.50 4.40 4.30 7.90 7.80 7.70 1.20 max 1.05 1.00 0.80 0.65 bsc 0.30 0.19 seating plane 0.20 0.09 8 0 0.75 0.60 0.45 5.02 5.00 4.95 3.25 3.20 3.15 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 78. 24-lead thin shrink small ou tline package, exposed pad [tssop_ep] (re-24) dimensions shown in millimeters 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bsc sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 072108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 79. 40-lead lead frame chip scale package [lfcsp_vq] 6 mm 6 mm body, very thin quad (cp-40-1) dimensions shown in millimeters
ad5412/ad5422 rev. c | page 39 of 40 ordering guide model 1 resolution i out tue v out tue temperature range package description package option ad5412arez 12 bits 0.5% fsr max 0.3% fsr ma x ?40c to +85c 24 lead tssop_ep re-24 ad5412arez-reel7 12 bits 0.5% fsr max 0.3% fs r max ?40c to +85c 24 lead tssop_ep re-24 ad5412acpz-reel 12 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 ad5412acpz-reel7 12 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 ad5422arez 16 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 24 lead tssop_ep re-24 ad5422arez-reel 16 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 24 lead tssop_ep re-24 AD5422BREZ 16 bits 0.3% fsr max 0.1% fsr max ?40c to+85c 24 lead tssop_ep re-24 AD5422BREZ-reel 16 bits 0.3% fsr max 0.1% fs r max ?40c to+85c 24 lead tssop_ep re-24 ad5422acpz-reel 16 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 ad5422acpz-reel7 16 bits 0.5% fsr max 0.3% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 ad5422bcpz-reel 16 bits 0.3% fsr max 0.1% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 ad5422bcpz-reel7 16 bits 0.3% fsr max 0.1% fsr max ?40c to+85c 40 lead lfcsp_vq cp-40-1 eval-ad5422ebz evaluation board 1 z = rohs compliant part.
ad5412/ad5422 rev. c | page 40 of 40 notes ?2009-2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06996-0-3/10(c)

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