smr100 this product has reached end of life ? summit microelectronics, inc. 2004 ? 1717 fox drive ? san jose ca 95131 ? phone 408 436-9890 ? fax 408 436-9897 the summit web site can be accessed by ?ri ght? or ?left? mouse clicking on the link: http://www.summitmicro.com/ 2076 1.6 06/30/04 1 features & applications ? de-bounced reset input with up to 40 second programmable delay time ? external push-button control provides a reliable end-user system reset function ? reset signal at 3.0v with a programmable timeout period ? brownout warning signal whenever the supply dips below 3.1v ? programmable glitch filtering of brownout warning (bad_pwr#) and reset function ? 8 pin soic package ? 6 ball ultra csp tm (chip-scale) package applications ? satellite and cable-tv set-top box ? handheld pcs, cameras, camcorders, pdas ? security/medical alert systems introduction the smr100 programmable reset controller is designed for consumer applications specified by satellite-tv set-top box standards. the smr100 provides a satellite box cont roller solution during initial setup, changing programming cards and/or system reset needs without removing power. the part can accommodate a long-delay hold down of an external reset push-button using an internal programmable de- bounced timer. the part is factory programmed, however, multiplexed programming pins are also provided for in-system programming for prototype purposes. the required hold down time is programmable from 0.325 to 40 sec with an internal on-chip oscillator. accurate warning of a 3.1v brownout condition (bad_pwr#), and a programmable reset (reset_out#) timeout period when the vdd supply pin reaches 3.0v are also provided. during a reset (reset_out#), the part enabl es the ?bad_pwr#? or brownout warning output until the reset has cleared. a programmable glitch filter avoids nuisance tripping of the internal comparators. simplified applications drawing filt_cap trim_c ap smr100 3.3v 3.3v gnd vdd prog reset_in# reset_out# bad_pwr# 0.1 f asic p manual reset switch figure 1 ? applications schematic using the smr100 to supervise the supply to digital components. as shown, the smr100 is designed to use a minimum of external components. programmable long-delay push-button reset controller for consumer equipment
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 2 general description the smr100 is a programmable reset controller for consumer equipment used to monitor the power supply in p and digital systems. it provides excellent circuit reliability and low cost by eliminating external components and adjustments when used with +3.3v powered circuits. the device performs several functions: it first asserts a ?bad power? signal and then a reset signal whenever the vdd supply voltage declines below two preset thresholds, keeping it asserted for a programmable time period after vdd has risen above the reset threshold. the part also provides a programmable delay push button input for manual system reset. the open-drain reset_out# and bad_pwr# outputs have on-chip 100k pull-up resistors and do not require external pull-up resistors unless more drive current is needed (see figure 3). the reset_out# and bad_pwr# comparators are designed to ignore fast transients on vdd, and the outputs are guaranteed to be in the correct logic state for vdd down to 1v. low supply current makes the smr100 ideal for use in portable equipment. the reset_in# input includes a programmable hold-down delay timer for use with a push button switch for consumer equipment such as set-top boxes and pcs. a microprocessor?s (p?s) reset input starts the p in a known state. the smr100 asserts a reset to prevent code -execution errors during power-up, power-down, or undervoltage (uv) conditions. it asserts a reset_out# signal whenever the vdd supply voltage declines below a 3.0v threshold, keeping it asserted for a programmable period after vdd has risen above the reset threshold. it also asserts a bad power signal to warn of an impending reset or brownout condition to allow time for the system to save data before a reset occurs. the bad_pwr# signal is also asserted whenever reset_out# is asserted to prevent erroneous or false bad power warnings during initial turn-on. in addition to issuing a reset to the p during power- up, power-down, and brow nout conditions, the smr100 is immune to short-duration vdd transients (glitches) due to a programmabl e glitch filter. typically, a vdd transient of 100mv less than the reset threshold and lasting for a duration less than the programmed glitch filter setting will not cause a reset pulse. a 0.1f bypass capacitor mounted as close as possible to the vdd pin provides additional transient immunity. since the bad _pwr# and reset_out# outputs are open drain, the de vice interfaces easily with ps that have bidirectional-reset pins. connecting the reset_out# output direct ly to the p?s reset pin allows either the p or the smr100 to assert a reset. vdd reset_out# bad_pwr# reset_in# push-button input t reset t reset_hd t reset 3.1v 3.0v t glitch push-button released figure 2 ? smr100 operation and timing diagram
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 3 8 khz ring oscillator, +/-10% accurate programmable delay generator/ logic z z z z z up count msb reset_out at 3.0v z programmable hold-down time, 0.3125 to 40sec vdd gnd user reset pushbutton z - - + + z 1.25v vref programmable duration glitch filter z programmable duration reset output reset user reset z z z z z z programmable duration glitch filter z z reset _in# reset_out# bad_pwr# 3.3v z bad_pwr at 3.1v 100k z 100k z 100k z z z z prog z z 2 figure 3 ? smr100 controller internal block diagram. internal block diagram
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 4 package and pin configuration reset_in# vdd reset_out# gnd prog a1 a2 b1 b2 c1 c2 bad_pwr# 1 2 4 3 8 7 5 6 prog nc reset_in# gnd vdd nc bad_pwr# reset_out# pin descriptions csp pin number soic pin number pin type pin name pin description a1 1 i prog high voltage programming pin. set to 12v in programming mode. connected to ground if not used. a2 8 pwr vdd positive supply voltage. b1 4 pwr gnd ground pin. b2 5 o reset_out# open drain active low reset out indicator. internally connected to vdd through a 100k ? resistor. c1 3 i reset_in# de-bounced push button switch input. internally connected to vdd through a 100k ? resistor. also used as the data input programming pin when the prog pin is set to 12v. c2 6 o bad_pwr# open drain active low bad power indicator. internally connected to vdd through a 100k ? resistor. na 2,7 nc nc no connect 6 ball ultra csp tm bottom view 8 pin soic top view
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 5 absolute maximum ratings temperature un der bias ......................-55 c to 125 c storage temper ature............................-65 c to 125 c terminal voltage with respect to gnd: v dd ???????????...?.-0.3v to 6.0v prog, reset_in#???...?.-0.3v to 16.0v all others?????????..?.vdd + 0.7v output short circuit current .................. 100ma reflow solder temp erature (30 secs)................ 240 c esd rating per jedec???????....??..2000v latch-up testing per jedec?????......? 100ma note - the device is not guarant eed to function outside its operating rating. stresses listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions outside those listed in the operational sections of the specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. devices are esd sensitive. handling precautions are recommended. recommended operating conditions temperature range (commercial)???.?5 c to +70 c supply voltage????????????..3.3v +/-10% 1 programming supply voltage??????12.0v +/-10% note 1 ? the device can operate over a supply range of 2.7v to 5.5v. package thermal resistance ( ja ) 8 pin soic???????.???.????.?23 o c/w 6 ball ultra csp tm ????.????.??.?tbd o c/w moisture classification level 1 (msl 1) per j-std- 020 reliability characteristics data retention?????...?????..?..100 years endurance??????...??. ???.100,000 cycles dc operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min. typ. max unit v dd supply voltage range 2.7 3.3 5.5 v v prog programming supply voltage range 10.0 12.0 15.0 v v rt reset threshold 2.95 3.0 3.05 v v bpt bad power warning threshold 3.05 3.1 3.15 v i dd power supply current vdd = 3.3v, no reset_out# in progress 100 200 a v ih input high voltage vdd = 3.3v 0.9xvdd vdd v v il input low voltage vdd = 3.3v 0.1xvdd v v ol programmable active high or low open drain outputs (reset_out#, bad_pwr#) isink = 1ma 0 0.4 v i ol output low current 0 1.0 ma
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 6 ac operating characteristics (over recommended operating conditions, unless otherwise noted. all voltages are relative to gnd.) symbol parameter notes min. typ. max unit 0.8 1 1.2 ms 20 25 30 ms 80 100 120 ms t reset_out reset timeout period programmed default = 25ms 160 200 240 ms 3 4 5 s 4.5 6 7.5 s 7.5 10 12.5 s t glitch programmable glitch filter times programmed default = 4 s 13.5 18 22.5 s 0.26 0.325 0.39 s 0.5 0.625 0.75 s 1 1.25 1.5 s 2 2.5 3 s 4 5 6 s 8 10 12 s 16 20 24 s t reset_hd programmable reset hold-down delay times programmed default = 10s 32 40 48 s
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 7 8 pin soic package .05 (1.27) typ. 1 8 pin soic 0.150 - 0.157 (3.80 - 4.00) 0.189 - 0.196 (4.80 - 5.00) 0.053 - 0.069 (1.35 - 1.75) 0.013 - 0.020 (0.33 - 0.51) 0.004 - 0.010 (0.10 - 0.25) 0.016 - 0.050 (0.40 - 1.27) 45 o 0.010 - 0.020 (0.25 - 0.50) 0.228 - 0.244 (5.80 - 6.20) ref. jedec ms-012 inches (millimeters) package outline
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 8 6 ball ultra csp tm ? chip scale package package outline (continued)
smr100 preliminary information summit microelectronics, inc 2076 1.6 06/30/04 9 part marking SMR100S ayyww pin 1 identifier annn summit part number date code (yyww) part number suffix (contains customer specific ordering requirements) lot tracking code (summit use) drawing not to scale xx status tracking code (blank, ms, es, 01, 02,...) (summit use) product tracking code (summit use) summit ordering information the default device ordering number is smr100e-100 and is programmed as described in the ac operating characteristics table on page 6 and tested over the commercial temperature range. notice note 1 - this is a preliminary information data sheet that describes a summit product current ly in pre-production with limited characterization. revision 1.6 - this document supersedes all previous versions. data sheet updates c an be accessed by ?right? or ?left? mouse c licking on the link: http://www.summitmicro.com/ device errata sheets can be accessed by ?right? or ?left? mouse clicking on the link: http://www.summitmicro.com/errata/ summit microelectronics, inc. reserves the ri ght to make changes to the products cont ained in this publication in order to impr ove design, performance or reliability. summit microelec tronics, inc. assumes no responsibility for the use of any circuits described herei n, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and sche dules contained herein reflect representative operating parameters, and may vary depending upon a user?s specific application. while the inform ation in this publication has been carefully checked, summi t microelectronics, inc. shall not be liabl e for any damages arising as a result o f any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expe cted to cause any failure of either syst em or to significantly affect their sa fety or effectiveness. products are not authorized for use in such applications unless su mmit microelectronics, inc. receiv es written assurances, to i ts satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2004 summit microelectronics, inc . programmable analog for a digital world? ultra csp tm is a registered name of flipchip international, llc. smr100 e package e = 6 ball ultra csp tm summit part number nnn part number suffix customer specific requirements are contained in the suffix such as hex code, hex code revision, etc. s = 8 pin soic annn ssyww ball a1 identifier part number suffix-nnn (customer specific ordering requirements) date code y = single digit year (4=2004, 5=2005, etc) drawing not to scale product tracking code (summit use)
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