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quad t1/e1/j1 long haul / short haul transceiver IDT82P2284 version 3 march 22, 2004 2975 stender way, santa clara, califormia 95054 telephone: (800) 345-7015 ? twx: 910-338-2070 ? fax: (408) 492-8674 printed in u.s.a. ? 2001 integrated device technology, inc.
disclaimer integrated device technology, inc. reserves the right to make changes to its products or specifications at any time, without no tice, in order to improve design or performance and to supply the best pos- sible product. idt does not assume any res ponsibility for use of any circuitry described other than the circuitry embodied in a n idt product. the company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent, pat ent rights or other rights, of integrated device technology, inc. life support policy integrated device technology's products ar e not authorized for use as critical com ponents in life support devices or systems un less a specific written agr eement pertaining to such intended use is exe- cuted between the manufacture r and an officer of idt. 1. life support devices or systems are devices or systems whic h (a) are intended for surgical implant into the body or (b) supp ort or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any components of a life support device or system whose fa ilure to perform can be reasonably expecte d to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.
table of contents i march 22, 2004 table of contents features ............ ................ ................. ................ ............... .............. .............. .............. .............. .............. ............... ....... 1 applications ........... ................ ................. .............. .............. .............. ............... ............. ................. ................. ............ 1 block diagram ................ ................. ................ ................. ................ ................. .............. ................. ................ .......... 2 1 pin assignment ....... ................ ................. .............. .............. .............. ............... .............. ................ ................. ............ 3 2 pin description ........... ................ ................. ................ ................. ................ ................. ................ ................. ............ 4 3 functional description ............... ................ ................. .............. .............. .............. ............. ............. ............ ........ 12 3.1 t1 / e1 / j1 mode selection ................................................................................................ .................................................................. 14 3.2 receiver impedance matching ................................................................................................ ......................................................... 15 3.3 adaptive equalizer ......................................................................................................... ..................................................................... 17 3.4 data slicer ................................................................................................................ .............................................................................. 17 3.5 clock and data recovery .................................................................................................... ............................................................ 17 3.6 receive jitter attenuator .................................................................................................. ............................................................. 18 3.7 decoder .................................................................................................................... ................................................................................ 19 3.7.1 line code rule ........................................................................................................... .................................................................... 19 3.7.1.1 t1 / j1 mode ........................................................................................................... ......................................................... 19 3.7.1.2 e1 mode ................................................................................................................ ........................................................... 19 3.7.2 decode error detection ................................................................................................... .............................................................. 19 3.7.2.1 t1 / j1 mode ........................................................................................................... ......................................................... 19 3.7.2.2 e1 mode ................................................................................................................ ........................................................... 19 3.7.3 los detection ............................................................................................................ .................................................................... 20 3.8 frame processor ............................................................................................................ ..................................................................... 23 3.8.1 t1/j1 mode ............................................................................................................... ....................................................................... 23 3.8.1.1 synchronization searching .............................................................................................. ................................................. 23 3.8.1.1.1 super frame (sf) format .............................................................................................. ............................... 23 3.8.1.1.2 extended super frame (esf) format .................................................................................... ....................... 24 3.8.1.1.3 t1 digital multiplexer (dm) format (t1 only) ......................................................................... ....................... 25 3.8.1.1.4 switch line carrier - 96 (slc-96) format (t1 only) ................................................................... ................... 26 3.8.1.2 error event and out of synchronization detection ....................................................................... ................................... 27 3.8.1.2.1 super frame (sf) format .............................................................................................. ............................... 27 3.8.1.2.2 extended super frame (esf) format .................................................................................... ....................... 27 3.8.1.2.3 t1 digital multiplexer (dm) format (t1 only) ......................................................................... ....................... 27 3.8.1.2.4 switch line carrier - 96 (slc-96) format (t1 only) ................................................................... ................... 27 3.8.1.3 overhead extraction (t1 mode slc-96 format only) ....................................................................... .............................. 28 3.8.1.4 interrupt summary ...................................................................................................... ...................................................... 28 3.8.2 e1 mode .................................................................................................................. ........................................................................ 30 3.8.2.1 synchronization searching .............................................................................................. ................................................. 32 3.8.2.1.1 basic frame .......................................................................................................... ........................................ 32 3.8.2.1.2 crc multi-frame ...................................................................................................... ..................................... 33 3.8.2.1.3 cas signaling multi-frame ............................................................................................ ............................... 34 3.8.2.2 error event and out of synchronization detection ....................................................................... ................................... 34 3.8.2.2.1 out of basic frame synchronization ................................................................................... ......................... 35 3.8.2.2.2 out of crc multi-frame synchronization ............................................................................... ..................... 35 3.8.2.2.3 out of cas signaling multi-frame synchronization ..................................................................... ................ 35 3.8.2.3 overhead extraction .................................................................................................... ..................................................... 35 3.8.2.3.1 international bit extraction ......................................................................................... .................................... 35 3.8.2.3.2 remote alarm indication bit extraction ............................................................................... .......................... 35
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver table of contents ii march 22, 2004 3.8.2.3.3 national bit extraction .............................................................................................. ..................................... 35 3.8.2.3.4 national bit codeword extraction ..................................................................................... ............................. 35 3.8.2.3.5 extra bit extraction ................................................................................................. ....................................... 35 3.8.2.3.6 remote signaling multi-frame alarm indication bit extraction ......................................................... ............ 35 3.8.2.3.7 sa6 code detection per ets 300 233 ................................................................................... ....................... 35 3.8.2.4 v5.2 link .............................................................................................................. ............................................................ 36 3.8.2.5 interrupt summary ...................................................................................................... ...................................................... 36 3.9 performance monitor ........................................................................................................ ................................................................ 38 3.9.1 t1/j1 mode ............................................................................................................... ....................................................................... 38 3.9.2 e1 mode .................................................................................................................. ........................................................................ 40 3.10 alarm detector ............................................................................................................ ........................................................................ 42 3.10.1 t1/j1 mode .............................................................................................................. ........................................................................ 42 3.10.2 e1 mode ................................................................................................................. ......................................................................... 44 3.11 hdlc receiver ............................................................................................................. ............................................................................ 45 3.11.1 hdlc channel configuration .............................................................................................. .......................................................... 45 3.11.2 two hdlc modes .......................................................................................................... ................................................................. 45 3.11.2.1 hdlc mode ............................................................................................................. ......................................................... 45 3.11.2.2 ss7 mode .............................................................................................................. ........................................................... 47 3.12 bit-oriented message receiver (t1/j1 only) ................................................................................ .............................................. 49 3.13 inband loopback code detector (t1/j1 only) ................................................................................ ........................................... 49 3.14 elastic store buffer ...................................................................................................... .................................................................... 50 3.15 receive cas/rbs buffer .................................................................................................... ................................................................. 50 3.15.1 t1/j1 mode .............................................................................................................. ........................................................................ 50 3.15.2 e1 mode ................................................................................................................. ......................................................................... 51 3.16 receive payload control ................................................................................................... .............................................................. 53 3.17 receive system interface .................................................................................................. ............................................................... 55 3.17.1 t1/j1 mode .............................................................................................................. ........................................................................ 55 3.17.1.1 receive clock master mode ............................................................................................. ............................................... 55 3.17.1.1.1 receive clock master full t1/j1 mode ................................................................................ ......................... 55 3.17.1.1.2 receive clock master fractional t1/j1 mode .......................................................................... ..................... 56 3.17.1.2 receive clock slave mode .............................................................................................. ................................................ 56 3.17.1.3 receive multiplexed mode .............................................................................................. ................................................. 57 3.17.1.4 offset ................................................................................................................ ................................................................ 57 3.17.1.5 output on rsdn/mrsda(mrsdb) & rsign/mrsiga(mrsigb) .................................................................... .............. 59 3.17.2 e1 mode ................................................................................................................. ......................................................................... 60 3.17.2.1 receive clock master mode ............................................................................................. ............................................... 60 3.17.2.1.1 receive clock master full e1 mode ................................................................................... .......................... 60 3.17.2.1.2 receive clock master fractional e1 mode ............................................................................. ...................... 60 3.17.2.2 receive clock slave mode .............................................................................................. ................................................ 60 3.17.2.3 receive multiplexed mode .............................................................................................. ................................................. 61 3.17.2.4 offset ................................................................................................................ ................................................................ 61 3.17.2.5 output on rsdn/mrsda(mrsdb) & rsign/mrsiga(mrsigb) .................................................................... .............. 61 3.18 transmit system interface ................................................................................................. ............................................................. 62 3.18.1 t1/j1 mode .............................................................................................................. ........................................................................ 62 3.18.1.1 transmit clock master mode ............................................................................................ ................................................ 62 3.18.1.1.1 transmit clock master full t1/j1 mode ............................................................................... ......................... 63 3.18.1.1.2 transmit clock master fractional t1/j1 mode ......................................................................... ..................... 63 3.18.1.2 transmit clock slave mode ............................................................................................. ................................................ 63 3.18.1.3 transmit multiplexed mode ............................................................................................. ................................................. 64 3.18.1.4 offset ................................................................................................................ ................................................................ 65 3.18.2 e1 mode ................................................................................................................. ......................................................................... 67 3.18.2.1 transmit clock master mode ............................................................................................ ................................................ 67 3.18.2.1.1 transmit clock master full e1 mode .................................................................................. .......................... 67 3.18.2.1.2 transmit clock master fractional e1 mode ............................................................................ ...................... 67
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver table of contents iii march 22, 2004 3.18.2.2 transmit clock slave mode ............................................................................................. ................................................ 67 3.18.2.3 transmit multiplexed mode ............................................................................................. ................................................. 68 3.18.2.4 offset ................................................................................................................ ................................................................ 68 3.19 transmit payload control .................................................................................................. ............................................................ 69 3.20 frame generator ........................................................................................................... ...................................................................... 70 3.20.1 generation .............................................................................................................. ........................................................................ 70 3.20.1.1 t1 / j1 mode .......................................................................................................... .......................................................... 70 3.20.1.1.1 super frame (sf) format ............................................................................................. ................................ 70 3.20.1.1.2 extended super frame (esf) format ................................................................................... ........................ 70 3.20.1.1.3 t1 digital multiplexer (dm) format (t1 only) ........................................................................ ........................ 70 3.20.1.1.4 switch line carrier - 96 (slc-96) format (t1 only) .................................................................. .................... 70 3.20.1.1.5 interrupt summary ................................................................................................... ...................................... 71 3.20.1.2 e1 mode ............................................................................................................... ............................................................ 72 3.20.1.2.1 interrupt summary ................................................................................................... ...................................... 73 3.20.2 hdlc transmitter ........................................................................................................ .................................................................. 75 3.20.2.1 hdlc channel configuration ............................................................................................ ............................................... 75 3.20.2.2 two hdlc modes ........................................................................................................ .................................................... 75 3.20.2.2.1 hdlc mode ........................................................................................................... ........................................ 75 3.20.2.2.2 ss7 mode ............................................................................................................ .......................................... 75 3.20.2.3 interrupt summary ..................................................................................................... ....................................................... 76 3.20.2.4 reset ................................................................................................................. ............................................................... 76 3.20.3 automatic performance report message (t1/j1 only) ....................................................................... ....................................... 77 3.20.4 bit-oriented message transmitter (t1/j1 only) ........................................................................... ............................................... 78 3.20.5 inband loopback code ge nerator (t1/j1 only) ............................................................................. ............................................. 78 3.20.6 all ?zero?s & all ?one?s ................................................................................................ ................................................................... 78 3.20.7 change of frame alignment ............................................................................................... .......................................................... 78 3.21 transmit buffer ........................................................................................................... ......................................................................... 79 3.22 encoder ................................................................................................................... ................................................................................. 79 3.22.1 line code rule .......................................................................................................... ..................................................................... 79 3.22.1.1 t1/j1 mode ............................................................................................................ .......................................................... 79 3.22.1.2 e1 mode ............................................................................................................... ............................................................ 79 3.22.2 bpv error insertion ..................................................................................................... ................................................................... 79 3.22.3 all ?one?s insertion .................................................................................................... .................................................................... 79 3.23 transmit jitter attenuator ................................................................................................ ............................................................ 80 3.24 waveform shaper / line build out .......................................................................................... ....................................................... 81 3.24.1 preset waveform template ................................................................................................ ........................................................... 81 3.24.1.1 t1/j1 mode ............................................................................................................ .......................................................... 81 3.24.1.2 e1 mode ............................................................................................................... ............................................................ 81 3.24.2 line build out (lbo) (t1 only) .......................................................................................... ........................................................... 82 3.24.3 user-programmable arbitrary waveform .................................................................................... ................................................ 82 3.25 line driver ............................................................................................................... ................................................................................ 89 3.26 transmitter impeda nce matching ............................................................................................ ..................................................... 90 3.27 testing and diagnostic facilities ......................................................................................... ........................................................ 91 3.27.1 prbs generator / detector ............................................................................................... ............................................................ 91 3.27.1.1 pattern generator ..................................................................................................... ........................................................ 91 3.27.1.2 pattern detector ...................................................................................................... ......................................................... 91 3.27.2 loopback ................................................................................................................ ........................................................................ 92 3.27.2.1 system loopback ....................................................................................................... ...................................................... 92 3.27.2.1.1 system remote loopback .............................................................................................. .............................. 92 3.27.2.1.2 system local loopback ............................................................................................... ................................. 92 3.27.2.2 payload loopback ...................................................................................................... ...................................................... 92 3.27.2.3 local digital loopback 1 .............................................................................................. .................................................... 92 3.27.2.4 remote loopback ....................................................................................................... ..................................................... 92 3.27.2.5 local digital loopback 2 .............................................................................................. .................................................... 92
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver table of contents iv march 22, 2004 3.27.2.6 analog loopback ....................................................................................................... ....................................................... 92 3.27.3 g.772 non-intrusive monitoring .......................................................................................... .......................................................... 92 3.28 interrupt summary ......................................................................................................... ..................................................................... 95 4 operation ............ ................. ................ .............. ............... .............. .............. .............. .............. .............. ............ ........ 96 4.1 power-on sequence .......................................................................................................... ................................................................... 96 4.2 reset ...................................................................................................................... .................................................................................... 96 4.3 receive / transmit path power down ......................................................................................... .................................................. 96 4.4 microprocessor interface ................................................................................................... .......................................................... 97 4.4.1 spi mode ................................................................................................................. ........................................................................ 97 4.4.2 parallel microprocessor interface ........................................................................................ ........................................................ 98 4.5 indirect register access scheme ............................................................................................ ..................................................... 99 4.5.1 indirect register read access ............................................................................................ ......................................................... 99 4.5.2 indirect register write access ........................................................................................... .......................................................... 99 5 programming information ... ................ ................. ................ ................. ................ ................. ................ ........... 100 5.1 register map ............................................................................................................... .......................................................................... 100 5.1.1 t1/j1 mode ............................................................................................................... ..................................................................... 100 5.1.1.1 direct register ........................................................................................................ ........................................................ 100 5.1.1.2 indirect register ...................................................................................................... ....................................................... 105 5.1.2 e1 mode .................................................................................................................. ...................................................................... 106 5.1.2.1 direct register ........................................................................................................ ........................................................ 106 5.1.2.2 indirect register ...................................................................................................... ....................................................... 111 5.2 register description ....................................................................................................... ................................................................. 113 5.2.1 t1/j1 mode ............................................................................................................... ..................................................................... 114 5.2.1.1 direct register ........................................................................................................ ........................................................ 114 5.2.1.2 indirect register ...................................................................................................... ....................................................... 216 5.2.2 e1 mode .................................................................................................................. ...................................................................... 229 5.2.2.1 direct register ........................................................................................................ ........................................................ 229 5.2.2.2 indirect register ...................................................................................................... ....................................................... 332 6 ieee std 1149.1 jtag test acc ess port .............. ................ ................. .............. .............. ............. ........... ........ 347 6.1 jtag instructions and inst ruction register (ir) ............................................................................ ...................................... 348 6.2 jtag data register ......................................................................................................... ................................................................... 349 6.2.1 device identification register (idr) ..................................................................................... ...................................................... 349 6.2.2 bypass register (byp) .................................................................................................... ............................................................ 349 6.2.3 boundary scan register (bsr) ............................................................................................. ...................................................... 349 6.3 test access port controller ................................................................................................ ...................................................... 352 7 physical and electrical spec ifications .......... ................. ................ ................. .............. ............. .............. 355 7.1 absolute maximum ratings ................................................................................................... ......................................................... 355 7.2 recommended operating conditions ........................................................................................... .............................................. 355 7.3 d.c. characteristics ....................................................................................................... .................................................................. 356 7.4 digital i/o timing characteristics ......................................................................................... ...................................................... 357 7.5 clock frequency requirement ................................................................................................ .................................................... 357 7.6 t1/j1 line receiver elec trical characteristics ............................................................................. ...................................... 358 7.7 e1 line receiver electrical characteristics ................................................................................ ........................................ 359 7.8 t1/j1 line transmitter elec trical characteristics .......................................................................... .................................. 360 7.9 e1 line transmitter electrical characteristics ............................................................................. ................................... 361 7.10 jitter tolerance .......................................................................................................... ...................................................................... 362 7.10.1 t1/j1 mode .............................................................................................................. ...................................................................... 362 7.10.2 e1 mode ................................................................................................................. ....................................................................... 363 7.11 jitter transfer ........................................................................................................... ........................................................................ 364 7.11.1 t1/j1 mode .............................................................................................................. ...................................................................... 364 7.11.2 e1 mode ................................................................................................................. ....................................................................... 365 7.12 microprocessor timing specification ....................................................................................... ................................................ 366 7.12.1 motorola non-multiplexed mode ........................................................................................... ...................................................... 366
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver table of contents v march 22, 2004 7.12.1.1 read cycle specification .............................................................................................. ................................................. 366 7.12.1.2 write cycle specification ............................................................................................. ................................................... 367 7.12.2 intel non-multiplexed mode .............................................................................................. ........................................................... 368 7.12.2.1 read cycle specification .............................................................................................. ................................................. 368 7.12.2.2 write cycle specification ............................................................................................. ................................................... 369 7.12.3 spi mode ................................................................................................................ ....................................................................... 370 ordering information ........ ................. ................ ................. ................. ................ ............... ........... ............ ........ 373
list of tables vi march 22, 2004 list of tables table 1: operating mode selection ............................................................................................ ............................................................................... 14 table 2: related bit / register in chapter 3.1 ................................................................................ ........................................................................... 14 table 3: impedance matching value for the receiver ........................................................................... .................................................................. 15 table 4: related bit / register in chapter 3.2 ................................................................................ ........................................................................... 16 table 5: related bit / register in chapter 3.3 & chapter 3.4 ................................................................... ................................................................. 17 table 6: criteria of speed adjustment start .................................................................................. ............................................................................ 18 table 7: related bit / register in chapter 3.6 ................................................................................ ........................................................................... 18 table 8: excessive zero error definition ..................................................................................... .............................................................................. 19 table 9: los condition in t1/j1 mode ......................................................................................... ............................................................................. 21 table 10: los condition in e1 mode ........................................................................................... ............................................................................... 21 table 11: related bit / register in chapter 3.7 ............................................................................... ............................................................................ 22 table 12: the structure of sf ................................................................................................ ..................................................................................... 23 table 13: the structure of esf ............................................................................................... .................................................................................... 24 table 14: the structure of t1 dm ............................................................................................. .................................................................................. 25 table 15: the structure of slc-96 ............................................................................................ .................................................................................. 26 table 16: interrupt source in t1/j1 frame processor .......................................................................... ...................................................................... 28 table 17: related bit / register in chapter 3.8.1 ............................................................................. ........................................................................... 29 table 18: the structure of ts0 in crc multi-frame ............................................................................ ...................................................................... 33 table 19: fas/nfas bit/pattern error criteria ................................................................................ ............................................................................ 34 table 20: interrupt source in e1 frame processor ............................................................................. ........................................................................ 36 table 21: related bit / register in chapter 3.8.2 ............................................................................. ........................................................................... 37 table 22: monitored events in t1/j1 mode ..................................................................................... ............................................................................ 38 table 23: related bit / register in chapter 3.9.1 ............................................................................. ........................................................................... 39 table 24: monitored events in e1 mode ........................................................................................ ............................................................................. 40 table 25: related bit / register in chapter 3.9.2 ............................................................................. ........................................................................... 41 table 26: red alarm, yellow al arm & blue alarm criteria ...................................................................... ................................................................... 42 table 27: related bit / register in chapter 3.10.1 ............................................................................ .......................................................................... 43 table 28: related bit / register in chapter 3.10.2 ............................................................................ .......................................................................... 44 table 29: related bit / register in chapter 3.11.1 ............................................................................ .......................................................................... 45 table 30: interrupt summarize in hdlc mode ................................................................................... ........................................................................ 46 table 31: related bit / register in chapter 3.11.2 ............................................................................ .......................................................................... 48 table 32: related bit / register in chapter 3.12 .............................................................................. ........................................................................... 49 table 33: related bit / register in chapter 3.13 .............................................................................. ........................................................................... 49 table 34: related bit / register in chapter 3.14 .............................................................................. ........................................................................... 50 table 35: related bit / register in chapter 3.15 .............................................................................. ........................................................................... 52 table 36: a-law digital milliwatt pattern .................................................................................... ................................................................................. 53 table 37: -law digital milliwatt pattern .................................................................................... ................................................................................. 53 table 38: related bit / register in chapter 3.16 .............................................................................. ........................................................................... 54 table 39: operating modes selection in t1/j1 receive path .................................................................... ................................................................. 55 table 40: operating modes selection in e1 receive path ....................................................................... ................................................................... 60 table 41: related bit / register in chapter 3.17 .............................................................................. ........................................................................... 61 table 42: operating modes selection in t1/j1 transmit path ................................................................... ................................................................. 62 table 43: operating modes selection in e1 transmit path ...................................................................... ................................................................... 67 table 44: related bit / register in chapter 3.18 .............................................................................. ........................................................................... 68 table 45: related bit / register in chapter 3.19 .............................................................................. ........................................................................... 69 table 46: related bit / register in chapter 3.20.1.1 .......................................................................... ......................................................................... 71 table 47: e1 frame generation ................................................................................................ .................................................................................. 72 table 48: control over e bits ................................................................................................ ...................................................................................... 72
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver list of tables vii march 22, 2004 table 49: interrupt summary in e1 mode ....................................................................................... ............................................................................. 73 table 50: related bit / register in chapter 3.20.1.2 .......................................................................... ......................................................................... 74 table 51: related bit / register in chapter 3.20.2.1 .......................................................................... ......................................................................... 75 table 52: related bit / register in chapter 3.20.2.2 ~ chapter 3.20.2.4 ........................................................ ............................................................ 76 table 53: aprm message format ................................................................................................ .............................................................................. 77 table 54: aprm interpretation ................................................................................................ .................................................................................... 77 table 55: related bit / register in chapter 3.20.3 ............................................................................ .......................................................................... 78 table 56: related bit / register in chapter 3.20.4 & chapter 3.20.5 ............................................................ .............................................................. 78 table 57: related bit / register in chapter 3.20.6, chapter 3.20.7 & chapter 3.21 ............................................... .................................................... 79 table 58: related bit / register in chapter 3.22 .............................................................................. ........................................................................... 79 table 59: related bit / register in chapter 3.23 .............................................................................. ........................................................................... 80 table 60: puls[3:0] setting in t1/j1 mode .................................................................................... ............................................................................ 81 table 61: lbo puls[3:0] setting in t1 mode ................................................................................... .......................................................................... 82 table 62: transmit waveform value for e1 75 ? .............................................................................................................................. ........................ 83 table 63: transmit waveform value for e1 120 ? .............................................................................................................................. ...................... 83 table 64: transmit waveform value for t1 0~133 ft ............................................................................ ..................................................................... 84 table 65: transmit waveform value for t1 133~266 ft .......................................................................... ................................................................... 84 table 66: transmit waveform value for t1 266~399 ft .......................................................................... ................................................................... 85 table 67: transmit waveform value for t1 399~533 ft .......................................................................... ................................................................... 85 table 68: transmit waveform value for t1 533~655 ft .......................................................................... ................................................................... 86 table 69: transmit waveform value for j1 0~655ft ............................................................................. ...................................................................... 86 table 70: transmit waveform value for ds1 0 db lbo ........................................................................... ................................................................. 87 table 71: transmit waveform value for ds1 -7.5 db lbo ........................................................................ ................................................................ 87 table 72: transmit waveform value for ds1 -15.0 db lbo ....................................................................... ............................................................... 88 table 73: transmit waveform value for ds1 -22.5 db lbo ....................................................................... ............................................................... 88 table 74: related bit / register in chapter 3.24 .............................................................................. ........................................................................... 88 table 75: impedance matching value for the transmitter ....................................................................... ................................................................. 90 table 76: related bit / register in chapter 3.25 & chapter 3.26 ................................................................ ................................................................ 90 table 77: related bit / register in chapter 3.27.1 ............................................................................ .......................................................................... 91 table 78: related bit / register in chapter 3.27.2 & chapter 3.27.3 ............................................................ .............................................................. 94 table 79: related bit / register in chapter 3.28 .............................................................................. ........................................................................... 95 table 80: parallel microprocessor interface .................................................................................. .............................................................................. 98 table 81: related bit / register in chapter 4 ................................................................................. ............................................................................. 99 table 82: ir code ............................................................................................................ .......................................................................................... 348 table 83: idr ................................................................................................................ ............................................................................................. 349 table 84: boundary scan (bs) sequence ........................................................................................ ......................................................................... 349 table 85: tap controller state description ................................................................................... ............................................................................ 352
list of figures viii march 22, 2004 list of figures figure 1. 208-pin pbga (top view) ............................................................................................ ................................................................................. 3 figure 2. receive / transmit line circuit .................................................................................... ................................................................................ 15 figure 3. monitoring receive path ............................................................................................ .................................................................................. 16 figure 4. monitoring transmit path ........................................................................................... .................................................................................. 16 figure 5. jitter attenuator .................................................................................................. .......................................................................................... 18 figure 6. ami bipolar violation error ........................................................................................ ................................................................................... 20 figure 7. b8zs excessive zero error .......................................................................................... ............................................................................... 20 figure 8. hdb3 code violation & excessive zero error ......................................................................... .................................................................... 20 figure 9. e1 frame searching process ......................................................................................... ............................................................................. 31 figure 10. basic frame searching process ..................................................................................... ........................................................................... 32 figure 11. ts16 structure of cas signaling multi-frame ....................................................................... ................................................................... 34 figure 12. standard hdlc packet .............................................................................................. ................................................................................ 45 figure 13. overhead indication in the fifo ................................................................................... ............................................................................ 46 figure 14. standard ss7 packet ............................................................................................... .................................................................................. 47 figure 15. signaling output in t1/j1 mode .................................................................................... ............................................................................. 51 figure 16. signaling output in e1 mode ....................................................................................... ............................................................................... 51 figure 17. t1/j1 to e1 format mapping - g.802 mode ........................................................................... ................................................................... 56 figure 18. t1/j1 to e1 format mapping - one filler every four channels mode .................................................. ................................................... 56 figure 19. t1/j1 to e1 format mapping - continuous channels mode ............................................................. ........................................................ 57 figure 20. no offset when fe = 1 & de = 1 in receive path .................................................................... ................................................................ 58 figure 21. no offset when fe = 0 & de = 0 in receive path .................................................................... ................................................................ 58 figure 22. no offset when fe = 0 & de = 1 in receive path .................................................................... ................................................................ 59 figure 23. no offset when fe = 1 & de = 0 in receive path .................................................................... ................................................................ 59 figure 24. e1 to t1/j1 format mapping - g.802 mode ........................................................................... ................................................................... 63 figure 25. e1 to t1/j1 format mapping - one filler every four channels mode .................................................. ................................................... 63 figure 26. e1 to t1/j1 format mapping - continuous channels mode ............................................................. ........................................................ 64 figure 27. no offset when fe = 1 & de = 1 in transmit path ................................................................... ................................................................ 65 figure 28. no offset when fe = 0 & de = 0 in transmit path ................................................................... ................................................................ 65 figure 29. no offset when fe = 0 & de = 1 in transmit path ................................................................... ................................................................ 66 figure 30. no offset when fe = 1 & de = 0 in transmit path ................................................................... ................................................................ 66 figure 31. dsx-1 waveform template ........................................................................................... ............................................................................. 81 figure 32. t1/j1 pulse template measurement circuit .......................................................................... .................................................................... 81 figure 33. e1 waveform template .............................................................................................. ................................................................................ 81 figure 34. e1 pulse templa te measurement circuit ............................................................................. ...................................................................... 81 figure 35. g.772 non-intrusive monitor ....................................................................................... ............................................................................... 93 figure 36. hardware re set when powere d-up .................................................................................... ...................................................................... 96 figure 37. hardware reset in normal operation ................................................................................ ........................................................................ 96 figure 38. read operation in spi mode ........................................................................................ ............................................................................. 97 figure 39. write operation in spi mode ....................................................................................... ............................................................................... 97 figure 40. jtag architecture ................................................................................................. ................................................................................... 347 figure 41. jtag state diagram ................................................................................................ ................................................................................ 354 figure 42. i/o timing in mode ................................................................................................ ................................................................................... 357 figure 43. t1/j1 jitter tolerance performance requirement .................................................................... ................................................................ 362 figure 44. e1 jitter tolerance performance requirement ....................................................................... ................................................................. 363 figure 45. t1/j1 jitter transfer performance r equirement (at&t62411 / gr-253-core / tr-tsy-000009) ........................... ............................ 364 figure 46. e1 jitter transfer performance requirement (g.736) ................................................................ .............................................................. 365 figure 47. motorola non-mu ltiplexed mode read cycle .......................................................................... ................................................................. 366 figure 48. motorola non-mult iplexed mode write cycle ......................................................................... .................................................................. 367
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver list of figures ix march 22, 2004 figure 49. intel non-multiplexed mode read cycle ............................................................................. ..................................................................... 368 figure 50. intel non-multiplexed mode write cycle ............................................................................ ...................................................................... 369 figure 51. spi timing diagram ................................................................................................ ................................................................................. 370
1 march 22, 2004 IDT82P2284 ? 2002 integrated device technology, inc. dsc-6226/3 quad t1/e1/j1 long haul / short haul transceiver the idt and the idt logo are registered tradem arks of integrated device technology, inc. features line interface ? each link can be configured as t1, e1 or j1 ? supports t1/e1/j1 long haul/short haul line interface ? hps for 1+1 protection without external relays ? receive sensitivity exceeds -36 db @ 772 hz and -43 db @ 1024 hz ? selectable internal line termination impedance: 100 ? (for t1), 75 ? / 120 ? (for e1) and 110 ? (for j1) ? supports ami/b8zs (for t1/j1) and ami/hdb3 (for e1) line encod- ing/decoding ? provides t1/e1/j1 short haul pulse templates, long haul lbo (per ansi t1.403 and fcc68: 0 db, -7.5 db, -15 db, -22 db) and user- programmable arbitrary pulse template ? supports g.772 non-intrusive monitoring ? supports t1.102 line monitor ? transmit line short-circ uit detection and protection ? separate transmit and receive jitter attenuators (2 per link) ? indicates the interval between the write pointer and the read pointer of the fifo in ja ? loss of signal indication with pr ogrammable thresholds according to itut-t g.775, ets 300 233 (e1) and ansi t1.403 (t1/j1) ? supports analog loopback, digital loopback and remote loop- back ? each receiver and transmitter can be individually powered down framer ? each link can be configured as t1, e1 or j1 ? frame alignment/generation for t1 (per itu-t g.704, ta-tsy- 000278, tr-tsy-000008), e1 (per itu- t g.704), j1 (per jt g.704) and un-framed mode ? supports t1/j1 super frame and ex tended super frame, t1 digi- tal multiplexer and switch line carrier - 96, e1 crc multi-frame and signaling multi-frame ? signaling extraction/insert ion for cas and rbs signaling ? provides programmable system interface supporting mitel tm st- bus, at&t tm chi and mvip bus, 8.192 mb/s multiplexed bus and 1.544 mb/s or 2.048 mb/s non-multiplexed bus ? three hdlc controllers per link with separate 128-byte transmit and receive fifos per controller ? supports signaling system #7 (ss7) ? programmable bit insertion and bit inversion on per channel/ timeslot basis ? provides bit oriented mess age (bom) generation and detection ? provides automatic performanc e report message (aprm) genera- tion ? detects and generates alarms (ais, rai) ? provides performance monitor to count bipolar violation error, excess zero error, crc error, framing bit error, far end crc error, out of frame and change of framing alignment position ? supports system loopback, payload loopback, digital loopback and inband loopback ? detects and generates selectable prbs and qrss control interface ? supports serial peripheral interf ace (spi) microprocessor and par- allel intel/motorola non-multiplexed microprocessor interface ? global hardware and software reset ? two general purpose i/o pins ? per link power down general ? flexible reference clock (n x 1.544 mhz or n x 2.048 mhz) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver block diagram 2 march 22, 2004 block diagram receive system interface rsfsn rsign rsdn mrsck mrsfs mrsiga[1]/ mrsigb[1] mrsda[1]/ mrsdb[1] receive payload control frame processor b8zs/ hdb3/ ami decoder receive jitter attenuator waveform shaper / line build out data slicer clk&data recovery (dpll) rtipn rringn transmit system interface tsign mtsfs tsdn mtsck mtsda[1]/ mtsdb[1] mtsiga[1]/ mtsigb[1] transmit payload control frame generator transmit buffer b8zs/ hdb3/ami encoder transmit jitter attenuator line driver ttipn tringn one of the four links (lp 1, 2) (lp 4) g.772 monitor control interface ieee1149.1 jtag tck tms tdi tdo trst vdddio / vdddc / vddar / vddat / vddax / vddap / vddab gnda / gndd ds / rd /sclk cs int a[9:0] d[7:1] note: lp1, 2 - system loopback lp3 - payload loopback lp4 - local digital loopback 1 lp5 - remote loopback lp6 - local digital loopback 2 lp7 - analog loopback rsckn elastic store buffer receive cas/ rbs buffer alarm detector hdlc receiver #1, #2, #3 bit-oriented message receiver inband loopback code detector performance monitor adaptive equalizer receive internal termination tsfsn tsckn bit-oriented message transmitter hdlc transmitter #1, #2, #3 inband loopback code generator automatic performance report message transmit internal termination prbs generator / detector refr mpm spien clock generator refa_out refb_out osci osco clk_sel[2:0] thz (lp 3) (lp 5) (lp 6) (lp 7) r w / wr /sdi reset gpio[1:0] clk_gen_1.544 clk_gen_2.048 d[0]/sdo
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin assignment 3 march 22, 2004 1 pin assignment figure 1. 208-pin pbga (top view) ttip4 tring4 vddat4 vddar4 vddar3 tring3 ttip3 ttip2 tring2 vddar1 tring1 ttip1 vddap reset refa_ out clk_ge n_1.544 nc vddax4 gnda rtip4 vddat3 gnda vddax3 vddax2 vddat2 gnda gnda vddat1 osci refb_ out clk_sel 2 thz nc nc gnda rring4 gnda gnda gnda gnda vddar2 gnda rtip1 vddax1 osco clk_sel 1 ic refr nc nc gnda gnda rring3 rtip3 gnda rtip2 rring2 gnda rring1 vddab gpio1 clk_ge n_2.048 clk_sel 0 ic tsig2/ mtsigb1 nc nc nc gpio0 vdddio vdddio nc tsig1/ mtsiga1 tsd2/ mtsdb1 tsd4 tsig4 gndd nc gndd nc tsfs4 tsd1/ mtsda1 tsd3 tsig3 gndd gndd gndd gndd gndd nc gndd vdddio tsfs3 tsck4 nc nc vdddc vdddc gndd gndd nc vdddio vdddio nc tsck3 tsfs2 nc nc vdddc vdddc vdddc vdddc nc gndd vdddio nc tsck2 tsfs1/ mtsfs nc nc vdddc vdddc vdddc vdddc gndd gndd vdddio nc tsck1/ mtsck nc nc nc nc gndd gndd nc nc nc nc nc nc gndd vdddio vdddio nc nc rsig4 rsfs3 rsfs1/ mrsfs a2 a6 nc d1 cs ic trst gndd nc nc vdddio rsd4 rsig2/ mrsigb1 rsd1/ mrsda1 rsck3 rsck1/ mrsck a3 a7 d7 d2 mpm r w / wr /sdi ic gndd gndd gndd vdddio rsig3 rsd2/ mrsdb1 rsfs4 rsfs2 a0 a4 a8 d6 d3 ds / rd /sclk spien nc tdi tms vdddio nc rsd3 rsig1/ mrsiga1 rsck4 rsck2 a1 a5 a9 d5 d4 d0/sdo int ic tdo tck nc nc 1 2 3 4 5 6 7 8 9 10 11 1 2 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 4 march 22, 2004 2 pin description name type pin no. description line and system interface rtip[1] rtip[2] rtip[3] rtip[4] rring[1] rring[2] rring[3] rring[4] input c11 d8 d6 b4 d11 d9 d5 c4 rtip[1:4] / rring[1:4]: receive bipolar tip/ring for link 1 ~ 4 these pins are the differential line receiver inputs. ttip[1] ttip[2] ttip[3] ttip[4] tring[1] tring[2] tring[3] tring[4] output a12 a8 a7 a1 a11 a9 a6 a2 ttip[1:4] / tring[1:4]: transmit bipolar tip/ring for link 1 ~ 4 these pins are the differential line driver outputs and can be set to high impedance state globally or individu- ally. a logic high on the thz pin sets all these pins to high impedance state. when the t_hz bit (b4, t1/j1- 023h,... / b4, e1-023h,...) * is set to ?1?, the ttipn/tringn pins in the corresponding link are set to high impedance state. besides, ttipn/tringn will also be set to high impedance state by other ways (refer to chapter 3.25 line driver for details). rsd[1] / mrsda[1] rsd[2] / mrsdb[1] rsd[3] rsd[4] high-z output p3 r2 t1 p1 rsd[1:4]: receive side system data for link 1 ~ 4 the processed data stream is output on these pins. in receive clock master mode, the rsdn pins are updated on the active edge of the corresponding rsckn. in receive clock slave mode, selected by the rslvck bit (b4, t1/j1-010h / b4, e1-010h), the rsdn pins are updated on the active edge of the corresponding rsckn or all four rsdn pins are updated on the active edge of rsck[1]. mrsda[1] / mrsdb[1]: multiplexed receive side system data a / b for link 1 ~ 4 in receive multiplexed mode, the mrsda[1] pin or the mrsdb[1] pin is used to output the processed data stream. using a byte-interleaved multiplexing scheme , the mrsda[1]/mrsdb[1] pins output the data from link 1 to link 4. the data on the mrsda[1]/mrsdb[1] pin is updated on the active edge of the mrsck. the data on mrsda[1] is the same as the data on mrsdb[1]. mrsdb[1] is for back-up purpose. rsig[1] / mrsiga[1] rsig[2] / mrsigb[1] rsig[3] rsig[4] high-z output t2 p2 r1 n3 rsig[1:4]: receive side system signaling for link 1 ~ 4 the extracted signaling bits are output on these pins. they are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data output on the corresponding rsdn pin. in receive clock master mode, the rsign pins are up dated on the active edge of the corresponding rsckn. in receive clock slave mode, selected by the rslvck bit (b4, t1/j1-010h / b4, e1-010h), the rsign pins are updated on the active edge of the corresponding rsckn or all four rsign are updated on the active edge of rsck[1]. mrsiga[1] / mrsigb[1]: multiplexed receive side system signaling a / b for link 1 ~ 4 in receive multiplexed mode, the mrsiga[1] pin or the mrsigb[1] pin is used to output the extracted signal- ing bits. the signaling bits are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data output on the corresponding mrsda[1]/mrsdb[1] pins. using the byte-interleaved multiplexing scheme, the mrsiga[1]/mrsigb[1] pins output the signaling bits from link 1 to link 4. the signaling bits on the mrsiga[1]/mrsigb[1] pin is updated on the active edge of the mrsck. the signaling bits on mrsiga[1] is the same as the signaling bits on mrsigb[1]. mrsigb[1] is for back-up purpose. note: * the contents in the brackets indicate the position of the preceding bit and the address of t he register. after the address, if the punctuation ?,...? is followed, this bit is in a per-link control reg- ister and the listed address belongs to link 1. users can find the omitted addresses in chapter 5. if there is no punctuation f ollowed the address, this bit is in a global control register.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 5 march 22, 2004 rsfs[1] / mrsfs rsfs[2] rsfs[3] rsfs[4] output / input n5 r4 n4 r3 rsfs[1:4]: receive side system frame pulse for link 1 ~ 4 in t1/j1 receive clock master mode, rsfsn outputs the pulse to indicate each f-bit, every second f-bit in sf frame, the first f-bit of every sf/esf/t1 dm/slc-9 6 multi-frame or the first f-bit of every second sf multi-frame. in t1/j1 receive clock slave mode, rsfsn inputs the pulse at a rate of integer multiple of 125 s to indicate the start of a frame. in e1 receive clock master mode, rsfsn outputs the pulse to indicate the basic frame, crc multi-frame, signaling multi-frame, or both the crc multi-frame an d signaling multi-frame, or the ts1 and ts16 over- head. in e1 receive clock slave mode, rsfsn inputs the pulse at a rate of integer multiple of 125 s to indicate the start of a frame. rsfsn is updated/sampled on the active edge of the corresponding rsckn. the active polarity of rsfsn is selected by the fsinv bit (b4, t1/j1-048h,... / b4, e1-048h,...). mrsfs: multiplexed receive side system frame pulse for link 1 ~ 4 in receive multiplexed mode, mrsfs inputs the pulse at a rate of integer multiple of 125 s to indicate the start of a frame on the multiplexed data bus. mrsfs is sampled on the active edge of mrsck. the active polarity of mrsfs is selected by the fsin v bit (b4, t1/j1-048h,... / b4, e1-048h,...). rsfs[1:4]/mrsfs are schmitt-triggered inputs/outputs with pull-up resistors. rsck[1] / mrsck rsck[2] rsck[3] rsck[4] output / input p5 t4 p4 t3 rsck[1:4]: receive side system clock for link 1 ~ 4 in receive clock master mode, the rsckn pins output a (gapped) 1.544 mhz (for t1/j1 mode) / 2.048 mhz (for e1 mode) clock used to update the signal on the corresponding rsdn, rsign and rsfsn pins. in receive clock slave mode, the rsckn pins input a 1.544 mhz (for t1/j1 mode only), 2.048 mhz or 4.096 mhz clock used to update the signals on the corresponding rsdn and rsign pins and sample the signals on the corresponding rsfsn pins. selected by the rslvck bit (b4, t1/j1-010h / b4, e1-010h), the rsck[1] pin can be used for all four links. mrsck: multiplexed receive side system clock for link 1 ~ 4 in receive multiplexed mode, mrsck inputs a 8.192 mhz or 16.384 mhz clock used to update the signals on the corresponding mrsda/mrsdb and mrsiga/mrsigb pins and sample the signal on the corresponding mrsfs pin. rsck[1:4]/mrsck are schmitt-triggered i nputs/outputs with pull-up resistors. tsd[1] / mtsda[1] tsd[2] / mtsdb[1] tsd[3] tsd[4] input g2 f2 g3 f3 tsd[1:4]: transmit side system data for link 1 ~ 4 the data stream from the system side is input on these pins. in transmit clock master mode, the tsdn pins are sampled on the active edge of the corresponding tsckn. in transmit clock slave mode, selected by the tslvck bit (b1, t1/j1-010h / b1, e1-010h), the tsdn pins are sampled on the active edge of the corresponding tsckn or all four tsdn pins are sampled on the active edge of tsck[1]. mtsda[1] / mtsdb[1]: multiplexed transmit side system data a / b for link 1 ~ 4 in transmit multiplexed mode, selected by the mtsda bit (b2, t1/j1-010h / b2, e1-010h), the mtsda[1] pin or the mtsdb[1] pin is used to input the data stream. using a byte-interleaved multiplexing scheme, the mtsda[1]/mtsdb[1] pins input the data for link 1 to link 4. the data on the mtsda[1]/mtsdb[1] pins are sampled on the active edge of mtsck. tsd[1:4]/mtsda[1]/mtsdb[1] ar e schmitt-triggered inputs. name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 6 march 22, 2004 tsig[1] / mtsiga[1] tsig[2] / mtsigb[1] tsig[3] tsig[4] input f1 e1 g4 f4 tsig[1:4]: transmit side system signaling for link 1 ~ 4 the signaling bits are input on these pins. they are located in the lower nibble (b5 ~ b8) and are channel/ timeslot-aligned with the data input on the corresponding tsdn pin. in transmit clock master mode, tsign is sampled on the active edge of the corresponding tsckn. in transmit clock slave mode, selected by the tslvck bit (b1, t1/j1-010h / b1, e1-010h), tsign is sam- pled on the active edge of the corresponding tsckn or all four tsign are updated on the active edge of tsck[1]. mtsiga[1] / mtsigb[1]: multiplexed transmit side system signaling a / b for link 1 ~ 4 in transmit multiplexed mode, selected by the mtsda bit (b2, t1/j1-010h / b2, e1-010h), the mtsiga[1] pin or the mtsigb[1] pin is used to input the signaling bits. the signaling bits are located in the lower nibble (b5 ~ b8) and are channel/timeslot-aligned with the data input on the corresponding mtsda[1]/mtsdb[1] pin. using the byte-interleaved multiplexing scheme, the mtsiga[1]/mtsigb[1] pins input the signaling bits for link 1 to link 4. the signaling bits on the mtsiga[1]/mtsigb[1] pin is sampled on the active edge of mtsck. tsig[1:4]/mtsiga[1]/mtsigb[1] are schmitt-triggered inputs. tsfs[1] / mtsfs tsfs[2] tsfs[3] tsfs[4] output / input k2 j2 h1 g1 tsfs[1:4]: transmit side system frame pulse for link 1 ~ 4 in t1/j1 transmit clock master mode, tsfsn outputs the pulse to indicate each f-bit or the first f-bit of every sf/esf/t1 dm/slc-96 multi-frame. in t1/j1 transmit clock slave mode, tsfsn inputs the pulse to indicate each f-bit or the first f-bit of every sf/esf/t1 dm/slc-96 multi-frame. in e1 transmit clock master mode, tsfsn outputs the pulse to indicate the basic frame, crc multi-frame and/or signaling multi-frame. in e1 transmit clock slave mode, tsfsn inputs the pulse to indicate the basic frame, crc multi-frame and/ or signaling multi-frame. tsfsn is updated/sampled on the active edge of the corresponding tsckn. the active polarity of tsfsn is selected by the fsinv bit (b1, t1/j1-042h,... / b1, e1-042h,...). mtsfs: multiplexed transmit side system frame pulse for link 1 ~ 4 in t1/j1 transmit multiplexed mode, mtsfs inputs the pulse to indicate each f-bit or the first f-bit of every sf/esf/t1 dm/slc-96 multi-frame of one link on the multiplexed data bus. in e1 transmit multiplexed mode, mtsfs inputs the pulse to indicate each basic frame, crc multi-frame and/or signaling multi-frame of one link on the multiplexed data bus. mtsfs is sampled on the active edge of mtsck. the active polarity of mtsfs is selected by the fsinv bit (b1, t1/j1-042h,... / b1, e1-042h,...). tsfs[1:4]/mtsfs are schmitt-triggered inputs/outputs with pull-up resistors. tsck[1] / mtsck tsck[2] tsck[3] tsck[4] output / input l1 k1 j1 h2 tsck[1:4]: transmit side system clock for link 1 ~ 4 in transmit clock master mode, tsckn outputs a (gapped) 1.544 mhz (for t1/j1 mode) / 2.048 mhz (for e1 mode) clock used to sample the signal on the corresponding tsdn and tsign pins and update the signal on the corresponding tsfsn pin. in transmit clock slave mode, tsckn inputs a 1.544 mhz (for t1/j1 mode only), 2.048 mhz or 4.096 mhz clock used to sample the signal on the corresponding tsdn, tsign and tsfsn pins. selected by the tslvck bit (b1, t1/j1-010h / b1, e1-010h), the tsck[1] can be used for all four links. mtsck: multiplexed transmit side system clock for link 1 ~ 4 in transmit multiplexed mode, mtsck inputs a 8.192 mhz or 16.384 mhz clock used to sample the signal on the corresponding mtsda/mtsdb, mtsiga/mtsigb and mtsfs pins. tsck[1:4]/mtsck are schmitt-triggered inputs/outputs with pull-up resistors. clock generator name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 7 march 22, 2004 osci input b13 osci: crystal oscillator input this pin is connected to an external clock source. the clock frequency of osci is defined by clk_sel[2:0]. the clock accuracy should be 32 ppm and duty cycle should be from 40% to 60%. osco output c13 osco: crystal oscillator output this pin outputs the inverted, buffered clock input from osci. clk_sel[0] clk_sel[1] clk_sel[2] input d15 c14 b15 clk_sel[2:0]: clock selection these three pins select the input clock signal: when the clk_sel[2] pin is low, the input clock signal is n x 1.544 mhz; when the clk_sel[2] pin is high, the input clock signal is n x 2.048 mhz. when the clk_sel[1:0] pins are ?00?, the n is 1; when the clk_sel[1:0] pins are ?01?, the n is 2; when the clk_sel[1:0] pins are ?10?, the n is 3; when the clk_sel[1:0] pins are ?11?, the n is 4. clk_sel[2:0] are schmitt-trigger inputs. clk_gen_1.544 output a16 clk_gen_1.544: clock generator 1.544 mhz output this pin outputs the 1.544 mhz clock signal generated by the clock generator. clk_gen_2.048 output d14 clk_gen_2.048: clock generator 2.048 mhz output this pin outputs the 2.048 mhz clock signal generated by the clock generator. refa_out output a15 refa_out: reference clock output a when no los is detected, this pin outputs a recovered clock from the clock and data recovery function block of one of the four links. the link is selected by the ro1[1:0] bits (b1~0, t1/j1-007h / b1~0, e1-007h). when los is detected, this pin outputs mclk or high level, as selected by the refh_los bit (b0, t1/j1- 03eh,... / b0, e1-03eh,...). * refb_out output b14 refb_out: reference clock output b when no los is detected, this pin outputs a recovered clock from the clock and data recovery function block of one of the four links. the link is selected by the ro2[1:0] bits (b4~3, t1/j1-007h / b4~3, e1-007h). when los is detected, this pin outputs mclk or high level, as selected by the refh_los bit (b0, t1/j1- 03eh,... / b0, e1-03eh,...). * control interface reset input a14 reset : reset (active low) a low pulse for more than 100 ns on this pin resets the device. all the registers are accessible 2 ms after the reset. the reset pin is a schmitt-trigger input with a weak pull-up resistor. gpio[0] gpio[1] output / input e13 d13 general purpose i/o [1:0] these two pins can be defined as input pins or output pins by the dir[1:0] bits (b1~0, t1/j1-006h / b1~0, e1- 006h) respectively. when the pins ar e input, their polarities ar e indicated by the level[1 :0] bits (b3~2, t1/j1- 006h / b3~2, e1-006h) respectively. when the pins are output, their polarities are controlled by the level[1:0] bits (b3~2, t1/j1-006h / b3~2, e1-006h) respectively. gpio[1:0] are schmitt-trigger input/output with a pull-up resistor. thz input b16 thz: transmit high-z a high level on this pin puts all the ttipn/tringn pins into high impedance state. thz is a schmitt-trigger input. int output t11 int : interrupt (active low) this is the open drain, active low interrupt output. this pin will stay low until all the active unmasked interrupt indication bits are cleared. refr output c16 refr: this pin should be connected to ground via an external 10k resistor. name type pin no. description note: * this feature is available in zb revistion only.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 8 march 22, 2004 cs input n10 cs : chip select (active low) this pin must be asserted low to enable the microprocessor interface. the signal must be asserted high at least once after power up to clear the internal test modes. a transition from high to low must occur on this pin for each read/write operation and can not return to high until the operation is completed. cs is a schmitt-trigger input. a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] input r5 t5 n6 p6 r6 t6 n7 p7 r7 t7 a[9:0]: address bus in parallel mode, the signals on these pins select the register for the microprocessor to access. in spi mode, these pins should be connected to ground. a[9:0] are schmitt-trigger inputs. d[0] / sdo d[1] d[2] d[3] d[4] d[5] d[6] d[7] output / input t10 n9 p9 r9 t9 t8 r8 p8 d[7:0]: bi-directional data bus in parallel mode, the signals on these pins are the data for read / write operation. in spi mode, the d[7:1] pins should be connected to the ground through a 10 k resistor. d[7:0] are schmitt-trigger inputs/outputs. sdo: serial data output in spi mode, the data is serially output on this pin. mpm input p11 mpm: micro controller mode in parallel mode, set this pin low for motorola mode or high for intel mode. in spi mode, set this pin to a fixed level (high or low). this pin is useless in spi mode. mpm is a schmitt-trigger input. r w / wr / sdi input p10 r w : read / write select in parallel motorola mode, this pin is active high for read operation and active low for write operation. wr : write strobe (active low) in parallel intel mode, this pin is active low for write operation. sdi: serial data input in spi mode, the address/control and/or data are serially input on this pin. r w / wr / sdi is a schmitt-trigger input. ds / rd / sclk input r10 ds : data strobe (active low) in parallel motorola mode, this pin is active low. rd : read strobe (active low) in parallel intel mode, this pin is active low for read operation. sclk: serial clock in spi mode, this pin inputs the timing for the sdo and sdi pins. the signal on the sdo pin is updated on the falling edge of sclk, while the signal on the sdi pin is sampled on the rising edge of sclk. ds / rd / sclk is a schmitt-trigger input. spien input r11 spien: serial microprocessor interface enable when this pin is low, the microprocessor interface is in parallel mode. when this pin is high, the microprocessor interface is in spi mode. spien is a schmitt-trigger input. jtag (per ieee 1149.1) name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 9 march 22, 2004 trst input n12 trst : test reset (active low) a low signal on this pin resets the jtag test port. this pin is a schmitt-triggered input with an internal pull-up resistor. it must be connected to the reset pin or ground when jtag is not used. tms input r14 tms: test mode select the signal on this pin controls the jtag test performance and is sampled on the rising edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tck input t14 tck: test clock the clock for the jtag test is input on this pin. tdi and tms are sampled on the rising edge of tck and tdo is clocked out of the device on the falling edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tdi input r13 tdi: test input the test data is sampled at this pin on the rising edge of tck. this pin is a schmitt-triggered input with an internal pull-up resistor. tdo high-z t13 tdo: test output the test data are output on this pin. it is updated on the falling edge of tck. this pin is high-z except during the process of data scanning. power & ground vdddio power e14 e15 g16 h14 h15 j15 k15 m15 m16 n16 p16 r15 vdddio: 3.3 v i/o power supply vdddc power h7 h8 j7 j8 j9 j10 k7 k8 k9 k10 vdddc: 1.8 v digital core power supply vddar[1] vddar[2] vddar[3] vddar[4] power a10 c9 a5 a4 vddar[8:1]: 3.3 v power supply for receiver vddat[1] vddat[2] vddat[3] vddat[4] power b12 b9 b5 a3 vddat[8:1]: 3.3 v power supply for transmitter vddax[1] vddax[2] vddax[3] vddax[4] power c12 b8 b7 b2 vddax[8:1]: 3.3 v power supply for transmit driver name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 10 march 22, 2004 vddap power a13 vddap: 3.3 v power analog pll vddab power d12 vddab: 3.3 v power analog bias gnda ground b3 b6 b10 b11 c3 c5 c6 c7 c8 c10 d3 d4 d7 d10 gnda: analog ground gndd ground f13 f15 g7 g8 g9 g10 g13 g15 h9 h10 j14 k13 k14 l14 l15 m14 n13 p13 p14 p15 gndd: digital ground test ic - c15 d16 n11 p12 t12 ic: internal connected these pins are for idt use only and should be connected to ground. others name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver pin description 11 march 22, 2004 nc - b1, c1, c2, d1, d2, e2, e3, e4, e16, f14, f16, g14, h3, h4, h13, h16, j3, j4, j13, j16, k3, k4, k16, l2, l3, l4, l13, l16, m1, m2, m3, m4, m13, n1, n2, n8, n14, n15, r12, r16, t15, t16 nc: not connected name type pin no. description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 12 march 22, 2004 3 functional description the IDT82P2284 is a highly featur ed single device solution for t1/ e1/j1 trunks. each link of the IDT82P2284 can be independently config- ured. the configuration is perform ed through an spi or parallel micro- processor interface. line interface - receive path in the receive path, the signals from the line side are coupled into the rtipn and rringn pins and pass through an impedance termina- tor. an adaptive equalizer is provided to increase the sensitivity for small signals. clock and data are recovered from the digital pulses output from the slicer. after passing through t he receive jitter attenuator (can be enabled or disabled), the recovered dat a is decoded using b8zs (for t1/ j1) / hdb3 (for e1) or ami line code rules and clocked into the frame processor. loss of signal, line code violations and excessive zero are detected. framer - receive path in t1/j1 mode, the recovered data and clock of each link can be configured in super frame (sf), ex tended super frame (esf), t1 digi- tal multiplexer (dm) or switch line carrier - 96 (slc-96) formats. (the t1 dm and slc-96 formats only exist in t1 mode). the framing can also be bypassed (unframed mode). the fr amer detects and indicates the out of sf/esf/dm/slc-96 synchroni zation event, the yellow, red and ais alarms. the framer also detec ts the presence of inband loopback codes and bit-oriented messages. fram e alignment signal errors, crc- 6 errors, out of sf/esf/t1 dm/slc-96 events and frame alignment position changes are counted. up to three hdlc links (in esf and t1 dm format) or two hdlc links (i n sf and slc-96 format) are provided to extract the hdlc message on the dl bit (in esf format) / d bit in ch24 (in t1 dm format) or any arbitr ary position. in the t1/j1 receive path, signaling debounce, signaling freeze, idle code substitution, digital milliwatt code insertion, idle code insertion, data inversion and pattern generation or detection are supported on a per-channel basis. an elastic store buffer that supports contro lled slip and adaptation to backplane timing may be enabled. in the receive system interface, various operat- ing modes can be selected to output signals to the system. in e1 mode, the recovered data and clock of each link can be con- figured to frame to basic frame, crc multi-frame and signaling multi- frame. the framing can be bypass ed (unframed mode). the framer detects and indicates the following event: out of basic frame sync, out of crc multi-frame, out of signali ng multi-frame, remote alarm indi- cation signal and remote signaling mu lti-frame alarm indication signal. the framer also monitors red and ais alarms. basic frame alignment signal errors, far end block er rors (febe) and crc errors are counted. up to three hdlc links ar e provided to extract the hdlc mes- sage on ts16, the sa national bits or any arbitrary timeslot. in the e1 receive path, signaling debounce, signali ng freezing, idle code substitu- tion, digital milliwatt code insertion, trunk conditioning, data inversion and pattern generation or detection ar e also supported on a per-timeslot basis. an elastic store buffer that supports slip buffering and adaptation to backplane timing may be enabled. in the receive system interface, various operating modes can be sele cted to output signals to the sys- tem. system interface on the system side, if the device is in t1/j1 mode, the data stream of 1.544 mbit/s can be converted to/fr om the data stream of 2.048 mbit/s by software configuration. in additi on, the four links can be grouped into one set. the set can be multiplexed to or de-multiplexed from one of the two 8.192 mbit/s buses. if the device is in e1 mode, the four links can be multiplexed to or de-multiplexed from one of the two 8.192 mbit/s buses. framer - transmit path in the transmit path, the transmit system interface inputs the sig- nals with various operat ing modes. in t1/j1 mode, the signals can be processed by a transmit payload contro l to execute the signaling inser- tion, idle code substitution, data inse rtion, data inversion and test pattern generation or detection on a per-c hannel basis. the transmit path of each transceiver can be configured to generate sf, esf, t1 dm or slc- 96. the framer can also be disabl ed (unframed mode). the framer can transmit yellow alarm and ais alar m. inband loopback codes and bit ori- ented message can be transmitted. up to three hdlc links (in esf and t1 dm format) or two hdlc link s (in sf and slc-96 format) are pro- vided to insert the hdlc message on the dl bit (in esf format) / d bit in ch24 (in t1 dm format) or any arbi trary position. after passing through a transmit buffer, the processed data and clock are input to the encoder. in e1 mode, the signals can be processed by a transmit payload control to execute the signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection on a per-timeslot basis. the transmit path of each transceiver can be config- ured to generate basic frame, cr c multi-frame and signaling multi- frame. the framer can be disabled (unframed mode). the framer can transmit remote alarm indication signal, the remote signaling multi- frame alarm indication signal, ais alarm and febe. three hdlc links are provided to insert the hdlc message on ts16, the sa national bits or any arbitrary timeslot. the proc essed data and clock are input to the encoder. line interface - transmit path the data is encoded using ami or b8zs (for t1/j1) and hdb3 (for e1) line code rules. the transmit jitter attenuator, if enabled, is pro- vided with a fifo in the transmit data path. a de-jittered clock is gener- ated by an integrated digital phase-lo cked loop and is used to read data from the fifo. the shapes of t he pulses are user programmable to ensure that the t1/e1/j1 pulse template is met after the signal passing through different cable lengths and types. bipolar violation can be inserted for diagnostic purposes if ami line code rule is enabled. the signal is transmitted on the ttipn and tringn pins through an imped- ance terminator.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 13 march 22, 2004 test and diagnoses to facilitate the testing and diagnostic functions, analog loopback, remote digital loopback, remote loopback, local digital loopback, payload loopback and system loopback are also integrated in the IDT82P2284. a programmable ps eudo random bit sequence can be generated in receive/transmit direction and detected in the opposite direction for testing purpose. the g.772 non-intrusive monitori ng and jtag are also supported by the IDT82P2284.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 14 march 22, 2004 3.1 t1 / e1 / j1 mode selection each link in the IDT82P2284 can be configured as a duplex t1 transceiver, or a duplex e1 transceiv er, or a duplex j1 transceiver. when it is in t1 mode, super frame (sf), extended super frame (esf), t1 digital multiplexer (t1 dm) and switch line carrier - 96 (slc-96) fram- ing formats can be selected. when it is in j1 mode, super frame (sf) and extended super frame (esf) formats can be selected. all the selections are made by the temode bit, the t1/j1 bit and the fm[1:0] bits as shown in table 1. table 1: operating mode selection temode t1/j1 fm[1:0] operating mode 1 0 0 0 t1 mode sf format 0 1 t1 mode esf format 1 0 t1 mode t1 dm format 1 1 t1 mode slc-96 format 1 0 0 j1 mode sf format 0 1 j1 mode esf format 0 x x e1 mode table 2: related bit / register in chapter 3.1 bit register address (hex) temode t1/j1 or e1 mode 020, 120, 220, 320 t1/j1 fm[1:0]
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 15 march 22, 2004 3.2 receiver impedance matching the receiver impedance matching c an be realized by using internal impedance matching circuit or exte rnal impedance matching circuit. when the r_term[2] bit is ?0?, the internal impedance matching circuit is enabled. 100 ? , 110 ? , 75 ? or 120 ? internal impedance matching circuit can be selected by the r_term[1:0] bits. when the r_term[2] bit is ?1?, the internal impedance matching circuit is disabled, and different extern al resistors should be used to real- ize different impedance matching. figure 2 shows the appropriate components to connect with the cable for one link. table 3 lists the recommended impedance matching value for the receiver. figure 2. receive / transmit line circuit in short haul applications, after the data stream passes through the receive internal impedance circuitry, the non-intrusive monitoring can be performed between two devices. the m onitored link of one device is in normal operation, and the monitoring li nk of the other device taps the monitored one through a high impedanc e bridging circuit (refer to figure 3 and figure 4). because of t he high resistance bridging circuit, the signal arriving at the rtipn/rringn of the monitoring link is dramat- ically attenuated. to compensate this attenuation, the monitor gain can be used to boost the signal by 22 db, 26 db and 32 db selected by the mg[1:0] bits. for normal operation, the monitor gain should be set to 0 db, i.e. the monitor gain of the monitored link should be 0 db. table 3: impedance matching value for the receiver cable configuration internal termination external termination r_term[2:0] r r r_term[2:0] r r 75 ? (e1) 0 0 0 120 ? 1 x x 75 ? 120 ? (e1) 0 0 1 120 ? 100 ? (t1) 0 1 0 100 ? 110 ? (j1) 0 1 1 110 ? a b ? ? ?? r x line r r ? ? t x line r t r t rtip rring tring ttip IDT82P2284 (one of the four identical links) vddax vddax d4 d3 d2 d1 1 : 1 2 : 1 d6 d5 d8 d7 cp vddar vddar note : 1. common decoupling capacitor 2. cp 0-560 (pf) 3. d1 - d8, motorola - mbr0540t1; international rectifier - 11dq04 or 10bq060 ? f gnda vddax 68 f 1 3.3 v ? f gnda vddar 68 f 3.3 v 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 16 march 22, 2004 figure 3. monitoring receive path figure 4. monitoring transmit path rtipn rringn rtipn rringn monitored link monitoring link dsx cross connect point r monitor gain = 0 db monitor gain =22/26/32 db ttipn tringn rtipn rringn monitored link monitoring link dsx cross connect point r monitor gain =22/26/32 db table 4: related bit / register in chapter 3.2 bit register address (hex) r_term[2:0] transmit and receive termination configuration 032, 132, 232, 332 mg[1:0] receive configuration 2 02a, 12a, 22a, 32a
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 17 march 22, 2004 3.3 adaptive equalizer the adaptive equalizer can remove most of the signal distortion due to intersymbol interference caus ed by cable attenuation and distor- tion. usually, the adaptive equalizer is off in short haul applications and is on in long haul applications, whic h is configured by the eq_on bit. the peak detector keeps on meas uring the peak value of the incoming signals during a selectable observation period. the observa- tion period is selected by the updw [1:0] bits. a shorter observation period allows quicker response to pulse amplitude variation, while a longer observation period can mini mize the possible overshoots. based on the observed peak value for a period, the equalizer will be adjusted to achieve a normalized si gnal. the latt[4:0] bits indicate the signal attenuation introduced by t he cable in approximately 2 db per step. in short haul application, the receive sensitivity is -10 db in both t1/ j1 and e1 modes. in long haul application, the receive sensitivity is -36 db in t1/j1 mode or -43 db in e1 mode. 3.4 data slicer the data slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. the criteria of mark or space generation are based on a selected ratio of the incoming signal amplitude against the peak value detected during the observation period. this ratio is selected by the slice[1:0] bits. the output of the data slicer is forwarded to t he clock and data recovery unit. 3.5 clock and data recovery the clock and data recovery is used to recover the clock signal from the received data. it is accomplished by digital phase locked loop (dpll). the recovered clock tracks t he jitter in the data output from the data slicer and keeps the phase relationship between data and clock during the absence of the incoming pulse. table 5: related bit / register in chapter 3.3 & chapter 3.4 bit register address (hex) eq_on receive configuration 1 029, 129, 229, 329 updw[1:0] receive configuration 2 02a, 12a, 22a, 32a slice[1:0] latt[4:0] line status register 1 037, 137, 237, 337
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 18 march 22, 2004 3.6 receive jitter attenuator the receive jitter attenuator of each link can be chosen to be used or not. this selection is made by the rja_e bit. the jitter attenuator consists of a fifo and a dpll, as shown in figure 5. figure 5. jitter attenuator the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bi ts, as selected by the rja_dp[1:0] bits. accordingly, the constant delay produced by the jitter attenuator is 16 bits, 32 bits or 64 bits. the 128-bi t fifo is used when large jitter tol- erance is expected, while the 32-bit fifo is used in delay sensitive applications. the dpll is used to generate a de-jittered clock to clock out the data stored in the fifo. the dpll can only attenuate the incoming jitter whose frequency is above corner fre quency (cf). the jitter whose fre- quency is lower than the cf passes through the dpll without any atten- uation. in t1/j1 applications, the cf of the dpll can be 5 hz or 1.26 hz, as selected by the rja_bw bit. in e1 applications, the cf of the dpll can be 6.77 hz or 0.87 hz, as selected by the rja_bw bit. the lower the cf is, the longer time is needed to achieve synchronization. if the incoming data moves faster than the outgoing data, the fifo will overflow. if the incoming data moves slower than the outgoing data, the fifo will underflow. the overflow or underflow is captured by the rja_is bit. when the rja_is bit is ?1?, an interrupt will be reported on the int pin if enabled by the rja_ie bit. to avoid overflow or underflow, the ja-limit function can be enabled by setting the rja_limt bit. when the ja-limit function is enabled, the speed of the outgoing data will be adjusted automatically if the fifo is close to its full or em ptiness. the criteria of speed adjust- ment start are listed in table 6. t hough the ja-limit function can reduce the possibility of fifo overflow and underflow, the quality of jitter attenu- ation is deteriorated. selected by the rjitt_test bit, the real time interval between the read and write pointer of the fifo or the peak-peak interval between the read and write pointer of the fifo can be indicated in the rjitt[6:0] bits. when the rjitt_test bit is ?0 ?, the current interval between the read and write pointer of the fifo will be written into the rjitt[6:0] bits. when the rjitt_test bit is ?1?, the current interval will be compared with the old one in the rjitt[6:0] bits and the larger one will be indi- cated by the rjitt[6:0] bits. the performance of receive jitter attenuator meets the itu-t i.431, g.703, g.736 - 739, g.823, g.824, etsi 300011, etsi tbr 12/ 13, at&t tr62411, tr43802, tr-t sy 009, tr-tsy 253, tr-try 499 standards. refer to chapter 7.10 jitter tolerance and chapter 7.11 jitter transfer for details. table 6: criteria of speed adjustment start fifo depth criteria of speed adjustment start 32 bits 2-bit close to full or empty 64 bits 3-bit close to full or empty 128 bits 4-bit close to full or empty fifo 32/64/128 dpll jittered data de-jittered data jittered clock de-jittered clock write pointer read pointer table 7: related bit / register in chapter 3.6 bit register address (hex) rja_e receive jitter attenuation configuration 027, 127, 227, 327 rja_dp[1:0] rja_bw rja_limt rjitt_test rja_is interrupt status 1 03b, 13b, 23b, 33b rja_ie interrupt enable control 1 034, 134, 234, 334 rjitt[6:0] receive jitter measure value indication 039, 139, 239, 339
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 19 march 22, 2004 3.7 decoder 3.7.1 line code rule 3.7.1.1 t1 / j1 mode in t1/j1 mode, the ami and b8zs line code rules are provided. the selection is made by the r_md bit. 3.7.1.2 e1 mode in e1 mode, the ami and hdb3 line code rules are provided. the selection is made by the r_md bit. 3.7.2 decode error detection 3.7.2.1 t1 / j1 mode the decode errors can be divided in to three types in t1/j1 mode: 1. bipolar violation (bpv) error: when ami line code rule is used, the bpv error will be detected if two consecutive pulses are received with the same polarity (refer to figur e 6). the event of the bipolar viola- tion (bpv) error is forwarded to the performance monitor. 2. b8zs code violation (cv) error: when b8zs line code rule is used, a cv error is detected when the received code does not match the standard b8zs line code pattern (ex pect the excessive zero error). 3. excessive zero (exz) error: exz error can be detected in both ami and b8zs line code rules. there are two standards defining the exz error: ansi and fcc. the exz_d ef bit chooses a standard for the corresponding link to judge the exz erro r. table 8 shows the definition of exz. to count the event of the excessive zero (exz) error, the exz_err[1:0] bits should be set to ?01?. the excessive zero (exz) error is counted in an internal 16-bit exz counter. the content in the exz counter is transferred to the exz error counter l-byte & h-byte registers in two ways: a. when the cnt_md bit is ?0?, the manual-report mode is selected. the exz counter transfers its content to the exz error counter l-byte & h-byte registers w hen there is a transition from ?0? to ?1? on the cnt_trf bit; b. when the cnt_md bit is ?1?, the auto-report mode is selected. the exz counter transfers its content to the exz error counter l-byte & h-byte registers every one second automatically. after the content in the counter is transferred to the exz error counter l-byte & h-byte registers, the counter will be cleared to ?0? and start a new round counting automatically . no error event is lost during data transferring. the overflow of the counter is reflected by the cntov_is bit, and can trigger an interrupt if the corresponding cnt_ie bit is set. when the bipolar violation (bpv) error or the b8zs code violation (cv) error is detected, it will be indicated by the cv_is bit. when the excessive zero (exz) error is detec ted, it will be indicated by the exz_is bit. when the cv_is bit or the exz_is bit is ?1?, an interrupt will be reported by the int pin if enabled by the corresponding cv_ie bit or the exz_ie bit. 3.7.2.2 e1 mode the decode errors can be divided into three types in e1 mode: 1. bipolar violation (bpv) error: when ami line code rule is used, the bpv error will be detected if tw o consecutive pulses are received with the same polarity (refer to figu re 6). the event of the bipolar viola- tion (bpv) error is forwarded to the performance monitor. 2. hdb3 code violation (cv) error: when hdb3 line code rule is used, a cv error is detected if tw o consecutive bpv errors are detected, and the pulses that have the same polarity as the previous pulse are not the hdb3 zero substitution pulsed (refer to figure 8). 3. excessive zero (exz) error: exz error can be detected in both ami and hdb3 line code rules. t here are two standards defining the exz error: ansi and fcc. the exz_d ef bit chooses a standard for the corresponding link to judge the exz erro r. table 8 shows the definition of exz. to count the event of the ex cessive zero (exz) error, the exz_err[1:0] bits should be set to ?01?. the excessive zero (exz) error is counted in an internal 16-bit exz counter. the content in the exz counter is transferred to the exz error counter l-byte & h-byte registers in two ways: a. when the cnt_md bit is ?0?, the manual-report mode is selected. the exz counter transfers its content to the exz error counter l-byte & h-byte registers w hen there is a transition from ?0? to ?1? on the cnt_trf bit; b. when the cnt_md bit is ?1?, the auto-report mode is selected. the exz counter transfers its content to the exz error counter l-byte & h-byte registers every one second automatically. after the content in the counter is transferred to the exz error counter l-byte & h-byte registers, the counter will be cleared to ?0? and start a new round counting automatical ly. no error event is lost during data transferring. the overflow of the counter is reflected by the cntov_is bit, and can trigger an interrupt if the corresponding cnt_ie bit is set. when the bipolar violation (bpv) er ror or the hdb3 code violation (cv) error is detected, it will be indicated by the cv_is bit. when the excessive zero (exz) error is detected, it will be indicated by the exz_is bit. when the cv_is bit or the exz_is bit is ?1?, an interrupt will be reported by the int pin if enabled by the corresponding cv_ie bit or the exz_ie bit. table 8: excessive zero error definition ansi fcc ami more than 15 consecutive 0s are detected. more than 80 consecutive 0s are detected. b8zs more than 7 consecutive 0s are detected (refer to figure 7). more than 7 consecutive 0s are detected (refer to figure 7). hdb3 more than 3 consecutive 0s are detected (refer to figure 8). more than 3 consecutive 0s are detected (refer to figure 8).
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 20 march 22, 2004 figure 6. ami bipolar violation error figure 7. b8zs excessive zero error figure 8. hdb3 code violatio n & excessive zero error 3.7.3 los detection the loss of signal (los) detector monitors the amplitude and den- sity of the received signal. when t he received signal is below an ampli- tude for continuous intervals, the los is detected. when the received signal is above the amplitude and t he density of marks meets the requirement, the los is cleared. the different criteria for los de claring/clearing are illustrated in table 9 and table 10. in t1/j1 mode, the los detection supports ansi t1.231 and i.431. in e1 mode, the los detection supports itu-t g.775 and i.431. the criteria are selected by the lac bit. when the los is detected, it will be indicated by the los_s bit. selected by the los_ies bit, a transition from '0' to '1' on the los_s bit or any transition (from ?0? to ?1? or fr om ?1? to ?0?) on the los_s bit will set the los_is bit to ?1?. when the los_is bit is ?1?, an interrupt will be reported by the int pin if enabled by the los_ie bit. during los, if the raise bit is set to ?1?, all ?one?s will be inserted to the received data stream. bipolar violation clock rtipn rringn 1 2 3 4 5v 6 7 excessive zero clock rtipn rringn 8 consecutive zeros 1 2 35 46 7 8 9 excessive zero clock rtipn rringn code violation 4 consecutive zeros 1 2 3 4vv 5 6
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 21 march 22, 2004 table 9: los condition in t1/j1 mode loss of signal in t1/j1 mode short haul application long haul application ansi t1.231 i.431 ansi t1.231 i.431 los detected amplitude below 800 mvpp below 800 mvpp below q db * below q db * continuous intervals 175 bits 1544 bits 175 bits 1544 bits los cleared amplitude above 1 vpp above 1 vpp above q + 4 db * above q + 4 db * mark density 12.5% (16 marks in a hopping 128-bit window **) with less than 100 continuous zeros 12.5% (16 marks in a hopping 128-bit window **) with less than 100 continuous zeros 12.5% (16 marks in a hopping 128-bit window **) with less than 100 continuous zeros 12.5% (16 marks in a hopping 128-bit window **) with less than 100 continuous zeros note: * the q db is set in the los[4:0] bits. ** a hopping 128-bit window means this: an ent ire 128 bits is taken from the data stream and is checked. if the criteria are no t met, all the 128 bits are th rown and another 128 bits are caught for checking. table 10: los condition in e1 mode loss of signal in e1 mode short haul application long haul application g.775 i.431 g.775 i.431 los detected amplitude below 800 mvpp below 800 mvpp below q db * below q db * continuous intervals 32 bits 2048 bits 32 bits 2048 bits los cleared amplitude above 1 vpp above 1 vpp above q + 4 db * above q + 4 db * mark density 12.5% (4 marks in a hopping 32-bit window **) with less than 16 continuous zeros 12.5% (4 marks in a hopping 32-bit window **) with less than 16 continuous zeros 12.5% (4 marks in a hopping 32-bit window **) with less than 16 continuous zeros 12.5% (4 marks in a hopping 32-bit window **) with less than 16 continuous zeros note: * the q db is set in the los[4:0] bits. ** a hopping 32-bit window means this: an entire 32 bits is taken fr om the data stream and is checked. if the criteria are not met, all the 32 bits are thrown and another 32 bits are caught for checking.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 22 march 22, 2004 table 11: related bit / register in chapter 3.7 bit register address (hex) r_md receive configuration 0 028, 128, 228, 328 exz_err maintenance function control 2 031, 131, 231, 331 exz_def cnt_md cnt_trf cntl[7:0] exz error counter l-byte 03d, 13d, 23d, 33d cnth[7:0] exz error counter h-byte 03c, 13c, 23c, 33c cv_is interrupt status 1 03b, 13b, 23b, 33b exz_is cntov_is cv_ie interrupt enable control 1 034, 134, 234, 334 exz_ie cnt_ie lac maintenance function control 1 02c, 12c, 22c, 32c raise los_s line status register 0 036, 136, 236, 336 los_ies interrupt trigger edges select 035, 135, 235, 335 los_is interrupt status 0 03a, 13a, 23a, 33a los_ie interrupt enable control 0 033, 133, 233, 333 los[4:0] receive configuration 1 029, 129, 229, 329
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 23 march 22, 2004 3.8 frame processor 3.8.1 t1/j1 mode in t1/j1 mode, the frame processo r searches for the frame align- ment patterns in the standard super-frame (sf), extended super- frame (esf), t1 digital multiplexe r (dm) or switch line carrier - 96 (slc-96) framing formats. the t1 dm and slc-96 formats are only sup- ported in t1 mode. the frame proc essor acquires frame alignment per itu-t requirement. when frame alignment is achieved, the framer processor contin- ues to monitor the received data stream. the frame processor will declare framing bit errors or bit er ror events if any. the frame processor can also detect out-of-frame events based on selected criteria. the frame processor can also be bypassed by setting the unfm bit. 3.8.1.1 synchronization searching 3.8.1.1.1 super frame (sf) format the structure of t1/j1 sf is illustrated in table 12. the sf is made up of 12 frames. each frame consists of one overhead bit (f-bit) and 24 8-bit channels. its frame alignment pattern is ?100011011100? for t1 and ?10001101110x? for j1 located in the f-bit position. the same pat- tern is a mimic pattern if it is received in the data stream other than f-bit. the synchronization criteria of sf fo rmat is selected by the mimicc bit. when the mimicc bit is set to ?1?, the sf synchronization is acquired if two consecutive frame alignment patte rns are received error free in the data stream without a mimic pattern. when the mimicc bit is set to ?0?, the sf synchronization is acquired if two consecutive frame alignment patterns are received error free in the data stream. in this case, the existence of mimic patterns is ignor ed. if a mimic pattern exists during the frame searching procedure, the mimi ci bit will be set to indicate the presence of a mimic pattern. the sf synchronization is indicated by ?0? in the oofv bit. the rmfbi bit is set at the first bit of each sf frame. table 12: the structure of sf frame no. in the sf f-bit (frame alignment) the bit in each channel ft fs data bit signaling bit 11 1 - 8- 201 - 8- 30 1 - 8- 401 - 8- 51 1 - 8- 6 1 1 - 7 a (bit 8) 70 1 - 8- 811 - 8- 91 1 - 8- 10 1 1 - 8 - 11 0 1 - 8 - 12 x 1 - 7 b (bit 8) note: ?x? should be logic 0 in t1 fas. ?x? can be logic 0 or 1 in j1 fas because this position is used as yellow alarm indication bit.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 24 march 22, 2004 3.8.1.1.2 extended super frame (esf) format the structure of t1/j1 esf is illustrated in table 13. the esf is made up of 24 frames. each frame consists of one overhead bit (f-bit) and 24 8-bit channels. the f-bit in fr ame (4n) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 25 march 22, 2004 3.8.1.1.3 t1 digital multiplexer (dm) format (t1 only) the structure of t1 dm is illustrated in table 14. the t1 dm is made up of 12 frames. each frame consists of one overhead bit (f-bit) and 24 8-bit channels. except for c hannel 24, all other channels carry data. channel 24 should be ?0dy11101?. its frame alignment pattern is ?100011011100? in the f-bit. the fix ed 6 bits in channel 24 are called dds. the synchronization criteria of t1 dm format are selected by the ddsc bit. when the ddsc bit is ?0?, the t1 dm synchronization is acquired if one correct dds pattern is received before the first f-bit of a single correct frame alignment pattern . when the ddsc bit is ?1?, the t1 dm synchronization is acquired if a single correct frame alignment pattern is received and twelve correct dds patterns before each f-bit of the correct frame alignment pattern are all detected. the t1-dm synchronization is indi cated by ?0? in the oofv bit. the rmfbi bit is set at the first bit of each t1 dm frame. table 14: the structure of t1 dm frame no. in the t1 dm f-bit (frame alignment) channel 24 ft fs 1 1 0dy11101 2 0 0dy11101 3 0 0dy11101 4 0 0dy11101 5 1 0dy11101 6 1 0dy11101 7 0 0dy11101 8 1 0dy11101 9 1 0dy11101 10 1 0dy11101 11 0 0dy11101 12 0 0dy11101 note: in channel 24, the ?d? bit is used for data link, and the ?y? bit is used for alarm. the other 6 bits are fixed and they are ca lled ?dds? pattern.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 26 march 22, 2004 3.8.1.1.4 switch line carrier - 96 (slc-96) format (t1 only) the structure of slc-96 is illustrated in table 15. the slc-96 is made up of 6 sfs, but some f-bit ar e used as concentrator bits, spoiler bits, maintenance bits, alarm bits and switch bits. each frame consists of one overhead bit (f-bit) and 24 8-bit channels. its frame alignment pattern is ?001000110111001000110111? in 24 consecutive f-bit posi- tions. if the frame alignment pattern is found in 24 consecutive f-bit positions in the data stream, the slc-96 synchronization is acquired. the first frame is numbered from the frame whose f-bit contains the first ?1? of the frame alignment pattern. the slc-96 synchronization is indi cated by ?0? in the oofv bit. the rmfbi bit is set at the first bit of each slc-96 frame. table 15: the structure of slc-96 frame no. f-bit (frame alignment) - ft the bit in each channel frame no. f-bit (frame alignment) - fs the bit in each channel data bit signaling bit data bit signaling bit 1 1 1 - 8 - 2 0 1 - 8 - 3 0 1 - 8 - 4 0 1 - 8 - 5 1 1 - 8 - 6 1 1 - 7 a (bit 8) 7 0 1 - 8 - 8 1 1 - 8 - 9 1 1 - 8 - 10 1 1 - 8 - 11 0 1 - 8 - 12 0 1 - 7 b (bit 8) 13 1 1 - 8 - 14 0 1 - 8 - 15 0 1 - 8 - 16 0 1 - 8 - 17 1 1 - 8 - 18 1 1 - 7 c (bit 8) 19 0 1 - 8 - 20 1 1 - 8 - 21 1 1 - 8 - 22 1 1 - 8 - 23 0 1 - 8 - 24 c1 (concentrator bit) 1 - 7 d (bit 8) 25 1 1 - 8 - 26 c2 (concentrator bit) 1 - 8 - 27 0 1 - 8 - 28 c3 (concentrator bit) 1 - 8 - 29 1 1 - 8 - 30 c4 (concentrator bit) 1 - 7 a (bit 8) 31 0 1 - 8 - 32 c5 (concentrator bit) 1 - 8 - 33 1 1 - 8 - 34 c6 (concentrator bit) 1 - 8 - 35 0 1 - 8 - 36 c7 (concentrator bit) 1 - 7 b (bit 8) 37 1 1 - 8 - 38 c8 (concentrator bit) 1 - 8 - 39 0 1 - 8 - 40 c9 (concentrator bit) 1 - 8 - 41 1 1 - 8 - 42 c10 (concentrator bit) 1 - 7 c (bit 8) 43 0 1 - 8 - 44 c11 (concentrator bit) 1 - 8 - 45 1 1 - 8 - 46 0 (spoiler bit) 1 - 8 - 47 0 1 - 8 - 48 1 (spoiler bit) 1 - 7 d (bit 8) 49 1 1 - 8 - 50 0 (spoiler bit) 1 - 8 - 51 0 1 - 8 - 52 m1 (maintenance bit) 1 - 8 - 53 1 1 - 8 - 54 m2 (maintenance bit) 1 - 7 a (bit 8) 55 0 1 - 8 - 56 m3 (maintenance bit) 1 - 8 - 57 1 1 - 8 - 58 a1 (alarm bit) 1 - 8 - 59 0 1 - 8 - 60 a2 (alarm bit) 1 - 7 b (bit 8) 61 1 1 - 8 - 62 s1 (switch bit) 1 - 8 - 63 0 1 - 8 - 64 s2 (switch bit) 1 - 8 - 65 1 1 - 8 - 66 s3 (switch bit) 1 - 7 c (bit 8) 67 0 1 - 8 - 68 s4 (switch bit) 1 - 8 - 69 1 1 - 8 - 70 1 (spoiler bit) 1 - 8 - 71 0 1 - 8 - 72 0 1 - 7 d (bit 8)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 27 march 22, 2004 3.8.1.2 error event and out of synchronization detection after the frame is in synchroniza tion, the frame processor contin- ues to monitor the received data stream to detect errors and judge if it is out of synchronization. 3.8.1.2.1 super frame (sf) format in sf format, two kinds of errors are detected: 1. severely ft bit error: each received ft bit is compared with the expected one (refer to table 12). each unmatched ft bit leads to an ft bit error event. when 2 or more ft bi t errors are detected in a 6-basic- frame fixed window, the severely ft bit error occurs. this error event is captured by the sfei bit. 2. f bit error: each received f bit is compared with the expected one (refer to table 12). each unmat ched f bit leads to an f bit error event. this error event is captured by the feri bit and is forwarded to the performance monitor. when the f bit error number exceeds the ratio set in the m2o[1:0] bits, it is out of synchronization. t hen if the refen bit is ?1?, the frame processor will start to search for synchronization again. if the refen bit is ?0?, no error can lead to reframe except for manually setting. the man- ual reframe is executed by a transiti on from ?0? to ?1? on the refr bit. during out of synchronization state, the error event detection is sus- pended. once resynchronized, if the new -found f bit position differs from the previous one, the change of frame alignment event is generated. this event is captured by the cofa i bit and is forwarded to the perfor- mance monitor. 3.8.1.2.2 extended super frame (esf) format in esf format, four kinds of errors are detected: 1. frame alignment bit error: ea ch received frame alignment bit is compared with the expected one (refer to table 13). each unmatched bit leads to a frame alignment bit error event. this error event is captured by the feri bit and is forwarded to the performance monitor. 2. crc-6 error: when the local calculated crc-6 of the current received esf frame does not match the received crc-6 of the next received esf frame, a single crc-6 er ror event is generated. this error event is captured by the beei bit and is forwarded to the performance monitor. 3. excessive crc-6 error: once the accumulated crc-6 errors exceed 319 occasions (> 319) in a 1 second fixed window, an excessive crc-6 error event is generated. this error event is captured by the excrceri bit and is forwarded to the performance monitor. 4. severely frame alignment bit error: when 2 or more frame alignment bit errors are detected in a 1-esf-frame fixed window, the severely frame alignment bit error o ccurs. this error event is captured by the sfei bit. when the frame alignment bit erro r number exceeds the ratio set in the m2o[1:0] bits, it is out of synchronization. then if the refen bit is ?1?, the frame processor will star t to search for synchronization again. additionally, the excessive crc-6 erro r also leads to out of esf syn- chronization. in this condition, both the refen bit being ?1? and the refcrce bit being ?1? will allow the frame processor to search for syn- chronization again. if the refen bit is ?0?, no error can lead to reframe except for manually setting. the manual reframe is executed by a transi- tion from ?0? to ?1? on the refr bi t. during out of synchronization state, the error event detection is suspended. once resynchronized, if the new -found f bit position differs from the previous one, the change of fr ame alignment event is generated. this event is captured by the cofai bit and is forwarded to the perfor- mance monitor. 3.8.1.2.3 t1 digital multiplexer (dm) format (t1 only) in t1 dm format, three kinds of errors are detected: 1. severely ft bit error: each received ft bit is compared with the expected one (refer to table 14). ea ch unmatched ft bit leads to an ft bit error event. when 2 or more ft bit errors are detected in a 6-basic- frame fixed window, the severely ft bit error occurs. this error event is captured by the sfei bit. 2. f bit error: each received f bit is compared with the expected one (refer to table 14). each unmat ched f bit leads to an f bit error event. this error event is captured by the feri bit and is forwarded to the performance monitor. 3. dds pattern error: the received 6-bit dds in each ch24 is compared with the dds pattern - ?0xx11101? (msb left and ?x? is not cared). when one or more bits do not match the dds pattern, a single dds pattern error event is generated. this error event is forwarded to the performance monitor. the 6-bit dds pattern and its follo wing f-bit make up a 7-bit pat- tern. when one or more bits do not match its pattern (refer to table 14), a single error is generated. when this error number exceeds the ratio set in the m2o[1:0] bits, it is out of synchronization. then if the refen bit is ?1?, the frame processor will start to search for synchronization again. if the refen bit is ?0?, no er ror can lead to reframe except for manually setting. the manual reframe is executed by a transition from ?0? to ?1? on the refr bit. during out of synchronization state, the error event detection is suspended. once resynchronized, if the new -found f bit position differs from the previous one, the change of fr ame alignment event is generated. this event is captured by the cofai bit and is forwarded to the perfor- mance monitor. 3.8.1.2.4 switch line carrier - 96 (slc-96) format (t1 only) in slc-96 format, only one kind of error is detected: 1. f bit error: the ft bit in each odd frame and the fs bit in frame (2n) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 28 march 22, 2004 once resynchronized, if the new -found f bit position differs from the previous one, the change of frame alignment event is generated. this event is captured by the cofa i bit and is forwarded to the perfor- mance monitor. 3.8.1.3 overhead extraction (t 1 mode slc-96 format only) in slc-96 format, the concentrator bits, maintenance bits, alarm bits and switch bits are all extrac ted to the rdl0, rdl1 & rdl2 regis- ters respectively. all these extractions will be set to de-bounce if the scdeb bit is set to ?1?. thus, the value in the rdl0, rdl1 & rdl2 registers are updated if the received corresponding code is the same for 2 consecutive slc- 96 frames. whether de-bounced or no t, a change indication will be set in the scci bit, scmi bit, scai bit and scsi bit respectively if the corre- sponding codes in the rdl0, rdl1 & rd l2 registers differ from the pre- vious ones. the value in the rdl0, rdl1 & rd l2 registers is held during out of slc-96 synchronization state. 3.8.1.4 interrupt summary the interrupt sources in this block are summarized in table 16. when there are conditions meeting t he interrupt sources, the corre- sponding status bit will be asserted high. when there is a transition (from ?1? to ?0? or from ?0? to ?1?) on the status bit, the corresponding sta- tus interrupt indication bit will be se t to ?1? (if the status bit does not exist, the source will cause its stat us interrupt indication bit to ?1? directly) and the status interrupt indication bit will be cleared by writing ?1?. a ?1? in the status interrupt indication bit indicates an interrupt occurred. the interrupt is reported by the int pin if its status interrupt enable bit was set to ?1?. table 16: interrupt source in t1/j1 frame processor sources status bit interrupt indication bit interrupt enable bit it is out of synchronization. oofv oofi oofe the first bit of each sf / esf / t1 dm / slc-96 frame is received. - rmfbi rmfbe the new-found f bit position differs from the previous one. - cofai cofae in sf / t1 dm / slc-96 format, the f bit error occurs. in esf format, the frame alignment bit error occurs. - feri fere in esf format, the crc-6 error occurs. (this interrupt does not exist in other formats.) - beei beee in sf / t1 dm format, the severely ft bit error occurs. in esf format, the severely frame alignment bit error occurs. (this interrupt does not exist in slc-96 format.) - sfei sfee in slc-96 format, the concentrator bits differ from the previous ones. - scci scce in slc-96 format, the maintenance bits differ from the previous ones. - scmi scme in slc-96 format, the alarm bits differ from the previous ones. - scai scae in slc-96 format, the switch bits differ from the previous ones. - scsi scse
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 29 march 22, 2004 table 17: related bit / register in chapter 3.8.1 bit register t1/j1 address (hex) unfm frmr mode 0 04d, 14d, 24d, 34d refen refr refcrce mimicc frmr mode 1 04e, 14e, 24e, 34e m2o[1:0] ddsc oofv frmr status 04f, 14f, 24f, 34f mimici frmr interrupt indication 0 052, 152, 252, 352 excrceri oofi rmfbi frmr interrupt indication 1 053, 153, 253, 353 sfei beei feri cofai oofe frmr interrupt control 0 050, 150, 250, 350 rmfbe frmr interrupt control 1 051, 151, 251, 351 sfee beee fere cofae c[11:1] rdl1 & rdl0 057, 157, 257, 357 & 056, 156, 256, 356 m[3:1] rdl1 057, 157, 257, 357 a[2:1] rdl2 058, 158, 258, 358 s[4:1] scai dlb interrupt indication 05d, 15d, 25d, 35d scsi scmi scci scdeb dlb interrupt control 05c, 15c, 25c, 35c scae scse scme scce
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 30 march 22, 2004 3.8.2 e1 mode in e1 mode, the frame processo r searches for basic frame syn- chronization, crc multi-frame syn chronization, and channel associated signaling (cas) multi-frame sync hronization in the received data stream. figure 9 shows the searching process. once the frame is synchronized, the frame processor keeps on monitoring the received data stream. if there are any framing bit errors, cas multi-frame alignment pattern errors, crc multi-frame alignment pattern errors or crc errors, the fr ame processor will indicate these errors. the status of loss of frame, loss of signaling multi-frame and loss of crc multi-frame can al so be detected and declared based on user-selectable criteria. a software reset can also make the frame pro- cessor reframe. the frame processor can extract the data stream in ts16, and output the extracted data on a separat e pin. the frame processor also extracts the contents of the internat ional bits (from both the fas and the nfas frames), the national bits and the extra bits (from ts16 in the frame 0 of the signaling multi-frame), and stores these data in registers. the crc sub multi-frame alignment 4 bit codeword in the national bit positions sa4 to sa8 can also be ex tracted and stored in registers, and updated every crc sub multi-frame. the framer processor identifies the remote alarm bit (bit 3 of ts0 of nfas frames) and remote signaling multi-frame alarm (bit 6 of ts16 of the frame 0 of the signal ing multi-frame). the ?de-bounced? remote alarm and remote signaling multi-frame alarm can be indi- cated if the corresponding bit has been a certain logic for 1 or 4 consec- utive times. the ais (alarm indication signal) alarm can also be detected. the frame processor can also dec lare a red alarm if the out- of-frame condition has persisted for at least 100 ms. an interrupt output is provided to indicate status changes and the occurrence of some events. the interrupts may be generated every basic frame, crc sub multi-frame, crc multi-frame or signaling multi-frame. the frame processor can also be bypassed by setting the unfm bit.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 31 march 22, 2004 figure 9. e1 frame searching process out of sync. oofv = 1, oocmfv = 1, oosmfv = 1, ooofv = 0 find fas in n frame search for basic fframe alignment patten (refer to basic frame) find nfas in (n+1) frame th no (n=n+1) yes find fas in (n+2) frame th yes no (n=n+3) basic frame sync. acquired oofv = 0 start to check fas errors search for crc multi-frame alignment pattern if crcen = 1 (refer to crc multi-frame) start 8ms and 400ms timer find 2 crc multi-frame alignment patterns within 8ms, with the interval time of each pattern being a multiple of 2ms yes crc multi-frame sync. acquired; start crc and e-bits processing; oocmfv = 0, oofv = 0 crc to crc interworking no, and 8ms expired c2nciwv = 1 crc to non-crc interworking stop crc processing if c2nciwck = 0 no, and 400ms expired with basic frame sync. yes find signaling multi-frame alignment pattern search for signaling multi-frame alignment if casen = 1 (refer to signaling multi-frame) yes signaling multi-frame sync. acquired no check for out of signaling multi-frame sync conditions which criteria are set in the smfasc & ts16c no (n=n+3) yes 3 consecutive fas or nfas errors (criteria selected by the bit2c) or manually re-frame > 914 crc errors in one second find nfas in (n+1) frame th yes find fas in (n+2) frame th yes yes lock the sync. position start offline frame search ooofv = 1 basic frame sync. acquired ooofv = 0 start 8ms timer find 2 crc multi-frame alignment patterns within 8ms, with the interval time of each pattern being a multiple of 2ms yes no (skip one frame, n=n+3) no no (skip one frame, n=n+3) th th find fas in n frame no (n = n+1) no, and 8ms expired
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 32 march 22, 2004 3.8.2.1 synchronization searching 3.8.2.1.1 basic frame the algorithm used to search fo r the e1 basic frame alignment pattern (as shown in figure 10) meets the itu-t recommendation g.706 4.1.2 and 4.2. generally, it is performed by detecting a successive fas/nfas/ fas sequence. if step 2 is not met, a new searching will start after the following frame is skipped. if step 3 is not met, a new searching will start immediately in the next fram e. once the basic frame alignment pattern is detected in the received pcm data stream, the basic frame synchronization is found and the oofv bit will be set to ?0? for indication. figure 10. basic frame searching process step1: search for 7-bit frame alignment sequence (fas) (x0011011) in the n frame step 2: find logic 1 in the 2nd bit of ts0 of the (n+1) frame to ensure that this is a non-frame alignment sequence (nfas) step 3: search for the correct 7-bit fas (x0011011) in the ts0 in the (n+2) frame yes no (n=n+1) yes yes basic frame synchronization found no (n=n+3) no (skip one frame, n=n+3) th th th
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 33 march 22, 2004 3.8.2.1.2 crc multi-frame the crc multi-frame is provided to enhance the ability of verifying the data stream. the structure of ts0 of the crc multi-frame is illus- trated in table 18. a crc multi-frame consists of 16 continuous basic frames (no. 0 ? 15) which are numbered from a basic frame with fas. each crc multi-frame can be divided into two s ub multi-frames (smf i & smf ii). the first bit of ts0 of each frame is called the international (si) bit. the si bit in each even frame is t he crc bit. thus, there are c1, c2, c3, c4 in each smf. the c1 is the most significant bit, while the c4 is the least significant bit. the si bit in the first six odd frames is the crc multi-frame alignment pattern. its pattern is ?001011?. the si bit in frame 13 and frame 15 are e1 and e2 bits. the value of the e bits can indicate the far end block errors (febe). after the basic frame has been synchronized, the frame proces- sor initiates an 8 and a 400 ms timer to check the crc multi-frame alignment signal if the crcen bit is ?1?. the crc multi-frame synchro- nization is declared with a ?0? in the oocmfv bit only if at least two crc multi-frame alignment patterns are f ound within 8 ms, with the interval time of each pattern being a multiple of 2 ms. then if the received crc multi-frame alignment signal does not meet its pattern, it will be indi- cated by the cmferi bit. if the 2 crc multi-frame alignment patterns can not be found within 8ms with the interval time being a multiple of 2 ms, an offline search for the basic frame alignment pattern will start which is indicated in the ooofv bit. the process is the same as shown in figure 10. this offline operation searches in paral lel with the pre-found basic frame synchronization searching process. after the new basic frame synchro- nization is found by this offline sear ch, the 8 ms timer is restarted to check whether the two crc multi- frame alignment patterns are found within 8 ms, with the interval time of each pattern being a multiple of 2 ms again. if the condition can not be met, the procedure will go on until the 400 ms timer ends. if the condition still can not be met at that time and the basic frame is still synchronized, the device declares by the c2nciwv bit to run under the crc to non-crc interworking process. in this process, the crc multi-fram e alignment pattern can still be searched if the c2nciwck bit is logic 1. table 18: the structure of ts0 in crc multi-frame smf basic frame no. / type the eight bits in timeslot 0 1 (si bit) 2 3 4 5 6 7 8 crc-4 multi-frame smf i 0 / fasc10011011 1 / nfas 0 1 a sa4 sa5 sa6 sa7 sa8 2 / fasc20011011 3 / nfas 0 1 a sa4 sa5 sa6 sa7 sa8 4 / fasc30011011 5 / nfas 1 1 a sa4 sa5 sa6 sa7 sa8 6 / fasc40011011 7 / nfas 0 1 a sa4 sa5 sa6 sa7 sa8 smf ii 8 / fasc10011011 9 / nfas 1 1 a sa4 sa5 sa6 sa7 sa8 10 / fasc20011011 11 / nfas 1 1 a sa4 sa5 sa6 sa7 sa8 12 / fasc30011011 13 / nfas e1 1 a sa4 sa5 sa6 sa7 sa8 14 / fasc40011011 15 / nfas e2 1 a sa4 sa5 sa6 sa7 sa8
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 34 march 22, 2004 3.8.2.1.3 cas signaling multi-frame after the basic frame has been synchronized, the frame proces- sor starts to search for cas signa ling multi-frame alignment signal if the casen bit is ?1?. the signaling multi-frame alignment pattern is located in the high nibble (bit 1 ~ bit 4) of ts16. its pattern is ?0000?. when the pattern is found in ts16 and the high nibble of the previous ts16 are not all zeros, the signaling multi-frame synchronizati on is acquired and it is indicated with a ?0? in the oosmfv bit. the frame containing the signaling multi- frame alignment pattern is frame 0 of signaling multi-frame. the ts16 structure of the signaling multi-fram e is shown in figure 11. the entire content in ts16 of frame 0 of signal ing multi-frame is ?0000xyxx?. ?y? is for remote signaling multi-frame alarm indication and ?x?s are extra bits. the codeword ?abcd? are the si gnaling bits for different timeslots. figure 11. ts16 structure of cas signaling multi- frame 3.8.2.2 error event and out of synchronization detection after the frame is in synchronization, the frame processor keeps on monitoring the received data stream to detect errors and judge if it is out of synchronization. the following ten kinds of errors are detected: 1. fas/nfas bit/pattern error: the criteria of this error are deter- mined by the worderr bit and the cn tnfas bit (refer to table 19). this error event is captured by the feri bit and is forwarded to the per- formance monitor. 2. crc multi-frame alignment pattern error: the received crc multi-frame alignment signals ar e compared with the expected ones (?001011?). when one or more bits do not match, a single crc multi- frame alignment pattern error even t is generated. this error event is captured by the cmferi bit. 3. crc-4 error: when the local calculated crc-4 of the current received crc sub multi-frame does not match the received crc-4 of the next received crc sub multi-fram e, a single crc-4 error event is generated. this error event is capt ured by the crcei bit and is for- warded to the performance monitor. 4. excessive crc-4 error: once the accumulated crc-4 errors are not less than 915 occasions (915 is included) in a 1 second fixed window, an excessive crc-4 error ev ent is generated. this error event is captured by the excrceri bit. 5. cas signaling multi-frame alignment pattern error: the received signaling multi-frame alignm ent signals are compared with the expected ones (?0000?). when one or mo re bits do not match, a single cas signaling multi-frame alignment pattern error event is generated. this error event is captured by the smferi bit. 6. far end block error (febe): when any of the crc error indica- tion (e1 or e2) bits is received as a logic 0, a far end block error event is generated. this error event is capt ured by the febei bit and is for- warded to the performance monitor. 7. continuous rai & febe error: when a logic 1 is received in the a bit and a logic 0 is received in any of the e1 or e2 bit for 10 ms, the raicrcv bit is set. this bit is clear ed if any of the conditions is not met. 8. continuous febe error: when a logic 0 is received in any of the e1 or e2 bits on 990 occasions per second for the latest 5 consecutive seconds, the cfebev bit is set, other wise this bit will be cleared. 9. nt febe error (per ets 300 233): if the 4-bit sa6 codeword of a crc sub multi-frame is matched with ?0001? or ?0011?, the network ter- minal far end block error event is generated. this error event is cap- tured by the tfebei bit and is fo rwarded to the performance monitor. abcdabcd for ts31 for ts15 abcdabcd for ts18 for ts2 abcdabcd for ts17 for ts1 f1 f2 f15 0000x0yx1x2 f0 signaling multi-frame alignment pattern rmai extra bits ts16 (bit 1 - bit 8) table 19: fas/nfas bit/pattern error criteria worderr cntnfas error generation 0 0 each bit error in fas is counted as an error event. 1 0 a fas pattern error is co unted as an error event. 0 1 each bit error in fas or nfas error is counted as an error event. 1 1 a fas pattern error or nfas error is counted as an error event.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 35 march 22, 2004 10. nt crc error (per ets 300 233): if the 4-bit sa6 codeword of a crc sub multi-frame is matched wi th ?0010? or ?0011?, the network terminal crc error event is generated. this error event is captured by the tcrcei bit and is forwarded to the performance monitor. various errors will lead to out of synchronization: 3.8.2.2.1 out of basic frame synchronization if there is one or more bit errors in a fas pattern, a fas pattern error will occur. if the nfas bit position is received as zero, a nfas error will occur. determined by the bit2c bit, if this bit is ?0?, 3 consecutive fas pattern errors lead to out of basi c frame synchronization; if this bit is ?1?, 3 consecutive fas pattern errors or 3 consecutive nfas errors lead to out of basic frame synchronization. then if the refen bit is ?1?, the frame processor will start to s earch for synchronization again. addi- tionally, excessive crc-4 error also leads to out of basic frame syn- chronization. in this condition, both the refen bit being ?1? and the refcrce bit being ?1? will allow the frame processor to search for syn- chronization again. if the refen bit is ?0?, no error can lead to reframe except for manually setting. the m anual reframe searches from basic frame and is executed by a transition fr om ?0? to ?1? on the refr bit. dur- ing out of basic frame synchronization state, the fas/nfas bit/pattern error detection is suspended. once resynchronized, if the new -found basic frame alignment pat- tern position differs from the prev ious one, the change of frame align- ment event is generated. this event is captured by the cofai bit and is forwarded to the performance monitor. 3.8.2.2.2 out of crc multi-frame synchronization the conditions introducing out of basic frame synchronization will also cause out of crc multi-frame synchronization. during out of crc multi-frame synchronization state, the fas/nfas bit/pattern error detection, crc multi-fr ame alignment pattern error detection, crc-4 error detection, excessive crc-4 error detection, far end block error detection, continuous rai & febe error detection, continuous febe error detection, nt crc error det ection and nt febe error detection are suspended. 3.8.2.2.3 out of cas signaling multi-frame synchronization the conditions introducing out of basic frame synchronization will also cause out of cas signali ng multi-frame synchronization. in addition, determined by the smfasc bit and the ts16c bit, if the cas signaling multi-frame alignment pattern error occurs or all the contents in ts16 are zeros, it is out of cas signaling multi-frame syn- chronization. then no matter what the value in the refen bit is, the frame processor will search for the cas signaling multi-frame syn- chronization again only if the basic frame is in synchronization. during out of cas signaling multi-frame syn chronization state, the cas sig- naling multi-frame alignment pa ttern error detection is suspended. 3.8.2.3 overhead extraction 3.8.2.3.1 international bit extraction the international bits (si bits, refe r to table 18) are extracted to the si[0:1] bits in the ts0 international / national register. the si[0:1] bits in the ts0 international / national register are updated on the boundary of the associated fas/nfas frame and ar e held during out of basic frame state. 3.8.2.3.2 remote alarm indication bit extraction the remote alarm indication bit (a bit, refer to table 18) is extracted to the a bit in the ts0 in ternational / national register. the a bit in the ts0 international / na tional register is updated on the bound- ary of the associated nfas frame and is held during out of basic frame state. 3.8.2.3.3 national bit extraction the national bits (sa bits, refer to table 18) are extracted to the sa[4:8] bits in the ts0 international / national register. the sa[4:8] bits in the ts0 international / national register are updated on the boundary of the associated nfas frame and ar e held during out of basic frame. 3.8.2.3.4 national bit codeword extraction the five sets of the national bit codewords (sa4[1:4] to sa8[1:4] in the crc sub multi-frame, refer to t able 18) are extracted to the corre- sponding sax codeword register. here the ?x? is from 4 through 8. the national bit codeword extraction wi ll be set to de-bounce if the sadeb bit is set to ?1?. thus, the sax codeword registers are updated if the received national bit codeword is t he same for 2 consecutive crc sub multi-frames. whether de-bounced or not, a change indication will be set in the saxi bit (?x? is from 4 through 8) if the corresponding codeword in the sax codeword register differs from the previous one. the value in the sax codeword r egisters is held during out of crc multi-frame synchronization state. 3.8.2.3.5 extra bit extraction the extra bits (x bits, refer to fi gure 11) are extracted to the x[0:2] bits in the ts16 spare register. the x[ 0:2] bits in the ts16 spare regis- ter are updated at the first bit of the next cas signaling multi-frame and are held during out of cas signaling multi-frame state. 3.8.2.3.6 remote signaling multi-frame alarm indication bit extraction the remote signaling multi-frame al arm indication bit (y bit, refer to figure 11) are extracted to the y bit in the ts16 spare register. the y bit in the ts16 spare register is updat ed at the first bit of the next cas signaling multi-frame and is held du ring out of cas signaling multi- frame state. 3.8.2.3.7 sa6 code detection per ets 300 233 when basic frame is synchroniz ed, any 12 consecutive sa6 bits (msb is the first received bit) ar e compared with 0x888, 0xaaa, 0xccc, 0xeee and 0xfff. when crc multi-fr ame is synchronized, any 3 con- secutive 4-bit sa6 codewords in the crc sub multi-frame are com-
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 36 march 22, 2004 pared if the sa6syn bit is ?1?. if a matched code is detected, the corresponding indication bit in the s a6 code indication register will be set. 3.8.2.4 v5.2 link the v5.2 link id signal, i.e., 2 out of 3 sliding sa7 bits being logic 0, is detected with the indication in the v52linkv bit. this detection is dis- abled when the basic frame is out of synchronization. 3.8.2.5 interrupt summary the interrupt sources in this block are summarized in table 20. when there are conditions meeting the interrupt sources, the corre- sponding status bit will be asserted high. when there is a transition (from ?1? to ?0? or from ?0? to ?1?) on the status bit, the corresponding sta- tus interrupt indication bit will be se t to ?1? (if the status bit does not exist, the source will cause its stat us interrupt indication bit to ?1? directly) and the status interrupt indication bit will be cleared by a write signal. a ?1? in the status interr upt indication bit means an interrupt occurred. the interrupt will be reported by the int pin if its status inter- rupt enable bit is ?1?. table 20: interrupt source in e1 frame processor sources status bit interrupt indication bit interrupt enable bit in crc to non-crc inter-w orking. c2nciwv c2nciwi c2nciwe it is out of basic frame synchronization. oofv oofi oofe it is out of crc multi-frame synchronization. oocmfv oocmfi oocmfe it is out of cas signaling multi-frame synchronization. oosmfv oosmfi oosmfe the new-found basic frame alignment pattern position differs from the previous one. - cofai cofae fas/nfas bit/pattern error occurs. - feri fere crc multi-frame alignment patte rn error occurs. - cmferi cmfere cas signaling multi-frame alignment pattern error occurs. - smferi smfere crc-4 error occurs. - crcei crcee offline basic frame search indication. ooofv ooofi ooofe far end block error occurs. - febei febee continuous rai & febe error occurs. raicrcv raicrci raicrce continuous febe error occurs. cfebev cfebei cfebee at the first bit of each crc multi-frame. - icmfpi icmfpe at the first bit of each crc sub multi-frame. - icsmfpi icsmfpe at the first bit of each cas signaling multi-frame. - ismfpi ismfpe there is change in the corresponding sax[1:4] bits. the ?x? is from 4 through 8. - sa4i / sa5i / sa6i / sa7i / sa8i sa4e / sa5e / sa6e / sa7e / sa8e any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords are matched with 0x888, 0xaaa, 0xccc, 0xeee or 0xfff. - sa6sci sa6sce nt febe error occurs. - tfebei tfebee nt crc error occurs. - tcrcei tcrcee 2 out of 3 sliding sa7 bits are received as logic 0. v52linkv v52linki v52linke
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 37 march 22, 2004 table 21: related bit / register in chapter 3.8.2 bit register e1 address (hex) unfm frmr mode 0 04d, 14d, 24d, 34d refen refcrce refr crcen frmr mode 1 04e, 14e, 24e, 34e c2nciwck casen worderr cntnfas bit2c smfasc ts16c oofv frmr status 04f, 14f, 24f, 34f oocmfv ooofv c2nciwv oosmfv excrceri frmr interrupt indication 0 052, 152, 252, 352 c2nciwi oofi oocmfi oosmfi ooofi oofe frmr interrupt control 0 050, 150, 250, 350 oocmfe ooofe c2nciwe oosmfe cmferi frmr interrupt indication 1 053, 153, 253, 353 feri crcei smferi cofai icmfpi icsmfpi ismfpi cmfere frmr interrupt control 1 051, 151, 251, 351 fere crcee smfere cofae icmfpe icsmfpe ismfpe raicrcv overhead error status 05f, 15f, 25f, 35f cfebev v52linkv febei overhead interrupt indication 061, 161, 261, 361 tfebei tcrcei raicrci cfebei v52linki febee overhead interrupt control 060, 160, 260, 360 tfebee tcrcee raicrce cfebee v52linke si[0:1] ts0 international / national 054, 154, 254, 354 a sa[4:8] x[0:2] ts16 spare 055, 155, 255, 355 y sax[1:4] (?x? is from 4 to 8) sa4 codeword ~ sa8 codeword 056 ~ 05a, 156 ~ 15a, 256 ~ 25a, 356 ~ 35a saxi (?x? is from 4 to 8) sa codeword interrupt indication 05d, 15d, 25d, 35d sa6sci saxe (?x? is from 4 to 8) sa codeword interrupt control 05c, 15c, 25c, 35c sadeb sa6syn sa6sce sa6-8i sa6 codeword indication 05b, 15b, 25b, 35b sa6-ai sa6-ci sa6-ei sa6-fi table 21: related bit / register in chapter 3.8.2 (continued) bit register e1 address (hex)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 38 march 22, 2004 3.9 performance monitor 3.9.1 t1/j1 mode several internal counters are used to count different events for per- formance monitoring. for different fr aming format, the counters are used differently. the overflow of each counter is reflected by an overflow indi- cation bit, and can trigger an interr upt if the corresponding overflow interrupt enable bit is set. this is shown in table 22. these internal counters are indirect registers, and can only be accessed through other direct registers. at one time, only one internal counter can be accessed. users s hould use the linksel[1:0] bits to select the link, then use the addr[3:0] bits to select one internal counter. the content of the selected counter is transferred to the data[7:0] bits in the following two ways: 1. auto-report: when the autoup bit is ?1?, the selected counter transfers its content to the data [7:0] bits every one second automati- cally; 2. manual-report: no matter the autoupd bit is ?1? or ?0?, at any time, when there is a transition from ?0? to ?1? on the updat bit, the selected counter will transfer its content to the data[7:0] bits. after the content in the selected counter is transferred to the data[7:0] bits, all counters belong to the selected link will be cleared to ?0? as a group and start a new round counting automatically. no error event is lost during updating. table 22: monitored events in t1/j1 mode format event counter overflow interrupt indi cation bit overflow interrupt enable bit sf bipolar violation (bpv) error (i n ami decoding) or b8zs code violation (cv) error (in b8zs decoding) lcv[15:0] lcvovi lcvove f bit error fer[11:0] ferovi ferove the new-found f bit position differs from the previous one cofa[2:0] cofaovi cofaove out of sf synchronization oof[4:0] oofovi oofove prgd bit error prgd[15:0] prgdovi prgdove esf bipolar violation (bpv) error (i n ami decoding) or b8zs code violation (cv) error (in b8zs decoding) lcv[15:0] lcvovi lcvove frame alignment bit error fer[11:0] ferovi ferove crc-6 error crce[9:0] crcovi crcove the new-found f bit position differs from the previous one cofa[2:0] cofaovi cofaove out of esf synchronizati on oof[4:0] oofovi oofove prgd bit error prgd[15:0] prgdovi prgdove t1 dm (t1 only) bipolar violation (bpv) error (i n ami decoding) or b8zs code violation (cv) error (in b8zs decoding) lcv[15:0] lcvovi lcvove f bit error fer[11:0] ferovi ferove dds pattern error ddse[9:0] ddsovi ddsove the new-found f bit position differs from the previous one cofa[2:0] cofaovi cofaove out of t1 dm synchronization oof[4:0] oofovi oofove prgd bit error prgd[15:0] prgdovi prgdove slc-96 (t1 only) bipolar violation (bpv) error (i n ami decoding) or b8zs code violation (cv) error (in b8zs decoding) lcv[15:0] lcvovi lcvove f bit error fer[11:0] ferovi ferove the new-found f bit position differs from the previous one cofa[2:0] cofaovi cofaove out of slc-96 synchronization oof[4:0] oofovi oofove prgd bit error prgd[15:0] prgdovi prgdove
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 39 march 22, 2004 table 23: related bit / register in chapter 3.9.1 bit register t1/j1 address (hex) lcv[15:0] id* - lcv counter mapping 1 & 0 pmon id - 09 & 08 fer[11:0] id - fer counter mapping 1 & 0 pmon id - 03 & 02 cofa[2:0] id - cofa counter mapping pmon id - 04 oof[4:0] id - oof counter mapping pmon id - 05 prgd[15:0] id - prgd counter mapping 1 & 0 pmon id - 07 & 06 crce[9:0] id - crce counter mapping 1 & 0 pmon id - 01 & 00 ddse[9:0] id - ddse counter mapping 1 & 0 pmon id - 0b & 0a lcvovi pmon interrupt 1 0c6, 1c6, 2c6, 3c6 ferovi pmon interrupt 0 0c5, 1c5, 2c5, 3c5 cofaovi oofovi prgdovi crcovi ddsovi lcvove pmon interrupt control 1 0c4, 1c4, 2c4, 3c4 ferove pmon interrupt control 0 0c3, 1c3, 2c3, 3c3 cofaove oofove prgdove crcove ddsove linksel[1:0] pmon access port 00e addr[3:0] data[7:0] pmon access data 00f updat pmon control 0c2, 1c2, 2c2, 3c2 autoupd note: * id means indirect register in t he performance monitor function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 40 march 22, 2004 3.9.2 e1 mode several internal counters are used to count different events for per- formance monitoring. the overflow of each counter is reflected by an overflow indication bit, and can tri gger an interrupt if the corresponding overflow interrupt enable bit is set. this is shown in table 24. these internal counters are indirect registers, and can only be accessed through other direct registers. at one time, only one internal counter can be accessed. users s hould use the linksel[1:0] bits to select the link, then use the addr[3:0] bits to select one internal counter. the content of the select ed counter is transferred to the data[7:0] bits in the following two ways: 1. auto-report: when the autoup bit is ?1?, the selected counter transfers its content to the data [7:0] bits every one second automati- cally; 2. manual-report: no matter the autoupd bit is ?1? or ?0?, at any time, when there is a transition from ?0? to ?1? on the updat bit, the selected counter will transfer its content to the data[7:0] bits. after the content in the selected counter is transferred to the data[7:0] bits, all counters belong to the selected link will be cleared to ?0? as a group and start a new round counting automatically. no error event is lost during updating. table 24: monitored events in e1 mode event counter overflow interrupt indication bit overflow interrupt enable bit bipolar violation (bpv) error (in ami deco ding) or hdb3 code violation (cv) error (in hdb3 decoding) lcv[15:0] lcvovi lcvove fas/nfas bit/pattern error fer[11:0] ferovi ferove crc-4 error crce[9:0] crcovi crcove far end block error febe[9:0] febeovi febeove the the new-found basic frame alignment pattern position differs from the previous one cofa[2:0] cofaovi cofaove out of basic frame synchronization oof[4:0] oofovi oofove prgd bit error prgd[15:0] prgdovi prgdove nt febe error tfebe[9:0] tfebeovi tfebeove nt crc error tcrce[9:0] tcrcovi tcrcove
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 41 march 22, 2004 table 25: related bit / register in chapter 3.9.2 bit register e1 address (hex) lcv[15:0] id* - lcv counter mapping 1 & 0 pmon id - 09 & 08 fer[11:0] id - fer counter mapping 1 & 0 pmon id - 03 & 02 crce[9:0] id - crce counter mapping 1 & 0 pmon id - 01 & 00 febe[9:0] id - febe counter mapping 1 & 0 pmon id - 0d & 0c cofa[2:0] id - cofa counter mapping pmon id - 04 oof[4:0] id - oof counter mapping pmon id - 05 prgd[15:0] id - prgd counter mapping 1 & 0 pmon id - 07 & 06 tfebe[9:0] id - tfebe counter mapping 1 & 0 pmon id - 0f & 0e tcrce[9:0] id - tcrce counter mapping 1 & 0 pmon id - 0b & 0a lcvovi pmon interrupt 1 0c6, 1c6, 2c6, 3c6 ferovi pmon interrupt 0 0c5, 1c5, 2c5, 3c5 crcovi febeovi cofaovi oofovi prgdovi tfebeovi tcrcovi lcvove pmon interrupt control 1 0c4, 1c4, 2c4, 3c4 ferove pmon interrupt control 0 0c3, 1c3, 2c3, 3c3 crcove febeove cofaove oofove prgdove tfebeove tcrcove linksel[1:0] pmon access port 00e addr[3:0] data[7:0] pmon access data 00f updat pmon control 0c2, 1c2, 2c2, 3c2 autoupd note: * id means indirect register in the performance monitor function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 42 march 22, 2004 3.10 alarm detector 3.10.1 t1/j1 mode the red alarm, yellow alarm and blue alarm are detected in this block (refer to table 26). the status of the red alarm, ye llow alarm and blue alarm are indi- cated by the corresponding status bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the status bit wi ll set the corresponding interrupt indi- cation bit to ?1? and the interrupt indi cation bit will be cleared by writing a ?1?. a ?1? in the interrupt indication bit means there is an interrupt. the interrupt will be reported by the int pin if its interrupt enable bit is ?1?. table 26: red alarm, yellow alarm & blue alarm criteria declare condition clear condition status bit int errupt indication bit interrupt enable bit red alarm (per t1.403, t1.231) the out of sf/esf/t1 dm/slc-96 syn- chronization status persists nx40 ms. here ?n? is decided by the reddth[7:0] bits. the in sf/esf/t1 dm/slc-96 synchro- nization status persists mx120 ms. here ?m? is decided by the redcth[7:0] bits. red redi rede yellow alarm* t1 sf/ slc-96 format less than 77 ?one?s are detected on the bit 2 of each channel during a 40 ms fixed win- dow and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bits. more than 76 ?one?s are detected on the bit 2 of each channel during a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bits. yel yeli yele t1 esf format more than 7 ?0xff00? (msb first) are detected on the dl bits during a 40 ms fixed window and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bits. less than 8 ?0xff00? (msb first) are detected on the dl bits during a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bits. yel yeli yele t1 dm format less than 4 ?one?s are detected on the y bit (bit 6 in each ch 24) during a 40 ms fixed window and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bits. more than 3 ?one?s are detected on the y bit (bit 6 in each ch 24) during a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bits. yel yeli yele j1 sf format less than 4 zeros are detected on the f-bit of the 12nd frame during a 40 ms fixed win- dow and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bits. more than 3 zeros are detected on the f-bit of the 12nd frame during a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bits. yel yeli yele j1 esf format less than 3 zeros are detected on the dl bits during a 40 ms fixed window and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bits. more than 2 zeros are detected on the dl bits during a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bits. yel yeli yele blue alarm (per t1.231) less than 61 zeros are detected in a 40 ms fixed window and this status persists for nx40 ms. here ?n? is decided by the ais- dth[7:0] bits. more than 60 zeros are detected in a 40 ms fixed window and this status persists for mx40 ms. here ?m? is decided by the aiscth[7:0] bits. ais aisi aise note: * the yellow alarm can only be detected when the frame is synchronized.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 43 march 22, 2004 table 27: related bit / register in chapter 3.10.1 bit register t1/j1 address (hex) reddth[7:0] red declare threshold 0bc, 1bc, 2bc, 3bc redcth[7:0] red clear threshold 0bd, 1bd, 2bd, 3bd yeldth[7:0] yellow declare threshold 0be,1be, 2be, 3be yelcth[7:0] yellow clear threshold 0bf, 1bf, 2bf, 3bf aisdth[7:0] ais declare threshold 0c0, 1c0, 2c0, 3c0 aiscth[7:0] ais clear threshold 0c1, 1c1, 2c1, 3c1 red alarm status 0b9, 1b9, 2b9, 3b9 yel ais redi alarm indication 0bb, 1bb, 2bb, 3bb yeli aisi rede alarm control 0ba, 1ba, 2ba, 3ba yele aise
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 44 march 22, 2004 3.10.2 e1 mode the remote alarm, remote si gnaling multi-frame alarm, red alarm, ais alarm, ais in ts16 and los in ts16 are detected in this block. the remote alarm indication bit is the a bit (refer to table 18). it is detected on the base of basic frame synchronization. the criteria of remote alarm detection are defined by the raic bit. if the raic bit is ?0?, the remote alarm will be decla red when 4 consecutive a bits are received as ?1?, and the remote al arm will be cleared when a single a bit is received as ?0?. if the raic bit is ?1?, the remote alarm will be declared when a single a bit is received as ?1?, and the remote alarm will be cleared when a single a bit is received as ?0?. the remote alarm status is reflected by the raiv bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the raiv bit will set the raii bit to ?1? and the raii bit will be cleared by writing a ?1?. a ?1? in the raii bit means there is an interrupt. the inter- rupt will be reported by the int pin if the raie bit is ?1?. the remote signaling multi-frame al arm indication bit is the y bit (refer to figure 11). it is detected on the base of cas signaling multi- frame synchronization. the remote signaling multi-fram e alarm will be declared when 3 consecutive y bits are received as ?1?, and the remote signaling multi-frame alarm will be cleared when a single y bit is received as ?0?. the remote signal ing multi-frame alarm status is reflected by the rmaiv bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the rmaiv bit will set the rmaii bit to ?1? and the rmaii bit will be cleared by writing a ?1?. a ?1? in the rmaii bit means there is an interrupt. the interrupt will be reported by the int pin if the rmaie bit is ?1?. the criteria of red alarm detection meet i.431. the red alarm will be declared when out of basic fram e synchronization persists for 100 ms, and the red alarm will be clear ed when in basic frame synchroni- zation persists for 100 ms. the red al arm status is reflected by the red bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the red bit will set the redi bit to ?1? and the redi bit will be cleared by writing a ?1?. a ?1? in the redi bit means there is an interrupt. the interrupt will be reported by the int pin if the rede bit is ?1?. the ais alarm is detected whether it is in synchronization or not. the criteria of ais alarm are defined by the aisc bit. when the aisc bit is ?0?, the criteria meet i.431. the ais alarm will be declared when less than 3 zeros are detected in a 512-bit fixed window and it is out of basic frame synchronization, and the ai s alarm will be cleared when more than 2 zeros are detected in a 512-bit fixed window. when the aisc bit is ?1?, the criteria meet g.775. the ais alarm will be declared when less than 3 zeros are detected in each of 2 consecutive 512-bit fixed win- dows, and the ais alarm will be cleared when more than 2 zeros are detected in each of 2 consecutive 512 -bit fixed windows. the ais alarm status is reflected by the ais bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the ais bit will set the aisi bit to ?1? and the aisi bit will be cleared by writing a ?1?. a ?1? in the aisi bit means there is an interrupt. the interrupt will be reported by the int pin if the aise bit is ?1?. the ais in ts16 is detected on t he base of basic frame synchroni- zation. the ais in ts16 will be declared when ts16 contains less than 4 zeros in each of two 16-consecut ive-basic-frame periods. the ais in ts16 will be cleared when ts16 contains more than 3 zeros in a 16- consecutive-basic-frame period. the ais in ts16 status is reflected by the ts16aisv bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the ts16aisv bit will set the ts16aisi bit to ?1? and the ts16aisi bit will be cleared by writing a ?1?. a ?1? in the ts16aisi bit means there is an inter- rupt. the interrupt will be reported by the int pin if the ts16aise bit is ?1?. the los in ts16 is detected on the base of basic frame synchroni- zation. the los in ts16 will be dec lared when 16 consecutive ts16 are all received as ?0?. the los in ts16 will be cleared when 16 consecutive ts16 are not all received as ?0?. t he los in ts16 status is reflected by the ts16losv bit. any transition (from ?0? to ?1? or from ?1? to ?0?) on the ts16losv bit will set the ts16losi bit to ?1? and the ts16losi bit will be cleared by writing a ?1?. a ?1? in the ts16losi bit means there is an interrupt. the interrupt will be reported by the int pin if the ts16lose bit is ?1?. table 28: related bit / register in chapter 3.10.2 bit register e1 address (hex) raic alarm criteria control 0bc, 1bc, 2bc, 3bc aisc raiv alarm status 0b9, 1b9, 2b9, 3b9 rmaiv red ais ts16aisv ts16losv raii alarm indication 0bb, 1bb, 2bb, 3bb rmaii redi aisi ts16aisi ts16losi raie alarm control 0ba, 1ba, 2ba, 3ba rmaie rede aise ts16aise ts16lose
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 45 march 22, 2004 3.11 hdlc receiver the hdlc receiver extracts the hdlc/ss7 data stream from the selected position and processes the data according to the selected mode. 3.11.1 hdlc channel configuration in t1/j1 mode esf & t1 dm formats, three hdlc receivers (#1, #2 & #3) per link are provided for hdlc extraction from the received data stream. in t1/j1 mode sf & sl c-96 formats, two hdlc receivers (#2 & #3) per link are provided for hdlc extraction. in e1 mode, three hdlc receivers (#1, #2 & #3) per li nk are provided for hdlc extraction. except in t1/j1 mode esf & t1 dm formats, the hdlc channel of hdlc #1 is fixed in the dl bit (i n esf format) and d bit in ch24 (in t1 dm format) respectively (refer to table 13 & table 14), the other hdlc channels are configured as follows: 1. set the even bit and/or the odd bit to select the even and/or odd frames; 2. set the ts[4:0] bits to define the channel/timeslot of the assigned frame; 3. set the biten[7:0] bits to select the bits of the assigned channel/ timeslot. then all the functions of the hdlc receiver will be enabled only if the corresponding rdlen bit is set to ?1?. 3.11.2 two hdlc modes two modes are selected by the rhdlcm bit in the corresponding hdlc receiver. the two modes ar e: hdlc mode (per q.921) and ss7 mode (per q.703). 3.11.2.1 hdlc mode the structure of a standard hdlc packet consists of the following parts as shown in figure 12. each hdlc packet starts with a 7e (hex) opening flag and ends with the same flag. the closing flag may also serve as the opening flag of the next hdlc packet. following the open- ing flag, two-byte address is compar ed if the address comparison mode is selected. before the closing fl ag, two bytes of crc-ccitt frame check sequences (fcs) are provided to check all the hdlc packet (excluding the opening flag and closing flag). figure 12. standard hdlc packet after the stuffed zero (the zero following five consecutive ?one?s) is discarded, the data stream between the opening flag and the fcs is divided into blocks. each block (except the last block) has 32 bytes. the block will be pushed into a fifo with one-byte overhead ahead until any of the following invalid packet conditions occurs: - a packet with error fcs; table 29: related bit / register in chapter 3.11.1 bit register address (hex) even rhdlc1 assignment (e1 only) / rhdlc2 assignment / rhdlc3 assignment 08c, 18c, 28c, 38c (e1 only) / 08d, 18d, 28d, 38d / 08e, 18e, 28e, 38e odd ts[4:0] biten[7:0] rhdlc1 bit select (e1 only) / rhdlc2 bit select / rhdlc3 bit select 08f, 18f, 28f, 38f (e1 only) / 090, 190, 290, 390 / 091, 191, 291, 391 rdlen3 rhdlc enable control 08b, 18b, 28b, 38b rdlen2 rdlen1 flag one byte '01111110' fcs two bytes information n bytes control one byte address (optional) low byte address one byte high byte address one byte flag one byte '01111110' b7 b0 b0 c/r b7
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 46 march 22, 2004 - the data between the opening flag and the closing flag is less than 5 bytes (including the fcs, excluding the flags); - the extracted hdlc packet does not consist of an integral num- ber of octets; - a 7f (hex) abort sequence is received; - address is not matched if the address comparison is enabled. (the address comparison mode is se lected by the adrm[1:0] bits. if high byte address comparison is r equired, the high byte address posi- tion (the byte following the opening fl ag) is compared with the value in the ha[7:0] bits, or with ?0xfc? or ?0xfe?. here the ?c/r? bit position is excluded to compare. if low byte address comparison is required, the high byte address position is compared wi th the value in the la[7:0] bits. here the ?c/r? bit position is incl uded to compare. if both bytes address comparison is required, the high by te address position is compared with the value in the ha[7:0] bits, or with ?0xfc? or ?0xfe?. here the ?c/r? bit position is excluded to compare. and the low byte position (the byte fol- lowing the high byte address position) is compared with the value in the la[7:0] bits. if any of the above conditions is detected, the current block will be discarded, but the one-byte overhead will still be written into the fifo. the overhead consists of the m[2:0] bits and the length indication bits as shown in figure 13. figure 13. overhead indication in the fifo the fifo depth is 128 bytes. the fifo is accessed by the dat[7:0] bits. when the overhead is read from the fifo, it will be indi- cated by the pack bit. when all va lid hdlc blocks are pushed into the fifo or all the blocks are read from the fifo, it will be indicated by the emp bit. the interrupt sources in this block are summarized in table 30. when there are conditions meeting the interrupt sources, the corre- sponding interrupt indication bit will be set to ?1? and the interrupt indica- tion bit will be cleared by writing a ?1?. a ?1? in the interrupt indication bit means there is an interrupt. the interrupt will be reported by the int pin if its interrupt enable bit is ?1?. the hdlc receiver will be reset w hen there is a transition from ?0? to ?1? on the rrst bit. the reset will clear the fifo, the pack bit and the emp bit. overhead (one byte) bit 7 bit 0 m2 m1 m0 length indication m[2:0]: = 000: a valid short hdlc/ss7 packet is received, i.e., the data stream between the opening flag and the fcs is less than 32 by tes (including 32 bytes). = 001: the current block is not the last block of the hdlc/ss7 packet. = 010: the current block is the last block of a valid long (more than 32 bytes) hdlc/ss7 packet. = 011: reserved. = 100: an invalid short hdlc/ss7 packet is received and the current block is discarded. = 101: the current block is the last block of an invalid long hdlc/ss7 packet and the block is discarded. = 110: reserved. = 111: reserved. the length indication is valid when th e m2 bit is zero: length indication = n - 1 (n is the number of byte). otherwise, the length indication is zero. table 30: interrupt su mmarize in hdlc mode sources interrupt indication bit interrupt enable bit a block is pushed into the fifo. rmbei rmbee data is still attempted to write into the fifo when the fifo has been already full (128 bytes). ovfli ovfle
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 47 march 22, 2004 3.11.2.2 ss7 mode in ss7 mode, there are three kinds of signaling units - msu, lssu and fisu (refer to figure 14). t heir opening flag and closing flag are both 7e (hex). the closing flag ma y also serve as the opening flag of the next hdlc packet. figure 14. standard ss7 packet after the stuffed zero (the zero following five consecutive ?one?s) is discarded, the extracted ss7 data st ream is compared with the standard ss7 packet. if the value of the 6-bit l ength indication is equal to ?0?, the ss7 packet is fisu; if it is equal to ?1? or ?2?, the ss7 packet is lssu; if it is more than ?2?, the ss7 packet is msu. the data stream between the op ening flag and the fcs are divided into blocks. each block (except the last block) has 32 bytes. the block will be pushed into a fifo with one-by te overhead until any of the fol- lowing invalid packet conditions occurs: - a packet with error fcs; - the data between the opening flag and the closing flag is less than 5 bytes (including the fcs, excluding the flags); - the extracted ss7 packet does not consist of an integral number of octets; - a 7f (hex) abort sequence is received; - if the ss7 packet is fisu, the data between the opening flag and the closing flag is not 5 bytes (inc luding the fcs, excluding the flags); - if the ss7 packet is lssu, the data between the opening flag and the closing flag is not 6 or 7 byte s (including the fcs, excluding the flags); - if the ss7 packet is msu, the data between the opening flag and the closing flag is less than 8 byte s or more than 271 bytes (including the fcs, excluding the flags). if any of the above conditions is detected, the current block will be discarded, but the one-byte overhead will still be written into the fifo. the overhead consists of the m[2:0] bits and the length indication bits as shown in figure 13. in fisu/lssu, if the fisu/lssu filter is set by the fisufil/lssufil bit respectively, the current fisu/lssu will be dis- carded if it is the same with the previous fisu/lssu. in this condition, no data and overhead of the current fisu/lssu will be written into the fifo. the fifo depth is 128 bytes. the fifo is accessed by the dat[7:0] bits. when the overhead is r ead from the fifo, it will be indi- cated by the pack bit. when all valid ss7 blocks are pushed into the fifo or all the blocks are read from the fifo, it will be indicated by the emp bit. the interrupt sources in this bl ock are summarized in the table 30. when there are conditions meeting t he interrupt sources, the corre- sponding interrupt indication bit will be set to ?1? and the interrupt indica- tion bit will be cleared by wr iting a ?1?. a ?1? in the interrupt indication bit flag one byte '01111110' fcs two bytes signaling field n bytes (n>1) flag one byte '01111110' service information octet one byte two bits length indication six bits ( > 2 ) forward indication bit one bit forward sequence number seven bits seven bits backward indication bit one bit backward sequence number flag one byte '01111110' two bits length indication six bits ( = 1 or 2 ) forward indication bit one bit forward sequence number seven bits seven bits backward indication bit one bit backward sequence number flag one byte '01111110' fcs two bytes status one or two bytes flag one byte '01111110' two bits length indication six bits ( = 0 ) forward indication bit one bit forward sequence number seven bits seven bits backward indication bit one bit backward sequence number flag one byte '01111110' fcs two bytes message signaling unit (msu) link status signaling unit (lssu) fill in signaling unit (fisu)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 48 march 22, 2004 means there is an interrupt. the interrupt will be reported by the int pin if its interrupt enable bit is ?1?. the hdlc receiver will be reset w hen there is a transition from ?0? to ?1? on the rrst bit. the reset will clear the fifo, the pack bit and the emp bit. table 31: related bit / register in chapter 3.11.2 bit register address (hex) rhdlcm rhdlc1 control register / rhdlc2 control register / rhdlc3 control register 092, 192, 292, 392 / 093, 193, 293, 393 / 094, 194, 294, 394 adrm[1:0] rrst fisufil lssufil ha[7:0] rhdlc1 high address / rhdlc2 high address / rhdlc3 high addres s 0a1, 1a1, 2a1, 3a1 / 0a2, 1a2, 2a2, 3a2 / 0a3, 1a3, 2a3, 3a3 la[7:0] rhdlc1 low address / rhdlc2 low addres s / rhdlc3 low address 0a4, 1a4, 2a4, 3a4 / 0a5, 1a5, 2a5, 3a5 / 0a6, 1a6, 2a6, 3a6 dat[7:0] rhdlc1 data / rhdlc2 data / rhdlc3 data 098, 198, 298, 398 / 099, 199, 299, 399 / 09a, 19a, 29a, 39a, 49a pack rhdlc1 rfifo access status / 095, 195, 295, 395 / 096, 196, 296, 396 / 097, 197, 297, 397 emp rmbei rhdlc1 interrupt indication / rhdl c2 interrupt indication / rhdlc3 interrupt indication 09e, 19e, 29e, 39e / 09f, 19f, 29f, 39f / 0a0, 1a0, 2a0, 3a0 ovfli rmbee rhdlc1 interrupt control / rhdlc2 interru pt control / rh dlc3 interrupt control 09b, 19b, 29b, 39b / 09c, 19c, 29c, 39c / 09d, 19d, 29d, 39d ovfle
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 49 march 22, 2004 3.12 bit-oriented message receiver (t1/j1 only) the bit-oriented message (bom) can only be received in the esf format in t1/j1 mode. the bom pattern is ?111111110 xxxxxx0? which occupies the dl of the f-bit in the esf format (refer to table 13). the six ?x?s represent the message. the bom is declared only when the pattern is matched and the received message is identical 4 out of 5 consecutive times or 8 out of 10 consecutive times and differs from the previous message. the identi- fication time is selected by the avc bit. after a new bom is declared, the message is loaded into the boc[5:0] bits. every time when the boc[5:0] bits are updated, it will be indicated by the boci bit. a ?1? in the boci bit means there is an interrupt. the interrupt will be reported by the int pin if the boce bit is ?1?. 3.13 inband loopback co de detector (t1/j1 only) the inband loopback code detector tracks the loopback activate/ deactivate codes only in framed or unframed t1/j1 data stream, and meets ansi t1.403 9.3.1. the received data stream is compared with the target activate/ deactivate code whose length and c ontent are programmed in the asel[1:0]/dsel[1:0] bits and the act[7:0]/dact[7:0] bits respectively. in framed mode, the f-bit is select ed by the ibcdidle bit to compare with the target activate/deactivate code or not. in unframed mode, all 193 bits are compared with the ta rget activate/deactivate code. after four consecutive correct ac tivate/deactivate codes are found in the received data stream, the inband loopback code detector keeps on monitoring the bit error, i.e., the bit differs from the target activate/ deactivate code. if in more than 126 consecutive 39.8ms fixed periods, less than 600 bit errors are detected in each 39.8ms, the activate/deacti- vate code is detected and the corresponding lba/lbd bit will indicate it. once more than 600 bit errors are det ected in a 39.8ms fixed period, the activate/deactivate code is out of synchronization and the corresponding lba/lbd bit will be cleared. howeve r, even if the f-bit is compared, whether it is matched or not, the result will not cause bit errors, that is, the comparison result of the f-bit is discarded. any transition (from ?0? to ?1? or from ?1? to ?0?) on the lba/lbd bit will set the lbai/lbdi bit, which means there is an interrupt. the inter- rupt will be reported by the int pin if the corresponding lbae/lbde bit is set to ?1?. table 32: related bit / register in chapter 3.12 bit register t1/j1 address (hex) avc boc control 081, 181, 281, 381 boce boc[5:0] rboc code 083, 183, 283, 383 boci boc interrupt indication 082, 182, 282, 382 table 33: related bit / register in chapter 3.13 bit register t1/j1 address (hex) asel[1:0] ibcd detector configuration 076, 176, 276, 376 dsel[1:0] ibcdidle act[7:0] ibcd activate code 078, 178, 278, 378 dact[7:0] ibcd deactivate code 079, 179, 279, 379 lba ibcd detector status 077, 177, 277, 377 lbd lbai ibcd interrupt indication 07b, 17b, 27b, 37b lbdi lbae ibcd interrupt control 07a, 17a, 27a, 37a lbde
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 50 march 22, 2004 3.14 elastic store buffer in receive clock slave mode and receive multiplexed mode, a 2- basic-frame depth elastic store buffer is used to synchronize the incom- ing frames to the (mul tiplexed) receive side sy stem clock derived from the rsckn/mrsck pin, and to the (multiplexed) receive side system frame pulse derived from the rsfs n/mrsfs pin. a write pointer is used to write the data to the elastic store buffer, while a read pointer is used to read the data from the elastic store buffer. when the average frequency of the incoming data is greater than the average frequency of the (multipl exed) receive side system clock (rsckn/mrsck), the write pointer wi ll be faster than the read pointer and the elastic store buffer will be f illed. until there is less than or equal to 2 bytes between the write pointer and the read pointer, a frame will be deleted after its prior frame is read. when the read pointer crosses the frame boundary, a controlled slip will occur with a ?1? indicated in the slipd bit. when the average frequency of the incoming data is less than the average frequency of the rsckn/mr sck, the write pointer will be slower than the read pointer and the el astic store buffer will be empty. until there is less than or equal to 2 bytes between the write pointer and the read pointer, the frame will be repeated after it is read. when the read pointer crosses the next frame boundar y, a controlled slip will occur with a ?0? indicated in the slipd bit. when the slip occurs, the slipi bit will indicate it. an interrupt on the int pin will occur if the slipe bit is ?1?. in receive clock slave mode and receive multiplexed mode, if it is out of synchronization, the tr unk code programmed in the trk- code[7:0] bits will be set to replace the data if the trken bit is set to ?1?. in receive clock master mode, the elastic store buffer is bypassed unless the device is in the payload loopback diagnosis mode (refer to chapter 3.27.2.2 payload loopback). 3.15 receive cas/rbs buffer the receive cas/rbs buffer extrac ts the signaling bits from the received data stream. 3.15.1 t1/j1 mode in sf/esf/slc-96 format, the signaling bits are located in the bit 8 of frame 6n (n = 1,2 in sf format; 1 n 4 in esf format; 1 n 12 in slc-96 format) (refer to table 12, table 13 and table 15 respectively). the signaling codewords (ab or abc d) are clocked out on the rsign/ mrsiga(mrsigb) pins. they are in the lower nibble of the channel with its corresponding data serializing on the rsdn/mrsda(mrsigb) pins (as shown in figure 15). when the extract bit is set to ?1?, the signaling bits in its corre- sponding channel are extracted to the a, b,c,d bits in the extracted sig- naling data/extract enable register. in sf format, the c,d bits in the register are the repetition of the signaling bits a,b. the data in the a,b,c,d bits in the extracted signali ng data/extract enable register are the data to be output on the rsign/mrsiga(mrsigb) pins. however, in t1-dm format, there is no signaling bits. signaling de-bounce will be executed when the deb bit is set to ?1?. thus, the a,b,c,d bits in the extracted signaling data/extract enable register are updated only if 2 cons ecutive received ab/abcd codewords of the same channel are identical. signaling freezing is performed aut omatically when it is out of frame synchronization or when slips occu rs in the elastic store buffer. it is also performed when the freeze bit is set to ?1?. the signaling freez- ing freezes the signaling data in the a, b,c,d bits in the extracted signal- ing data/extract enable register as the previous valid value. in the esf and slc-96 format, if the sigf bit is set to ?0?, the extracted signaling bits are in 4 stat es signaling, i.e., the signaling bits on framer 6 & 18 of a signaling mult i-frame are recognized as ?a? and the signaling bits on framer 12 & 24 ar e recognized as ?b?. only the sig- naling bits a & b will be saved in the extracted signaling data/extract enable register, and the c & d bits in the extracted signaling data/ extract enable register are don?t-care. if the sigf bit is set to ?1?, the extracted signaling bits are in 16 stat es signaling, i.e., four signaling bits a, b, c & d are all saved in the extracted signaling data/extract enable register. each time the extracted signaling bits stored in the extracted sig- naling data/extract enable register are changed, it is captured by the corresponding cosi[x] bit (1 x 24). when the sige bit is set to ?1?, any one of the cosi[x] bits being ?1? will generate an interrupt and will be reported by the int pin. the extract bit and the a,b,c,d bits are in the indirect registers of the receive cas/rbs buffer. t hey are accessed by specifying the address in the address[6:0] bits. whether the data is read from or written into the specified indirect register is determined by the rwn bit and the data is in the d[7:0] bits. the access status is indicated in the busy bit. refer to chapter 4.5 indirect register access scheme for details about the indirect registers write/read access. table 34: related bit / register in chapter 3.14 bit register address (hex) slipd elst configuration 07c, 17c, 27c, 37c slipe trken slipi elst interrupt indication 07d, 17d, 27d, 37d trkcode[7:0] elst trunk code 07e, 17e, 27e, 37e
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 51 march 22, 2004 figure 15. signaling output in t1/j1 mode 3.15.2 e1 mode in signaling multi-frame, the signaling bits are located in ts16 (refer to figure 11), which are channel associated signalings (cas). the signaling codewords (abcd) are clocked out on the rsign/ mrsiga(mrsigb) pins. they are in the lower nibble of the timeslot with its corresponding data serializing on the rsdn/mrsda(mrsdb) pins (as shown in figure 16). when the extract bit is set to ?1?, the signaling bits in its corre- sponding timeslot are extracted to the a,b,c,d bits in the extracted sig- naling data/extract enable register. the data in the a,b,c,d bits in the register are the data to be output on the rsign/mrsiga(mrsigb) pins. the bits corresponding to ts0 and ts16 output on the rsign/ mrsiga(mrsigb) pins are don?t-care. signaling de-bounce will be executed when the deb bit is set to ?1?. thus, the a,b,c,d bits in the extr acted signaling data/extract enable register are updated only if 2 cons ecutive received abcd codewords of the same timeslot are identical. signaling freezing is performed automat ically when it is out of basic frame synchronization, out of signa ling multi-frame synchronization or slips occurs in the elastic store bu ffer. it is also performed when the freeze bit is set to ?1?. the si gnaling freezing freezes the signaling data in the a,b,c,d bits in the extracted signaling data/extract enable register as the previous valid value. each time the extracted signaling bits in the a,b,c,d bits in the extracted signaling data/extract enab le register are changed, it is cap- tured by the corresponding cosi[x] bit (1 x 30). when the sige bit is set to ?1?, any one of the cosi[x] bits being ?1? will generate an inter- rupt and will be reported by the int pin. the extract bit and the a,b,c,d bits are in the indirect registers of the receive cas/rbs buffer. t hey are accessed by specifying the address in the address[6:0] bits. whether the data is read from or written into the specified indirect register is determined by the rwn bit and the data is in the d[7:0] bits. the access status is indicated in the busy bit. refer to chapter 4.5 indirect register access scheme for details about the indirect registers write/read access. figure 16. signaling output in e1 mode channel 24 channel 1 channel 2 channel 24 a b c d rsdn/ mrsda(mrsdb) rsign/ mrsiga(mrsigb) f 1 2 3 4 5 6 7 8 channel 1 f f-bit f-bit 1 2 3 4 5 6 7 81 2 3 4 5 6 7 8 1 2 3 4 5 6 7 81 2 3 4 5 6 7 8 a b c d a b c d a b c d a b c d 1 2 3 4 5 6 78 ts31 ts0 ts1 ts15 ts16 ts17 ts31 ts0 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 abcd abcd abcd abcd abcd rsdn/ mrsda(mrsdb) rsign/ mrsiga(mrsigb)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 52 march 22, 2004 table 35: related bit / register in chapter 3.15 bit register address (hex) extract id* - extracted signaling data/extract enable rcrb id - 01~18 (for t1/j1) / 01~0f & 11~1f (for e1) a,b,c,d deb rcrb configuration 0d2, 1d2, 2d2, 3d2 freeze sigf (t1/j1 only) sige cosi[x] (1 x 24 in t1/j1) (1 x 30 in e1) rcrb state change indication 3 (e1 only) & rcrb state change indication 2 ~ 0 0d9, 1d9, 2d9, 3d9 (e1 only) & 0d8, 1d8, 2d8, 3d8 & 0d7, 1d7, 2d7, 3d7 & 0d6, 1d6, 2d6, 3d6 address[6:0] rcrb access control 0d4, 1d4, 2d4, 3d4 rwn d[7:0] rcrb access data 0d5, 1d5, 2d5, 3d5 busy rcrb access status 0d3, 1d3, 2d3, 3d3 note: * id means indirect register in the receive cas/rbs buffer function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 53 march 22, 2004 3.16 receive payload control different test patterns can be inserted in the received data stream or the received data stream can be extracted to the prbs generator/ detector for test in this block. to enable all the functions in the receive payload control, the pcce bit must be set to ?1?. the following methods can be executed on the data to be output on the rsdn/mrsda(mrsdb) pins on a per-channel/per-ts basis or on a global basis of the corresponding li nk (the methods are arranged from the highest to the lowest in priority): - when the testen bit is enabled and the prbsdir bit is ?0?, the received data will be extracted to the prbs generator/detector. the received data can be extracted in unframed mode, in 8-bit-based mode or in 7-bit-based mode. this sele ction is made by the prbsmode[1:0] bits. in unframed mode, all the received data stream is extracted and the per-channel/per-ts configurat ion in the test bit is ignored. in 8-bit- based mode or in 7-bit-based mode, the received data will only be extracted on the channel/timeslot conf igured by the test bit. refer to chapter 3.27.1 prbs generator / detector for details. - selected by the gsubst[2:0] bits, the data of all channels/ timeslots of the corresponding link will be replaced by the data trunk code set in the dtrk[7:0] bits, or the milliwatt pattern defined in the table 36 and table 37. when the gsubst[2:0] bits are set to ?000?, these replacements will be perform ed on a per-channel/per-ts basis by setting the subst[2:0] bits in the corresponding channel/timeslot. - when the sigfix bit is set to ?1 ?, the signaling bits (abcd) will be fixed to the value set in the pol bit. this function is only supported in the sf, esf and slc-96 formats in t1/j1 mode. - invert the most significant bit, the even bits and/or the odd bits by setting the sinv, oinv, einv bits. - when the testen bit is enabled and the prbsdir bit is ?1?, the received data will be replaced by the test pattern generated from the prbs generator/detector. the received data can be replaced in unframed mode, in 8-bit-based mode or in 7-bit-based mode. this selec- tion is made by the prbsmode[1:0] bits. in unframed mode, all the received data stream is replaced and the per-channel/per-ts configura- tion in the test bit is ignored. in 8-bit-based mode or in 7-bit-based mode, the received data will only be replaced on the channel/timeslot configured by the test bit. refer to chapter 3.27.1 prbs generator / detector for details. the following methods can be execut ed on the signaling bits to be output on the rsign/mrsiga(mrsig b) pins on a per-channel/per-ts basis or on a global basis of t he corresponding link (the methods are arranged from the highest to the lowest in priority): - selected by the abxx bit, the signaling bits can be valid in the upper 2-bit positions of the lower ni bble of each channel or in the lower nibble of each channel. the other bi ts of the channel are don?t care conditions. this function is only s upported in t1/j1 mode esf/slc-96 format. - enabled by the sigsnap bit, t he signaling snapshot will be exe- cuted. the signaling snapshot means t hat the signaling bits of the first basic frame are locked and output as the signaling bits of the current whole multi-frame. this function is not supported in t1 dm format. - enabled by the gstrken bit, the signaling bits (abcd) of all channels/timeslots of the corresponding link will be replaced by the sig- naling trunk conditioning code in t he a,b,c,d bits. when the gstrken bit is ?0?, the replacement will be performed on a per-channel/per-ts basis by setting the strken bit in the corresponding channel/timeslot. the indirect registers of the re ceive payload control are accessed by specifying the address in the addr ess[6:0] bits. whether the data is table 36: a-law digital milliwatt pattern bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 byte 1 00110100 byte 2 00100001 byte 3 00100001 byte 4 00110100 byte 5 10110100 byte 6 10100001 byte 7 10100001 byte 8 10110100 table 37: -law digital milliwatt pattern bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 byte 1 00011110 byte 2 00001011 byte 3 00001011 byte 4 00011110 byte 5 10011110 byte 6 10001011 byte 7 10001011 byte 8 10011110
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 54 march 22, 2004 read from or written into the specifi ed indirect register is determined by the rwn bit and the data is in the d[7: 0] bits. the access status is indi- cated in the busy bit. refer to chapter 4.5 indirect register access scheme for details about the indire ct registers write/read access. table 38: related bit / register in chapter 3.16 bit register address (hex) pcce rplc control enable 0d1, 1d1, 2d1, 3d1 sigfix (t1/j1 only) pol (t1/j1 only) abxx (t1/j1 only) testen tplc / rplc / prgd test conf iguration 0c7, 1c7, 2c7, 3c7 prbsdir prbsmode[1:0] test id * - signaling trunk conditioning code rplc id - 41~58 (for t1/j1) / 41~4f & 51~5f (for e1) strken a,b,c,d gsubst[2:0] rplc configuration 0d0, 1d0, 2d0, 3d0 sigsnap gstrken dtrk[7:0] id - data trunk condit ioning code rplc id - 21~38 (for t1/j1) / 20~3f (for e1) subst[2:0] id - channel control (for t1/j1) / timeslot control (f or e1) rplc id - 01~18 (for t1/j1) / 00~1f (for e1) sinv oinv einv address[6:0] rplc access control 0ce, 1ce, 2ce, 3ce rwn d[7:0] rplc access data 0cf, 1cf, 2cf, 3cf busy rplc access status 0cd, 1cd, 2cd, 3cd note: * id means indirect register in the receive payload control function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 55 march 22, 2004 3.17 receive system interface the receive system interface determines how to output the received data stream to the system backplane. the data from the four links can be aligned with each other or be output independently. the tim- ing clocks and framing pulses can be provided by the system backplane or obtained from the far end. the receive system interface supports various configurations to meet vari ous requirements in different applica- tions. 3.17.1 t1/j1 mode in t1/j1 mode, the receive system interface can be set in non- multiplexed mode or multiplexed mode. in the non-multiplexed mode, the rsdn pin is used to output the re ceived data from each link at the bit rate of 1.544 mb/s or 2.048 mb/s (t1/j1 mode e1 rate). while in the mul- tiplexed mode, the received data from the four links is converted to 2.048 mb/s format and byte interleaved to form one high speed data stream and output on the mrsda1 (mrsdb1) pins at the bit rate of 8.192 mb/s. in the non-multiplexed mode, if the receive system interface and the receive line side are timed to a same clock source, the receive sys- tem interface is in receive clock master mode. if the receive system interface and the receive line side are timed to different clock sources, the receive system interface is in receive clock slave mode. in the receive clock master mode, if rsckn outputs pulses during the entire t1/j1 frame, the receive system interface is in receive clock master full t1/j1 mode. if only the clocks aligned to the selected chan- nels are output on rsckn, the receive system interface is in receive clock master fractional t1/j1 mode. in the receive clock slave mode, the backplane data rate may be equal to 1.544 mb/s (i.e., the line data rate) or 2.048 mb/s. if the back- plane data rate is 2.048 mb/s, the receive system interface is in t1/j1 mode e1 rate and the received data stream (1.544 mb/s) should be mapped per 3 kinds of schemes. in the receive multiplexed mode, since the received data from the four links should be converted to 2.048 mb/s format first and then multi- plexed to 8.192 mb/s, there are still 3 kinds of schemes to be selected. table 39 summarizes how to set the receive system interface of each link into various operating modes and the pins? direction of the receive system interface in different operating modes. 3.17.1.1 receive clock master mode in the receive clock master m ode, each link uses its own timing signal on the rsckn pin and framing pulse on the rsfsn pin to output the data on each rsdn pin. the signal ing bits on the rsign pin are per- channel aligned with the data on the rsdn pin. in the receive clock master mode, the data on the system inter- face is clocked by the rsckn. the active edge of the rsckn used to update the pulse on the rsfsn is det ermined by the fe bit. the active edge of the rsckn used to update the data on the rsdn and rsign is determined by the de bit. if the fe bi t and the de bit are not equal, the pulse on the rsfsn is ahead. in the receive clock master mode, the rsfsn can indicate each f-bit or the first f-bit of every sf /esf/t1 dm/slc-96 multi-frame. in sf format, the rsfsn can also indicate every second f-bit or the first f-bit of every second sf multi-frame. all the indications are selected by the cmfs bit and the altifs bit. the active polarity of the rsfsn is selected by the fsinv bit. the receive clock master mode includes two sub-modes: receive clock master full t1/j1 mode and receive clock master fractional t1/ j1 mode. 3.17.1.1.1 receive clock master full t1/j1 mode besides all the common functions described in the receive clock master mode, the special feature in this mode is that the rsckn is a standard 1.544 mhz clock, and the data in the f-bit and all 24 channels in a standard t1/j1 frame are clocked out by the rsckn. table 39: operating modes se lection in t1/j1 receive path rmux rmode g56k, gap / fbitgap map[1:0] 2 operating mode receive system interface pin input output 0 0 00 / 0 x receive clock master full t1/j1 x rsckn, rsfsn, rsdn, rsign not all 0s 1 receive clock master fractional t1/j1 1x 00 receive clock slave - t1/j1 rate rsckn, rsfsn rsdn, rsign 01 receive clock slave - t1/j1 mode e1 rate per g.802 10 receive clock slave - t1/j1 mode e1 rate per one filler every four chs 11 receive clock slave - t1/j1 mode e1 rate per continuous chs 1x x 01 receive multiplexed - t1/j1 mode e1 rate per g.802 mrsck, mrsfs mrsda[1], mrsiga[1] (mrsdb[1], mrsigb[1]) 3 10 receive multiplexed - t1/j1 mode e1 rate per one filler every four chs 11 receive multiplexed - t1/j1 mode e1 rate per continuous chs note: 1. when the g56k, gap bits in rplc indirect re gisters are set, the pcce bit must be set to ?1?. 2. the map[1:0] bits can not be set to ?00? in the receive multiplexed mode. 3. in receive multiplexed mode, two sets of multiplexed data and signaling pins (a and b) are pr ovided. their functions are the same. one is the backup for the other.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 56 march 22, 2004 3.17.1.1.2 receive clock master fractional t1/j1 mode besides all the common functions described in the receive clock master mode, the special feature in this mode is that the rsckn is a gapped 1.544 mhz clock (no clock signal during the selected position). the rsckn is gapped during the f-bit if the fbitgap bit is set to ?1?. the rsckn is also gapped during the channels or the bit 8 duration by selecting the g56k & gap bits in the receive payload control. the data in the corresponding gapped durat ion is a don't care condition. 3.17.1.2 receive clock slave mode in the receive clock slave mode, the system data rate can be 1.544 mb/s or 2.048 mb/s. if the system data rate is 1.544 mb/s, it works in t1/j1 mode. if the system data rate is 2.048 mb/s, the received data stream (1.544 mb/s) should be mapped to the same rate as the system side, that is, to work in t1/j1 mode e1 rate. three kinds of schemes are provided by selecting the map[1:0] bits: 1. t1/j1 mode e1 rate per g.802 (refer to figure 17): channel 1 to channel 15 of frame n from the device are converted into ts1 to ts15 of frame n on the system side; c hannel 16 to channel 24 of frame n from the device are converted into ts17 to ts25 of frame n on the sys- tem side. the f-bit of frame n from t he device is converted into the first bit of ts26 of frame (n-1) on the system side. ts0, ts16, ts27~ts31 and the other 7 bits in ts26 on the syst em side are all filled with ?0?s and they are meaningless. 2. t1/j1 mode e1 rate per one fi ller every four chs (refer to figure 18): one dummy byte is inserted on the system side before 3 bytes of frame n from the device ar e converted. this process repeats 8 times and the conversion of frame n of 1.544 mb/s data rate to 2.048 mb/s data rate is completed. however, the f-bit of frame n of the 1.544 mb/s data rate is inserted as the 8th bit of frame n of the 2.048 mb/s data rate. the dummy bytes are filled with all ?0?s and they are meaning- less. 3. t1/j1 mode e1 rate per cont inuous chs (refer to figure 19): channel 1 to channel 24 of frame n from the device are converted into ts1 to ts24 of frame n on the system side. the f-bit of frame n from the device is converted into the 8t h bit of frame n on the system side. the first 7 bits and ts25 to ts31 on the system side are all filled with ?0?s and they are meaningless. figure 17. t1/j1 to e1 format mapping - g.802 mode figure 18. t1/j1 to e1 format mapping - one filler every four channels mode 1.544 mb/s 2.048 mb/s ch1 ch2 ch14 f ch15 ch16 ch17 ch23 ch24 ch1 ch2 f ch23 ts0 ts2 ts1 ts14 ts15 ts16 ts17 ts18 ts24 ts25 ts26 ts27~ts31 ts0 ts1 the 1st bit filler filler filler filler filler 1.544 mb/s 2.048 mb/s ch1 ch2 ch3 f ch4 ch5 ch6 ch22 ch23 ch24 ch1 f ch2 ts0 ts2 ts1 ts4 ts5 ts6 ts7 ts8 ts28 ts29 ts30 ts31 ts1 ts0 the 8th bit ch7 ts3 ts9 the 8th bit filler filler filler filler filler
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 57 march 22, 2004 figure 19. t1/j1 to e1 format mapping - continuous channels mode in the receive clock slave mode, the timing signal on the rsckn pin and the framing pulse on the rsfsn pin to output the data on the rsdn pin are provided by the system side. when the rslvck bit is set to ?0?, each link uses its own rsckn and rsfsn; when the rslvck bit is set to ?1? and all four links are in the receive clock slave mode, the four links use the rsck[1] and rsfs [1] to output the data. the signal- ing bits on the rsign pin are per -channel aligned with the data on the rsdn pin. in the receive clock slave mode, the data on the system interface is clocked by the rsckn. the active edge of the rsckn used to sample the pulse on the rsfsn is determined by the fe bit. the active edge of the rsckn used to update the data on the rsdn and rsign is deter- mined by the de bit. if the fe bit and the de bit are not equal, the pulse on the rsfsn is ahead. the data rate of the system side is 1.544 mb/s or 2.048 mb/s. when it is 2.048 mb/s, the rsckn can be selected by the cms bit to be the same rate as the data rate on the system side (2.048 mhz) or double the data rate (4.096 mhz). if all four links use the rsck[1] and rsfs[1] to output the data, the cms bit of the four links should be set to the same value. if the speed of the rsckn is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit determines the active edge to update the data on the rsdn and rsign pins. the pulse on the rsfsn pin is always sampled on its first active edge. in the receive clock slave mode, the rsfsn asserts at a rate of integer multiple of 125 s to indicate the start of a frame. the active polarity of the rsfsn is selected by the fsinv bit. if the pulse on the rsfsn pin is not an integer multiple of 125 s, this detection will be indi- cated by the rcofai bit. if the rcofae bit is enabled, an interrupt will be reported by the int pin when the rcofai bit is ?1?. 3.17.1.3 receive multiplexed mode in the receive multiplexed mode, since the received data from the four links should be mapped to 2.048 mb /s format first, the 3 kinds of schemes should be selected by the map[1:0] bits. the mapping per g.802, per one filler every four chs and per continuous chs are the same as the description in chapter 3.17.1.2 receive clock slave mode. in the receive multiplexed mode, a multiplexed bus is used to out- put the data from all four links. the dat a of link 1 to link 4 is byte-inter- leaved output on the multiplexed bus 1. when the data from the four links is output on one multiplexed bus, the sequence of the data is arranged by setting the channel offset. the data from different links on one multiplexed bus must be shifted at a different channel offset to avoid data mixing. in the receive multiplexed mode, the timing signal on the mrsck pin and the framing pulse on the mr sfs pin are provided by the system side and common to all four links. the signaling bits on the mrsiga (mrsigb) pin are per-channel ali gned with the corresponding data on the mrsda (mrsdb) pin. in the receive multiplexed mode, the data on the system interface is clocked by the mrsck. the ac tive edge of the mrsck used to sam- ple the pulse on the mrsfs is det ermined by the fe bit. the active edge of the mrsck used to update the data on the mrsda (mrsdb) and mrsiga (mrsigb) is determined by the de bit. the fe bit and the de bit of the four links should be set to the same value respectively. if the fe bit and the de bit are not equal, the pulse on the mrsfs is ahead. the mrsck can be selected by the cms bit to be the same rate as the data rate on the system side (8.192 mhz) or double the data rate (16.384 mhz). the cms bit of the f our links should be set to the same value. if the speed of the mrsck is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit deter- mines the active edge to update the data on the mrsda (mrsdb) and mrsiga (mrsigb) pins. the pulse on the mrsfs pin is always sam- pled on its first active edge. in the receive multiplexed mode, the mrsfs asserts at a rate of integer multiple of 125 s to indicate the start of a frame. the active polarity of the mrsfs is selected by the fsinv bit. the fsinv bit of the four links should be set to the same value. if the pulse on the mrsfs pin is not an integer multiple of 125 s, this detection will be indicated by the rcofai bit. if the rcofae bit is enabled, an interrupt will be reported by the int pin when the rcofai bit is ?1?. 3.17.1.4 offset bit offset and channel offset are both supported in all the operating modes. the offset is between the framing pulse on rsfsn/mrsfs pin and the start of the corresponding frame output on the rsdn/ mrsda(mrsdb) pin. the si gnaling bits on the rsign/ 1.544 mb/s 2.048 mb/s ch1 ch2 ch3 f ch23 ch1 ch2 ch24 ts0 ts2 ts1 ts23 ts24 ts0 ts1 ts2 ts24 the 8th bit ch24 ts3 ts25~ts31 the 8th bit f f ch1 filler filler filler
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 58 march 22, 2004 mrsiga(mrsigb) pin are always per-channel aligned with the data on the rsdn/mrsda(mrsdb) pin. figure 20 to figure 23 show the base line without offset. figure 20. no offset when fe = 1 & de = 1 in receive path figure 21. no offset when fe = 0 & de = 0 in receive path rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) receive clock slave mode / receive multiplexed mode: receive clock master mode: bit 1 of ch1 / ts0 bit 2 bit 2 bit 1 of ch1 / ts0 fe = 1, de = 1 rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) bit 1 of ch1 / ts0 bit 2 bit 2 bit 1 of ch1 / ts0 fe = 0, de = 0 receive clock slave mode / receive multiplexed mode: rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) receive clock master mode:
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 59 march 22, 2004 figure 22. no offset when fe = 0 & de = 1 in receive path figure 23. no offset when fe = 1 & de = 0 in receive path the bit offset and channel of fset are configured when the boff[2:0] bits and the tsoff[6:0] bits are not ?0? respectively. when the cms bit is ?0? and the boff[2:0] bits are set, the start of the corresponding frame output on t he rsdn/mrsda(mrsdb) pin will delay ?n? clock cycles to the fr aming pulse on the rsfsn/mrsfs pin. (here ?n? is defined by the boff[2:0 ] bits.) when the cms bit is ?0? and the tsoff[6:0] bits are set, the start of the corresponding frame output on the rsdn/mrsda(mrsdb) pin will del ay ?8 x m? clock cycles to the framing pulse on the rsfsn/mrsfs pi n. (here ?m? is defined by the tsoff[6:0].) when the cms bit is ?1? (i.e., in double clock mode) and the boff[2:0] bits are set, the start of the corresponding frame output on the rsdn/mrsda(mrsdb) pin will delay ?2 x n? clock cycles to the framing pulse on the rsfsn/mrsfs pi n. (here ?n? is defined by the boff[2:0] bits.) when the cms bit is ?1? (i.e., in double clock mode) and the tsoff[6:0] bits are set, the start of the corresponding frame output on the rsdn/mrsda(mrsdb) pin will delay ?16 x m? clock cycles to the framing pulse on the rsfsn/mrsfs pi n. (here ?m? is defined by the tsoff[6:0].) in non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). in multiplexed mode, the channel offset can be configured fr om 0 to 127 channels (0 & 127 are included). 3.17.1.5 output on rsdn/mrsda(mrsdb) & rsign/ mrsiga(mrsigb) the output on the rsdn/mrsda(mrsdb) and the rsign/ mrsiga(mrsigb) pins can be confi gured by the tri bit of the corre- sponding link to be in high impedance state or to output the processed data stream. bit 1 of ch1 / ts0 bit 2 bit 2 bit 1 of ch1 / ts0 fe = 0, de = 1 receive clock slave mode / receive multiplexed mode: rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) receive clock master mode: bit 2 bit 1 of ch1 / ts0 fe = 1, de = 0 bit 1 of ch1 / ts0 bit 2 receive clock slave mode / receive multiplexed mode: rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) rsfsn / mrsfs rsckn / mrsck rsdn / mrsda(b) receive clock master mode:
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 60 march 22, 2004 3.17.2 e1 mode in e1 mode, the receive system interface can be set in non-multi- plexed mode or multiplexed mode. in the non-multiplexed mode, the rsdn pin is used to output the received data from each link at the bit rate of 2.048 mb/s. while in the multiplexed mode, the received data from the four links is byte interleaved to form one high speed data stream and output on the mrsda1 (mrsdb1) pins at the bit rate of 8.192 mb/s. in the non-multiplexed mode, if the receive system interface and the receive line side are timed to a same clock source, the receive sys- tem interface is in receive clock master mode. if the receive system interface and the receive line side are timed to different clock sources, the receive system interface is in receive clock slave mode. in the receive clock master mode, if rsckn outputs pulses during the entire e1 frame, the receive system interface is in receive clock master full e1 mode. if only the clocks aligned to the selected timeslots are output on rsckn, the receive system interface is in receive clock master fractional e1 mode. table 40 summarizes how to set the receive system interface of each link into various operating modes and the pins? direction of the receive system interface in different operating modes. 3.17.2.1 receive clock master mode in the receive clock master m ode, each link uses its own timing signal on the rsckn pin and framing pulse on the rsfsn pin to output the data on each rsdn pin. the signal ing bits on the rsign pin are per- timeslot aligned with the data on the rsdn pin. in the receive clock master mode, the data on the system inter- face is clocked by the rsckn. the active edge of the rsckn used to update the pulse on the rsfsn is det ermined by the fe bit. the active edge of the rsckn used to update the data on the rsdn and rsign is determined by the de bit. if the fe bi t and the de bit are not equal, the pulse on the rsfsn is ahead. in the receive clock master mode, the rsfsn can indicate the basic frame, crc multi-frame, signa ling multi-frame, or both the crc multi-frame and signaling multi-fram e, or the ts1 and ts 16 overhead. all the indications are selected by the ohd bit, the smfs bit and the cmfs bit. the active polarity of the rsfsn is selected by the fsinv bit. the receive clock master mode includes two sub-modes: receive clock master full e1 mode and receive clock master fractional e1 mode. 3.17.2.1.1 receive clock master full e1 mode besides all the common functions described in the receive clock master mode, the special feature in this mode is that the rsckn is a standard 2.048 mhz clock, and the data in all 32 timeslots in a standard e1 frame is clocked out by the rsckn. 3.17.2.1.2 receive clock master fractional e1 mode besides all the common functions described in the receive clock master mode, the special feature in this mode is that the rsckn is a gapped 2.048 mhz clock (no clock signal during the selected timeslot). the rsckn is gapped during the time slots or the bit 8 duration by selecting the g56k & gap bits in t he receive payload control. the data in the corresponding gapped duration is a don't care condition. 3.17.2.2 receive clock slave mode in the receive clock slave mode, the timing signal on the rsckn pin and framing pulse on the rsfsn pin to output the data on the rsdn pin are provided by the system side. when the rslvck bit is set to ?0?, each link uses its own rsckn and rs fsn; when the rslvck bit is set to ?1? and all four links are in the receive clock slave mode, the four links use the rsck[1] and rsfs[1] to output the data. the signaling bits on the rsign pin are per-timeslot aligned with the data on the rsdn pin. in the receive clock slave mode, the data on the system interface is clocked by the rsckn. the active edge of the rsckn used to sample the pulse on the rsfsn is determined by the fe bit. the active edge of the rsckn used to update the data on the rsdn and rsign is deter- mined by the de bit. if the fe bit and the de bit are not equal, the pulse on the rsfsn is ahead. the speed of the rsckn can be selected by the cms bit to be the same rate as the data rate on the system side (2.048 mhz) or double the data rate (4.096 mhz). if all four links use the rsck[1] and rsfs[1] to output the data, the cms bit of the four links should be set to the same value. if the speed of the rsckn is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit determines the active edge to update the data on the table 40: operating modes selection in e1 receive path rmux rmode g56k, ga p operating mode receive system interface pin input output 0 0 00 receive clock master full e1 x rsckn, rsfsn, rsdn, rsign not both 0s 1 receive clock master fractional e1 1 x receive clock slave rsc kn, rsfsn rsdn, rsign 1x x receive multiplexed mrsck, mrsfs mrsda[1], mrsiga[1] (mrsdb[1], mrsigb[1]) 2 note: 1. when the g56k, gap bits in rplc indirect regi sters are set, the pcce bit must be set to ?1?. 2. in receive multiplexed mode, two sets of multiplexed data and signaling pins (a and b) are provided. their functions are the same. one is the backup for the other.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver functional description 61 march 22, 2004 rsdn and rsign pins. the pulse on the rsfsn pin is always sampled on its first active edge. in the receive clock slave mode, the rsfsn asserts at a rate of integer multiple of 125 s to indicate the start of a frame. the active polarity of the rsfsn is selected by the fsinv bit. if the pulse on the rsfsn pin is not an integer multiple of 125 s, this detection will be indi- cated by the rcofai bit. if the rcofae bit is enabled, an interrupt will be reported by the int pin when the rcofai bit is ?1?. 3.17.2.3 receive multiplexed mode in the receive multiplexed mode, one multiplexed bus is used to output the data from all four links. the data of link 1 to link 4 is byte- interleaved output on the multiplexed bus 1. when the data from the four links is output on one multiplexed bus, the sequence of the data is arranged by setting the timeslot offs et. the data from different links on one multiplexed bus must be shifted at a different timeslot offset to avoid data mixing. in the receive multiplexed mode, the timing signal on the mrsck pin and the framing pulse on the mr sfs pin are provided by the system side and common to all four links. the signaling bits on the mrsiga (mrsigb) pin are per-timeslot aligned with the corresponding data on the mrsda (mrsdb) pin. in the receive multiplexed mode, the data on the system interface is clocked by the mrsck. the active edge of the mrsck used to sam- ple the pulse on the mrsfs is det ermined by the fe bit. the active edge of the mrsck used to update the data on the mrsda (mrsdb) and mrsiga (mrsigb) is determined by the de bit. the fe bit and the de bit of the four links should be set to the same value respectively. if the fe bit and the de bit are not equal, the pulse on the mrsfs is ahead. the mrsck can be selected by the cms bit to be the same rate as the data rate on the system side (8.192 mhz) or double the data rate (16.384 mhz). the cms bit of the fo ur links should be set to the same value. if the speed of the mrsck is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit deter- mines the active edge to update the data on the mrsda (mrsdb) and mrsiga (mrsigb) pins. the pulse on the mrsfs pin is always sam- pled on its first active edge. in the receive multiplexed mode, the mrsfs asserts at a rate of integer multiple of 125 s to indicate the start of a frame. the active polarity of the mrsfs is selected by the fsinv bit. the fsinv bit of the four links should be set to the same value. if the pulse on the mrsfs pin is not an integer multiple of 125 s, this detection will be indicated by the rcofai bit. if the rcofae bit is enabled, an interrupt will be reported by the int pin when the rcofai bit is ?1?. 3.17.2.4 offset except that in the receive master mode, when the ohd bit, the smfs bit and the cmfs bit are se t to ts1 and ts16 overhead indica- tion, the bit offset and timeslot offset are both supported in all the other conditions. the offset is between the framing pulse on rsfsn/mrsfs pin and the start of the corresponding frame output on the rsdn/ mrsda(mrsdb) pin. the si gnaling bits on the rsign/ mrsiga(mrsigb) pin are always per -timeslot aligned with the data on the rsdn/mrsda(mrsdb) pin. refer to chapter 3.17.1.4 offset for the base line without offset in different operating modes and the configuration of the offset. in non-multiplexed mode, the ti meslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). in multiplexed mode, the timeslot offset can be configured fr om 0 to 127 timeslots (0 & 127 are included). 3.17.2.5 output on rsdn/mrsda(mrsdb) & rsign/ mrsiga(mrsigb) the output on the rsdn/mrsda(mrsdb) and the rsign/ mrsiga(mrsigb) pins can be confi gured by the tri bit of the corre- sponding link to be in high impedance state or to output the processed data stream. table 41: related bit / register in chapter 3.17 bit register address (hex) rmux backplane global configuration 010 rslvck rmode rbif mode 047, 147, 247, 347 map[1:0] (t1/j1 only) g56k id * - channel control (for t1/ j1) / timeslot control (for e1) rplc id - 01~18 (for t1/j1) / 00~1f (for e1) gap fbitgap (t1/j1 only) rbif operation 046, 146, 246, 346 fe de cms tri pcce rplc control enable 0d1, 1d1, 2d1, 3d1 cmfs rbif frame pulse 048, 148, 248, 348 altifs (t1/j1 only) fsinv ohd (e1 only) smfs (e1 only) edge rbif bit offset 04a, 14a, 24a, 34a boff[2:0] rcofai rtsfs change indication 04bh, 14b, 24b, 34b rcofae rtsfs interrupt control 04c, 14c, 24c, 34c tsoff[6:0] rbit ts offset 049, 149, 249, 349 note: * id means indirect register in the re ceive payload control function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 62 march 22, 2004 3.18 transmit system interface the transmit system interface determines how to input the data to the device. the data input to the four links can be aligned with each other or input independently. the ti ming clocks and framing pulses can be provided by the system backpl ane or obtained from the processed data of each link. the transmit syst em interface supports various con- figurations to meet various requi rements in different applications. 3.18.1 t1/j1 mode in t1/j1 mode, the transmit system interface can be set in non- multiplexed mode or multiplexed mode. in the non-multiplexed mode, the tsdn pin is used to input the data to each link at the bit rate of 1.544 mb/s or 2.048 mb/s (t1/j1 mode e1 rate). while in the multiplexed mode, the data is byte-interleav ed from one high speed data stream and inputs on the mtsda1 (mtsdb1) pins at the bit rate of 8.192 mb/s. the demultiplexed data input to the four links is 2.048 mb/s on the system side and converted into 1.544 mb/s format to the device. in the non-multiplexed mode, if the transmit system interface and the transmit line side are timed to a same clock source, the transmit system interface is in transmit cl ock master mode. if the transmit sys- tem interface and the transmit line si de are timed to different clock sources, the transmit system inte rface is in transmit clock slave mode. in the transmit clock master mode, if tsckn outputs pulses during the entire t1/j1 frame, the transmit system interface is in transmit clock master full t1/j1 mode. if only the clocks aligned to the selected channels are output on tsckn, the transmit system interface is in transmit clock master fractional t1/j1 mode. in the transmit clock slave mode, the backplane data rate may be equal to 1.544 mb/s (i.e., the line data rate) or 2.048 mb/s. if the back- plane data rate is 2.048 mb/s, the trans mit system interface is in t1/j1 mode e1 rate and the data to be transmitted should be mapped to 1.544 mb/s per 3 kinds of schemes. in the transmit multiplexed mode, since the demultiplexed data rate on the system side (2.048 mb/s) should be mapped to the data rate in the line side (1.544 mb/s), there are still 3 kinds of schemes to be selected. table 42 summarizes how to set the transmit system interface of each link into various operating modes and the pins? direction of the transmit system interface in different operating modes. 3.18.1.1 transmit clock master mode in the transmit clock master m ode, each link uses its own timing signal on the tsckn pin and framing pulse on the tsfsn pin to input the data on each tsdn pin. the signal ing bits on the tsign pin are per- channel aligned with the data on the tsdn pin. in the transmit clock master mode, the data on the system inter- face is clocked by the tsckn. the active edge of the tsckn used to update the pulse on the tsfsn is determined by the fe bit. the active edge of the tsckn used to sample the data on the tsdn and tsign is determined by the de bit. if the fe bit and the de bit are not equal, the pulse on the tsfsn is ahead. in the transmit clock master mode, the tsfsn can indicate each f-bit or the first f-bit of every sf /esf/t1 dm/slc-96 multi-frame. the indications are selected by the fsty p bit. the active polarity of the tsfsn is selected by the fsinv bit. the transmit clock master mode includes two sub-modes: trans- mit clock master full t1/j1 mode and transmit clock master fractional t1/j1 mode. table 42: operating modes selection in t1/j1 transmit path tmux tmode g56k, gap / fbitgap map[1:0] 2 operating mode transmit system interface pin input output 0 0 00 / 0 x transmit clock master full t1/j1 tsdn, tsign tsckn, tsfsn not all 0s 1 transmit clock master fractional t1/j1 1x 00 transmit clock slave - t1/j1 rate tsdn, tsign, tsckn, tsfsn x 01 transmit clock slave - t1/j1 mode e1 rate per g.802 10 transmit clock slave - t1/j1 mode e1 rate per one filler every four chs 11 transmit clock slave - t1/j1 mode e1 rate per continuous chs 1x x 01 transmit multiplexed - t1/j1 mode e1 rate per g.802 mtsck, mtsfs, mtsda[1], mtsiga[1] (mtsdb[1], mtsigb[1]) 3 x 10 transmit multiplexed - t1/j1 mode e1 rate per one filler every four chs 11 transmit multiplexed - t1/j1 mode e1 rate per continuous chs note: 1. when the g56k, gap bits in tplc indirect r egisters are set, the pcce bit must be set to ?1?. 2. the map[1:0] bits can not be set to ?00? in the transmit multiplexed mode. 3. in transmit multiplexed mode, two sets of multiplexed data and signaling pins (a and b) are provided for one multiplexed bus . their functions are the same. one is the backup for the other. one set is selected by the mtsda bit when used.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 63 march 22, 2004 3.18.1.1.1 transmit clock master full t1/j1 mode besides all the common functions described in the transmit clock master mode, the special feature in this mode is that the tsckn is a standard 1.544 mhz clock, and the dat a in the f-bit and all 24 channels in a standard t1/j1 frame are clocked in by the tsckn. 3.18.1.1.2 transmit clock master fractional t1/j1 mode besides all the common functions described in the transmit clock master mode, the special feature in this mode is that the tsckn is a gapped 1.544 mhz clock (no clock signal during the selected channel). the tsckn is gapped during the f-bit if the fbitgap bit is set to ?1?. the tsckn is also gapped during the channels or the bit 8 duration by selecting the g56k & gap bits in the transmit payload control. the data in the corresponding gapped durati on is a don't care condition. 3.18.1.2 transmit clock slave mode in the transmit clock slave mode, the system data rate can be 1.544 mb/s or 2.048 mb/s. if the system data rate is 1.544 mb/s, it works in t1/j1 mode. if the system data rate is 2.048 mb/s, the data stream to be transmitted should be mapped to 1.544 mb/s, that is, to work in t1/j1 mode e1 rate. three kinds of schem es are provided by selecting the map[1:0] bits: 1. t1/j1 mode e1 rate per g.802 (refer to figure 24): ts1 to ts15 of frame n on the system side are converted into channel 1 to channel 15 of frame n to the device; ts17 to ts25 of frame n on the system side are converted into channel 16 to channel 24 of frame n to the device. the first bit of ts26 of fr ame (n-1) on the system side is con- verted into the f-bit of frame n to the device. ts0, ts16, ts27~ts31 and the other 7 bits in ts26 on the system side are all discarded. 2. t1/j1 mode e1 rate per one fi ller every four chs (refer to figure 25): the 8th bit of frame n on t he system side is converted to the f-bit of the frame n to the device. then one byte of the system side is discarded after the previous three by tes are converted into the device. this process repeats 8 times and the conversion of one frame is com- pleted. then the process goes on. 3. t1/j1 mode e1 rate per cont inuous chs (refer to figure 26): ts1 to ts24 of frame n on the system side are converted into channel 1 to channel 24 of frame n to the dev ice. the 8th bit of frame n on the system side is converted into the f-bi t of frame n to the device. the first 7 bits and ts25 to ts31 on the system side are all discarded. figure 24. e1 to t1/j1 format mapping - g.802 mode figure 25. e1 to t1/j1 format mapping - one filler every four channels mode 1.544 mb/s 2.048 mb/s ch1 ch2 ch14 f ch15 ch16 ch17 ch23 ch24 ch1 ch2 f ch23 ts0 ts2 ts1 ts14 ts15 ts16 ts17 ts18 ts24 ts25 ts26 ts27~ts31 ts0 ts1 the 1st bit discarded discarded discarded discarded discarded 1.544 mb/s 2.048 mb/s ch1 ch2 ch3 f ch4 ch5 ch6 ch22 ch23 ch24 ch1 f ch2 ts0 ts2 ts1 ts4 ts5 ts6 ts7 ts8 ts28 ts29 ts30 ts31 ts1 ts0 the 8th bit ch7 ts3 ts9 the 8th bit discarded discarded discarded discarded discarded
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 64 march 22, 2004 figure 26. e1 to t1/j1 format mapping - continuous channels mode in the transmit clock slave mode, the timing signal on the tsckn pin and the framing pulse on the tsfsn pin to input the data on the tsdn pin are provided by the system side. when the tslvck bit is set to ?0?, each link uses its own tsckn and tsfsn; when the tslvck bit is set to ?1? and all four links are in the transmit clock slave mode, the four links use the tsck[1] and tsfs[1] to input the data. the signaling bits on the tsign pin are per-channe l aligned with the data on the tsdn pin. in the transmit clock slave mode, the data on the system interface is clocked by the tsckn. the active edge of the tsckn used to sample the pulse on the tsfsn is determined by the fe bit. the active edge of the tsckn used to sample the data on the tsdn and tsign is deter- mined by the de bit. if the fe bit and the de bit are not equal, the pulse on the tsfsn is ahead. the data rate of the system side is 1.544 mb/s or 2.048 mb/s. when it is 2.048 mb/s, the tsckn can be selected by the cms bit to be the same rate as the data rate on the system side (2.048 mhz) or double the data rate (4.096 mhz). if all four links use the tsck[1] and tsfs[1] to input the data, the cms bit of the four links should be set to the same value. if the speed of the tsckn is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit determines the active edge to sample the data on the tsdn and tsign pins. the pulse on the tsfsn pin is always sampled on its first active edge. in the transmit clock slave mode, the tsfsn can indicate each f- bit or the first f-bit of every sf /esf/t1 dm/slc-96 multi-frame. the indications are selected by the fst yp bit. the active polarity of the tsfsn is selected by the fsinv bit. if the pulse on the tsfsn pin is not an integer multiple of 125 s, this detection will be indicated by the tcofai bit. if the tcofae bit is enabled, an interrupt will be reported by the int pin when the tcofai bit is ?1?. 3.18.1.3 transmit multiplexed mode in the transmit multiplexed mode, since the demultiplexed data rate on the system side (2.048 mb/s) should be mapped to the data rate in the line side (1.544 mb/s), 3 kinds of schemes should be selected by the map[1:0] bits. the schemes per g.802, per one filler every four chs and per continuous chs are the same as the description in chapter 3.18.1.2 transmit clock slave mode. in the transmit multiplexed mode, one multiplexed bus is used to transmit the data to all four links. the data of link 1 to link 4 is byte- interleaved input from the multiplexed bus 1. when the data on the mul- tiplexed bus is input to four lin ks, the sequence of the data is arranged by setting the channel offset. the data to different links from one multi- plexed bus must be shifted at a different channel offset to avoid data mixing. in the transmit multiplexed mode, the timing signal on the mtsck pin and the framing pulse on the mt sfs pin are provided by the system side and common to all four links. the signaling bits on the mtsiga (mtsigb) pin are per-channel ali gned with the corresponding data on the mtsda (mtsdb) pin. in the transmit multiplexed mode, the data on the system interface is clocked by the mtsck. the ac tive edge of the mtsck used to sam- ple the pulse on the mtsfs is det ermined by the fe bit. the active edge of the mtsck used to sample the data on the mtsda (mtsdb) and mtsiga (mtsigb) is determined by the de bit. the fe bit and the de bit of the four links should be set to the same value respectively. if the fe bit and the de bit are not equal, the pulse on the mtsfs is ahead. the mtsck can be selected by the cms bit to be the same rate as the data rate on the system side (8.192 mhz) or double the data rate (16.384 mhz). the cms bit of the f our links should be set to the same value. if the speed of the mtsck is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit deter- mines the active edge to sample the data on the mtsda (mtsdb) and mtsiga (mtsigb) pins. the pulse on the mtsfs pin is always sam- pled on its first active edge. in the transmit multiplexed mode, the mtsfs can indicate each f- bit of the first link or the first f- bit of every sf/esf/t1 dm/slc-96 multi- frame of the first link. the indicati ons are selected by the fstyp bit. the active polarity of the mtsfs is se lected by the fsinv bit. the fstyp bit and the fsinv bit of the four links should be set to the same value. if the pulse on the mtsfs pin is not an integer multiple of 125 s, this detection will be indicated by the tcofai bit. if the tcofae bit is enabled, an interrupt will be reported by the int pin when the tcofai bit is ?1?. 1.544 mb/s 2.048 mb/s ch1 ch2 ch3 f ch23 ch1 ch2 ch24 ts0 ts2 ts1 ts23 ts24 ts0 ts1 ts2 ts24 the 8th bit ch24 ts3 ts25~ts31 the 8th bit f f ch1 discarded discarded discarded
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 65 march 22, 2004 3.18.1.4 offset bit offset and channel offset are both supported in all the operating modes. the offset is between the framing pulse on the tsfsn/mtsfs pin and the start of the corresponding frame input on the tsdn/ mtsda(mtsdb) pin. the si gnaling bits on the tsign/ mtsiga(mtsigb) pin are always per-channel aligned with the data on the tsdn/mtsda(mtsdb) pin. figure 27 to figure 30 show the base line without offset. figure 27. no offset when fe = 1 & de = 1 in transmit path figure 28. no offset when fe = 0 & de = 0 in transmit path bit 2 bit 2 bit 1 of ch1 / ts0 bit 1 of ch1 / ts0 fe = 1, de = 1 transmit clock slave mode / transmit multiplexed mode: tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) transmit clock master mode: tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) bit 2 bit 2 bit 1 of ch1 / ts0 bit 1 of ch1 / ts0 fe = 0, de = 0 transmit clock slave mode / transmit multiplexed mode: transmit clock master mode: tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 66 march 22, 2004 figure 29. no offset when fe = 0 & de = 1 in transmit path figure 30. no offset when fe = 1 & de = 0 in transmit path the bit offset and channel of fset are configured when the boff[2:0] bits and the tsoff[6:0] bits are not ?0? respectively. when the cms bit is ?0? and the boff[2:0] bits are set, the start of the corresponding frame input on t he tsdn/mtsda(mtsdb) pin will delay ?n? clock cycles to the fr aming pulse on the tsfsn/mtsfs pin. (here ?n? is defined by the boff[2:0 ] bits.) when the cms bit is ?0? and the tsoff[6:0] bits are set, the start of the corresponding frame input on the tsdn/mtsda(mtsdb) pin will del ay ?8 x m? clock cycles to the framing pulse on the tsfsn/mtsfs pi n. (here ?m? is defined by the tsoff[6:0].) when the cms bit is ?1? (i.e., in double clock mode) and the boff[2:0] bits are set, the start of the corresponding frame input on the tsdn/mtsda(mtsdb) pin will delay ?2 x n? clock cycles to the framing pulse on the tsfsn/mtsfs pin. (here ?n? is defined by the boff[2:0] bits.) when the cms bit is ?1? (i.e., in double clock mode) and the tsoff[6:0] bits are set, the star t of the corresponding frame input on the tsdn/mtsda(mtsdb) pin will delay ?16 x m? clock cycles to the framing pulse on the tsfsn/mtsfs pi n. (here ?m? is defined by the tsoff[6:0].) in non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). in multiplexed mode, the channel offset can be configured fr om 0 to 127 channels (0 & 127 are included). bit 2 bit 1 of ch1 / ts0 fe = 0, de = 1 bit 2 bit 1 of ch1 / ts0 transmit clock slave mode / transmit multiplexed mode: transmit clock master mode: tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) bit 2 bit 2 bit 1 of ch1 / ts0 bit 1 of ch1 / ts0 fe = 1, de = 0 transmit clock slave mode / transmit multiplexed mode: transmit clock master mode: tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b) tsfsn / mtsfs tsckn / mtsck tsdn / mtsda(b)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 67 march 22, 2004 3.18.2 e1 mode in e1 mode, the transmit system interface can be set in non-multi- plexed mode or multiplexed mode. in the non-multiplexed mode, the tsdn pin is used to input the data to each link at the bit rate of 2.048 mb/s. while in the multiplexed mode, the data is byte interleaved from one high speed data stream and inputs on the mtsda1 (mtsdb1) pins at the bit rate of 8.192 mb/s. in the non-multiplexed mode, if the transmit system interface and the transmit line side are timed to a same clock source, the transmit system interface is in transmit cl ock master mode. if the transmit sys- tem interface and the transmit line si de are timed to different clock sources, the transmit system inte rface is in transmit clock slave mode. in the transmit clock master mode, if tsckn outputs pulses during the entire e1 frame, the transmit syst em interface is in transmit clock master full e1 mode. if only the clocks aligned to the selected timeslots are output on tsckn, the transmit system interface is in transmit clock master fractional e1 mode. table 43 summarizes how to set the transmit system interface of each link into various operating modes and the pins? direction of the transmit system interface in different operating modes. 3.18.2.1 transmit clock master mode in the transmit clock master m ode, each link uses its own timing signal on the tsckn pin and framing pulse on the tsfsn pin to input the data on each tsdn pin. the signal ing bits on the tsign pin are per- timeslot aligned with the data on the tsdn pin. in the transmit clock master mode, the data on the system inter- face is clocked by the tsckn. the active edge of the tsckn used to update the pulse on the tsfsn is determined by the fe bit. the active edge of the tsckn used to sample the data on the tsdn and tsign is determined by the de bit. if the fe bi t and the de bit are not equal, the pulse on the tsfsn is ahead. in the transmit clock master m ode, the tsfsn can indicate the basic frame, crc multi-frame and/or signaling multi-frame. the indica- tions are selected by the fstyp bit. the active polarity of the tsfsn is selected by the fsinv bit. the transmit clock master mode includes two sub-modes: trans- mit clock master full e1 mode and transmit clock master fractional e1 mode. 3.18.2.1.1 transmit clock master full e1 mode besides all the common functions described in the transmit clock master mode, the special feature in this mode is that the tsckn is a standard 2.048 mhz clock, and the data in all 32 timeslots in a standard e1 frame are clocked in by the tsckn. 3.18.2.1.2 transmit clock master fractional e1 mode besides all the common functions described in the transmit clock master mode, the special feature in this mode is that the tsckn is a gapped 2.048 mhz clock (no clock signal during the selected timeslot). the tsckn is gapped during the time slots or the bit 8 duration by selecting the g56k & gap bits in the transmit payload control. the data in the corresponding gapped duration is a don't care condition. 3.18.2.2 transmit clock slave mode in the transmit clock slave mode, the timing signal on the tsckn pin and the framing pulse on the tsfsn pin to input the data on the tsdn pin are provided by the system side. when the tslvck bit is set to ?0?, each link uses its own tsckn and tsfsn; when the tslvck bit is set to ?1? and all four links are in the transmit clock slave mode, the four links use the tsck[1] and tsfs[1] to input the data. the signaling bits on the tsign pin are per-times lot aligned with the data on the tsdn pin. in the transmit clock slave mode, the data on the system interface is clocked by the tsckn. the active edge of the tsckn used to sample the pulse on the tsfsn is determined by the fe bit. the active edge of the tsckn used to sample the data on the tsdn and tsign is deter- mined by the de bit. if the fe bit and the de bit are not equal, the pulse on the tsfsn is ahead. the speed of the tsckn can be selected by the cms bit to be the same rate as the data rate on the system side (2.048 mb/s) or double the data rate (4.096 mb/s). if all four links use the tsck[1] and tsfs[1] to input the data, the cms bit of the four links should be set to the same value. if the speed of the tsckn is double the data rate, there will be two active edges in one bit duration. in this case, table 43: operating modes sel ection in e1 transmit path tmux tmode g56k, gap operating mode transmit system interface pin input output 0 0 00 transmit clock master full e1 tsdn, tsign tsckn, tsfsn not both 0s 1 transmit clock master fractional e1 1 x transmit clock slave tsckn, tsfsn, tsdn, tsign x 1 x x transmit multiplexed mtsck, mtsfs, mtsda[1], mtsiga[1] (mtsdb[1], mtsigb[1]) 2 x note: 1. when the g56k, gap bits in tplc indirect registers are set, the pcce bit must be set to ?1?. 2. in transmit multiplexed mode, two sets of multiplexed data and signaling pins (a and b) are provided for one multiplexed bus . their functions are the same. one is the backup for the other. one set is selected by the mtsda bit when used.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 68 march 22, 2004 the edge bit determines the active edge to sample the data on the tsdn and tsign pins. the pulse on the tsfsn pin is always sampled on its first active edge. in the transmit clock slave mode, the tsfsn can indicate the basic frame, crc multi-frame and/or signaling multi-frame. the indica- tions are selected by the fstyp bit. the active polarity of the tsfsn is selected by the fsinv bit. if the pulse on the tsfsn pin is not an integer multiple of 125 s, this detection will be indicated by the tcofai bit. if the tcofae bit is enabled, an inte rrupt will be reported by the int pin when the tcofai bit is ?1?. 3.18.2.3 transmit multiplexed mode in the transmit multiplexed mode, one multiplexed bus is used to transmit the data to all four links. t he data of link 1 to link 4 is byte- interleaved input from the multiplexed bus 1. when the data on the mul- tiplexed bus is input to four links , the sequence of the data is arranged by setting the timeslot offset. the data to different links from one multi- plexed bus must be shifted at a differ ent timeslot offset to avoid data mixing. in the transmit multiplexed mode, the timing signal on the mtsck pin and the framing pulse on the mtsf s pin are provided by the system side and common to all four links. the signaling bits on the mtsiga (mtsigb) pin are per-timeslot al igned with the corresponding data on the mtsda (mtsdb) pin. in the transmit multiplexed mode, the data on the system interface is clocked by the mtsck. the ac tive edge of the mtsck used to sam- ple the pulse on the mtsfs is deter mined by the fe bit. the active edge of the mtsck used to sample the data on the mtsda (mtsdb) and mtsiga (mtsigb) is determined by the de bit. the fe bit and the de bit of the four links should be set to the same value respectively. if the fe bit and the de bit are not equal, the pulse on the mtsfs is ahead. the mtsck can be selected by the cms bit to be the same rate as the data rate on the system side (8.192 mhz) or double the data rate (16.384 mhz). the cms bit of the fo ur links should be set to the same value. if the speed of the mtsck is double the data rate, there will be two active edges in one bit duration. in this case, the edge bit deter- mines the active edge to sample the data on the mtsda (mtsdb) and mtsiga (mtsigb) pins. the pulse on the mtsfs pin is always sam- pled on its first active edge. in the transmit multiplexed mode, the mtsfs can indicate the basic frame, crc multi- frame and/or signaling mult i-frame of the first link. the indications are selected by the fstyp bit. the active polarity of the mtsfs is selected by the fsin v bit. the fstyp bit and the fsinv bit of the four links should be set to the same value. if the pulse on the mtsfs pin is not an integer multiple of 125 s, this detection will be indicated by the tcofai bit. if the tcofae bit is enabled, an interrupt will be reported by the int pin when the tcofai bit is ?1?. 3.18.2.4 offset bit offset and timeslot offset are both supported in all the operating modes. the offset is between the framing pulse on the tsfsn/mtsfs pin and the start of the corresponding frame input on the tsdn/ mtsda(mtsdb) pin. the si gnaling bits on the tsign/ mtsiga(mtsigb) pin are always per -timeslot aligned with the data on the tsdn/mtsda(mtsdb) pin. refer to chapter 3.18.1.4 offset for the base line without offset in different operating modes and the configuration of the offset. in non-multiplexed mode, the ti meslot offset can be configured from 0 to 31 timeslots (0 & 31 are included). in multiplexed mode, the timeslot offset can be configured fr om 0 to 127 timeslots (0 & 127 are included). table 44: related bit / register in chapter 3.18 bit register address (hex) tmux backplane global configuration 010 mtsda tslvck tmode tbif operating mode 043, 143, 243, 343 map[1:0] (t1/j1 only) g56k id * - channel control (for t1/j1) / timeslot control (for e1) tplc id * - 01~18 (for t1/j1) / 00~1f (for e1) gap pcce tplc control enable 0cc, 1cc, 2cc, 3cc fbitgap (t1/j1 only) tbif option register 042, 142, 242, 342 fe de fstyp fsinv cms edge tbif bit offset 045, 145, 245, 345 boff[2:0] tcofai rtsfs change indication 04b, 14b, 24b, 34b tcofae rtsfs interrupt control 04c, 14c, 24c, 34c tsoff[6:0] tbif ts offset 044, 144, 244, 344 note: * id means indirect register in the tr ansmit payload control function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 69 march 22, 2004 3.19 transmit payload control different test patterns can be inserted in the data stream to be transmitted or the data stream to be transmitted can be extracted to the prbs generator/detector for test in this block. to enable all the functions in the transmit payload control, the pcce bit must be set to ?1?. the following methods can be exec uted on the data input from the tsdn/mtsda (mtsdb) pins on a per -channel/per-ts basis or on a glo- bal basis of the corresponding link (the methods are arranged from the highest to the lowest in priority): - when the testen bit is enabled and the prbsdir bit is ?1?, the data to be transmitted will be extract ed to the prbs generator/detector. the data to be transmitted can be extr acted in unframed mode, in 8-bit- based mode or in 7-bit-based mode. this selection is made by the prb- smode[1:0] bits. in unframed mode, all the data stream to be transmit- ted is extracted and the per-channel/ per-ts configuration in the test bit is ignored. in 8-bit-based mode or in 7-bit-based mode, the data will only be extracted on the channel/timesl ot configured by the test bit. refer to chapter 3.27.1 prbs generator / detector for details. - configured by the zcs[2:0] bits, four types of zero code sup- pression can be selected to implement to the data of all the channels of the corresponding link. this function is only supported in t1/j1 mode. - selected by the gsubst[2:0] bits, the data of all channels/ timeslots of the corresponding link wi ll be replaced by the trunk code set in the dtrk[7:0] bits, the milliwatt pattern defined in table 36 and table 37, or the payload loopback data from the elastic store buffer (refer to chapter 3.27.2.2 payload loopback). when the gsubst[2:0] bits are set to ?000?, these r eplacements will be performed on a per- channel/per-ts basis by setting the su bst[2:0] bits in the correspond- ing channel/timeslot. - controlled by the sigins bit, the signaling bits input from the tsign/mtsiga (mtsigb) pins (afte r processed by the signaling trunk conditioning replacement and/or valid signaling bits selection) can be inserted into its signaling bit position of the data stream to be transmit- ted. - invert the most significant bit, the even bits and/or the odd bits by setting the sinv, oinv, einv bits. - when the testen bit is enabled and the prbsdir bit is ?0?, the data to be transmitted will be repl aced by the test pattern generated from the prbs generator/detector. the data to be transmitted can be replaced in unframed mode, in 8- bit-based mode or in 7-bit-based mode. this selection is made by the prbsmode[1:0] bits. in unframed mode, all the data stream to be transmitted is replaced and the per- channel/per-ts configuration in the t est bit is ignored. in 8-bit-based mode or in 7-bit-based mode, the da ta will only be replaced on the chan- nel/timeslot configured by the test bit. refer to chapter 3.27.1 prbs generator / detector for details. the following methods can be ex ecuted on the signaling bits input from the tsign/mtsiga (mtsigb) pins on a per-channel/per-ts basis or on a global basis of the corres ponding link. the processed signaling bits will be inserted to the data stream to be transmitted if frame is gen- erated. the methods are arranged from the highest to the lowest in pri- ority: - selected by the abxx bit, the signaling bits can be valid in the upper 2-bit positions of the lower ni bble of each channel or in the lower nibble of each channel. the other bi ts of the channel are don?t care conditions. this function is only s upported in t1/j1 mode esf/slc-96 format. - enabled by the sigsnap bit, t he signaling snapshot will be exe- cuted. the signaling snapshot means t hat the signaling bits of the first basic frame are locked and output as the signaling bits of the current whole multi-frame. this function is not supported in t1 dm format. - enabled by the gstrken bit, the signaling bits (abcd) of all channels/timeslots of the corresponding link will be replaced by the sig- naling trunk conditioning code in t he a,b,c,d bits. when the gstrken bit is ?0?, the replacement can be performed on a per-channel/per-ts basis by setting the strken bit in the corresponding channel/timeslot. the indirect registers of the tr ansmit payload control are accessed by specifying the address in the addr ess[6:0] bits. whether the data is read from or written into the specif ied indirect register is determined by the rwn bit and the data is in the d[7:0] bits. the access status is indi- cated in the busy bit. refer to chapter 4.5 indirect register access scheme for details about the indire ct registers write/read access. table 45: related bit / register in chapter 3.19 bit register address (hex) pcce tplc control enable 0cc, 1cc, 2cc, 3cc abxx (t1/j1 only) testen tplc / rplc / prgd test configuration 0c7, 1c7, 2c7, 3c7 prbsdir prbsmode[1:0] test id * - signaling trunk condi- tioning code tplc id * - 41~58 (for t1/j1) / 41~4f & 51~5f (for e1) sigins (t1/j1 only) a,b,c,d strken zcs[2:0] (t1/j1 only) tplc configuration 0cb, 1cb, 2cb, 3cb gsubst[2:0] sigsnap gstrken dtrk[7:0] id * - data trunk conditioning code tplc id * - 21~38 (for t1/j1) / 20~3f (for e1) subst[2:0] id * - channel control (for t1/ j1) / timeslot control (for e1) tplc id * - 01~18 (for t1/j1) / 00~1f (for e1) sinv oinv einv address[6:0] tplc access control 0c9, 1c9, 2c9, 3c9 rwn d[7:0] tplc access data 0ca, 1ca, 2ca, 3ca busy tplc access status 0c8, 1c8, 2c8, 3c8 note: * id means indirect register in the tr ansmit payload control function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 70 march 22, 2004 3.20 frame generator 3.20.1 generation 3.20.1.1 t1 / j1 mode in t1/j1 mode, the data to be transmitted can be generated as super-frame (sf), extended super-frame (esf), t1 digital multiplexer (dm) or switch line carrier - 96 (slc-96) format. 3.20.1.1.1 super frame (sf) format the sf is generated when the fdis bit is ?0?. the frame alignment pattern (?100011011100? for t1 / ?10001101110x? for j1) will replace the f- bit of each frame if the fdis bit is set to ?0?. the f-bit of the 12th frame in j1 mode should be ?0? unless yellow alarm signal is transmitted. when the fdis bit is ?0?, one ft bit (the f-bit in odd frame, refer to table 12) will be inverted if the ftinv bit is set; one fs bit (the f-bit in even frame, refer to table 12) will be inverted if the fsinv bit is set. when the fdis bit is ?0?, confi gured by the mimicen bit, the mimic pattern can be inserted into the bit right after each f-bit. the content of the mimic pattern is the same as t he f-bit. the mimic pattern insertion is for diagnostic purpose. the yellow alarm signal will be manually inserted in the data stream to be transmitted when the xyel bit is set, or the yellow alarm signal will be inserted automatica lly by setting the autoyellow bit when red alarm is declared in the received data stream. the pattern and the position of the yellow alarm is different in t1 and j1 modes: - in t1 mode, the yellow alarm signal is logic 0 on the 2nd bit of each channel; - in j1 mode, the yellow alarm signal is logic 1 on the 12th f-bit position. 3.20.1.1.2 extended super frame (esf) format the esf is generated when the fdis bit is ?0?. the frame alignment pattern (? 001011?) will replace the f-bit in frame (4n) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 71 march 22, 2004 the mimic pattern is the same as t he f-bit. the mimic pattern insertion is for diagnostic purpose. the yellow alarm signal will be manually inserted in the data stream to be transmitted when the xyel bit is set, or the yellow alarm signal will be inserted automatica lly by setting the autoyellow bit when red alarm is declared in the received data stream. the yellow alarm signal is logic 0 on the 2nd bit of each channel. 3.20.1.1.5 interrupt summary at the first bit of each basic frame, the bfi bit will be set. in this con- dition, if the bfe bit is enabled, an interrupt will be reported by the int pin. at the first bit of each sf/esf/t1 dm/slc-96 multiframe, the mfi bit will be set. in this condition, if the mfe bit is enabled, an interrupt will be reported by the int pin. table 46: related bit / register in chapter 3.20.1.1 bit register t1/j1 address (hex) fdis t1/j1 mode 062, 162, 262, 362 crcbyp fdlbyp ftinv error insertion 06f, 16f, 26f, 36f fsinv crcinv ddsinv mimicen fgen maintenance 1 06c, 16c, 26c, 36c xyel fgen maintenance 0 06b, 16b, 26b, 36b autoyellow c[11:1] xdl1 & xdl0 066, 166, 266, 366 & 065, 165, 265, 365 m[3:1] xdl1 066, 166, 266, 366 a[2:1] xdl2 067, 167, 267, 367 s[4:1] bfi fgen interrupt indication 06e, 16e, 26e, 36e mfi bfe fgen interrupt control 06d, 16d, 26d, 36d mfe
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 72 march 22, 2004 3.20.1.2 e1 mode in e1 mode, the frame generat or can generate basic frame, crc-4 multi-frame and channel as sociated signaling (cas) multi- frame. the frame generator can al so transmit alarm indication signal when special conditions occurs in the received data stream. interna- tional bits, national bits and extra bits replacements and data inversions are all supported in the frame generator. the generation of the basic fr ame, crc multi-frame and channel associated signaling (cas) multi-fram e are controlled by the fdis bit, the gencrc bit, the crcm bit and the sigen bit. refer to table 47 for details. when the basic frame is gener ated, the frame alignment sequence (fas) (?0011011?) will replace the bit 2 ~ bit 8 of ts0 of each even frame; the nfas bit (?1?) will r eplace the bit 2 of ts0 of each odd frame. if the fas1inv bit is set, one fas bit will be inverted; if the fasallinv bit is set, one 7-bit fas pattern will be inverted; if the nfas- inv bit is set, one nfas bit will be inverted. when the basic frame is generated, if the sidis bit is ?0?, the value set in the si[1] and si[0] bits will re place the international bit (bit 1) of fas frame and nfas frame respectively. when the basic frame is generated, the remote alarm indication (rai) can be transmitted as logic 1 in the a bit position. it is transmitted manually when the remais bit is ?1?. it can also be transmitted automat- ically when the autoyellow bit is set to ?1?. in this case, the rai transmission criteria are sele cted by the g706rai bit. when the basic frame is generated, the setting in the sax[1] bit will be transmitted in the sa bit posi tion if enabled by the corresponding saxen bit (?x? is from 4 to 8). the crc multi-frame is generated on the base of the basic frame generation. when it is generated, t he crc multi-frame alignment pat- tern (?001011?) will replace the bit 1 of ts0 of the first 6 odd frames; the calculated 4-bit crc of the previous sub-multi-frame will be inserted in the crc-bit positions of the curren t sub-multi-frame. the crc-bit posi- tion is the bit 1 of ts0 of each even frame. refer to table 18 for the crc multi-frame structure. if t he crcpinv bit is set, one 6-bit crc multi-frame alignment pattern will be inverted; if the crcinv bit is set, all 4 calculated crc bits in one sub-multi-frame will be inverted. when the crc multi-frame is generat ed, since 14 international bit positions have been occupied by the crc multi-frame alignment pat- tern and crc-4 checking bits, the rema ining 2 international bit positions are inserted by the e bits. the control over the e bits is illustrated in table 48. when the crc multi-frame is generated, the setting in the sax[1:4] bits will be transmitted in the sa bit position if enabled by the corresponding saxen bit (?x? is from 4 to 8). the channel associated signaling (cas) multi-frame is generated on the base of the basic frame generation. when it is generated, the signaling multi-frame alignment patte rn (?0000?) will replace the high nibble (bit 1 ~ bit 4) of ts16 of every 16 basic frames. if the caspinv bit is set, one 4-bit signaling multi- frame alignment pattern will be inverted. when the signaling multi-frame is generated, if the xdis bit is ?0?, the value set in the fgen extra regi ster will be inserted into the extra bits (the bit 5, 7 & 8 of ts16 of fr ame 0 of the signaling multi-frame). when the signaling multi-frame is generated, the value in the mfais bit will be continuously transmitt ed in the y bit position (the bit 6 of ts16 of frame 0 of the signaling multi-frame). when the signaling multi-frame is generated, all the bits in ts16 can be overwritten by all ?zero?s or all ?one?s by setting the ts16los bit or the ts16ais bit respectively. t he all zeros overwritten takes a higher priority. when the modified crc multi-frame is generated, only the sa bit position and the calculated crc-4 bit position can be changed. all the other bits are transparently transmitted unless all ?one?s or all ?zero?s are transmitted (refer to chapter 3.20.6 all ?zero?s & all ?one?s). the frame can only be generated on the base of the fdis bit being ?0?. if the fdis bit is set to ?1?, the data received from the transmit pay- load control will be transmitted trans parently to the hdlc transmitter. table 47: e1 frame generation desired frame type fdis gencrc crcm sigen basic frame 00 xx 01 0x crc multi-frame 0 1 0 x modified crc multi-frame 0 1 1 x channel associated signaling (cas) multi- frame 00 x1 01 01 table 48: control over e bits febedis oocmfv sidis e bits insertion 00x a single zero is inserted into the e bit when a crc-4 error event is detected in the receive path. (the e1 bit corresponds to s mfi and the e2 bit corresponds to smfii) 0 1 x the value in the si[1] bit is inserted into the e1 bit position. the value in the si[0] bit is inserted into the e2 bit posi tion. 1 x 0 the value in the si[1] bit is inserted into the e1 bit position. the value in the si[0] bit is inserted into the e2 bit posi tion. 1 x 1 the e bit positions are unchanged.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 73 march 22, 2004 3.20.1.2.1 interrupt summary in e1 mode, the interrupt is summarized in table 49. when there are conditions meeting the interrupt sources, the corre- sponding interrupt indication bit will be set. when the interrupt indication bit is ?1?, if enabled by the corresponding interrupt enable bit, an inter- rupt will be reported by the int pin. table 49: interrupt summary in e1 mode interrupt sources interrupt indi cation bit interrupt enable bit at the first bit of each fas. fasi fase at the first bit of each basic frame. bfi bfe at the first bit of each crc multi-frame. mfi mfe at the first bit of each crc sub multi-frame. smfi smfe at the first bit of each signaling multi-frame. sigmfi sigmfe
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 74 march 22, 2004 table 50: related bit / register in chapter 3.20.1.2 bit register e1 address (hex) fdis e1 mode 062, 162, 262, 362 gencrc crcm sigen sidis febedis xdis fas1inv error insertion 06f, 16f, 26f, 36f fasallinv nfasinv crcpinv caspinv crcinv si[1] fgen international bit 063, 163, 263, 363 si[0] remais fgen maintenance 0 06b, 16b, 26b, 36b autoyellow g706rai mfais ts16los ts16ais sax[1:4] (?x? is from 4 to 8) sa4 code-word ~ sa8 code-word 065 ~ 069, 165 ~ 169, 265 ~ 269, 365 ~ 369 saxen (?x? is from 4 to 8) fgen sa control 064, 164, 264, 364 oocmfv frmr status 04f, 14f, 24f, 34f x[0:2] fgen extra 06a, 16a, 26a, 36a fasi fgen interrupt indication 06e, 16e, 26e, 36e bfi mfi smfi sigmfi fase fgen interrupt control 06d, 16d, 26d, 36d bfe mfe smfe sigmfe
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 75 march 22, 2004 3.20.2 hdlc transmitter the hdlc transmitter inserts the data into the selected position to form hdlc or ss7 packet data stream. 3.20.2.1 hdlc channe l configuration in t1/j1 mode esf & t1 dm formats, three hdlc transmitters (#1, #2 & #3) per link are provided for hdlc insertion to the data stream to be transmitted. in t1/j1 mode sf & slc-96 formats, two hdlc transmitters (#2 & #3) per link are provided for hdlc insertion. in e1 mode, three hdlc transmitters (#1, #2 & #3) per link are provided for hdlc insertion. except in t1/j1 mode esf & t1 dm formats, the hdlc channel of hdlc transmitter #1 is fixed in the dl bit (in esf format) and d bit in ch24 (in t1 dm format) respectively (refer to table 13 & table 14), the other hdlc channel is configured as the follows: 1. set the even bit and/or the odd bit to select the even and/or odd frames; 2. set the ts[4:0] bits to define the channel/timeslot of the assigned frame; 3. set the biten[7:0] bits to select the bits of the assigned channel/ timeslot. then all the functions of the hdlc transmitter will be enabled only if the corresponding tdlen bit is set to ?1?. 3.20.2.2 two hdlc modes two modes are selected by the thdlcm bit in the hdlc transmit- ter. the two modes are: hdlc m ode (per q.921) and ss7 (per q.703). 3.20.2.2.1 hdlc mode a fifo buffer is used to store the hdlc data written in the dat[7:0] bits. the fifo depth is 128 byte s. when it is full, it will be indi- cated by the ful bit. when it is empty, it will be indicated by the emp bit. if an entire hdlc packet is stored in the fifo indicated by the eom bit, or if the data in the fifo exceeds the upper threshold set by the hl[1:0] bits, the data in the fifo will be transmitted. the opening flag (?01111110?) will be pr epended before the data automatically. the transmission will not stop until t he entire hdlc data are transmitted. then the 2-byte fcs and the closing flag (?0 1111110?) will be added to the end of the hdlc data automatically. during the hdlc data trans- mission, a zero is stuffed automatically into the serial output data if there are five consecutive ?one?s ahead. the abort sequence (?0 1111111?) will be inserted to the hdlc packet anytime when the abort bit is set. or when the fifo is empty and the transmitted last byte is not the end of the current hdlc packet, the abort sequence will be transmitted automatically. if the tdlen bit is enabled and ther e is no hdlc packet in the fifo to be transmitted, the 7e (h ex) flag will always be transmitted. 3.20.2.2.2 ss7 mode a fifo buffer is used to store the ss7 data written in the dat[7:0] bits. the fifo depth is 128 bytes. when it is full, it will be indicated by the ful bit. when it is empty, it will be indicated by the emp bit. if an entire ss7 packet is stored in the fifo indicated by the eom bit, or if the data in the fifo exceeds the upper threshold set by the hl[1:0] bits, the data in the fifo will be transmitted. the opening flag (?01111110?) will be pr epended before the data automatically. the trans- mission will not stop until the entire ss7 data are transmitted. then the 2-byte fcs and the closing flag (?0 1111110?) will be added to the end of the ss7 data automatically. during t he ss7 data transmission, a zero is stuffed automatically into the serial output data if there are five consecu- tive ?one?s ahead. the abort sequence (?0 1111111?) will be inserted to the ss7 packet anytime when the abort bit is set. or when the fifo is empty and the last transmitted byte is not the end of the current ss7 packet, the abort sequence will be transmitted automatically. when the fifo is empty, if less than 16 bytes are written into the fifo and the xrep bit is set to ?1?, t hese bytes in the fifo will be trans- mitted repeatedly with the opening flag, fcs and closing flag, until the xrep bit is disabled and the current packet transmission is finished. however, during the cyclic transmissi on period, the data written into the fifo will not be transmitted. if the autofisu bit is set and there is no data in the fifo to be transmitted, the 7e (hex) flags will be transmitted n times (the ?n? is determined by the fl[1:0] bits), then the fisu packet will be transmitted (refer to figure 14) with the bsn and fsn the same as the last transmit- ted packet. if the tdlen bit is enabled and there is no ss7 packet in the fifo to be transmitted, the 7e (hex ) flag will always be transmitted. table 51: related bit / register in chapter 3.20.2.1 bit register address (hex) even thdlc1 assignment (e1 only) / thdlc2 assign- ment / thdlc3 assignment 085, 185, 285, 385(e1 only) / 086, 186, 286, 386 / 087, 187, 287, 387 odd ts[4:0] biten[7:0] thdlc1 bit select (e1 only) / thdlc2 bit select / thdlc3 bit select 088, 188, 288, 388 (e1 only) / 089, 189, 289, 389 / 08a, 18a, 28a, 38a tdlen3 thdlc enable control 084, 184, 284, 384 tdlen2 tdlen1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 76 march 22, 2004 3.20.2.3 interrupt summary in both of the two hdlc modes, when the data in the fifo is below the lower threshold set by the ll[1:0] bits, it will be indicated by the rdy bit. when there is a transition (from ?0? to ?1?) on the rdy bit, the rdyi bit will be set. in this case, if enabled by the rdye bit, an interrupt will be reported by the int pin. in both of the two hdlc modes, when the fifo is empty and the last transmitted byte is not the end of the current hdlc/ss7 packet, the udruni bit will be set. in this ca se, if enabled by the udrune bit, an interrupt will be reported by the int pin. 3.20.2.4 reset the hdlc transmitter will be reset when there is a transition from ?0? to ?1? on the trst bit. the reset will clear the fifo. table 52: related bit / register in chapter 3.20.2.2 ~ chapter 3.20.2.4 bit register address (hex) thdlcm thdlc1 control / thdlc2 control / thdlc3 control 0a7, 1a7, 2a7, 3a7 / 0a8, 1a8, 2a8, 3a8 / 0a9, 1a9, 2a9, 3a9 eom abort xrep autofisu trst dat[7:0] thdlc1 data / thdlc2 data / t hdlc3 data 0ad, 1ad, 2ad, 3ad / 0ae, 1ae, 2ae, 3ae / 0af, 1af, 2af, 3af ful tfifo1 status / tfifo2 status / tfifo3 status 0b0, 1b0, 2b0, 3b0 / 0b1, 1b1, 2b1, 3b1 / 0b2, 1b2, 2b2, 3b2 emp rdy tdlen3 thdlc enable control 084, 184, 284, 384 tdlen2 tdlen1 hl[1:0] tfifo1 threshold / tfifo2 threshold / tfifo3 threshold 0aa, 1aa, 2aa, 3aa / 0ab, 1ab, 2ab, 3ab / 0ac, 1ac, 2ac, 3ac fl[1:0] ll[1:0] rdyi thdlc1 interrupt indication / thdlc2 interrupt indication / thdlc3 interrupt indication 0b6, 1b6, 2b6, 3b6 / 0b7, 1b7, 2b7, 3b7 / 0b8, 1b8, 2b8, 3b8 udruni rdye thdlc1 interrupt control / thdl c2 interrupt control / thdlc3 interrupt control 0b3, 1b3, 2b3, 3b3 / 0b4, 1b4, 2b4, 3b4 / 0b5, 1b5, 2b5, 3b5 udrune
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 77 march 22, 2004 3.20.3 automatic performance report message (t1/ j1 only) the automatic performance report message (aprm) can only be transmitted in the esf format in t1/j1 mode. five kinds of events are counted every second in the aprm: 1. the bipolar violation (bpv) error / hdb3 code violation (cv) error event detected in the b8zs/hdl3/ami decoder; 2. the crc-6 error event detec ted in the frame processor; 3. the frame alignment bit error event detected in the frame pro- cessor; 4. the severely frame alignment bit error event detected in the frame processor; 5. the buffer slip event occurred in the elastic store buffer. enabled by the autoprm bit, the automatic performance report message is generated every one sec ond and transmitted on the dl bit positions. the aprm format is illustrated in table 53. the aprm is transmitted bit by bit from bit 1 to bit 8 and from octet no. 1 to octet no. 14. in the above table, the value in the c/r bit posi- tion, the r bit position, the u1 bit position, the u2 bit position and the lb bit position are determined by the crbit bit, the rbit bit, the u1bit bit, the u2bit bit and the lbbit bit in the aprm control register respec- tively. the nm and ni bit position is a module 4 counter. the remaining bits in octet no.5 to octet no. 12 interpret the event numbers counted by the aprm. the details are listed in table 54. their default value are ?0?s. table 53: aprm message format octet no. bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 1 flag (?01111110?) 2 sapi (?001110c/r0?) 3 tei (?00000001?) 4 control (?00000011?) 5 g3 lv g4 u1 u2 g5 sl g6 6 fe se lb g1 r g2 nm ni 7 g3 lv g4 u1 u2 g5 sl g6 8 fe se lb g1 r g2 nm ni 9 g3 lv g4 u1 u2 g5 sl g6 10 fe se lb g1 r g2 nm ni 11 g3 lv g4 u1 u2 g5 sl g6 12 fe se lb g1 r g2 nm ni 13 fcs 14 table 54: aprm interpretation a logic 1 in the following bit position interpretation g1 crc-6 error event = 1 g2 1 < crc-6 error event 5 g3 5 < crc-6 error event 10 g4 10 < crc-6 error event 100 g5 100 < crc-6 error event 319 g6 crc-6 error event > 320 se severely frame alignment bit error event 1 fe frame alignment bit error event 1 lv bipolar violation (bpv) error / hdb3 code violation (cv) error event 1 sl buffer slip event 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 78 march 22, 2004 3.20.4 bit-oriented message transmitter (t1/j1 only) the bit oriented message (bom) can only be transmitted in the esf format in t1/j1 mode. the bom pattern is ?111111110 xxxxxx0? which occupies the dl of the f-bit in the esf format. the six ?x?s represent the code that is pro- grammed in the xboc[5:0] bits. t he bom is transmitted only if the xboc[5:0] bits are not all ?one?s. 3.20.5 inband loopback code generator (t1/j1 only) the inband loopback code generator can only transmit inband loopback code in a framed or unframed t1/j1 data stream. the length and the content of the inband loopback code are pro- grammed in the cl[1:0] bits and the ibc[7:0] bits respectively. the code can only be transmitted when the ib cden bit is enabled. in framed mode, which is configured by the ib cdunfm bit, the bits in all 24 chan- nels are overwritten with the i nband loopback code and the f-bit is not changed. in unframed mode, which is configured by the ibcdunfm bit, all the bits in 24 channels and the f- bit are overwritten with the inband loopback code. 3.20.6 all ?zero?s & all ?one?s after all the above processes, all ?o ne?s or all ?zero?s will overwrite all the data stream if the tais bit and the txdis bit are set. the all zeros transmission takes a higher priority. 3.20.7 change of frame alignment any transition (from ?0? to ?1? or fr om ?1? to ?0?) on the cofaen bit will lead to one-bit deletion or one-bit repetition in the data stream to be transmitted, that is, to change the fr ame alignment position. the one-bit deletion or repetition occurs randomly. table 55: related bit / register in chapter 3.20.3 bit register t1/j1 address (hex) autoprm aprm control 07f, 17f, 27f, 37f crbit rbit u1bit u2bit lbbit table 56: related bit / register in chapter 3.20.4 & chapter 3.20.5 bit register t1/j1 address (hex) xboc[5:0] xboc code 080, 180, 280, 380 ibc[7:0] xibc code 075, 175, 275, 375 cl[1:0] xibc control 074, 174, 274, 374 ibcden ibcdunfm
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 79 march 22, 2004 3.21 transmit buffer transmit buffer can be used in t he circumstances that backplane timing is different from the line side timing in transmit slave mode. the function of timing option is al so integrated in this block. the source of the transmit clock can be selected in the recovered clock from the line side, the processed clock from the backplane or the master clock generated by the clock generator. in transmit master mode, the trans mit buffer is bypassed automat- ically. the source of the transmi t clock can be selected between the recovered clock from the line si de and the master clock generated by the internal clock generator (1.544 mhz in t1/j1 mode or 2.048 mhz in e1 mode). the selection is made by the xts bit. in transmit clock slave t1/j1 m ode e1 rate, for the backplane tim- ing is 2.048 mhz from backplane and the line timing is 1.544 mhz from the internal clock generator, the trans mit buffer is selected automati- cally to absorb high frequency mappi ng jitter due to the e1 to t1/j1 mapping scheme. in this case, 1.544 mhz must be locked to 2.048 mhz by pll of the internal clock generator. the xts bit in the transmit tim- ing option register does not take effect. in other transmit clock slave modes, whether the transmit buffer is bypassed and the source of the tr ansmit clock selection are selected by the xts bit. when the xts bit is set to ?1?, line side timing is from internal clock generator, but backplane timing is from backplane, so the transmit buffer is selected to acco mmodate the different clocks. if these two clocks are not locked, an internal slip will occur in the transmit buffer. the source of the transmit cl ock is from the master clock gener- ated by the internal clock generator (1.544 mhz in t1/j1 mode or 2.048 mhz in e1 mode). when the xts bit is set to ?0?, the line side timing is also from the backplane timing, so t he transmit buffer is bypassed. the source of the transmit clock is from the processed clock from the back- plane. in transmit multiplexed mode, whether the transmit buffer is bypassed and the source of the transmit clock selection are the same as that described in other tr ansmit clock slave modes. in most applications of transmit clock slave mode, the xts bit can be set to ?0? to bypass the transmit buffer (the transmit buffer is selected automatically in t1/j1 mode e1 rate). 3.22 encoder 3.22.1 line code rule 3.22.1.1 t1/j1 mode in t1/j1 mode, the b8zs line code rule or the ami line code rule can be selected by the t_md bit. 3.22.1.2 e1 mode in e1 mode, the hdb3 line code rule or the ami line code rule can be selected by the t_md bit. 3.22.2 bpv error insertion for test purpose, a bpv error can be inserted to the data stream to be transmitted by a transition from ?0? to ?1? on the bpv_ins bit. 3.22.3 all ?one?s insertion when the los is detected in the receive path, all ?one?s will be inserted automatically to the data stream to be transmitted by setting the atao bit. table 57: related bit / register in chapter 3.20.6, chapter 3.20.7 & chapter 3.21 bit register address (hex) tais fgen maintenance 1 06c, 16c, 26c, 36c txdis cofaen xts transmit timing option 070, 170, 270, 370 table 58: related bit / register in chapter 3.22 bit register address (hex) t_md transmit configuration 0 022, 122, 222, 322 bpv_ins maintenance function control 2 031, 131, 231, 331 atao maintenance function control 1 02c, 12c, 22c, 32c
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 80 march 22, 2004 3.23 transmit jitter attenuator the transmit jitter attenuator of each link can be chosen to be used or not. this selection is made by the tja_e bit. the jitter attenuator consists of a fifo and a dpll, as shown in figure 5. the fifo is used as a pool to buffer the jittered input data, then the data is clocked out of the fifo by a de-jittered clock. the depth of the fifo can be 32 bits, 64 bits or 128 bits, as selected by the tja_dp[1:0] bits. accordingly, the constant delay produced by the jitter attenuator is 16 bits, 32 bits or 64 bits. the 128-bi t fifo is used when large jitter tol- erance is expected, and the 32-bit fifo is used in delay sensitive appli- cations. the dpll is used to generate a de-jittered clock to clock out the data stored in the fifo. the dpll can only attenuate the incoming jitter whose frequency is above corner fr equency (cf). the jitter which fre- quency is lower than the cf passes through the dpll without any atten- uation. in t1/j1 applications, the cf of the dpll can be 5 hz or 1.26 hz, as selected by the tja_bw bit. in e1 applications, the cf of the dpll can be 6.77 hz or 0.87 hz, as selected by the tja_bw bit. the lower the cf is, the longer time is needed to achieve synchronization. if the incoming data moves faster than the outgoing data, the fifo will overflow. if the incoming data moves slower than the outgoing data, the fifo will underflow. the overflow or underflow is captured by the tja_is bit. when the tja_is bit is ?1?, an interrupt will be reported on the int pin if enabled by the tja_ie bit. to avoid overflowing or underflowi ng, the ja-limit function can be enabled by setting the tja_limt bit. when the ja-limit function is enabled, the speed of the outgoing data will be adjusted automatically if the fifo is close to its full or em ptiness. the criteria of speed adjust- ment start are listed in table 6. t hough the la-limit function can reduce the possibility of fifo overflow and underflow, the quality of jitter attenu- ation is deteriorated. selected by the tjitt_test bit, t he real time interval between the read and write pointer of the fifo or the peak-peak interval between the read and write pointer of the fifo can be indicated in the tjitt[6:0] bits. when the tjitt_test bit is ?0 ?, the current interval between the read and write pointer of the fifo will be written into the tjitt[6:0] bits. when the tjitt_test bit is ?1?, t he current interval is compared with the old one in the tjitt[6:0] bits and the larger one will be indicated by the tjitt[6:0] bits. the performance of receive jitter attenuator meets the itut i.431, g.703, g.736 - 739, g.823, g.824, etsi 300011, etsi tbr 12/ 13, at&t tr62411, tr43802, tr-t sy 009, tr-tsy 253, tr-try 499 standards. refer to chapter 7.10 jitte r tolerance and chapter 7.10 jit- ter tolerance for details. table 59: related bit / register in chapter 3.23 bit register address (hex) tja_e transmit jitter attenuation configuration 021, 121, 221, 321 tja_dp[1:0] tja_bw tja_limt tjitt_test tja_is interrupt status 1 03b, 13b, 23b, 33b tja_ie interrupt enable control 1 034, 134, 234, 334 tjitt[6:0] transmit jitter measure value indication 038, 138, 238, 338
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 81 march 22, 2004 3.24 waveform shaper / line build out according to the various cables, configured by the puls[3:0] bits, three ways of manipulating the wave form shaper can be selected before the data is transmitted: 1. preset waveform template; 2. line build out (lbo ) filter (t1 only); 3. user-programmable arbitrary waveform. 3.24.1 preset waveform template the preset waveform template is provided for short haul applica- tions. 3.24.1.1 t1/j1 mode in t1/j1 applications, the waveform template is shown in figure 31, which meets t1.102 and g.703, and it is measured in the far end as shown in figure 32. figure 31. dsx-1 waveform template figure 32. t1/j1 pulse template measurement circuit in t1 applications, to meet the template, five preset waveform tem- plates are provided corresponding to five grades of cable length. the selection is made by the puls[3:0 ] bits. in j1 applications, the puls[3:0] bits should be set to ?0010? . the details are listed in table 60. 3.24.1.2 e1 mode in e1 applications, the waveform template is shown in figure 33, which meets g.703, and it is measured on the near line side as shown in figure 34. figure 33. e1 waveform template figure 34. e1 pulse temp late measurement circuit -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2 0 250 500 750 1000 1250 time (ns) normalized amplitude IDT82P2284 ttipn tringn cable r load v out note: r load = 100 ? + 5% table 60: puls[3:0] setting in t1/j1 mode cable configuration puls[3:0] t1 - 0 ~ 133 ft 0 0 1 0 t1 - 133 ~ 266 ft 0 0 1 1 t1 - 266 ~ 399 ft 0 1 0 0 t1 - 399 ~ 533 ft 0 1 0 1 t1 - 533 ~ 655 ft 0 1 1 0 j1 - 0 ~ 655 ft 0 0 1 0 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 normalized amplitude time in unit intervals IDT82P2284 v out r load ttipn tringn note: r load = 75 ? or 120 ? (+ 5%)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 82 march 22, 2004 to meet the template, two preset waveform templates are provided corresponding to two kinds of cabl e impedance. the selection is made by the puls[3:0] bits. in internal impedance matching mode, if the cable impedance is 75 ? , the puls[3:0] bits should be set to ?0000?; if the cable impedance is 120 ? , the puls[3:0] bits should be set to ?0001?. in external impedance matching mode, for both 75 ? and 120 ? cable impedance, the puls[3:0] bits should be set to ?0001?. 3.24.2 line build out (lbo) (t1 only) in long haul applications, the output on the ttipn/tringn pins should be attenuated before transmission to prevent the cross-talk in the far end. three lbos are used to implement the pulse attenuation. four grades of attenuation with each step of 7.5 db are specified in the fcc part 68 regulations. the attenuation grade is selected by the puls[3:0] bits. the details are listed in table 61. 3.24.3 user-programmable arbitrary waveform user-programmable arbitrary wave form can be used in both short haul applications and long haul applications if the puls[3:0] bits are set to ?11xx? in the corresponding link. this allows the transmitter perfor- mance to be tuned for a wide variety of line condition or special applica- tion. each pulse shape can extend up to 4 uis (unit interval) addressed by the ui[1:0] bits, and each ui is divided into 16 sub-phases addressed by the samp[3:0] bits. the pulse amplitude of each phase is repre- sented by a binary byte, within the r ange from +63 to -63, stored in the wdat[6:0] bits in signed magnitude form. the maximum number +63 (d) represents the positive maximum amplitude of the transmit pulse while the most negative number -63 (d) represents the maximum nega- tive amplitude of the transmit pulse. thus, up to 64 bytes are used. for each channel, a 64 bytes ram is available. there are twelve standard templates which are stored in a local rom. one of them can be selected as reference and made some changes to get the desired waveform. to do this, the first step is to choose a set of waveform value, which is the most similar to the desired pulse shape, from the following 12 tables (table 62 to table 73), and set the scal[5:0] bits to the corre- sponding standard value. table 62 to table 73 list the sample data and the standard scaling value of each of the 12 templates. modifying the corresponding samp le data can get the desired transmit pulse shape. by increasing or decreasing by ?1? from the stan- dard value in the scal[5:0] bits, the pulse amplitude can be scaled up or down at the percentage ratio agai nst the standard pulse amplitude if necessary. for different pulse shapes, the value of the scal[5:0] bits and the scaling percentage ratio are different. the values are listed in table 62 to table 73. do the followings step by step, the desired waveform can be pro- grammed based on the selected waveform template: 1. select the ui by the ui[1:0] bits; 2. specify the sample address in the selected ui by the samp[3:0] bits; 3. write sample data to the wdat[6:0] bits. it contains the data to be stored in the ram, addressed by the selected ui and the correspond- ing sample address; 4. set the rw bit to ?0? to write data to ram, or to ?1? to read data from ram; 5. set the done bit to implement the read or write operation; (repeat the above steps until all the sample data are written to or read from the internal ram). 6. write the scaling data to the scal[5:0] bits to scale the ampli- tude of the waveform based on the selected standard pulse amplitude. table 62 to table 73 give all the sample data based on preset pulse templates and lbos in details for refe rence. for preset pulse templates and lbos, scaling up/down against t he pulse amplitude is not sup- ported. 1. table 62 - transmit waveform value for e1 75 ? 2. table 63 - transmit waveform value for e1 120 ? 3. table 64 - transmit waveform value for t1 0~133 ft 4. table 65 - transmit waveform value for t1 133~266 ft 5. table 66 - transmit waveform value for t1 266~399 ft 6. table 67 - transmit waveform value for t1 399~533 ft 7. table 68 - transmit waveform value for t1 533~655 ft 8. table 69 - transmit waveform value for j1 0~655 ft 9. table 70 - transmit waveform value for ds1 0 db lbo 10. table 71 - transmit waveform value for ds1 -7.5 db lbo 11. table 72 - transmit waveform value for ds1 -15.0 db lbo 12. table 73 - transmit waveform value for ds1 -22.5 db lbo table 61: lbo puls[3:0] setting in t1 mode cable configuration puls[3:0] 0 db lbo 0 0 1 0 -7.5 db lbo 1 0 0 1 -15.0 db lbo 1 0 1 0 -22.5 db lbo 1 0 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 83 march 22, 2004 table 62: transmit waveform value for e1 75 ? ui 1 ui 2 ui 3 ui 4 sample 1 0000000 0000000 0000000 0000000 sample 2 0000000 0000000 0000000 0000000 sample 3 0000000 0000000 0000000 0000000 sample 4 0001100 0000000 0000000 0000000 sample 5 0110000 0000000 0000000 0000000 sample 6 0110000 0000000 0000000 0000000 sample 7 0110000 0000000 0000000 0000000 sample 8 0110000 0000000 0000000 0000000 sample 9 0110000 0000000 0000000 0000000 sample 10 0110000 0000000 0000000 0000000 sample 11 0110000 0000000 0000000 0000000 sample 12 0110000 0000000 0000000 0000000 sample 13 0000000 0000000 0000000 0000000 sample 14 0000000 0000000 0000000 0000000 sample 15 0000000 0000000 0000000 0000000 sample 16 0000000 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?100001?. one step change of this value results in 3% scaling up/down against the pulse amplitude. table 63: transmit waveform value for e1 120 ? ui 1ui 2ui 3ui 4 sample 1 0000000 0000000 0000000 0000000 sample 2 0000000 0000000 0000000 0000000 sample 3 0000000 0000000 0000000 0000000 sample 4 0001111 0000000 0000000 0000000 sample 5 0111100 0000000 0000000 0000000 sample 6 0111100 0000000 0000000 0000000 sample 7 0111100 0000000 0000000 0000000 sample 8 0111100 0000000 0000000 0000000 sample 9 0111100 0000000 0000000 0000000 sample 10 0111100 0000000 0000000 0000000 sample 11 0111100 0000000 0000000 0000000 sample 12 0111100 0000000 0000000 0000000 sample 13 0000000 0000000 0000000 0000000 sample 14 0000000 0000000 0000000 0000000 sample 15 0000000 0000000 0000000 0000000 sample 16 0000000 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?100001?. one step change of this value results in 3% scaling up/down against the pulse amplitude.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 84 march 22, 2004 table 64: transmit waveform value for t1 0~133 ft ui 1ui 2ui 3ui 4 sample 1 0010111 1000010 0000000 0000000 sample 2 0100111 1000001 0000000 0000000 sample 3 0100111 0000000 0000000 0000000 sample 4 0100110 0000000 0000000 0000000 sample 5 0100101 0000000 0000000 0000000 sample 6 0100101 0000000 0000000 0000000 sample 7 0100101 0000000 0000000 0000000 sample 8 0100100 0000000 0000000 0000000 sample 9 0100011 0000000 0000000 0000000 sample 10 1001010 0000000 0000000 0000000 sample 11 1001010 0000000 0000000 0000000 sample 12 1001001 0000000 0000000 0000000 sample 13 1000111 0000000 0000000 0000000 sample 14 1000101 0000000 0000000 0000000 sample 15 1000100 0000000 0000000 0000000 sample 16 1000011 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude. table 65: transmit waveform value for t1 133~266 ft ui 1 ui 2 ui 3 ui 4 sample 1 0011011 1000011 0000000 0000000 sample 2 0101100 1000010 0000000 0000000 sample 3 0101011 1000001 0000000 0000000 sample 4 0101010 0000000 0000000 0000000 sample 5 0101000 0000000 0000000 0000000 sample 6 0101000 0000000 0000000 0000000 sample 7 0100111 0000000 0000000 0000000 sample 8 0100110 0000000 0000000 0000000 sample 9 0100101 0000000 0000000 0000000 sample 10 1010000 0000000 0000000 0000000 sample 11 1001111 0000000 0000000 0000000 sample 12 1001101 0000000 0000000 0000000 sample 13 1001010 0000000 0000000 0000000 sample 14 1001000 0000000 0000000 0000000 sample 15 1000110 0000000 0000000 0000000 sample 16 1000100 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 85 march 22, 2004 table 66: transmit waveform value for t1 266~399 ft ui 1 ui 2 ui 3 ui 4 sample 1 0011111 1000011 0000000 0000000 sample 2 0110001 1000010 0000000 0000000 sample 3 0101111 1000001 0000000 0000000 sample 4 0101100 0000000 0000000 0000000 sample 5 0101011 0000000 0000000 0000000 sample 6 0101010 0000000 0000000 0000000 sample 7 0101001 0000000 0000000 0000000 sample 8 0101000 0000000 0000000 0000000 sample 9 0100101 0000000 0000000 0000000 sample 10 1010111 0000000 0000000 0000000 sample 11 1010011 0000000 0000000 0000000 sample 12 1010000 0000000 0000000 0000000 sample 13 1001011 0000000 0000000 0000000 sample 14 1001000 0000000 0000000 0000000 sample 15 1000110 0000000 0000000 0000000 sample 16 1000100 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude. table 67: transmit waveform value for t1 399~533 ft ui 1 ui 2 ui 3 ui 4 sample 1 0100000 1000011 0000000 0000000 sample 2 0111000 1000010 0000000 0000000 sample 3 0110011 1000001 0000000 0000000 sample 4 0101111 0000000 0000000 0000000 sample 5 0101110 0000000 0000000 0000000 sample 6 0101101 0000000 0000000 0000000 sample 7 0101100 0000000 0000000 0000000 sample 8 0101010 0000000 0000000 0000000 sample 9 0101000 0000000 0000000 0000000 sample 10 1011000 0000000 0000000 0000000 sample 11 1011000 0000000 0000000 0000000 sample 12 1010011 0000000 0000000 0000000 sample 13 1001100 0000000 0000000 0000000 sample 14 1001000 0000000 0000000 0000000 sample 15 1000110 0000000 0000000 0000000 sample 16 1000100 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 86 march 22, 2004 table 68: transmit waveform value for t1 533~655 ft ui 1 ui 2 ui 3 ui 4 sample 1 0100000 1000011 0000000 0000000 sample 2 0111111 1000010 0000000 0000000 sample 3 0111000 1000001 0000000 0000000 sample 4 0110011 0000000 0000000 0000000 sample 5 0101111 0000000 0000000 0000000 sample 6 0101110 0000000 0000000 0000000 sample 7 0101101 0000000 0000000 0000000 sample 8 0101100 0000000 0000000 0000000 sample 9 0101001 0000000 0000000 0000000 sample 10 1011111 0000000 0000000 0000000 sample 11 1011110 0000000 0000000 0000000 sample 12 1010111 0000000 0000000 0000000 sample 13 1001111 0000000 0000000 0000000 sample 14 1001001 0000000 0000000 0000000 sample 15 1000111 0000000 0000000 0000000 sample 16 1000100 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude. table 69: transmit waveform value for j1 0~655ft ui 1 ui 2 ui 3 ui 4 sample 1 0010111 1000010 0000000 0000000 sample 2 0100111 1000001 0000000 0000000 sample 3 0100111 0000000 0000000 0000000 sample 4 0100110 0000000 0000000 0000000 sample 5 0100101 0000000 0000000 0000000 sample 6 0100101 0000000 0000000 0000000 sample 7 0100101 0000000 0000000 0000000 sample 8 0100100 0000000 0000000 0000000 sample 9 0100011 0000000 0000000 0000000 sample 10 1001010 0000000 0000000 0000000 sample 11 1001010 0000000 0000000 0000000 sample 12 1001001 0000000 0000000 0000000 sample 13 1000111 0000000 0000000 0000000 sample 14 1000101 0000000 0000000 0000000 sample 15 1000100 0000000 0000000 0000000 sample 16 1000011 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 87 march 22, 2004 table 70: transmit waveform value for ds1 0 db lbo ui 1ui 2ui 3ui 4 sample 1 0010111 1000010 0000000 0000000 sample 2 0100111 1000001 0000000 0000000 sample 3 0100111 0000000 0000000 0000000 sample 4 0100110 0000000 0000000 0000000 sample 5 0100101 0000000 0000000 0000000 sample 6 0100101 0000000 0000000 0000000 sample 7 0100101 0000000 0000000 0000000 sample 8 0100100 0000000 0000000 0000000 sample 9 0100011 0000000 0000000 0000000 sample 10 1001010 0000000 0000000 0000000 sample 11 1001010 0000000 0000000 0000000 sample 12 1001001 0000000 0000000 0000000 sample 13 1000111 0000000 0000000 0000000 sample 14 1000101 0000000 0000000 0000000 sample 15 1000100 0000000 0000000 0000000 sample 16 1000011 0000000 0000000 0000000 the standard value of the scal[5:0] bits is ?110110?. one step change of this value results in 2% scaling up/dow n against the pulse amplitude. table 71: transmit waveform value for ds1 -7.5 db lbo ui 1 ui 2 ui 3 ui 4 sample 1 0000000 0010100 0000010 0000000 sample 2 0000010 0010010 0000010 0000000 sample 3 0001001 0010000 0000010 0000000 sample 4 0010011 0001110 0000010 0000000 sample 5 0011101 0001100 0000010 0000000 sample 6 0100101 0001011 0000001 0000000 sample 7 0101011 0001010 0000001 0000000 sample 8 0110001 0001001 0000001 0000000 sample 9 0110110 0001000 0000001 0000000 sample 10 0111010 0000111 0000001 0000000 sample 11 0111001 0000110 0000001 0000000 sample 12 0110000 0000101 0000001 0000000 sample 13 0101000 0000100 0000000 0000000 sample 14 0100000 0000100 0000000 0000000 sample 15 0011010 0000011 0000000 0000000 sample 16 0010111 0000011 0000000 0000000 the standard value of the scal[5:0] bits is ?010001?. one step change of this value results in 6.25% scaling up/d own against the pulse amplitude.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 88 march 22, 2004 when more than one ui are used to compose the pulse template and the pulse amplitude is not set pr operly, the overlap of two consecu- tive pulses will make the pulse am plitude overflow (exceed the maxi- mum limitation). this overflow is captured by the dac_is bit, and if enabled by the dac_ie bit, an interrupt will be reported by the int pin. table 72: transmit waveform value for ds1 -15.0 db lbo ui 1 ui 2 ui 3 ui 4 sample 1 0000000 0110101 0001111 0000011 sample 2 0000000 0110011 0001101 0000010 sample 3 0000000 0110000 0001100 0000010 sample 4 0000001 0101101 0001011 0000010 sample 5 0000100 0101010 0001010 0000010 sample 6 0001000 0100111 0001001 0000001 sample 7 0001110 0100100 0001000 0000001 sample 8 0010100 0100001 0000111 0000001 sample 9 0011011 0011110 0000110 0000001 sample 10 0100010 0011100 0000110 0000001 sample 11 0101010 0011010 0000101 0000001 sample 12 0110000 0010111 0000101 0000001 sample 13 0110101 0010101 0000100 0000001 sample 14 0110111 0010100 0000100 0000000 sample 15 0111000 0010010 0000011 0000000 sample 16 0110111 0010000 0000011 0000000 the standard value of the scal[5:0] bits is ?001000?. one step change of the value results in 12.5% scaling up/dow n against the pulse amplitude. table 73: transmit waveform value for ds1 -22.5 db lbo ui 1 ui 2 ui 3 ui 4 sample 1 0000000 0101100 0011110 0001000 sample 2 0000000 0101110 0011100 0000111 sample 3 0000000 0110000 0011010 0000110 sample 4 0000000 0110001 0011000 0000101 sample 5 0000001 0110010 0010111 0000101 sample 6 0000011 0110010 0010101 0000100 sample 7 0000111 0110010 0010100 0000100 sample 8 0001011 0110001 0010011 0000011 sample 9 0001111 0110000 0010001 0000011 sample 10 0010101 0101110 0010000 0000010 sample 11 0011001 0101100 0001111 0000010 sample 12 0011100 0101001 0001110 0000010 sample 13 0100000 0100111 0001101 0000001 sample 14 0100011 0100100 0001100 0000001 sample 15 0100111 0100010 0001010 0000001 sample 16 0101010 0100000 0001001 0000001 the standard value of the scal[5:0] bits is ?000100?. one step change of this value results in 25% scaling up/down against the pulse amplitude. table 74: related bit / register in chapter 3.24 bit register address (hex) puls[3:0] transmit configuration 1 023, 123, 223, 323 ui[1:0] transmit configuration 3 025, 125, 225, 325 samp[3:0] rw done wdat[6:0] transmit configuration 4 026, 126, 226, 326 scal[5:0] transmit configuration 2 024, 124, 224, 324 dac_is interrupt status 1 03b, 13b, 23b, 33b dac_ie interrupt enable control 1 034, 134, 234, 334
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 89 march 22, 2004 3.25 line driver the line driver can be set to high-z for redundant application. the following ways will set the drivers to high-z: 1. setting the thz pin to high will globally set all the line drivers to high-z; 2. when there is no clock input on the osci pin, all the line drivers will be high-z (no clock means this: t he input on the osci pin is in high/ low level, or the duty cycle is le ss than 30% or larger than 70%); 3. after software reset, hardware reset or power on, all the line drivers will be high-z; 4. setting the t_hz bit to ?1? wi ll set the corresponding line driver to high-z; 5. in transmit clock master mode, if the xts bit is ?1?, the source of the transmit clock is from the reco vered clock from the line side. when the recovered clock from the line side is lost, the line driver in the corre- sponding link will be high-z; 6. in transmit clock slave mode, if the xts bit is ?0?, the source of the transmit clock is from the bac kplane timing clock. when the back- plane timing clock is lost (i.e., no transition for more than 72 t1/e1/j1 cycles), the line driver in the co rresponding link will be high-z. how- ever, there is an exception in this case. that is, if the link is in remote loopback mode, the line driver will not be high-z. 7. when the transmit path is power down, the line driver in the cor- responding link will be high-z. by these ways, the ttipn and tringn pins will enter into high impedance state immediately. controlled by the dfm_on bit, the output driver short-circuit pro- tection can be enabled. the driver?s output current (peak to peak) is lim- ited to 110 ma typically. when the output current exceeds the limitation, the transmit driver failure will be captured by the df_s bit. selected by the df_ies bit, a transition from ?0? to ?1? on the df_s bit or any transi- tion from ?0? to ?1? or from ?1? to ?0? on the df_s bit will set the df_is bit. when the df_is bit is ?1?, an interrupt on the int pin will be reported if enabled by the df_ie bit.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 90 march 22, 2004 3.26 transmitter impedance matching in t1/j1 mode, the transmitte r impedance matching can be real- ized by using internal impedance matching circuit. 100 ? , 110 ? , 75 ? or 120 ? internal impedance matching ci rcuit can be selected by the t_term[1:0] bits. the external im pedance circuitry is not supported in t1/j1 mode. in e1 mode, the transmitter impedance matching can be realized by using internal impedance matchi ng circuit or external impedance matching circuit. when the t_term[2] bit is ?0?, the internal impedance matching circuit is enabled. 100 ? , 110 ? , 75 ? or 120 ? internal impedance matching circuit can be sele cted by the t_term[1:0] bits. when the t_term[2] bit is ?1?, t he internal impedance matching circuit is disabled, and different external resi stors should be used to realize dif- ferent impedance matching. figure 2 shows the appropriate components to connect with the cable for one link. table 75 lists the recommended impedance matching values for the transmitter. table 75: impedance matching value for the transmitter cable configuration internal termination external termination t_term[2:0] r t t_term[2:0] r t 75 ? (e1) 0 0 0 0 ? 1 x x 9.4 ? 120 ? (e1) 0 0 1 100 ? (t1) 0 1 0 - - 110 ? (j1) 0 1 1 - - table 76: related bit / register in chapter 3.25 & chapter 3.26 bit register address (hex) t_hz transmit configuration 1 023, 123, 223, 323 dfm_on xts transmit timing option 070, 170, 270, 370 df_s line status register 0 036, 136, 236, 336 df_ies interrupt trigger edges select 035, 135, 235, 335 df_is interrupt status 0 03a, 13a, 23a, 33a df_ie interrupt enable control 0 033, 133, 233, 333 t_term[2:0] transmit and receive termina- tion configuration 032, 132, 232, 332
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 91 march 22, 2004 3.27 testing and diagnostic facilities 3.27.1 prbs generator / detector the prbs generator / detector generat es test pattern to either the transmit or receive direction, and detects the pattern in the opposite direction. the direction is deter mined by the prbsdir bit. the pattern can be generated or detected in unf ramed mode, in 8-bit-based mode or in 7-bit-based mode. this select ion is made by the prbsmode[1:0] bits. in unframed mode, all the data streams are extracted or replaced and the per-channel/per-ts configuration in the test bit is ignored. in 8-bit-based mode or in 7-bit-based mode, the extracted or replaced channel/timeslot is specif ied by the test bit. (in 7-bit-based mode, only the higher 7 bits of the selected channel/timeslot are used for prbs test). 3.27.1.1 pattern generator three patterns are generated: 2 11 -1 pattern per o.150, 2 15 -1 pat- tern per o.152 and 2 20 -1 pattern per o.150-4.5. they are selected by the pats[1:0] bits. the selected pattern is generated once there is a transition from ?0? to ?1? on the testen bit. a single bit error will be inserted to the generated pattern when the inv bit is set to ?1?. before the insertion, the generated pattern can be inverted when the tinv bit is set. 3.27.1.2 pattern detector when there is a transition from ?0? to ?1? on the testen bit, the pat- tern detector starts to extract the dat a. the extracted data is used to re- generate a desired pattern which is selected by the pats[1:0] bits. the extracted data is compared with the re-generated pattern. if the extracted data coincides with the pattern, the pattern is synchronized and it will be indicated by the syncv bit. in synchronization state, each mismatched bit will generat e a prgd bit error event. this event is cap- tured by the beri bit and is forwar ded to the performance monitor. an interrupt reported on the int pin will be enabled by the bere bit if the beri bit is ?1?. when there are more than 10-bit errors detected in the fixed 48-bit window, the extracted data is out of synchronization and it also will be indicated by the syncv bit. any transition (from ?1? to ?0? or from ?0? to ?1?) on the syncv bit will set the synci bit. an interrupt reported on the int pin will be enabled by the synce bit if the synci bit is ?1?. before the data extracted to the pattern detector, the data can be inverted by setting the rinv bit. table 77: related bit / register in chapter 3.27.1 bit register address (hex) prbsdir tplc / rplc / prgd test configuration 0c7, 1c7, 2c7, 3c7 prbsmode[1:0] testen test id * - signaling trunk conditioning code rplc & tplc id * - 41~58 (for t1/j1) / 41~4f & 51~5f (for e1) pats[1:0] prgd control 071, 171, 271, 371 tinv rinv inv prgd status/error control 072, 172, 272, 372 syncv bere synce beri prgd interrupt indication 073, 173, 273, 373 synci note: * id means indirect register in the receiv e & transmit payload control function blocks.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 92 march 22, 2004 3.27.2 loopback system loopback, payload loopback, local digital loopback 1 & 2, remote loopback and analog loopback are all supported in the IDT82P2284. their routes are shown in the functional block diagram. 3.27.2.1 system loopback the system loopback can only be implemented when the receive system interface and the transmit system interface are in different non-multiplexed operating modes (one in clock master mode and the other in clock slave mode). however, in t1/j1 mode, when either the receive path or the transmit path is in t1/j1 mode e1 rate, the system loopback is not supported. distinguished by the loopback direction, the system loopback can be divided into system remote loopback and system local loopback. when the data and signaling bits fr om the transmit path are looped to the receive path, it is system remote loopback. when the data and sig- naling bits from the receive path ar e looped to the transmit path, it is system local loopback. 3.27.2.1.1 system remote loopback enabled by the srlp bit, the system remote loopback is imple- mented. the data and signaling bits to be transmitted on the tsdn and tsign pins are internally looped to the rsdn and rsign pins. when the receive path is in receive cl ock master mode and the transmit path is in transmit clock slave mode, t he clock signal and the framing pulse from the system side on the tsckn and tsfsn pins are looped to the rsckn and rsfsn pins respectively. when the transmit path is in transmit clock master mode and the receive path is in receive clock slave mode, the clock signal and the fr aming pulse from the system side on the rsckn and rsfsn pins are looped to the tsckn and tsfsn pins respectively. in system remote loopback mode, the data stream to be transmit- ted is still output to the line side, while the data stream received from the line side is replaced by the system remote loopback data. 3.27.2.1.2 system local loopback enabled by the sllp bit, the system local loopback is imple- mented. the received data and signaling bits to be output on the rsdn and rsign pins are internally looped to the tsdn and tsign pins. when the receive path is in receive clock master mode and the trans- mit path is in transmit clock slave mode, the recovered clock signal and framing pulse on the rsckn and rsfsn pins are looped to the tsckn and tsfsn pins respectively. when the transmit path is in transmit clock master mode and the receive path is in receive clock slave mode, the tsckn and tsfsn pins are looped to the rsckn and rsfsn pins respectively. in system local loopback mode, the data stream received from the line side is still output to t he system through the rsdn and rsign pins, while the data stream to be transmitted through the tsdn and tsign pins are replaced by the system local loopback data. 3.27.2.2 payload loopback by programming the gsubst[2:0] bi ts or the subst[2:0] bits, the payload loopback can be implemented. the received data output from the elastic store buffer is internal ly looped to the transmit payload con- trol. in payload loopback mode, the received data is still output to the system side, while the data to be transmitted from the system side is replaced by the payload loopback data. 3.27.2.3 local digital loopback 1 enabled by the dllp bit, the loc al digital loopback 1 is imple- mented. the data stream output from the transmit buffer is internally looped to the frame processor. in local digital loopback 1 mode, the data stream to be transmit- ted is still output to the line side, while the data stream received from the line side is replaced by the local digital loopback 1 data. 3.27.2.4 remote loopback enabled by the rlp bit, the remote loopback is implemented. the data stream output from the optional receive jitter attenuator is inter- nally looped to the optional transmit jitter attenuator. in remote loopback mode, the data stream received from the line side is still output to the system, wh ile the data stream to be transmitted is replaced by the remote loopback data. 3.27.2.5 local digital loopback 2 enabled by the dlp bit, the local digital loopback 2 is imple- mented. the data stream output from the optional transmit jitter attenu- ator is internally looped to the optional receive jitter attenuator. in local digital loopback 2 mode, the data stream to be transmit- ted is still output to the line side, while the data stream received from the line side is replaced by the local digital loopback 2 data. 3.27.2.6 analog loopback enabled by the alp bit, the analog loopback is implemented. the data stream to be transmitted on the ttipn/tringn pins is internally looped to the rtipn/rringn pins. in analog loopback mode, the data stream to be transmitted is still output to the line side, while the data stream received from the line side is replaced by the analog loopback data. 3.27.3 g.772 non-intrusive monitoring when the g.772 non-intrusive m onitoring is implemented, only three links are in normal operation and the link 1 is configured to moni- tor the receive path or transmit path of any of the remaining links. whether the g.772 non-intrusiv e monitoring is implemented and which direction (receive/transmit) and link is monitored are both deter- mined by the mon[3:0] bits. the g.772 non-intrusive monitori ng meets the itu-t g.772. it is shown in figure 35. the data stream of link 1 is received from the selected path of any of the remaining links, then processed as normal. the operation of the monitored link is not effected.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 93 march 22, 2004 figure 35. g.772 non-intrusive monitor transmit system interface transmit internal termination tsck1 / mtsck tsfs1 / mtsfs tsig1 / mtsiga1 tsd1 / mtsda1 receive system interface receive internal termination rsd1 / mrsda1 rsig1 / mrsiga1 rsck1 / mrsck rsfs1 / mrsfs transmit system interface transmit internal termination tsckn tsfsn tsign / mtsigb1 tsdn / mtsdb1 receive system interface receive internal termination rsdn / mrsdb1 rsign / mrsigb1 rsckn rsfsn link 1 any of the remaining links (4 > n > 2) g.772 non- intrusive monitor rring1 rtip1 ttip1 tring1 ttipn tringn rtipn rringn
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 94 march 22, 2004 table 78: related bit / register in chapter 3.27.2 & chapter 3.27.3 bit register address (hex) srlp maintenance function control 0 02b, 12b, 22b, 32b sllp dllp rlp dlp alp gsubst[2:0] tplc configuration 0cb, 1cb, 2cb, 3cb subst[2:0] id * - channel control (for t1/j1) / timeslot contro l (for e1) tplc id * - 01~18 (for t1/j1) / 00~1f (for e1) mon[3:0] g.772 monitor control 005 note: * id means indirect register in the transmit payload control function block.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver 95 march 22, 2004 3.28 interrupt summary when the int pin is asserted low, it means at least one interrupt has occurred in the device. reading the timer interrupt indication regis- ter and interrupt requisition link id r egister will find whether the timer interrupt occurs or in which link the interrupt occurs. if the tmovi bit in the timer interrupt indication register is ?1? and the tmove bit in the timer interrupt control register is enabled, the one second timer of the device generates an interrupt. then the source is served after it is found. after reading the interrupt requisiti on link id register, the interrupt module indication registers of the in terrupting link are read. the interrupt module indication bits will be ?1? if there are interrupts in the correspond- ing function block. to find the event ual interrupt sources, the interrupt indication and status bits in the bloc k are polled if their interrupt enable bits are enabled. then the sources are served after they are found. table 79: related bit / register in chapter 3.28 bit register address (hex) tmovi timer interrupt indication 00b int[4:1] interrupt requisition link id 009 tmove timer interrupt control 00a liu interrupt module indication 2 03f, 13f, 23f, 33f ibcd (t1/j1 only) interrupt module indication 0 040, 140, 240, 340 rboc (t1/j1 only) alarm pmon prgd rcrb fgen frmr thdlc3 interrupt module indication 1 041, 141, 241, 341 thdlc2 thdlc1 rhdlc3 rhdlc2 rhdlc1 elst trsi/resi
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver operation 96 march 22, 2004 4operation 4.1 power-on sequence to power on the device, the following sequence should be followed: 1. apply ground; 2. apply 3.3 v; 3. apply 1.8 v. 4.2 reset when the device is powered-up, al l the registers contain random values. the hardware reset pin reset must be asserted low during the power-up and the low signal should last at least 10 ms to initialize the device. after the reset pin is asserted high, all the registers are in their default values and can be accessed after 2 ms (refer to figure 36). during normal operation, the devic e can be reset by hardware or software anytime. when it is hardware reset, the reset pin should be asserted low for at least 100 ns. then al l the registers are in their default values and can be accessed after 2 ms (refer to figure 37). when it is software reset, a write signal to the so ftware reset register will reset all the registers except the t1/j1 or e1 mode register to their default val- ues. then the registers are accessible after 2 ms. however, the t1/j1 or e1 mode register can not be reset by the software reset. it can only be reset by the hardware reset. it should be mentioned that when the setting in the t1/j1 or e1 mode register is changed, a software reset must be applied. figure 36. hardware reset when powered-up figure 37. hardware rese t in normal operation 4.3 receive / transmit path power down the receive path of any of the four links can be power down by set- ting the r_off bit. during the receive path power down, the output of the corresponding path is low. the transmit path of any of the f our links can be set to power down by the t_off bit. during the transmit path power down, the output of the corresponding path is high-z. vdd reset microprocessor interface 10ms 2ms access reset microprocessor interface 2ms access 100 ns
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver operation 97 march 22, 2004 4.4 microprocessor interface the microprocessor interface prov ides access to read and write the registers in the device. the interface consists of serial peripheral inter- face (spi) and parallel microprocessor interface. 4.4.1 spi mode pull the spien pin to high, and t he microprocessor interface will be set in spi mode. in this mode, only the cs , sclk, sdi and sdo pins are interfaced with the microprocessor. a falling transition on cs pin indicates the start of a read/write operation, and a risi ng transition indicates the end of the operation. after the cs pin is set to low, one instruction byte on the sdi pin is input to the device on the rising edge of the sclk pin. if the msb is ?1?, it is read operation. if the lsb is ?0?, it is write operation. following the instruction byte, one address byte is clocked in on the sdi pin to specify the register. if the device is in read operation, the data read from the specified register is output on the sdo pin on the falling edge of the sclk (refer to figure 38). if the dev ice is in write operation, the data written to the specified register is input on the sdi pin following the address byte (refer to figure 39). figure 38. read operation in spi mode figure 39. write operation in spi mode cs sclk sdi sdo 10 123456789 11121314151617181920212223 a0 a7 a6 a5 a4 a3 a2 a1 instruction register address high impedance d0 d7 d6 d5 d4 d3 d2 d1 don't care a9 x x x a11 a10 a8 0 cs sclk sdi sdo 10 0123456789 11121314151617181920212223 a0 a7 a6 a5 a4 a3 a2 a1 instruction data byte high impedance d0 d7 d6 d5 d4 d3 d2 d1 register address a8 x x x a11 a10 a9
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver operation 98 march 22, 2004 4.4.2 parallel microprocessor interface pull the spien pin to low, the microprocessor interface will be set in parallel mode. in this mode, the interf ace is compatible with the motorola and the intel microprocessor, which is selected by the mpm pin. the IDT82P2284 uses separate address bus and data bus. the mode selec- tion and the interfaced pin are tabularized in table 80. table 80: parallel microprocessor interface pin mpm microprocessor interface interfaced pin low motorola cs , ds , r w , a[ 9 :0], d[7:0] high intel cs , rd , wr , a[ 9 :0], d[7:0]
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver operation 99 march 22, 2004 4.5 indirect register access scheme in receive cas/rbs buffer, receive payload control and trans- mit payload control blocks, per-channel/p er-timeslot indirect register is accessed by using an indire ct register access scheme. 4.5.1 indirect register read access the indirect register read access is as follows: - read the busy bit in the access status register to confirm the bit is ?0?; - write the access control register to initiate the read operation and specify the indirect register address; - read the busy bit in the access status register again to confirm the bit is ?0?; - read the indirect register data from the access data register. an indirect register access request is completed within 4 s. 4.5.2 indirect register write access the indirect register wr ite access is as follows: - read the busy bit in the access st atus register to confirm the bit is ?0?; - write the access data register; - write the access control register to initiate the write operation and specify the indirect register address. an indirect register access request is completed within 4 s. table 81: related bit / register in chapter 4 bit register address (hex) - software reset 004 t1/j1 t1/j1 or e1 mode 020, 120, 220, 320 fm[1:0] temode r_off receive configuration 0 028, 128, 228, 328 t_off transmit configuration 0 022, 122, 222, 322 busy tplc access status / rplc access status / rcrb access status 0c 8, 1c8, 2c8, 3c8 / 0cd, 1cd, 2cd, 3cd / 0d3, 1d3, 2d3, 3d3 rwn tplc access control / rplc access control / rcrb access control 0c9, 1c9, 2c9, 3c9 / 0ce, 1ce, 2ce, 3ce / 0d4, 1d4, 2d4, 3d4 address[6:0] d[7:0] tplc access data / rplc access data / rcrb access data 0ca, 1ca, 2ca, 3ca / 0cf, 1cf, 2cf, 3cf / 0d5, 1d5, 2d5, 3d5
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 100 march 22, 2004 5 programming information 5.1 register map in the ?reg? column, the ?x? represents 0 ~ 3, corresponding to the four links. 5.1.1 t1/j1 mode 5.1.1.1 direct register t1/j1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page 001 id7 id6 id5 id4 id3 id2 id1 id0 chip id for quad transceiver p 114 002 ~ 003 - - - - - - - - reserved - 004 - - - - - - - - software reset p 114 005 - - - - mon3 mon2 mon1 mon0 g.772 monitor control p 115 006 - - - - level1 level0 dir1 dir0 gpio control p 116 007 - - - ro21 ro20 - ro11 ro10 reference clock output select p 117 008 - - - - - - - - reserved - 009 - - - - int4 int3 int2 int1 interrupt requisition link id p 118 00a - - - - - - - tmove timer interrupt control p 118 00b - - - - - - - tmovi timer interrupt indication p 118 00c ~ 00d - - - - - - - - reserved - 00e - linksel1 linksel0 - addr3 addr2 addr 1 addr0 pmon access port p 119 00f dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 pmon access data p 119 010 - - - rslvck rmux mtsda tslvck tmux backplane global configura- tion p 120 011 ~ 01f - - - - - - - - reserved - x20 - - - - t1/j1 fm1 fm0 temode t1/j1 or e1 mode p 113 x21 - - tjitt_tes t tja_limt tja_e tja_dp1 tja_dp0 tja_bw transmit jitter attenuation configuration p 121 x22 - - - t_off - - - t_md transmit configuration 0 p 122 x23 - - dfm_on t_hz puls3 puls2 puls1 puls0 transmit configuration 1 p 123 x24 - - scal5 scal4 scal3 scal2 scal1 scal0 transmit configuration 2 p 124 x25 done rw ui1 ui0 samp3 samp2 samp1 sam p0 transmit configuration 3 p 125 x26 - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 transmit configuration 4 p 126 x27 - - rjitt_tes t rja_limt rja_e rja_dp1 rja_dp0 rja_bw receive jitter attenuation con- figuration p 126 x28 - - - r_off - - - r_md receive configuration 0 p 127 x29 - eq_on - los4 los3 los2 los1 los0 receive configuration 1 p 128 x2a - - slice1 slice0 updw1 updw0 mg1 mg0 receive configuration 2 p 129 x2b - dllp sllp srlp - rlp alp dlp maintenance function control 0 p 130 x2c - - - - - lac raise atao maintenance function control 1 p 131 x2d ~ x30 - - - - - - - - reserved - x31 - bpv_ins - exz_def exz_err1 exz_err0 cnt_md c nt_trf maintenance function control 2 p 132 x32 - - t_term2 t_term1 t_term0 r_term2 r_term1 r_term0 transmit and receive termi- nation configuration p 133 x33 - - - - - df_ie - los_ie interrupt enable control 0 p 133
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 101 march 22, 2004 x34 - dac_ie tja_ie rja_ie - exz_ie cv_ie cnt_ie interrupt enable control 1 p 134 x35 - - - - - df_ies - los_ies interrupt trigger edges select p 135 x36 - - - - - df_s - los_s line status register 0 p 135 x37 - - - latt4 latt3 latt2 latt1 latt0 line status register 1 p 136 x38 - tjitt6 tjitt5 tjitt4 tjitt3 tjitt2 tjitt1 tjitt0 transmit jitter measure value indication p 137 x39 - rjitt6 rjitt5 rjitt4 rjitt3 rjitt2 rji tt1 rjitt0 receive jitter measure value indication p 137 x3a - - - - - df_is - los_is interrupt status 0 p 138 x3b - dac_is tja_is rja_is - exz_is cv_is cntov_is interrupt status 1 p 139 x3c cnth[7] cnth[6] cnth[5] cnth[4] cnth[3] cnth[2] cnth[1] cnth[0] exz error counter h-byte p 140 x3d cntl[7] cntl[6] cntl[5] cntl[4] cntl[3] cntl[2] cntl[1] cntl[0] exz error counter l-byte p 140 x3e - - - - - - - refh_los reference clock output con- trol * p 140 x3f - - - - - - - liu interrupt module indication 2 p 141 x40 ibcd rboc alarm pmon prgd rcrb fgen fr mr interrupt module indication 0 p 142 x41 thdlc3 thdlc2 thdlc1 rhdlc3 rhdlc2 rhdlc1 els t trsi/resi interrupt module indication 1 p 143 x42 - - fbitgap de fe cms fsinv fsty p tbif option register p 144 x43 - - - - - map1 map0 tmode tbif operating mode p 145 x44 - tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 tbif ts offset p 146 x45 - - - - edge boff2 boff1 boff0 tbif bit offset p 146 x46 - - - fbitgap de fe cms tri rbif option register p 147 x47 - - - - - map1 map0 rmode rbif mode p 148 x48 - - - fsinv - - cmfs altfis rbif frame pulse p 149 x49 - tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 rbif ts offset p 150 x4a - - - - edge boff2 boff1 boff0 rbif bit offset p 150 x4b - - - - - - rcofai tcofai rtsfs change indication p 151 x4c - - - - - - rcofae tcofae rtsfs interrupt control p 151 x4d - - - - unfm refcrce refen refr frmr mode 0 p 152 x4e - - - - ddsc mimicc m2o1 m2o0 frmr mode 1 p 153 x4f - - - - - - - oofv frmr status p 154 x50 - - - - - - - oofe frmr interrupt control 0 p 154 x51 - - - rmfbe sfee beee fere cofae f rmr interrupt control 1 p 155 x52 - - excrceri mimici - - - oofi frmr interrupt indication 0 p 156 x53 - - - rmfbi sfei beei feri cofai frm r interrupt indication 1 p 157 x54 ~ x55 - - - - - - - - reserved - x56c8c7c6c5c4c3c2c1rdl0 p158 x57 - - m3 m2 m1 c11 c10 c9 rdl1 p 158 x58 - - s4s3s2s1a2a1rdl2 p159 x59 ~ x5b - - - - - - - - reserved - x5c scdeb scae scse scme scce dlb interrupt control p 160 x5d - - - - scai scsi scmi scci dlb interrupt indication p 161 x5e ~ x61 - - - - - - - - reserved - x62 - - - - - fdlbyp crcbyp fdis t1/j1 mode p 162 x63 ~ x64 - - - - - - - - reserved - x65c8c7c6c5c4c3c2c1xdl0 p163 x66 - - m3 m2 m1 c11 c10 c9 xdl1 p 163 x67 - - s4s3s2s1a2a1xdl2 p164 t1/j1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 102 march 22, 2004 x68 ~ x6a - - - - - - - - reserved - x6b - - - - - - autoyel- low xyel fgen maintenance 0 p 164 x6c - - - - mimicen cofaen txdis tais fgen maintenance 1 p 165 x6d - - - - - - mfe bfe fgen interrupt control p 166 x6e - - - - - - mfi bfi fgen interrupt indication p 166 x6f - - - - ddsinv crcinv fsinv ftinv error insertion p 167 x70 - - - - - - - xts transmit timing option p 168 x71 - - - - rinv tinv pats1 pats0 prgd control p 168 x72 - - - - bere inv syncv synce prgd status/error control p 169 x73 - - - - beri - - synci prgd interrupt indication p 169 x74 - - - - ibcden ibcdunfm cl1 cl0 xibc control p 170 x75 ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 xibc code p 170 x76 - - - ibcdidle dsel1 dsel0 asel1 asel0 i bcd detector configuration p 171 x77 - - - - - - lba lbd ibcd detector status p 172 x78 act7 act6 act5 act4 act3 act2 act1 act0 ibcd activate code p 172 x79 dact7 dact6 dact5 dact4 dact3 dact2 dact1 dact0 ibcd deactivate code p 172 x7a - - - - - - lbae lbde ibcd interrupt control p 173 x7b - - - - - - lbai lbdi ibcd interrupt indication p 173 x7c - - - - - trken slipd slipe elst configuration p 174 x7d - - - - - - - slipi elst interrupt indication p 174 x7e trkcode 7 trkcode 6 trkcode 5 trkcode 4 trkcode 3 trkcode2 trkcode 1 trkcode 0 elst trunk code p 174 x7f - - lbbit u2bit u1bit rbit crbit autoprm aprm control p 175 x80 - - xboc5 xboc4 xboc3 xbo c2 xboc1 xboc0 xboc code p 176 x81 - - - - - - avc boce boc control p 176 x82 - - - - - - - boci boc interrupt indication p 177 x83 - - boc5boc4boc3boc2boc1boc0rboc code p177 x84 - - - - - tdlen3 tdlen2 tdlen1 thdlc enable control p 178 x85 - - - - - - - - reserved - x86 - even odd ts4 ts3 ts2 ts1 ts0 thdlc2 assignment p 179 x87 - even odd ts4 ts3 ts2 ts1 ts0 thdlc3 assignment p 179 x88 - - - - - - - - reserved - x89 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 thdlc2 bit select p 180 x8a biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 thdlc3 bit select p 180 x8b - - - - - rdlen3 rdlen2 rdlen1 rhdlc enable control p 181 x8c - - - - - - - - reserved - x8d - even odd ts4 ts3 ts2 ts1 ts0 rhdlc2 assignment p 182 x8e - even odd ts4 ts3 ts2 ts1 ts0 rhdlc3 assignment p 182 x8f - - - - - - - - reserved - x90 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 rhdlc2 bit select p 183 x91 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 rhdlc3 bit select p 183 x92 - - lssufil fisufil adrm 1 adrm0 rhdlcm rrst rhdlc1 control register p 184 x93 - - lssufil fisufil adrm 1 adrm0 rhdlcm rrst rhdlc2 control register p 184 x94 - - lssufil fisufil adrm 1 adrm0 rhdlcm rrst rhdlc3 control register p 184 x95 - - - - - - emp pack rhdlc1 rfifo access status p 185 x96 - - - - - - emp pack rhdlc2 rfifo access status p 185 x97 - - - - - - emp pack rhdlc3 rfifo access status p 185 t1/j1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 103 march 22, 2004 x98 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc1 data p 186 x99 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc2 data p 186 x9a dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc3 data p 186 x9b - - - - - - ovfle rmbee rhdlc1 interrupt control p 187 x9c - - - - - - ovfle rmbee rhdlc2 interrupt control p 187 x9d - - - - - - ovfle rmbee rhdlc3 interrupt control p 187 x9e - - - - - - ovfli rmbei rhdlc1 interrupt indication p 188 x9f - - - - - - ovfli rmbei rhdlc2 interrupt indication p 188 xa0 - - - - - - ovfli rmbei rhdlc3 interrupt indication p 188 xa1 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc1 high address p 189 xa2 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc2 high address p 189 xa3 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc3 high address p 189 xa4 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc1 low address p 190 xa5 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc2 low address p 190 xa6 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc3 low address p 190 xa7 - - autofisu eom xrep abort thdlcm trst thdlc1 control p 191 xa8 - - autofisu eom xrep abort thdlcm trst thdlc2 control p 191 xa9 - - autofisu eom xrep abort thdlcm trst thdlc3 control p 191 xaa - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo1 threshold p 193 xab - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo2 threshold p 193 xac - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo3 threshold p 193 xad dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc1 data p 194 xae dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc2 data p 194 xaf dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc3 data p 194 xb0 - - - - - ful emp rdy tfifo1 status p 195 xb1 - - - - - ful emp rdy tfifo2 status p 195 xb2 - - - - - ful emp rdy tfifo3 status p 195 xb3 - - - - - - udrune rdye thdlc1 interrupt control p 196 xb4 - - - - - - udrune rdye thdlc2 interrupt control p 196 xb5 - - - - - - udrune rdye thdlc3 interrupt control p 196 xb6 - - - - - - udruni rdyi thdlc1 interrupt indication p 197 xb7 - - - - - - udruni rdyi thdlc2 interrupt indication p 197 xb8 - - - - - - udruni rdyi thdlc3 interrupt indication p 197 xb9 - - - - - ais yel red alarm status p 198 xba - - - - - aise yele rede alarm control p 199 xbb - - - - - aisi yeli redi alarm indication p 199 xbc reddth7 reddth6 reddth5 reddth4 reddth3 reddth2 reddth1 reddth0 red declare threshold p 200 xbd redcth7 redcth6 redcth5 redcth4 redcth3 redcth2 redcth1 redcth0 red clear threshold p 200 xbe yeldth7 yeldth6 yeldth5 yeldth4 yeldth3 yeldth2 yeldth1 yeldth0 yellow declare threshold p 201 xbf yelcth7 yelcth6 yelcth5 yelcth4 yelcth3 yelcth2 yelcth1 yelcth0 yellow clear threshold p 201 xc0 aisdth7 aisdth6 aisdth5 aisdth4 aisdth3 aisd th2 aisdth1 aisdth0 ais declare threshold p 202 xc1 aiscth7 aiscth6 aiscth5 aiscth4 aiscth3 aisc th2 aiscth1 aiscth0 ais clear threshold p 202 xc2 - - - - - - updat autoupd pmon control p 203 xc3 prdgove - - ddsove cofaove oofove ferov e crcove pmon interrupt control 0 p 204 xc4 - - - - - - - lcvove pmon interrupt control 1 p 204 xc5 prdgovi - - ddsovi/ cofaovi oofovi ferovi crcovi pmon interrupt indication 0 p 205 xc6 - - - - - - - lcvovi pmon interrupt indication 1 p 205 t1/j1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 104 march 22, 2004 xc7 - - - - prbsmod e1 prbsmod e0 prbsdir testen tplc / rplc / prgd test configuration p 206 xc8 - - - - - - - busy tplc access status p 207 xc9 rwn address 6 address 5 address 4 address 3 address2 address 1 address 0 tplc access control p 207 xca d7 d6 d5 d4 d3 d2 d1 d0 tplc access data p 207 xcb sigsnap gstrken zcs2 zcs1 zcs0 gsubst 2 gsubst1 gsubst0 tplc configuration p 208 xcc - - - - abxx - - pcce tplc control enable p 209 xcd - - - - - - - busy rplc access status p 210 xce rwn address 6 address 5 address 4 address 3 address2 address 1 address 0 rplc access control p 210 xcf d7 d6 d5 d4 d3 d2 d1 d0 rplc access data p 210 xd0 sigsnap gstrken - - - gsubst2 gsubst1 gsubst0 rplc configuration p 211 xd1 - - - - abxx sigfix pol pcce rplc control enable p 212 xd2 - - - - freeze deb sige sigf rcrb configuration p 213 xd3 - - - - - - - busy rcrb access status p 214 xd4 rwn address 6 address 5 address 4 address 3 address2 address 1 address 0 rcrb access control p 214 xd5 d7 d6 d5 d4 d3 d2 d1 d0 rcrb access data p 214 xd6 cosi8 cosi7 cosi6 cosi5 cosi4 cosi3 cosi2 cosi1 rcrb state change indication 0 p 215 xd7 cosi16 cosi15 cosi14 cosi13 cosi12 cosi11 cosi10 cosi9 rcrb state change indication 1 p 215 xd8 cosi24 cosi23 cosi22 cosi21 cosi20 cosi19 cosi18 cosi17 rcrb state change indication 2 p 215 note: * the reference clock output control regist er (addressed x3e) is available in zb revision only, otherwise, it is reserved. t1/j1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 105 march 22, 2004 5.1.1.2 indirect register pmon rcrb rplc tplc address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 00 crce7 crce6 crce5 crce4 crce3 crce2 crce1 crce0 crce counter mapping 0 p 216 01 - - - - - - crce9 crce8 crce counter mapping 1 p 216 02 fer7 fer6 fer5 fer4 fer3 fer2 fer1 fer0 fer counter mapping 0 p 217 03 - - - - fer11 fer10 fer9 fer8 fer counter mapping 1 p 217 04 - - - - - cofa2 cofa1 cofa0 cofa counter mapping p 218 05 - - - oof4 oof3 oof2 oof1 oof0 oof counter mapping p 218 06 prgd7 prgd6 prgd5 prgd4 prgd3 prgd2 prgd1 prgd0 prgd counter mapping 0 p 219 07 prgd15 prgd14 prgd13 prgd12 prgd11 prgd10 prgd9 prgd8 prgd counter mapping 1 p 219 08 lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 lcv counter mapping 0 p 220 09 lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 lcv counter mapping 1 p 220 0a ddse7 ddse6 ddse5 ddse4 ddse3 ddse2 ddse1 ddse0 ddse counter mapping 0 p 221 0b - - - - - - ddse9 ddse8 ddse counter mapping 1 p 221 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 01 ~ 18 - - - extract a b c d extracted signaling data/extract enable register for ch1 ~ ch24 p222 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 01 ~ 18 subst2 subst1 subst0 sinv oinv einv g56 k gap channel control register for ch1 ~ ch24 p223 21 ~ 38 dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 data trunk conditioning code register for ch1 ~ ch24 p224 41 ~ 58 - test - strken a b c d signaling trunk conditioning code register for ch1 ~ ch24 p225 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 01 ~ 18 subst2 subst1 subst0 sinv oinv einv g56k gap channel control register for ch1 ~ ch24 p226 21 ~ 38 dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk 1 dtrk0 data trunk conditioning code register for ch1 ~ ch24 p227 41 ~ 58 - test sigins strken a b c d signaling trunk conditioning code register for ch1 ~ ch24 p228
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 106 march 22, 2004 5.1.2 e1 mode 5.1.2.1 direct register e1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page 001 id7 id6 id5 id4 id3 id2 id1 id0 chip id for quad transceiver p 229 002 ~ 003 - - - - - - - - reserved - 004 - - - - - - - - software reset p 229 005 - - - - mon3 mon2 mon1 mon0 g.772 monitor control p 230 006 - - - - level1 level0 dir1 dir0 gpio control p 231 007 - - - ro21 ro20 - ro11 ro10 reference clock output select p 232 008 - - - - - - - - reserved - 009 - - - - int4 int3 int2 int1 interrupt requisition link id p 233 00a - - - - - - - tmove timer interrupt control p 233 00b - - - - - - - tmovi timer interrupt indication p 233 00c ~ 00d - - - - - - - - reserved - 00e - linksel1 linksel0 - addr3 addr2 ad dr1 addr0 pmon access port p 234 00f dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 pmon access data p 234 010 - - - rslvck rmux mtsda tslvck tmux backplane global configuration p 235 011 ~ 01f - - - - - - - - reserved - x20 - - - - t1/j1 fm1 fm0 temode t1/j1 or e1 mode p 113 x21 - - tjitt_tes t tja_limt tja_e tja_dp1 tja_dp0 tja_bw transmit jitter attenuation con- figuration p 236 x22 - - - t_off - - - t_md transmit configuration 0 p 237 x23 - - dfm_on t_hz puls3 puls2 puls1 puls0 transmit configuration 1 p 238 x24 - - scal5 scal4 scal3 scal2 scal1 scal0 transmit configuration 2 p 239 x25 done rw ui1 ui0 samp3 samp2 samp1 sam p0 transmit configuration 3 p 240 x26 - wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 transmit configuration 4 p 241 x27 - - rjitt_tes t rja_limt rja_e rja_dp1 rja_dp0 rja_bw receive jitter attenuation con- figuration p 242 x28 - - - r_off - - - r_md receive configuration 0 p 243 x29 - eq_on - los4 los3 los2 los1 los0 receive configuration 1 p 244 x2a - - slice1 slice0 updw1 updw0 mg1 mg0 receive configuration 2 p 245 x2b - dllp sllp srlp - rlp alp dlp maintenance function control 0 p 246 x2c - - - - - lac raise atao maintenance function control 1 p 247 x2d ~ x30 - - - - - - - - reserved - x31 - bpv_ins - exz_def exz_err1 exz_err0 cnt_md cnt_trf maintenance function control 2 p 248 x32 - - t_term2 t_term1 t_term0 r_term2 r_term1 r_term0 transmit and receive termina- tion configuration p 249 x33 - - - - - df_ie - los_ie interrupt enable control 0 p 249 x34 - dac_ie tja_ie rja_ie - exz_ie cv_ie cnt _ie interrupt enable control 1 p 250 x35 - - - - - df_ies - los_ies interrupt trigger edges select p 251 x36 - - - - - df_s - los_s line status register 0 p 251 x37 - - - latt4 latt3 latt2 latt1 latt0 line status register 1 p 252
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 107 march 22, 2004 x38 - tjitt6 tjitt5 tjitt4 tjitt3 tjitt2 tji tt1 tjitt0 transmit jitter measure value indication p 253 x39 - rjitt6 rjitt5 rjitt4 rjitt3 rjitt2 rji tt1 rjitt0 receive jitter measure value indication p 253 x3a - - - - - df_is - los_is interrupt status 0 p 254 x3b - dac_is tja_is rja_is - exz_is cv_is cntov_is interrupt status 1 p 255 x3c cnth[7] cnth[6] cnth[5] cnth[4] cnth[3] cnth[2] cnth[1] cnth[0] exz error counter h-byte p 256 x3d cntl[7] cntl[6] cntl[5] cntl[4 ] cntl[3] cntl[2] cntl[1] cntl[0] exz error counter l-byte p 256 x3e - - - - - - - refh_los reference clock output control * p 256 x3f - - - - - - - liu interrupt module indication 2 p 257 x40 - - alarm pmon prgd rcrb fgen frmr interrupt module indication 0 p 257 x41 thdlc3 thdlc2 thdlc1 rhdlc3 rhdlc2 rhdlc1 elst tr si/resi interrupt module indication 1 p 258 x42 - - - de fe cms fsinv fstyp tbif option register p 259 x43 - - - - - - - tmode tbif operating mode p 260 x44 - tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 tbif ts offset p 261 x45 - - - - edge boff2 boff1 boff0 tbif bit offset p 261 x46 - - - - de fe cms tri rbif option register p 262 x47 - - - - - - - rmode rbif mode p 263 x48 - - - fsinv ohd smfs cmfs - rbif frame pulse p 263 x49 - tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 rbif ts offset p 264 x4a - - - - edge boff2 boff1 boff0 rbif bit offset p 264 x4b - - - - - - rcofai tcofai rtsfs change indication p 265 x4c - - - - - - rcofae tcofae rtsfs interrupt control p 265 x4d - - - - unfm refcrce refen refr frmr mode 0 p 266 x4e bit2c casen crcen cntnfas worderr ts 16c smfasc c2nciwck frmr mode 1 p 267 x4f - - - c2nciwv oosmfv oocmfv ooofv oofv frmr status p 268 x50 - - - c2nciwe oosmfe oocmfe ooofe oofe frmr interrupt control 0 p 269 x51 ismfpe icsmfpe smfere icmfpe cmfere crcee fere cofae frmr interrupt control 1 p 270 x52 - - excrceri c2nciwi oosmfi oocmfi ooofi oofi frmr interrupt indication 0 p 271 x53 ismfpi icsmfpi smferi icmfpi cmferi crcei fe ri cofai frmr interrupt indication 1 p 272 x54 si0 si1 a sa4 sa5 sa6 sa7 sa8 ts0 international / national p 273 x55 - - - - x0 y x1 x2 ts16 spare p 274 x56 - - - - sa41 sa42 sa43 sa44 sa4 codeword p 274 x57 - - - - sa51 sa52 sa53 sa54 sa5 codeword p 275 x58 - - - - sa61 sa62 sa63 sa64 sa6 codeword p 275 x59 - - - - sa71 sa72 sa73 sa74 sa7 codeword p 276 x5a - - - - sa81 sa82 sa83 sa84 sa8 codeword p 276 x5b - - - sa6-fi sa6-ei sa6-ci sa6-ai s a6-8i sa6 codeword indication p 277 x5c sa6syn sadeb sa6sce sa4e sa5e sa6e sa7e sa8e sa codeword interrupt control p 278 x5d - - sa6sci sa4i sa5i sa6i sa7i sa8i sa codeword interrupt indica- tion p 279 x5e - - - - - - - - reserved - x5f - - - - - raicrcv cfebev v52linkv overhead error status p 280 x60 - - tcrcee tfebee febee raicrce cfebee v52l inke overhead interrupt control p 281 x61 - - tcrcei tfebei febei raicrci cfebei v52lin ki overhead interrupt indication p 282 x62 - xdis sidis febedis crcm si gen gencrc fdis e1 mode p 283 x63 - - - - - - si0 si1 fgen international bit p 284 e1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 108 march 22, 2004 x64 - - - sa4en sa5en sa6en sa7en sa8en fgen sa control p 285 x65 - - - - sa41 sa42 sa43 sa44 sa4 code-word p 286 x66 - - - - sa51 sa52 sa53 sa54 sa5 code-word p 286 x67 - - - - sa61 sa62 sa63 sa64 sa6 code-word p 286 x68 - - - - sa71 sa72 sa73 sa74 sa7 code-word p 287 x69 - - - - sa81 sa82 sa83 sa84 sa8 code-word p 287 x6a - - - - x0 - x1 x2 fgen extra p 287 x6b - - ts16los ts16ais mfais g706rai autoyel- low remais fgen maintenance 0 p 288 x6c - - - - - cofaen txdis tais fgen maintenance 1 p 289 x6d - - - smfe fase sigmfe mfe bfe fgen interrupt control p 290 x6e - - - smfi fasi sigmfi mfi bfi fgen interrupt indication p 291 x6f - - crcinv crcpinv caspinv nfasinv f asallinv fas1inv error insertion p 292 x70 - - - - - - - xts transmit timing option p 293 x71 - - - - rinv tinv pats1 pats0 prgd control p 293 x72 - - - - bere inv syncv synce prgd status/error control p 294 x73 - - - - beri - - synci prgd interrupt indication p 294 x74 ~ x7b - - - - - - - - reserved - x7c - - - - - trken slipd slipe elst configuration p 295 x7d - - - - - - - slipi elst interrupt indication p 295 x7e trkcode7 trkcode 6 trkcode 5 trkcode 4 trkcode 3 trkcode2 trkcode1 trkcode0 elst trunk code p 295 x7f ~ x83 - - - - - - - - reserved - x84 - - - - - tdlen3 tdlen2 tdlen1 thdlc enable control p 296 x85 - even odd ts4 ts3 ts2 ts1 ts0 thdlc1 assignment p 297 x86 - even odd ts4 ts3 ts2 ts1 ts0 thdlc2 assignment p 297 x87 - even odd ts4 ts3 ts2 ts1 ts0 thdlc3 assignment p 297 x88 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 thdlc1 bit select p 298 x89 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 thdlc2 bit select p 298 x8a biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 thdlc3 bit select p 298 x8b - - - - - rdlen3 rdlen2 rdlen1 rhdlc enable control p 299 x8c - even odd ts4 ts3 ts2 ts1 ts0 rhdlc1 assignment p 300 x8d - even odd ts4 ts3 ts2 ts1 ts0 rhdlc2 assignment p 300 x8e - even odd ts4 ts3 ts2 ts1 ts0 rhdlc3 assignment p 300 x8f biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 rhdlc1 bit select p 301 x90 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 rhdlc2 bit select p 301 x91 biten7 biten6 biten5 biten4 biten3 bit en2 biten1 biten0 rhdlc3 bit select p 301 x92 - - lssufil fisufil adrm1 adrm0 rhdlcm rrst rhdlc1 control register p 302 x93 - - lssufil fisufil adrm1 adrm0 rhdlcm rrst rhdlc2 control register p 302 x94 - - lssufil fisufil adrm1 adrm0 rhdlcm rrst rhdlc3 control register p 302 x95 - - - - - - emp pack rhdlc1 rfifo access status p 303 x96 - - - - - - emp pack rhdlc2 rfifo access status p 303 x97 - - - - - - emp pack rhdlc3 rfifo access status p 303 x98 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc1 data p 304 x99 dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc2 data p 304 x9a dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 rhdlc3 data p 304 e1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 109 march 22, 2004 x9b - - - - - - ovfle rmbee rhdlc1 interrupt control p 305 x9c - - - - - - ovfle rmbee rhdlc2 interrupt control p 305 x9d - - - - - - ovfle rmbee rhdlc3 interrupt control p 305 x9e - - - - - - ovfli rmbei rhdlc1 interrupt indication p 306 x9f - - - - - - ovfli rmbei rhdlc2 interrupt indication p 306 xa0 - - - - - - ovfli rmbei rhdlc3 interrupt indication p 306 xa1 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc1 high address p 307 xa2 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc2 high address p 307 xa3 ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 rhdlc3 high address p 307 xa4 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc1 low address p 308 xa5 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc2 low address p 308 xa6 la7 la6 la5 la4 la3 la2 la1 la0 rhdlc3 low address p 308 xa7 - - autofisu eom xrep abort thdlcm trst thdlc1 control p 309 xa8 - - autofisu eom xrep abort thdlcm trst thdlc2 control p 309 xa9 - - autofisu eom xrep abort thdlcm trst thdlc3 control p 309 xaa - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo1 threshold p 311 xab - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo2 threshold p 311 xac - - fl1 fl0 ll1 ll0 hl1 hl0 tfifo3 threshold p 311 xad dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc1 data p 312 xae dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc2 data p 312 xaf dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 thdlc3 data p 312 xb0 - - - - - ful emp rdy tfifo1 status p 313 xb1 - - - - - ful emp rdy tfifo2 status p 313 xb2 - - - - - ful emp rdy tfifo3 status p 313 xb3 - - - - - - udrune rdye thdlc1 interrupt control p 314 xb4 - - - - - - udrune rdye thdlc2 interrupt control p 314 xb5 - - - - - - udrune rdye thdlc3 interrupt control p 314 xb6 - - - - - - udruni rdyi thdlc1 interrupt indication p 315 xb7 - - - - - - udruni rdyi thdlc2 interrupt indication p 315 xb8 - - - - - - udruni rdyi thdlc3 interrupt indication p 315 xb9 - - ts16losv ts16aisv rmaiv ais raiv red alarm status p 316 xba - - ts16lose ts16aise rmaie aise raie rede alarm control p 317 xbb - - ts16losi ts16aisi rmaii aisi r aii redi alarm indication p 318 xbc - - - - - - aisc raic alarm criteria control p 319 xbd ~ xc1 - - - - - - - - reserved - xc2 - - - - - - updat autoupd pmon control p 319 xc3 prdgove tfebeove febeove tcrcove cofaove oofov e ferove crcove pmon interrupt control 0 p 320 xc4 - - - - - - - lcvove pmon interrupt control 1 p 321 xc5 prdgovi tfebeovi febeovi tcrcovi cofaovi oofovi ferovi crcovi pmon inte rrupt indication 0 p 322 xc6 - - - - - - - lcvovi pmon interrupt indication 1 p 323 xc7 - - - - prbsmod e1 prbsmod e0 prbsdir testen tplc / rplc / prgd test con- figuration p 323 xc8 - - - - - - - busy tplc access status p 324 xc9 rwn address6 address5 address4 address3 address2 address1 address0 tplc access control p 324 xcad7d6d5d4d3d2d1 d0tplc access data p324 xcb sigsnap gstrken - - - gsubst2 gsubst 1 gsubst0 tplc configuration p 325 xcc - - - - - - - pcce tplc control enable p 325 e1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 110 march 22, 2004 xcd - - - - - - - busy rplc access status p 326 xce rwn address6 address5 address4 address3 address2 address1 address0 rplc access control p 326 xcfd7d6d5d4d3d2d1 d0rplc access data p326 xd0 sigsnap gstrken - - - gsubst2 gsubst 1 gsubst0 rplc configuration p 327 xd1 - - - - - - - pcce rplc control enable p 328 xd2 - - - - freeze deb sige - rcrb configuration p 328 xd3 - - - - - - - busy rcrb access status p 329 xd4 rwn address6 address5 address4 address3 address2 address1 address0 rcrb access control p 329 xd5d7d6d5d4d3d2d1 d0rcrb access data p329 xd6 cosi8 cosi7 cosi6 cosi5 cosi4 cosi3 cosi2 cosi1 rcrb state change indication 0 p 330 xd7 cosi16 cosi15 cosi14 cosi13 cosi12 cosi11 cosi10 cosi9 rcrb state change indication 1 p 330 xd8 cosi24 cosi23 cosi22 cosi21 cosi20 cosi19 cosi18 cosi17 rcrb state change indication 2 p 331 xd9 - - cosi30 cosi29 cosi28 cosi27 cosi26 cosi25 rcrb state change indication 3 p 331 note: * the reference clock output control register (addressed x3e) is available in zb revision on ly, otherwise, it is reserved. e1 reg (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register name reference page
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 111 march 22, 2004 5.1.2.2 indirect register pmon rcrb rplc address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 00 crce7 crce6 crce5 crce4 crce3 crce2 crce1 crce0 crce counter mapping 0 p 332 01 - - - - - - crce9 crce8 crce counter mapping 1 p 332 02 fer7 fer6 fer5 fer4 fer3 fer2 fer1 fer0 fer counter mapping 0 p 333 03 - - - - fer11 fer10 fer9 fer8 fer counter mapping 1 p 333 04 - - - - - cofa2 cofa1 cofa0 cofa counter mapping p 334 05 - - - oof4 oof3 oof2 oof1 oof0 oof counter mapping p 334 06 prgd7 prgd6 prgd5 prgd4 prgd3 prgd2 prgd1 prgd0 prgd counter mapping 0 p 335 07 prgd15 prgd14 prgd13 prgd12 prgd11 prgd10 prgd9 prgd8 prgd counter mapping 1 p 335 08 lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 lcv counter mapping 0 p 336 09 lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 lcv counter mapping 1 p 336 0a tcrce7 tcrce6 tcrce5 tcrce4 tcrce3 tcrce2 t crce1 tcrce0 tcrce counter mapping 0 p 337 0b - - - - - - tcrce9 tcrce8 tcrce counter mapping 1 p 337 0c febe7 febe6 febe5 febe4 febe3 febe2 febe1 febe0 febe counter mapping 0 p 338 0d - - - - - - febe9 febe8 febe counter mapping 1 p 338 0e tfebe7 tfebe6 tfebe5 tfebe4 tfebe3 tfebe2 tfebe1 tfebe0 tfebe counter mapping 0 p 339 0f - - - - - - tfebe9 tfebe8 tfebe counter mapping 1 p 339 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 01 ~ 0f - - - extract a b c d extracted signaling data/extract enable register for ts1 ~ ts15 p340 11 ~ 1f - - - extract a b c d extracted signaling data/extract enable register for ts17 ~ ts31 p340 address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 00 ~ 1f subst2 subst1 subst0 sinv oinv einv g56k g ap timeslot control register for ts0 ~ ts31 p341 20 ~ 3f dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 data trunk conditioning code register for ts0 ~ ts31 p342 41 ~ 4f - test - strken a b c d signaling trunk conditioning code register for ts1 ~ ts15 p343 51 ~ 5f - test - strken a b c d signaling trunk conditioning code register for ts17 ~ ts31 p343
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 112 march 22, 2004 tplc address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register reference page 00 ~ 1f subst2 subst1 subst0 sinv oinv einv g56k gap timeslot control register for ts0 ~ ts31 p 344 20 ~ 3f dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 data trunk conditioning code register for ts0 ~ ts31 p 345 41 ~ 4f - test - strken a b c d signaling trunk conditioning code register for ts1 ~ ts15 p 346 51 ~ 5f - test - strken a b c d signaling trunk conditioning code register for ts17 ~ ts31 p 346
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 113 march 22, 2004 5.2 register description depending on the operating mode, the registers are configured for t1/j1 or e1. befo re setting any other registers, the operatin g mode should be selected in registers 020h, 120h, 220h and 320h. according to the access method, the register s can be divided into direct registers and i ndirect registers. in the direct regist ers, the registers can be divided into global configuration regist ers and per-link configuration registers. the register wi th only one address followi ng its name is the global configuration register, and the r egister with a set of address (four addresses) following its name is t he per-link configuratio n register. t1/j1 or e1 mode (020h, 120h, 220h, 320h) t1/j1: this bit is valid when t1/j1 operating mode is selected by the corresponding temode bit (b0, 020h,...). it selects the operatin g mode between t1 and j1 for the current link. = 0: t1 mode is selected. = 1: j1 mode is selected. fm[1:0]: these two bits are valid when t1/j1 operating mode is selected by the correspondi ng temode bit (b0, 020h,...). they select the operating for- mat. = 00: sf format is selected. = 01: esf format is selected. = 10: t1 dm format is selected. this selection is valid in t1 operating mode only. = 11: slc-96 format is selected. this selection is valid in t1 operating mode only. temode: this bit selects the operating mode for the current link. = 0: e1 mode is selected. = 1: t1/j1 mode is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved t1/j1 fm1 fm0 temode type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 114 march 22, 2004 5.2.1 t1/j1 mode 5.2.1.1 direct register t1/j1 chip id for quad transceiver (001h) id[7:0]: the id[7:0] bits are pre-set. the id[7:4] bits represent the IDT82P2284 device. the id [3:0] bits represent the current version number (?0001? is for the first version). t1/j1 software reset (004h) a write operation to this register will generate a software reset. the software reset will set all the register s except the t1/j1 or e1 mode register (020h,...) to their default values. if the s etting is changed in the t1/j1 or e1 mode register (020h,...), a software reset must be applied. bit no. 7 6 5 4 3 2 1 0 bit name id7 id6 id5 id4 id3 id2 id1 id0 type rrrrrrrr default 0010xxxx bit no. 7 6 5 4 3 2 1 0 bit name x type default
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 115 march 22, 2004 t1/j1 g.772 monitor control (005h) mon[3:0]: these bits determine whether the g.772 monitor is implemented. when the g.772 monito r is implemented, these bits select one tra nsmitter or receiver to be monitored by the link 1. bit no. 7 6 5 4 3 2 1 0 bit name reserved mon3 mon2 mon1 mon0 type r/w r/w r/w r/w default 0000 mon[3:0] monitored path mon[3:0] monitored path 0000 no transmitter or receiver is monitored. 1000 no transmitter or receiver is monitored. 0001 the receiver of the link 2 is monitored. 1001 the transmitter of the link 2 is monitored. 0010 the receiver of the link 3 is monitored. 1010 the transmitter of the link 3 is monitored. 0011 the receiver of the link 4 is monitored. 1011 the transmitter of the link 4 is monitored. 0100 reserved 1100 reserved 0101 1101 0110 1110 0111 1111
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 116 march 22, 2004 t1/j1 gpio control (006h) level[1]: when the gpio[1] pin is defined as an output port, this bit can be read and written: = 0: the gpio[1] pin outputs low level. = 1: the gpio[1] pin outputs high level. when the gpio[1] pin is defined as an input port, this bit can only be read: = 0: low level is input on the gpio[1] pin. = 1: high level is input on the gpio[1] pin. level[0]: when the gpio[0] pin is defined as an output port, this bit can be read and written: = 0: the gpio[0] pin outputs low level. = 1: the gpio[0] pin outputs high level. when the gpio[0] pin is defined as an input port, this bit can only be read: = 0: low level is input on the gpio[0] pin. = 1: high level is input on the gpio[0] pin. dir[1]: = 0: the gpio[1] pin is used as an output port. = 1: the gpio[1] pin is used as an input port. dir[0]: = 0: the gpio[0] pin is used as an output port. = 1: the gpio[0] pin is used as an input port. bit no. 7 6 5 4 3 2 1 0 bit name reserved level1 level0 dir1 dir0 type r/w r/w r/w r/w default 001 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 117 march 22, 2004 t1/j1 reference clock output select (007h) ro2[1:0]: when no los is detected, the refb_out pin out puts a recovered clock from the clock and data recovery function block of one of t he four links. the link is selected by these bits: when los is detected, the refb_out pin outputs mclk or high leve l, as selected by the refh_los bit (b0, t1/j1-03eh,...). (this feature is available in zb revision only). ro1[1:0]: when no los is detected, the refa_out pin outputs a recovered cl ock from the clock and data recovery function block of one of t he four links. the link is selected by these bits: when los is detected, the refa_out pin outputs mclk or high le vel, as selected by the refh_los bit (b0, t1/j1-03eh,...). (this feature is available in zb revision only). bit no. 7 6 5 4 3 2 1 0 bit name reserved ro21 ro20 reserved ro11 ro10 type r/w r/w r/w r/w default 00 00 ro2[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4 ro2[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 118 march 22, 2004 t1/j1 interrupt requisition link id (009h) intn: = 0: no interrupt is generated in the corresponding link. = 1: at least one interrupt is generated in the corresponding link. t1/j1 timer interrupt control (00ah) tmove: = 0: disable the interrupt on the int pin when the tmovi bit (b0, t1/j1-00bh) is ?1?. = 1: enable the interrupt on the int pin when the tmovi bit (b0, t1/j1-00bh) is ?1?. t1/j1 timer interrupt indication (00bh) tmovi: the device times every one second. = 0: one second timer is not over. = 1: one second timer is over. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved int4 int3 int2 int1 type rrr r default 000 0 bit no.7 6 543210 bit name reserved tmove type r/w default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved tmovi type r default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 119 march 22, 2004 t1/j1 pmon access port (00eh) linksel[1:0]: these bits select one of the four links. one of the pmon indire ct registers of the selected li nk can be accessed by the micropr ocessor. addr[3:0]: these bits select one of the pmon indirect registers of the selected link to be accessed by the microprocessor. t1/j1 pmon access data (00fh) dat[7:0]: these bits hold the value which is read fr om the selected pmon indirect register. bit no. 7 6 5 4 3 2 1 0 bit name reserved linksel1 linksel0 reserved addr3 addr2 addr1 addr0 type r/w r/w r/w r/w r/w r/w default 00 0000 linksel[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4 address pmon indirect register address pmon indirect register 00h crce counter mapping 0 06h prgd counter mapping 0 01h crce counter mapping 1 07h prgd counter mapping 1 02h fer counter mapping 0 08h lcv counter mapping 0 03h fer counter mapping 1 09h lcv counter mapping 1 04h cofa counter mapping 0ah ddse counter mapping 0 05h oof counter mapping 0bh ddse counter mapping 1 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r r r r rrrr default 00000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 120 march 22, 2004 t1/j1 backplane global configuration (010h) rslvck: this bit is valid when all four link s are in the receive clock slave mode. = 0: each link uses its own clock signal on t he rsckn pin and framing pulse on the rsfsn pin. = 1: all four links use the clock signal on the rs ck[1] pin and the framing pulse on the rsfs[1] pin. rmux: = 0: the receive system interface of the device is operated in the non-multiplexed mode. = 1: the receive system interface of the device is operated in the multiplexed mode. mtsda: this bit is valid in transmit multiplexed mode. it selects one mu ltiplexed bus for the transmit system interface of the device. = 0: the multiplexed bus b is selected. the data and si gnaling bits are de-multiplexed from multiplexed bus b. = 1: the multiplexed bus a is selected. the data and si gnaling bits are de-multiplexed from multiplexed bus a. tslvck: this bit is valid when all four links are in the transmit clock slave mode. = 0: each link uses its own timing signal on t he tsckn pin and framing pulse on the tsfsn pin. = 1: all four links use the timing signal on the ts ck[1] pin and the framing pulse on the tsfs[1] pin. tmux: = 0: the transmit system interface of the dev ice is operated in the non-multiplexed mode. = 1: the transmit system interface of the device is operated in the multiplexed mode. bit no. 7 6 5 4 3 2 1 0 bit name reserved rslvck rmux mtsda tslvck tmux type r/w r/w r/w r/w r/w default 10110
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 121 march 22, 2004 t1/j1 transmit jitter at tenuation configuration (021h, 121h, 221h, 321h) tjitt_test: = 0: the real time interval between the r ead and write pointer of the fifo is indicat ed in the tjitt[6:0] bits (b6~0, t1/j1-038 h,...). that is, the current interval between the read and write pointer of the fifo will be written into the tjitt[6:0] bits (b6~0, t1/j1-038h,...) . = 1: the peak-peak interval between the read and write pointer of the fifo is indicated in the tjitt[6:0] bits (b6~0, t1/j1-038 h,...). that is, the current interval is compared with the old one in the tjitt[6:0] bits (b6~0, t1/j1-038h,...) and the larger one will be indicate d by the tjitt[6:0] bits (b6~0, t1/j1-038h,...); otherwise, the value in the tjit t[6:0] bits (b6~0, t1/j 1-038h,...) will not be changed. tja_limt: when the read and write pointer of the fifo are within 2/3/4 bi ts (corresponding to the fifo dept h) of overflowing or underflow ing, the bandwidth of the ja can be widened to track the short term input jitter, t hereby avoiding data corruption. th is bit selects whether the b andwidth is normal or wid- ened. = 0: normal bandwidth is selected. = 1: widen bandwidth is selected. in this case, the ja will not attenuate the input jitter until the read/write pointer?s posit ion is outside the 2/3/4 bits window. tja_e: = 0: disable the transmit jitter attenuator. = 1: enable the transmit jitter attenuator. tja_dp[1:0]: these two bits select the jitter attenuation depth. = 00: the jitter attenuation depth is 128-bit. = 01: the jitter attenuation depth is 64-bit. = 10 / 11: the jitter attenuation depth is 32-bit. tja_bw: this bit select the jitter transfer function bandwidth. = 0: 5 hz. = 1: 1.26 hz. bit no. 7 6 5 4 3 2 1 0 bit name reserved tjitt_test tja_limt tja_ e tja_dp1 tja_dp0 tja_bw type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 122 march 22, 2004 t1/j1 transmit configuration 0 (022h, 122h, 222h, 322h) t_off: = 0: the transmit path is power up. = 1: the transmit path is power down. the line driver is in high impedance. t_md: this bit selects the line code rule to encode the data stream to be transmitted. = 0: the b8zs encoder is selected. = 1: the ami encoder is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved t_off reserved t_md type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 123 march 22, 2004 t1/j1 transmit configuration 1 (023h, 123h, 223h, 323h) dfm_on: = 0: the driver failur e monitor is disabled. = 1: the driver failure monitor is enabled. t_hz: = 0: the line driver works normally. = 1: set the line driver high-z . (the other parts of the transmit path still work normally.) puls[3:0]: these bits determine the template shapes for short/long haul transmission: bit no. 7 6 5 4 3 2 1 0 bit name reserved dfm_on t_hz puls3 puls2 puls1 puls0 type r/w r/w r/w r/w r/w r/w default 010000 puls[3:0] operating mode transmit clock cable impedance application 0000 reserved 0001 0010 dsx1 1.544 mhz 100 ? 0 - 133 ft j1 1.544 mhz 110 ? 0 - 655 ft ds1 1.544 mhz 100 ? 0 db lbo 0011 dsx1 1.544 mhz 100 ? 133 - 266 ft 0100 dsx1 1.544 mhz 100 ? 266 - 399 ft 0101 dsx1 1.544 mhz 100 ? 399 - 533 ft 0110 dsx1 1.544 mhz 100 ? 533 - 655 ft 0111 reserved 1000 1001 ds1 1.544 mhz 100 ? -7.5 db lbo 1010 ds1 1.544 mhz 100 ? -15.0 db lbo 1011 ds1 1.544 mhz 100 ? -22.5 db lbo 11xx arbitrary waveform setting.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 124 march 22, 2004 t1/j1 transmit configuration 2 (024h, 124h, 224h, 324h) scal[5:0]: the following setting lists the standard values of normal amp litude in different operating modes. each step change (one increas ing or decreasing from the standard value) will scale the am plitude of the d/a output by a certain offs et. these bits are only effective when use r programmable arbitrary waveform is used. = 000100: normal amplitude in t1 long haul lbo/-22.5 db operating mode. each step change scales about 25% offset. = 001000: normal amplitude in t1 long haul lbo/-15 db oper ating mode. each step change scales about 12.5% offset. = 010001: normal amplitude in t1 long haul lbo/-7.5 db operating mode. each step change scales about 6.25% offset. = 110110: normal amplitude in t1 0~133 ft, 133~266 ft, 266~399 ft, 399~533 ft, 533~655 ft, ds1 0 db & j1 0~655 ft operating mod es. each step change scales about 2% offset. bit no. 7 6 5 4 3 2 1 0 bit name reserved scal5 scal4 scal3 scal2 scal1 scal0 type r/w r/w r/w r/w r/w r/w default 100001
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 125 march 22, 2004 t1/j1 transmit configuration 3 (025h, 125h, 225h, 325h) this register is valid when the puls[3:0] bi ts (b3~0, t1/j1-023h,...) are set to ?11xx?. done: = 0: disable the read/write operat ion to the pulse template ram. = 1: enable the read/write operation to the pulse template ram. rw: = 0: write the data to the pulse template ram. = 1: read the data to the pulse template ram. ui[1:0]: these bits specify one unit interval (ui) address. = 00: ui addressed 0 is specified. = 01: ui addressed 1 is specified. = 10: ui addressed 2 is specified. = 11: ui addressed 3 is specified. samp[3:0]: there bits specify one sample address. there are 16 samples in each ui. bit no. 7 6 5 4 3 2 1 0 bit name done rw ui1 ui0 samp3 samp2 samp1 samp0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 samp[3:0] specified sample address sa mp[3:0] specified sample address 0000 0 1000 8 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 126 march 22, 2004 t1/j1 transmit configuration 4 (026h, 126h, 226h, 326h) wdat[6:0]: these bits contain the data to be stored in the pulse template ra m which is addressed by the ui[1:0] bits (b5~4, t1/j1-025h,... ) and the samp[3:0] bits (b3~0, t1/j1-025h,...). t1/j1 receive jitter at tenuation configuration (027h, 127h, 227h, 327h) rjitt_test: = 0: the real time interval between the read and write pointer of the fifo is indicated in the rj itt[6:0] bits (b6~0, t1/j1-039 h,...). that is, the current interval between the read and write pointer of the fifo will be written into the rjitt[6:0] bits (b6~0, t1/j1-039h,...) . = 1: the peak-peak interval between the read and write pointer of the fifo is indicated in the rjitt[6:0] bits (b6~0, t1/j1-039 h,...). that is, the current interval is compared with the old one in the rjitt[6:0] bits (b6~0, t1/j1-039h,...) and the larger one will be indicate d by the rjitt[6:0] bits (b6~0, t1/j1-039h,...); otherwise, the value in the rj itt[6:0] bits (b6~0, t1/j1-039h,...) will not be changed. rja_limt: when the read and write pointer of the fifo are within 2/3/4 bi ts (corresponding to the fifo dept h) of overflowing or underflow ing, the bandwidth of the ja can be widened to track the short term input jitter, t hereby avoiding data corruption. th is bit selects whether the b andwidth is normal or wid- ened. = 0: normal bandwidth is selected. = 1: widen bandwidth is selected. in this case, the ja will not attenuate the input jitter until the read/write pointer?s posit ion is outside the 2/3/4 bits window. rja_e: = 0: disable the receive jitter attenuator. = 1: enable the receive jitter attenuator. rja_dp[1:0]: these two bits select the jitter attenuation depth. = 00: the jitter attenuation depth is 128-bit. = 01: the jitter attenuation depth is 64-bit. = 10 / 11: the jitter attenuation depth is 32-bit. rja_bw: this bit select the jitter transfer function bandwidth. = 0: 5 hz. = 1: 1.26 hz. bit no. 7 6 5 4 3 2 1 0 bit name reserved wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved rjitt_test rja_limt rja_e rja_dp1 rja_dp0 rja_bw type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 127 march 22, 2004 t1/j1 receive configuration 0 (028h, 128h, 228h, 328h) r_off: = 0: the receive path is power up. = 1: the receive path is power down. r_md: this bit selects the line code rule to decode the received data stream. = 0: the b8zs decoder is selected. = 1: the ami decoder is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved r_off reserved r_md type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 128 march 22, 2004 t1/j1 receive configuration 1 (029h, 129h, 229h, 329h) eq_on: = 0: the equalizer is off in short haul applications. = 1: the equalizer is on in long haul applications. los[4:0]: a los is detected when the incoming signals has ?no transitions?, i.e., when the signal level is less than q db below nominal f or n consecutive pulse intervals. in long haul applications, t hese bits select the los declare threshold (q). these bits are invalid in short ha ul applications. bit no. 7 6 5 4 3 2 1 0 bit name reserved eq_on reserved los4 los3 los2 los1 los0 type r/w r/w r/w r/w r/w r/w default 010101 los[4:0] los declare threshold (q) l os[4:0] los declare threshold (q) 00000 -4 db 01100 -28 db 00001 -6 db 01101 -30 db 00010 -8 db 01110 -32 db 00011 -10 db 01111 -34 db 00100 -12 db 10000 -36 db 00101 -14 db 10001 -38 db 00110 -16 db 10010 -40 db 00111 -18 db 10011 -42 db 01000 -20 db 10100 -44 db 01001 -22 db 10101 -46 db 01010 -24 db 10110 - 11111 -48 db 01011 -26 db
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 129 march 22, 2004 t1/j1 receive configuration 2 (02ah, 12ah, 22ah, 32ah) slice[1:0]: these two bits define the data slicer threshold. = 00: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 40% of the peak amplitude. = 01: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 50% of the peak amplitude. = 10: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 60% of the peak amplitude. = 11: the data slicer generates a mark if the voltage on the rtipn/rringn pins exc eeds 70% of the peak amplitude. updw[1:0]: these two bits select the observation period, during wh ich the peak value of the incoming signals is measured. = 00: the observation period is 32 bits. = 01: the observation period is 64 bits. = 10: the observation period is 128 bits. = 11: the observation period is 256 bits. mg[1:0]: these two bits select the monitor gain. = 00: the monitor gain is 0 db. = 01: the monitor gain is 22 db. = 10: the monitor gain is 26 db. = 11: the monitor gain is 32 db. bit no. 7 6 5 4 3 2 1 0 bit name reserved slice1 slice0 updw1 updw0 mg1 mg0 type r/w r/w r/w r/w r/w r/w default 01 1 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 130 march 22, 2004 t1/j1 maintenance function control 0 (02bh, 12bh, 22bh, 32bh) dllp: = 0: disable the loc al digital loopback 1. = 1: enable the local digital loopback 1. sllp: = 0: disable the system local loopback. = 1: enable the system local loopback. srlp: = 0: disable the system remote loopback. = 1: enable the system remote loopback. rlp: = 0: disable the remote loopback. = 1: enable the remote loopback. alp: = 0: disable the analog loopback. = 1: enable the analog loopback. dlp: = 0: disable the loc al digital loopback 2. = 1: enable the local digital loopback 2. bit no. 7 6 5 4 3 2 1 0 bit name reserved dllp sllp srlp reserved rlp alp dlp type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 131 march 22, 2004 t1/j1 maintenance function control 1 (02ch, 12ch, 22ch, 32ch) lac: this bit selects the los criterion. = 0: the t1.231 is selected. in short haul application, the los is declared when the incoming signal level is less than 800 mvp p for 175 consec- utive bit intervals and is cleared when the incoming signal level is greater than 1 vpp and has an average mark density of at l east 12.5% and less than 100 consecutive zeros in 128 consecutive bi t periods. in long haul application, the lo s is declared when the incoming signal le vel is less than q db below nominal (set in the los[4:0] bits (b4~0, t1/j1-029h,...)) for 175 consecutive bi t intervals and is cleared when the incom ing signal level is greater than (q + 4 db) and has an average mark density of at l east 12.5% and less than 100 consecutive zeros in 128 consecutiv e bit periods. = 1: the i.431 is selected. in short haul application, the los is declared when the incoming signal level is less than 800 mvpp for 1544 consecu- tive bit intervals and is cleared when the incoming signal level is greater than 1 v pp and has an average mark density of at le ast 12.5% and less than 100 consecutive zeros in 128 consecutive bi t periods. in long haul application, the lo s is declared when the incoming signal le vel is less than q db below nominal (set in the los[4:0] bits (b4~0, t1/j1-029h,...)) for 1544 consecutive bit intervals and is cleared when the inco ming signal level is greater than (q + 4 db) and has an average mark density of at l east 12.5% and less than 100 consecutive zeros in 128 consecutiv e bit periods. raise: this bit determines whether all ?one?s can be inse rted in the receive path when the los is detected. = 0: disable the insertion. = 1: enable the insertion. atao: this bit determines whether all ?one?s can be inserted in the transmit path when the los is detected in the receive path. = 0: disable the insertion. = 1: enable the insertion. bit no. 7 6 5 4 3 2 1 0 bit name reserved lac raise atao type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 132 march 22, 2004 t1/j1 maintenance function control 2 (031h, 131h, 231h, 331h) bpv_ins: a transition from ?0? to ?1? on this bit gener ates a single bipolar violation (bpv) erro r to be inserted to the data stream to be transmitted. this bit must be cleared and set again for the next bpv error insertion. exz_def: this bit selects the excessive zero (exz) error criterion. = 0: the ansi is selected. in ami line code rule, the exz erro r is defined as more than 15 consecutive zeros in the data stream . in b8zs line code rule, the exz error is defined as more th an 7 consecutive zeros in the data stream. = 1: the fcc is selected. in ami line code rule, the exz error is defined as more than 80 consecutive zeros in the data stream. in b8zs line code rule, the exz error is defined as more than 7 consecutive zeros in the data stream. exz_err[1:0]: these bits must be set to ?01? to enable the excessive zero ( exz) error event to be counted in an internal 16-bit exz counter. cnt_md: = 0: the manual report mode is selected. t he internal 16-bit exz counter transfers its content to the exz error counter l-byte & h-byte regis- ters when there is a transition fr om ?0? to ?1? on the cnt_trf bit. = 1: the auto report mode is selected. the internal 16-bit exz counter transfers its c ontent to the exz error counter l-byte & h-byte registers every one second automatically. cnt_trf: this bit is valid when the cnt_md bit is ?0?. a transition from ?0? to ?1? on this bit updates the content in t he exz error counter l-byte & h- byte registers with the value in the internal 16-bit exz counter. this bit must be cleared and set again for the next updating. bit no. 7 6 5 4 3 2 1 0 bit name reserved bpv_ins reserved exz_def exz_err1 exz_err0 cnt_md cnt_trf type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 133 march 22, 2004 t1/j1 transmit and receive termination configuration (032h, 132h, 232h, 332h) t_term[2:0]: these bits select the internal impedance of the transmit path to match the cable impedance: = 000: the 75 ? internal impedance matching is selected. = 001: the 120 ? internal impedance matching is selected. = 010: the 100 ? internal impedance matching is selected. (it is the standard value for t1 mode). = 011: the 110 ? internal impedance matching is selected. (it is the standard value for j1 mode). = 1xx: reserved. in t1/j1 mode, the external impedance circ uit is not supported in transmit path. r_term[2:0]: these bits select the internal impedance of the receive path to match the cable impedance: = 000: the 75 ? internal impedance matching is selected. = 001: the 120 ? internal impedance matching is selected. = 010: the 100 ? internal impedance matching is selected. (it is the standard value for t1 mode). = 011: the 110 ? internal impedance matching is selected. (it is the standard value for j1 mode). = 1xx: the internal impedance matching is bypa ssed, and external impedance circuit should be used. t1/j1 interrupt en able control 0 (033h, 133h, 233h, 333h) df_ie: = 0: disable the interrupt on the int pin when the df_is bit (b2, t1/j1-03ah,...) is ?1?. = 1: enable the interrupt on the int pin when the df_is bit (b2, t1/j1-03ah,...) is ?1?. los_ie: = 0: disable the interrupt on the int pin when the los_is bit (b0, t1/j1-03ah,...) is ?1?. = 1: enable the interrupt on the int pin when the los_is bit (b0, t1/j1-03ah,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved t_term2 t_term1 t_term0 r _term2 r_term1 r_term0 type r/w r/w r/w r/w r/w r/w default 00 0 1 1 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved df_ie reserved los_ie type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 134 march 22, 2004 t1/j1 interrupt en able control 1 (034h, 134h, 234h, 334h) dac_ie: = 0: disable the interrupt on the int pin when the dac_is bit (b6, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the dac_is bit (b6, t1/j1-03bh,...) is ?1?. tja_ie: = 0: disable the interrupt on the int pin when the tja_is bit ( b5, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the tja_is bit (b5, t1/j1-03bh,...) is ?1?. rja_ie: = 0: disable the interrupt on the int pin when the rja_is bit (b4, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the rja_is bit ( b4, t1/j1-03bh,...) is ?1?. exz_ie: = 0: disable the interrupt on the int pin when the exz_is bit (b2, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the exz_is bit ( b2, t1/j1-03bh,...) is ?1?. cv_ie: = 0: disable the interrupt on the int pin when the cv_is bit (b1, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the cv_is bit ( b1, t1/j1-03bh,...) is ?1?. cnt_ie: = 0: disable the interrupt on the int pin when the cntov_is bit (b0, t1/j1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the cntov_is bit (b0, t1/j1-03bh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved dac_ie tja_ie rja_ie reserved exz_ie cv_ie cnt_ie type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 135 march 22, 2004 t1/j1 interrupt trigger edges select (035h, 135h, 235h, 335h) df_ies: = 0: the df_is bit (b2, t1/j1-03ah,...) will be set to ?1? when there is a transition from ?0? to ?1? on the df_s bit (b2, t1/j 1-036h,...). = 1: the df_is bit (b2, t1/j1-03ah,...) will be set to ?1? when there is any transition from ?0? to ?1? or from ?1? to ?0? on t he df_s bit (b2, t1/j1- 036h,...). los_ies: = 0: the los_is bit (b0, t1/j1-03ah,...) w ill be set to ?1? when there is a transition from ?0? to ?1? on the los_s bit (b0, t1 /j1-036h,...). = 1: the los_is bit (b0, t1/j1-03ah,...) will be set to ?1? when t here is any transition from ?0? to ?1? or from ?1? to ?0? on the los_s bit (b0, t1/j1- 036h,...). t1/j1 line status register 0 (036h, 136h, 236h, 336h) df_s: = 0: no transmit driver failure is detected. = 1: transmit driver failure is detected. los_s: = 0: no los is detected. = 1: loss of signal (los) is detected. bit no. 7 6 5 4 3 2 1 0 bit name reserved df_ies reserved los_ies type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved df_s reserved los_s type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 136 march 22, 2004 t1/j1 line status register 1 (037h, 137h, 237h, 337h) latt[4:0]: these bits indicate the current gain of the vga relative to 3 v peak pulse level. bit no. 7 6 5 4 3 2 1 0 bit name reserved latt4 latt3 latt2 latt1 latt0 type rrr r r default 000 0 0 latt[4:0] gain (db) latt[4:0] gain (db) 00000 0 - 2 01011 22 - 24 00001 2 - 4 01100 24 - 26 00010 4 - 6 01101 26 - 28 00011 6 - 8 01110 28 - 30 00100 8 - 10 01111 30 - 32 00101 10 - 12 10000 32 - 34 00110 12 - 14 10001 34 - 36 00111 14 - 16 10010 36 - 38 01000 16 - 18 10011 38 - 40 01001 18 - 20 10100 40 - 42 01010 20 - 22 10101 ~ 11111 42 - 44
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 137 march 22, 2004 t1/j1 transmit jitter measure value indication (038h, 138h, 238h, 338h) tjitt[6:0]: when the tjitt_test bit (b5, t1/j1-021h,...) is ?0?, these bits represent the current interval between the read and write point er of the fifo. when the tjitt_test bit (b5, t1/j1-021h,...) is ?1?, these bits represent the p-p in terval between the read and write pointer o f the fifo since last read. these bits will be cleared if a ?1 ? is written to the register. t1/j1 receive jitter measure value indication (039h, 139h, 239h, 339h) rjitt[6:0]: when the rjitt_test bit (b5, t1/j1-027h,...) is ?0?, these bits represent the current interval between the read and write point er of the fifo. when the rjitt_test bit (b5, t1/j1-027h,...) is ?1?, these bits represent the p-p in terval between the read and write pointer o f the fifo since last read. these bits will be cleared if a ?1 ? is written to the register. bit no. 7 6 5 4 3 2 1 0 bit name reserved tjitt6 tjitt5 tjitt4 tjitt3 tjitt2 tjitt1 tjitt0 type rr r r r r r default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved rjitt6 rjitt5 rjitt4 rjitt3 rjitt2 rjitt1 rjitt0 type rr r r r r r default 00 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 138 march 22, 2004 t1/j1 interrupt status 0 (03ah, 13ah, 23ah, 33ah) df_is: = 0: there is no status change on the df_s bit (b2, t1/j1-036h,...). = 1: when the df_ies bit (b2, t1/j1-035h,...) is ?0?, the ?1? on th is bit indicates there is a transition from ?0? to ?1? on th e df_s bit (b2, t1/j1- 036h,...); when the df_ies bit (b2, t1/j1-035h,...) is ?1?, the ?1? on this bit indicates there is a transition from ?0? to ?1? or from ?1? to ?0? on the df_s bit (b2, t1/j1-036h,...). this bit will be cleared if a ?1? is written to it. los_is: = 0: there is no status change on the los_s bit (b0, t1/j1-036h,...). = 1: when the los_ies bit (b0, t1/j1-035h,...) is ?0?, the ?1? on this bit indicates there is a transition from ?0? to ?1? on t he los_s bit (b0, t1/j1- 036h,...); when the los_ies bit (b0, t1/j1-035h,...) is ?1?, the ?1 ? on this bit indicates there is a transition from ?0? to ?1 ? or from ?1? to ?0? on the los_s bit (b0, t1/j1-036h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved df_is reserved los_is type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 139 march 22, 2004 t1/j1 interrupt status 1 (03bh, 13bh, 23bh, 33bh) dac_is: = 0: the sum of a pulse template does not exceed the d/a limitation (+ 63) when more than one ui is used to compose the arbitrary pulse tem- plate. = 1: the sum of a pulse template exceeds the d/a limitation (+ 63) when more than one ui is used to compose the arbitrary pulse template. this bit will be cleared if a ?1? is written to it. tja_is: = 0: the transmit ja fifo has not overflowed or underflowed. = 1: the transmit ja fifo has overflowed or underflowed. this bit will be cleared if a ?1? is written to it. rja_is: = 0: the receive ja fifo has not overflowed or underflowed. = 1: the receive ja fifo has overflowed or underflowed. this bit will be cleared if a ?1? is written to it. exz_is: = 0: no excessive zero (exz) error is detected. = 1: the excessive zero (exz) error is detected. this bit will be cleared if a ?1? is written to it. cv_is: = 0: no bipolar violation (bpv) error is detected. = 1: the bipolar violation (bpv) error is detected. this bit will be cleared if a ?1? is written to it. cntov_is: = 0: the internal 16-bit exz counter has not overflowed. = 1: the internal 16-bit exz counter has overflowed. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved dac_is tja_is rja_is reserved exz_is cv_is cntov_is type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 140 march 22, 2004 t1/j1 exz error counter h-byte (03ch, 13ch, 23ch, 33ch) cnth[7:0]: these bits, together with the cntl[7:0] bits, reflec t the content in the internal 16-bit exz counter. t1/j1 exz error counter l-byte (03dh, 13dh, 23dh, 33dh) cntl[7:0]: these bits, together with the cnth[7 :0] bits, reflect the content in the internal 16-bit exz counter. t1/j1 reference clock output control (03eh, 13eh, 23eh, 33eh) refh_los: in case of los, this bit determines t he outputs on the refa_out and refb_out pins. = 0: output mclk. = 1: output high level. bit no. 7 6 5 4 3 2 1 0 bit name cnth[7] cnth[6] cnth[5] cnth[4] cnth[3] cnth[2] cnth[1] cnth[0] type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name cntl[7] cntl[6] cntl[5] cntl[4] cntl[3] cntl[2] cntl[1] cntl[0] type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved refh_los type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 141 march 22, 2004 t1/j1 interrupt modu le indication 2 (03fh, 13fh, 23fh, 33fh) liu: = 0: no interrupt is generated in the receive / transmit internal termination, adaptive equalizer, data slicer, clk&data recove ry, receive / transmit jitter attenuator, b8zs/hdb3/ami decoder / encoder, waveform shaper / line build out or line driver block. = 1: interrupt is generated in the receive / transmit internal termination, adaptive equalizer, data slicer, clk&data recovery, receive / trans- mit jitter attenuator, b8zs/hdb3/ami decoder / encoder, wavefo rm shaper / line build out or line driver function block. bit no. 7 6 5 4 3 2 1 0 bit name reserved liu type r default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 142 march 22, 2004 t1/j1 interrupt modu le indication 0 (040h, 140h, 240h, 340h) ibcd: = 0: no interrupt is generated in the inband loopback code detector function block. = 1: interrupt is generated in the inband loopback code detector function block. rboc: = 0: no interrupt is generated in the bi t-oriented message receiver function block. = 1: interrupt is generated in the bit- oriented message receiver function block. alarm: = 0: no interrupt is generated in the alarm detector function block. = 1: interrupt is generated in t he alarm detector function block. pmon: = 0: no interrupt is generated in t he performance monitor function block. = 1: interrupt is generated in the performance monitor function block. prgd: = 0: no interrupt is generated in the pr bs generator / detector function block. = 1: interrupt is generated in the prbs generator / detector function block. rcrb: = 0: no interrupt is generated in the receive cas/rbs buffer function block. = 1: interrupt is generated in the re ceive cas/rbs buffer function block. fgen: = 0: no interrupt is generated in the frame generator function block. = 1: interrupt is generated in t he frame generator function block. frmr: = 0: no interrupt is generated in the frame processor function block. = 1: interrupt is generated in t he frame processor function block. bit no. 7 6 5 4 3 2 1 0 bit name ibcd rboc alarm pmon prgd rcrb fgen frmr type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 143 march 22, 2004 t1/j1 interrupt modu le indication 1 (041h, 141h, 241h, 341h) thdlc3: = 0: no interrupt is generated in t he hdlc transmitter #3 function block. = 1: interrupt is generated in the hdlc transmitter #3 function block. thdlc2: = 0: no interrupt is generated in t he hdlc transmitter #2 function block. = 1: interrupt is generated in the hdlc transmitter #2 function block. thdlc1: = 0: no interrupt is generated in t he hdlc transmitter #1 function block. = 1: interrupt is generated in the hdlc transmitter #1 function block. rhdlc3: = 0: no interrupt is generated in the hdlc receiver #3 function block. = 1: interrupt is generated in the hdlc receiver #3 function block. rhdlc2: = 0: no interrupt is generated in the hdlc receiver #2 function block. = 1: interrupt is generated in the hdlc receiver #2 function block. rhdlc1: = 0: no interrupt is generated in the hdlc receiver #1 function block. = 1: interrupt is generated in the hdlc receiver #1 function block. elst: = 0: no interrupt is generated in the elastic store buffer function block. = 1: interrupt is generated in the elastic store buffer function block. trsi/resi: = 0: no interrupt is generated in the transmi t / receive system interface function block. = 1: interrupt is generated in the transmit / receive system interface function block. bit no. 7 6 5 4 3 2 1 0 bit name thdlc3 thdlc2 thdlc1 rhdlc3 rhdlc2 rhdlc1 elst trsi/resi type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 144 march 22, 2004 t1/j1 tbif option register (042h, 142h, 242h, 342h) fbitgap: this bit is valid in transmit clock master mode. = 0: the f-bit is not gapped. = 1: the f-bit is gapped (no cl ock signal during the f-bit). de: this bit selects the active edge of tsckn to sample the data on tsdn and tsign and the active edge of mtsck to sample the data on mtsda (mtsdb) and mtsiga (mtsigb). = 0: the falling edge is selected. = 1: the rising edge is selected. in transmit multiplexed mode, the bit of the four links should be set to the same value. fe: this bit selects the active edge of tsckn to update/sample the pulse on tsfsn and the active edge of mtsck to sample the pulse on mtsfs. = 0: the falling edge is selected. = 1: the rising edge is selected. in transmit multiplexed mode, the bit of the four links should be set to the same value. cms: this bit is valid in transmit clock slave t1 /j1 mode e1 rate and transmit multiplexed mode. = 0: the speed of the tsckn / mtsck is the same as the data rate on the system side (2.048 mhz / 8.192 mhz). = 1: the speed of the tsckn / mtsck is double the dat a rate on the system side (4.096 mhz / 16.384 mhz). in transmit clock slave t1/j1 mode e1 rate, if all four links use the tsck[1] and tsfs[1] to input the data (i.e., the tslvck b it (b, t1/j1-010h) is set to ?1?), the bit of the four links should be set to the same value. in transmit multiplexed mode, the bit of the four links should be set to the same value. fsinv: = 0: the transmit framing pul se tsfsn is active high. = 1: the transmit framing pulse tsfsn is active low. in transmit multiplexed mode, this bit of the four links should be set to the same value. fstyp: = 0: in transmit non-multiplexed mode, tsfsn pulses during each f-bit. in transmit multiplexed mode, mtsfs pulses during each f -bit of the first link. = 1: in transmit non-multiplexed mode, tsfsn pulses during the fi rst f-bit of every sf/esf/t1 dm /slc-96 frame. in transmit mult iplexed mode, mtsfs pulses during the first f-bit of ever y sf/esf/t1 dm/slc-96 frame of the first link. in transmit multiplexed mode, this bit of t he four links should be set to the same value. bit no. 7 6 5 4 3 2 1 0 bit name reserved fbitgap de fe cms fsinv fstyp type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 145 march 22, 2004 t1/j1 tbif operating mode (043h, 143h, 243h, 343h) map[1:0]: in transmit clock slave mode and transmit multiplexed mode, thes e 2 bits select the t1/j1 to e1 format mapping schemes. tmode: in transmit non-multiplexed mode, this bit selects the sub-mode. = 0: the transmit system interface is oper ated in transmit clock master mode. the timing signal for clocking the data and the f raming pulse to align the data input on the tsdn pin are prov ided from the processed data from the device. = 1: the transmit system interface is operated in transmit cl ock slave mode. the timing signal for clocking the data and the fr aming pulse to align the data input on the tsdn pin are provided by the system side. bit no. 7 6 5 4 3 2 1 0 bit name reserved map1 map0 tmode type r/w r/w r/w default 001 map[1:0] t1/j1 to e1 format mapping schemes 0 0 * t1/j1 rate 0 1 t1/j1 mode e1 rate per g.802 1 0 t1/j1 mode e1 rate per one filler every four chs 1 1 t1/j1 mode e1 rate per continuous chs note: * these 2 bits can not be set to ?00? in the transmit multiplexed mode.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 146 march 22, 2004 t1/j1 tbif ts offset (044h, 144h, 244h, 344h) tsoff[6:0]: these bits give a binary number to define the channel offset. the channel offset is between the framing pulse on the tsfsn/mtsf s pin and the start of the corresponding frame input on the tsdn/mtsda(mtsdb) pin. the signaling bits on the tsig n/mtsiga(mtsigb) pin are alw ays per- channel aligned with the data on the tsdn/mtsda(mtsdb) pin. in non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). in multiplexed mode, the channel off- set can be configured from 0 to 127 channels (0 & 127 are included). t1/j1 tbif bit offset (045h, 145h, 245h, 345h) edge: this bit is valid when the cms bit (b2, t1/j1-042h,...) is ?1?. = 0: the first active edge of tsckn/mtsck is selected to sample the data on the tsdn/mtsda(mtsdb) and tsign/mtsiga(mtsigb) pins . = 1: the second active edge of tsckn/mtsck is selected to sa mple the data on the tsdn/mtsda(mtsdb) and tsign/mtsiga(mtsigb) pins. boff[2:0]: these bits give a binary number to define the bit offset. the bit offset is between the framing pulse on the tsfsn/mtsfs pin an d the start of the corresponding frame input on the tsdn/mtsda(mtsdb) pin. the signal ing bits on the tsign/mtsiga(m tsigb) pin are always per-chann el aligned with the data on the tsdn/mtsda(mtsdb) pin. bit no. 7 6 5 4 3 2 1 0 bit name reserved tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved edge boff2 boff1 boff0 type r/w r/w r/w r/w default 000 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 147 march 22, 2004 t1/j1 rbif option register (046h, 146h, 246h, 346h) fbitgap: this bit is valid in receive clock master mode. = 0: the f-bit is not gapped. = 1: the f-bit is gapped (no cl ock signal during the f-bit). de: this bit selects the active edge of rsckn to update the data on rsdn and rsign and the active edge of mrsck to update the data on mrsda (mrsdb) and mrsiga (mrsigb). = 0: the falling edge is selected. = 1: the rising edge is selected. in receive multiplexed mode, the bit of the four links should be set to the same value. fe: this bit selects the active edge of rsckn to update/sample the pulse on rsfsn and the active edge of mrsck to sample the pulse on mrsfs. = 0: the falling edge is selected. = 1: the rising edge is selected. in receive multiplexed mode, the bit of the four links should be set to the same value. cms: this bit is valid in receive clock slave t1 /j1 mode e1 rate and receive multiplexed mode. = 0: the speed of the rsckn/mrsck is the same as t he data rate on the system side (2.048 mhz / 8.192 mhz). = 1: the speed of the rsckn/mrsck is double the dat a rate on the system side (4.096 mhz / 16.384 mhz). in receive clock slave t1/j1 mode e1 rate, if all four links use the rsck[1] and rsfs[1] to output the data (i.e., the rslvck b it (b, t1/j1- 010h) is set to ?1?), the bit of the four links should be set to the same value. in receive multiplexed mode, the bit of the four links should be set to the same value. tri: = 0: the processed data and signaling bits are output on the rsdn/m rsda(mrsdb) pins and the rsign/mr siga(mrsigb) pins respectiv ely. = 1: the output on the rsdn/mrsda(mrsdb) pins and the rsign/mrsiga(mrsigb) pins are in high impedance. bit no. 7 6 5 4 3 2 1 0 bit name reserved fbitgap de fe cms tri type r/w r/w r/w r/w r/w default 011 0 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 148 march 22, 2004 t1/j1 rbif mode (047h, 147h, 247h, 347h) map[1:0]: in receive clock slave mode and receive multiplexed mode, thes e 2 bits select the t1/j1 to e1 format mapping schemes. rmode: in receive non-multiplexed mode, this bit selects the sub-mode. = 0: the receive system interface is oper ated in receive clock master mode. the ti ming signal for clocking the data and the fra ming pulse to align the data output on the rsdn pin are received from each line side. = 1: the receive system interface is operated in receive cloc k slave mode. the timing signal fo r clocking the data and the fram ing pulse to align the data output on the rsdn pin are provided by the system side. bit no. 7 6 5 4 3 2 1 0 bit name reserved map1 map0 rmode type r/w r/w r/w default 001 map[1:0] t1/j1 to e1 format mapping schemes 0 0 * t1/j1 rate 0 1 t1/j1 mode e1 rate per g.802 1 0 t1/j1 mode e1 rate per one filler every four chs 1 1 t1/j1 mode e1 rate per continuous chs note: * these 2 bits can not be set to ?00? in the receive multiplexed mode.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 149 march 22, 2004 t1/j1 rbif frame pulse (048h, 148h, 248h, 348h) fsinv: = 0: the receive framing pulse rsfsn is active high. = 1: the receive framing pulse rsfsn is active low. in receive multiplexed mode, this bit of the four links should be set to the same value. cmfs, altifs: in receive clock master mode, these bits se lect what the pulse on rsfsn indicates. t he altifs bit is only valid in sf format. bit no. 7 6 5 4 3 2 1 0 bit name reserved fsinv reserved cmfs altfis type r/w r/w r/w default 000 format cmfs altifs rsfsn indication sf 0 0 the rsfsn pulses during each f-bit. 0 1 the rsfsn pulses during every second f-bit. 1 0 the rsfsn pulses during the first f-bit of every sf frame. 1 1 the rsfsn pulses during the first f-bit of every second sf frame. esf, t1dm, slc-96 0 x the rsfsn pulses during each f-bit. 1 x the rsfsn pulses during the first f-bit of every esf/t1 dm/slc-96 frame.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 150 march 22, 2004 t1/j1 rbif ts offset (049h, 149h, 249h, 349h) tsoff[6:0]: these bits give a binary number to define the channel offset. the channel offset is between the framing pulse on the rsfsn/mrsf s pin and the start of the corresponding frame output on the rsdn/mrsda(mrsdb) pin. the signaling bits on the rs ign/mrsiga(mrsigb) pin are al ways per- channel aligned with the data on the rsdn/mrsda(mrsdb) pin. in non-multiplexed mode, the channel offset can be configured from 0 to 23 channels (0 & 23 are included). in multiplexed mode, the channel off- set can be configured from 0 to 127 channels (0 & 127 are included). t1/j1 rbif bit offset (04ah, 14ah, 24ah, 34ah) edge: this bit is valid when the cms bit (b1, t1/j1-046h,...) is ?1?. = 0: the first active edge of rsckn/mrsck is selected to update the data on the rsdn/mrsda(mrsdb) and rsign/mrsiga(mrsigb) pins . = 1: the second active edge of rsckn/mrsck is selected to updat e the data on the rsdn/mrsda(mrsdb) and rsign/mrsiga(mrsigb) pins. boff[2:0]: these bits give a binary number to define the bit offset. the bi t offset is between the framing pulse on the rsfsn/mrsfs pin an d the start of the corresponding frame output on the rsdn/mrsda(m rsdb) pin. the signaling bits on the rsig n/mrsiga(mrsigb) pin are always per-chan nel aligned with the data on the rsdn/mrsda(mrsdb) pin. bit no. 7 6 5 4 3 2 1 0 bit name reserved tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved edge boff2 boff1 boff0 type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 151 march 22, 2004 t1/j1 rtsfs change indication (04bh, 14bh, 24bh, 34bh) rcofai: this bit is valid in receive clock slave mode and receive multiplexed mode. = 0: the interval of the pulses on the rsfs n/mrsfs pin is an integer multiple of 125 s. = 1: the interval of the pulses on the rsfsn/mr sfs pin is not an integer multiple of 125 s. this bit will be cleared if a ?1? is written to it. tcofai: this bit is valid in transmit clock slave mode and transmit multiplexed mode. = 0: the interval of the pulses on the tsfsn/mtsfs pin is an integer multiple of 125 s. = 1: the interval of the pulses on the tsfsn/mtsfs pin is not an integer multiple of 125 s. this bit will be cleared if a ?1? is written to it. t1/j1 rtsfs interrupt control (04ch, 14ch, 24ch, 34ch) rcofae: = 0: disable the interrupt on the int pin when the rcofai bit ( b1, t1/j1-04bh,...) is ?1?. = 1: enable the interrupt on the int pin when the rcofai bit ( b1, t1/j1-04bh,...) is ?1?. tcofae: = 0: disable the interrupt on the int pin when the tcofai bit ( b0, t1/j1-04bh,...) is ?1?. = 1: enable the interrupt on the int pin when the tcofai bit (b0, t1/j1-04bh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved rcofai tcofai type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved rcofae tcofae type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 152 march 22, 2004 t1/j1 frmr mode 0 (04dh, 14dh, 24dh, 34dh) unfm: = 0: the data stream is received in framed mode and is processed by the frame processor. = 1: the data stream is received in unfra med mode and the frame processor is bypassed. refcrce: in esf format: = 0: disable from re-searching for synchroni zation when the excessive crc-6 error occurs. = 1: search for synchronization again when the excessive crc-6 er ror occurs. this function can only be implemented only if the refen bit is logic 1. refen: = 0: ?locked in frame?. once the previous frame synchronization is acquired, no errors can lead to reframe except for manually setting by the refr bit. = 1: search for synchronization again when it is out of synchronization. refr: a transition from logic 0 to l ogic 1 forces to re-search for a new sf, esf, t1 dm frame. bit no. 7 6 5 4 3 2 1 0 bit name reserved unfm refcrce refen refr type r/w r/w r/w r/w default 0110
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 153 march 22, 2004 t1/j1 frmr mode 1 (04eh, 14eh, 24eh, 34eh) ddsc: this bit selects the synchronizati on criteria of t1 dm format. = 0: if a correct dds pattern is received before the first f-bi t of a single correct frame ali gnment pattern and there is no mi mic pattern, the t1 dm synchronization is acquired. = 1: if a single correct frame alignment pattern is received, and twelve correct dds patterns before each f-bit of the correct frame alignment pattern are all detected, and there is no mimic pa ttern, the t1 dm synchronization is acquired. mimicc: this bit selects the synchronization cr iteria in sf format and esf format. in sf format: = 0: when two consecutive frame alignment patterns are received er ror free in the data stream, the sf is synchronized. in this case, the exist- ence of mimic patterns is ignored. = 1: when two consecutive frame alignment patterns are received error free in the data stream without mimic pattern, the sf is synchronized. in esf format: = 0: when a single correct frame alignment pattern and a single co rrect crc-6 are found in the same frame, the esf is synchroni zed. in this case, the existence of mimic patterns is ignored. = 1: when four consecutive frame alignment patterns are detect ed error free in the received data stream without mimic pattern, the esf is syn- chronized. m2o[2:1]: in sf format, these two bits define the threshold of the f bi t error numbers in n-bit sliding f bits window. exceeding the thre shold will lead to out of synchronization. in esf format, these two bits define the th reshold of the frame alignment bit error numbers in n-bit sliding frame alignment bi ts window. exceeding the threshold will l ead to out of synchronization. in t1 dm format, these two bits define the threshold of the 7- bit pattern error numbers in n-pa ttern sliding 7-bit patterns win dow. the 7-bit pattern consists of the 6-bit dds pattern and its following f-bit. exceeding the threshol d will lead to out of synchronization. in slc-96 format, these two bits define the threshold of the ft bit error numbers in n-bit sliding ft bits window or the fs bit error numbers in n-bit sliding fs bits in frame (2n) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 154 march 22, 2004 t1/j1 frmr status (04fh, 14fh, 24fh, 34fh) oofv: = 0: the sf/esf/t1 dm/slc-96 frame is in synchronization. = 1: the frame is out of synchronization. t1/j1 frmr interrupt control 0 (050h, 150h, 250h, 350h) oofe: = 0: disable the interrupt on the int pin when the oofi bit ( b0, t1/j1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the oofi bit (b0, t1/j1-052h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved oofv type r default 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved oofe type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 155 march 22, 2004 t1/j1 frmr interrupt control 1 (051h, 151h, 251h, 351h) rmfbe: = 0: disable the interrupt on the int pin when the rmfbi bit (b4, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the rmfbi bit (b4, t1/j1-053h,...) is ?1?. sfee: = 0: disable the interrupt on the int pin when the sfei bit (b3, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the sfei bit (b3, t1/j1-053h,...) is ?1?. beee: = 0: disable the interrupt on the int pin when the beei bit (b2, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the beei bit (b2, t1/j1-053h,...) is ?1?. fere: = 0: disable the interrupt on the int pin when the feri bit (b1, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the feri bit ( b1, t1/j1-053h,...) is ?1?. cofae: = 0: disable the interrupt on the int pin when the cofai bit (b0, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the cofai bit (b0, t1/j1-053h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved rmfbe sfee beee fere cofae type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 156 march 22, 2004 t1/j1 frmr interrupt indication 0 (052h, 152h, 252h, 352h) excrceri: in esf format, once the accumulated crc-6 errors exceed 319 (>319) in a 1 second fix ed window, an excessive crc-6 error event i s generated = 0: no excessive crc-6 error event is detected. = 1: the excessive crc-6 error event is detected. this bit will be cleared if a ?1? is written to it. mimici: this bit is valid in sf and esf formats. = 0: no mimic pattern is detected in the received data stream. = 1: mimic pattern is detected in the received data stream. this bit will be cleared if a ?1? is written to it. oofi: = 0: there is no status change on the oofv bit (b0, t1/j1-04fh,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the oofv bit (b0, t1/j1-04fh,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved excrceri mimici reserved oofi type rr r default 00 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 157 march 22, 2004 t1/j1 frmr interrupt indication 1 (053h, 153h, 253h, 353h) rmfbi: = 0: the received bit is not the first bit of each sf/esf/t1 dm/slc-96 frame. = 1: the first bit of each sf/esf /t1 dm/slc-96 frame is received. this bit will be cleared if a ?1? is written to it. th is bit can not be updated during out of synchronization state. sfei: in sf format, each received ft bit is compared with the expected one (refer to table 12). each unmatched ft bit leads to an ft b it error event. when 2 or more ft bit errors are detected in a 6-basic -frame fixed window, the severely ft bit error occurs = 0: no severely ft bit error event is detected. = 1: the severely ft bit error event is detected. in esf format, when 2 or more frame alignm ent bit errors are detected in a 1-esf-frame fixed window, the severely frame alignme nt bit error occurs. = 0: no severely frame alignm ent bit error event is detected. = 1: the severely frame alignm ent bit error event is detected. in t1 dm format, each received ft bit is compared with the expec ted one (refer to table 14). each unmatched ft bit leads to an f t bit error event. when 2 or more ft bit errors are detected in a 6-basic -frame fixed window, the severely ft bit error occurs. = 0: no severely ft bit error event is detected. = 1: the severely ft bit error event is detected. this bit will be cleared if a ?1? is written to it. beei: in esf format, when the local calculated crc-6 of the current received esf frame does not match the received crc-6 of the next received esf frame, a single crc-6 error event is generated = 0: no crc-6 error event is detected. = 1: the crc-6 error event is detected. this bit will be cleared if a ?1? is written to it. feri: in sf format, each received f bit is com pared with the expected one (refer to table 12). each unmatched f bit leads to an f bit error event. = 0: no f bit error event is detected. = 1: the f bit error event is detected. in esf format, each received frame alignment bit is compared with the expected one (refer to t able 13). each unmatched bit leads to a frame alignment bit error event. = 0: no frame alignment bit error event is detected. = 1: the frame alignment bit error event is detected. in t1 dm format, each received f bit is compared with the expe cted one (refer to table 14). each unmatched f bit leads to an f b it error event = 0: no f bit error event is detected. = 1: the f bit error event is detected. in slc-96 format, the ft bit in each odd frame and the fs bit in frame (2n) (0 IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 158 march 22, 2004 cofai: = 0: the f bit position is not changed. = 1: the new-found f bit position differs from the previous one. this bit will be cleared if a ?1? is written to it. t1/j1 rdl0 (056h, 156h, 256h, 356h) c[8:1]: in slc-96 format, these bits together with the c[11:9] bits reflect the content in t he concentrator bits. the c[1] bit is the l sb. in de-bounce condition, these bits are updated if the received concentrator bits are t he same for 2 consecutive slc-96 frames; otherwise they are updated every slc-96 frame. they are held during out of slc-96 synchronization state. t1/j1 rdl1 (057h, 157h, 257h, 357h) m[3:1]: in slc-96 format, these bits reflect the content in the maintenance bits. the m[1] bit is the lsb. in de-bounce condition, these bits are updated if the received mainte nance bits are the same for 2 consecutive slc-96 frames; o therwise they are updated every slc-96 frame. they are held during out of slc-96 synchronization state. c[11:9]: in slc-96 format, these bits together with the c[8:1] bits reflect the content in t he concentrator bits. the c[11] bit is the m sb. in de-bounce condition, these bits are updated if the received concentrator bits are t he same for 2 consecutive slc-96 frames; otherwise they are updated every slc-96 frame. they are held during out of slc-96 synchronization state. bit no. 7 6 5 4 3 2 1 0 bit name c8 c7 c6 c5 c4 c3 c2 c1 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved m3 m2 m1 c11 c10 c9 type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 159 march 22, 2004 t1/j1 rdl2 (058h, 158h, 258h, 358h) s[4:1]: in slc-96 format, these bits reflect the content in the switch bits. the s[1] bit is the lsb. in de-bounce condition, these bits are updated if the received switch bits are the same for 2 consecutive slc-96 frames; otherw ise they are updated every slc-96 frame. they are held during out of slc-96 synchronization state. a[2:1]: in slc-96 format, these bits reflect the content in the alarm bits. the a[1] bit is the lsb. in de-bounce condition, these bits are updated if the received alarm bits are the same for 2 consecutive slc-96 frames; otherwi se they are updated every slc-96 frame. they are held during out of slc-96 synchronization state. bit no. 7 6 5 4 3 2 1 0 bit name reserved s4 s3 s2 s1 a2 a1 type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 160 march 22, 2004 t1/j1 dlb interrupt control (05ch, 15ch, 25ch, 35ch) scdeb: = 0: disable the de-bounce func tion of the overhead extraction. = 1: enable the de-dounce func tion of the overhead extraction. scae: = 0: disable the interrupt on the int pin when the scai bit (b3, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the scai bit (b3, t1/j1-05dh,...) is ?1?. scse: = 0: disable the interrupt on the int pin when the scsi bit (b2, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the scsi bit (b2, t1/j1-05dh,...) is ?1?. scme: = 0: disable the interrupt on the int pin when the scmi bit (b1, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the scmi bit (b1, t1/j1-05dh,...) is ?1?. scce: = 0: disable the interrupt on the int pin when the scci bit (b0, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the scci bit (b0, t1/j1-05dh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved scdeb scae scse scme scce type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 161 march 22, 2004 t1/j1 dlb interrupt indication (05dh, 15dh, 25dh, 35dh) scai: = 0: the value in the a[2:1] bits is not changed. = 1: the value in the a[2:1] bits is changed. scsi: = 0: the value in the s[4:1] bits is not changed. = 1: the value in the s[4:1] bits is changed. scmi: = 0: the value in the m[3:1] bits is not changed. = 1: the value in the m[3:1] bits is changed. scci: = 0: the value in the c[11:1] bits is not changed. = 1: the value in the c[11:1] bits is changed. bit no. 7 6 5 4 3 2 1 0 bit name reserved scai scsi scmi scci type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 162 march 22, 2004 t1/j1 mode (062h, 162h, 262h, 362h) fdlbyp: in esf format, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. = 0: enable the dl bit position to be replaced by the bit-ori ented code, the automatic perform ance report message, the hdlc dat a or the idle code (?ffff? for t1 / ?ff7e? for j1). = 1: disable the dl bit position to be replaced by the above codes. in t1 dm format, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. = 0: the ?d? bit in bit 6 of each chann el 24 is replaced with the hdlc data. = 1: disable the d bit position to be replaced by the hdlc data. in slc-96 format, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. = 0: the concentrator (c) bit, the maintenance (m) bit, the alar m (a) bit and the switch (s) bit are replaced by the contents i n the c[11:1] bits (b2~0, t1/j1-066h,... & b7~0, t1/j1-065h,...), the m[3:1] bits ( b5~3, t1/j1-066h,...), the a[2:1] bits (b1~0, t1/j1-067h,...) a nd the s[4:1] bits (b5~2, t1/j1-067h,...) respectively. = 1: disable the concentrator (c) bit, the maintenance (m) bit, the alarm (a) bi t and the switch (s) bit replacement. crcbyp: this bit is valid in esf format when the fdis bit (b0, t1/j1-062h,...) is ?0?. = 0: the calculated 6-bit crc of the previ ous esf frame is inserted in the current cr c-bit positions in every 4th frame startin g with frame 2 of the current esf frame. = 1: disable the crc-6 insertion. fdis: = 0: enable the generation of the sf / esf / t1 dm / slc-96 frame. = 1: disable the generation of the sf / esf / t1 dm / slc-96 frame. bit no. 7 6 5 4 3 2 1 0 bit name reserved fdlbyp crcbyp fdis type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 163 march 22, 2004 t1/j1 xdl0 (065h, 165h, 265h, 365h) c[8:1]: these bits, together with the c[11:9] bits (b2~0, t1/j1-066h,...), are valid in slc-96 format when the fdis bit (b0, t1/j1-062h ,...) and the fdl- byp bit (b2, t1/j1-062h,...) are both ?0?s. they contain the data to replace the concentrator (c) bit. the c[1] is the lsb and it is transmitted first. t1/j1 xdl1 (066h, 166h, 266h, 366h) m[3:1]: these bits are valid in slc-96 format when the fdis bit ( b0, t1/j1-062h,...) and the fdlbyp bit (b2, t1/j1-062h,...) are both ? 0?s. they contain the data to replace the maintenance (m ) bit. the m[1] is transmitted first. c[11:9]: these bits, together with the c[8:1] bits (b7~1, t1/j1-065h,...), are valid in slc-96 format when the fdis bit (b0, t1/j1-062h, ...) and the fdl- byp bit (b2, t1/j1-062h,...) are both ?0?s. they contain the data to replace the concentrator (c) bit. the c[11] is the msb and it is transmitted last. bit no. 7 6 5 4 3 2 1 0 bit name c8 c7 c6 c5 c4 c3 c2 c1 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved m3 m2 m1 c11 c10 c9 type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 164 march 22, 2004 t1/j1 xdl2 (067h, 167h, 267h, 367h) s[4:1]: these bits are valid in slc-96 format when the fdis bit ( b0, t1/j1-062h,...) and the fdlbyp bit (b2, t1/j1-062h,...) are both ? 0?s. they contain the data to replace the switch (s) bit. the s[1] is transmitted first. a[2:1]: these bits are valid in slc-96 format when the fdis bit ( b0, t1/j1-062h,...) and the fdlbyp bit (b2, t1/j1-062h,...) are both ? 0?s. they contain the data to replace the alarm (a) bit. the a[1] is transmitted first. t1/j1 fgen maintenance 0 (06bh, 16bh, 26bh, 36bh) autoyellow: = 0: disable the automatic yellow alarm signal insertion. = 1: the yellow alarm signal is automatical ly inserted into the data stream to be tr ansmitted when red alarm is declared in the received data stream. xyel: = 0: disable the manual yell ow alarm signal insertion. = 1: the yellow alarm signal is manually in serted into the data stream to be transmitted. bit no. 7 6 5 4 3 2 1 0 bit name reserved s4 s3 s2 s1 a2 a1 type rr r r r r default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved autoyellow xyel type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 165 march 22, 2004 t1/j1 fgen maintenance 1 (06ch, 16ch, 26ch, 36ch) mimicen: this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. = 0: disable the mimic pattern insertion. = 1: the mimic pattern is inserted into the bit right after each f-bit. the content of the mimic pattern is the same as the f-b it. cofaen: any transition (from ?0? to ?1? or from ?1? to ?0?) on this bit will lead to one bit deletion or one bit repetition in the data stream to be transmitted, that is, to change the frame alignment position. t he one bit deletion or repetition occurs randomly. txdis: = 0: normal operation. = 1: the data stream to be transmitt ed are overwritten with all ?zero?s. tais: = 0: normal operation. = 1: the data stream to be transmitt ed are overwritten with all ?one?s. bit no. 7 6 5 4 3 2 1 0 bit name reserved mimicen cofaen txdis tais type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 166 march 22, 2004 t1/j1 fgen interrupt control (06dh, 16dh, 26dh, 36dh) mfe: = 0: disable the interrupt on the int pin when the mfi bit (b1, t1/j1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the mfi bit (b1, t1/j1-06eh,...) is ?1?. bfe: = 0: disable the interrupt on the int pin when the bfi bit (b0, t1/j1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the bfi bit (b0, t1/j1-06eh,...) is ?1?. t1/j1 fgen interrupt indication (06eh, 16eh, 26eh, 36eh) mfi: = 0: the bit input to the frame generator is not t he first bit of each sf/esf/t1 dm/slc-96 multiframe. = 1: the first bit of each sf/esf/t1 dm/slc-96 multiframe is input to the frame generator. this bit will be cleared if a ?1? is written to it. bfi: = 0: the bit input to the frame generator is not the first bit of each basic frame. = 1: the first bit of each basic fram e is input to the frame generator. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved mfe bfe type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved mfi bfi type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 167 march 22, 2004 t1/j1 error insertion (06fh, 16fh, 26fh, 36fh) ddsinv: this bit is valid in t1 dm format w hen the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bit wil invert one 6-bit dds pattern. this bit is cleared when the inversion is completed. crcinv: this bit is valid in esf format when the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bi t will invert one 6-bit crc pattern. this bit is cleared when the invertion is completed. fsinv: in sf, t1 dm formats, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bit will invert one fs bit (the f-bit in even frame). in esf format, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bi t will invert one frame alignment bit. in slc-96 format, this bit is valid when the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bit will invert one synchronization fs bit. this bit is cleared when the inversion is completed. ftinv: in sf, t1 dm, slc-96 formats, this bit is va lid when the fdis bit (b0, t1/j1-062h,...) is ?0?. a transition from ?0? to ?1? on this bit will invert one ft bit (the f-bit in odd frame). this bit is cleared when the inversion is completed. bit no. 7 6 5 4 3 2 1 0 bit name reserved ddsinv crcinv fsinv ftinv type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 168 march 22, 2004 t1/j1 transmit timing option (070h, 170h, 270h, 370h) xts: in transmit clock master mode: = 0: the source of the transmit clock is selected from t he clock generated by the internal clock generator (1.544 mhz). = 1: the source of the transmit clock is select ed from the recovered clock from the line side. in transmit clock master mode, the trans mit buffer is bypassed automatically. in transmit clock slave t1/j1 mode e1 rate, this bit is invalid . in the other transmit clock slave modes and in transmit multip lexed mode: = 0: the source of the transmit clock is selected from t he clock from the backplane. t he transmit buffer is bypassed. = 1: the source of the transmit clock is selected from the clock generated by the inter nal clock generator (1.544 mhz). the tra nsmit buffer is not bypassed. t1/j1 prgd control (071h, 171h, 271h, 371h) rinv: = 0: the data is not inverted before extracted to the pattern detector. = 1: the data is inverted before extracted to the pattern detector. tinv: = 0: the generated pattern is not inverted. = 1: the generated pattern is inverted. pats[1:0]: these bits select the prbs generated and detected pattern. = 00: the 2 15 -1 pattern per o.152 is selected. = 01: the 2 20 -1 pattern per o.150-4.5 is selected. = 10: the 2 11 -1 pattern per o.150 is selected. = 11: reserved. bit no. 7 6 5 4 3 2 1 0 bit name reserved xts type r/w default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved rinv tinv pats1 pats0 type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 169 march 22, 2004 t1/j1 prgd status/error control (072h, 172h, 272h, 372h) bere: = 0: disable the interrupt on the int pin when the beri bit (b3, t1/j1-073h,...) is ?1?. = 1: enable the interrupt on the int pin when the beri bit (b3, t1/j1-073h,...) is ?1?. inv: = 0: no bit error is inserted to the generated pattern. = 1: a single bit error is inserted to the generated pattern. this bit is cleared after the single bit error insertion is completed. syncv: = 0: the pattern is out of synchronization (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window). = 1: the pattern is in synchronization (the pattern detector has detected at leas t 48 consecutive erro r-free bit periods). synce: = 0: disable the interrupt on the int pin when the synci bit (b0, t1/j1-073h,...) is ?1?. = 1: enable the interrupt on the int pin when the synci bit (b0, t1/j1-073h,...) is ?1?. t1/j1 prgd interrupt indication (073h, 173h, 273h, 373h) beri: = 0: no bit is mismatched with the prgd pattern when the extracted data is in synchronization state. = 1: at least one bit is mismatched with the prgd patte rn when the extracted data is in synchronization state. this bit will be cleared if a ?1? is written to it. synci: = 0: there is no status change on the syncv bit (b1, t1/j1-072h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the syncv bit (b1, t1/j1-072h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved bere inv syncv synce type r/w r/w r r/w default 0000 bit no. 7 6 5 4 3 2 1 0 bit name reserved beri reserved synci type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 170 march 22, 2004 t1/j1 xibc control (074h, 174h, 274h, 374h) ibcden: = 0: disable transmitti ng the inband loopback code. = 1: enable transmitting the inband loopback code. ibcdunfm: = 0: the inband loopback code is transmitted in framed mode, that is, the bits in all 24 channels are overwritten with the inba nd loopback code and the f-bit is not changed. = 1: the inband loopback code is transmitted in unframed mode, that is, all the bits in 24 channel s and the f-bit are overwritt en with the inband loopback code. cl[1:0]: these 2 bits define the length of the inband loopback code to be transmitted, meanwhile, they define the valid code in the ibc[ 7:0] bits (b7~0, t1/ j1-075h,...). t1/j1 xibc code (075h, 175h, 275h, 375h) ibc[7:0]: the ibc[7:x] bits define the content of the inband loopback code. the ?x? is one of 0 to 3 which depends on the length defined by the cl[1:0] bits (b1~0, t1/j1-074h,...). the ibc[7] is the msb. bit no. 7 6 5 4 3 2 1 0 bit name reserved ibcden ibcdunfm cl1 cl0 type r/w r/w r/w r/w default 0000 cl[1:0] loopback code length & valid code in the ibc[7:0] 0 0 5-bit length & the code in the ibc[7:3] is valid 0 1 6-bit length & the code in the ibc[7:2] is valid 1 0 7-bit length & the code in the ibc[7:1] is valid 1 1 8-bit length & the code in the ibc[7:0] is valid bit no. 7 6 5 4 3 2 1 0 bit name ibc7 ibc6 ibc5 ibc4 ibc3 ibc2 ibc1 ibc0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 171 march 22, 2004 t1/j1 ibcd detector configuration (076h, 176h, 276h, 376h) ibcdidle: = 0: the f-bit is compared with the tar get activate/deactivate inband loopback code, but the result of the f-bit comparison is discarded. = 1: the f-bit is skipped in the comparison process. dsel[1:0]: these two bits define the length of the target deactivate i nband loopback code, meanwhile, they define the valid code in the da ct[7:0] bits (b7~0, t1/j1-079h,...). asel[1:0]: these two bits define the length of the ta rget activate inband loopback code, meanwhile , they define the valid code in the act[ 7:0] bits (b7~0, t1/ j1-078h,...). bit no. 7 6 5 4 3 2 1 0 bit name reserved ibcdidle dsel1 dsel0 asel1 asel0 type r/w r/w r/w r/w r/w default 00100 dsel[1:0] deactivate code length & valid code in the dact[7:0] 0 0 5-bit length & the code in the dact[7:3] is valid 0 1 6-bit or 3-bit length & the code in the dact[7:2] is valid 1 0 7-bit length & the code in the dact[7:1] is valid 1 1 8-bit or 4-bit length & the code in the dact[7:0] is valid asel[1:0] activate code length & valid code in the act[7:0] 0 0 5-bit length & the code in the act[7:3] is valid 0 1 6-bit or 3-bit length & the code in the act[7:2] is valid 1 0 7-bit length & the code in the act[7:1] is valid 1 1 8-bit or 4-bit length & the code in the act[7:0] is valid
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 172 march 22, 2004 t1/j1 ibcd detector status (077h, 177h, 277h, 377h) lba: = 0: the activate code is loss. that is, more than 600 bits are not matched with the target activate inband loopback code in a 39.8ms fixed period. = 1: the activate code is detected. that is, in more than 126 consecutive 39.8ms fix ed periods, the target activate inband loop back code is matched with less than 600 bit errors in each 39.8ms. lbd: = 0: the deactivate code is loss. that is, more than 600 bits are not matched with the target deactivate inband loopback code i n a 39.8ms fixed period. = 1: the deactivate code is detected. that is, in more than 126 consecutive 39.8ms fixed periods , the target deactivate inband loopback code is matched with less than 600 bit errors in each 39.8ms. t1/j1 ibcd activate code (078h, 178h, 278h, 378h) act[7:0]: the act[7:x] bits define the content of the target activate inband loopback code. the ?x? is 3, 2, 1 or 0 which depends on the definition by the asel[1:0] bits (b1~0, t1/j1-076h,...). the unus ed bits should be ignored. the act[7] bit is the msb and compares with the first received code bit. t1/j1 ibcd deactivate code (079h, 179h, 279h, 379h) dact[7:0]: the dact[7:x] bits define the content of the target deactivate inband loopback code. the ?x? is 3, 2, 1 or 0 which depends on t he definition by the dsel[1:0] bits (b3~2, t1/j1-076h,...). the unused bits should be i gnored. the dact[7] bit is the msb and compares with the firs t received code bit. bit no. 7 6 5 4 3 2 1 0 bit name reserved lba lbd type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name act7 act6 act5 act4 act3 act2 act1 act0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 1 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dact7 dact6 dact5 dact4 dact3 dact2 dact1 dact0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 1 0 0 1 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 173 march 22, 2004 t1/j1 ibcd interrupt control (07ah, 17ah, 27ah, 37ah) lbae: = 0: disable the interrupt on the int pin when the lbai bit (b1, t1/j1-07bh,...) is ?1?. = 1: enable the interrupt on the int pin when the lbai bit (b1, t1/j1-07bh,...) is ?1?. lbde: = 0: disable the interrupt on the int pin when the lbdi bit (b0, t1/j1-07bh,...) is ?1?. = 1: enable the interrupt on the int pin when the lbdi bit ( b0, t1/j1-07bh,...) is ?1?. t1/j1 ibcd interrupt indication (07bh, 17bh, 27bh, 37bh) lbai: = 0: there is no status change on the lba bit (b1, t1/j1-077h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the lba bit (b1, t1/j1-077h,...). this bit will be cleared if a ?1? is written to it. lbdi: = 0: there is no status change on the lbd bit (b0, t1/j1-077h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the lbd bit (b0, t1/j1-077h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved lbae lbde type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved lbai lbdi type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 174 march 22, 2004 t1/j1 elst configuration (07ch, 17ch, 27ch, 37ch) trken: in receive clock slave mode and receive multiplexed mode, if it is out of synchronization, the trunk code programmed in the trk code[7:0] bits (b7~0, t1/j1-07eh,...) can be set to replace the data or not. = 0: disable the replacement. = 1: enable the replacement. slipd: this bit makes sense only when the sl ipi bit (b0, t1/j1-07dh,...) is ?1?. = 0: the latest slip is due to the elastic store buffer being empty. = 1: the latest slip is due to the elastic store buffer being full. slipe: = 0: disable the interrupt on the int pin when the slipi bit (b0, t1/j1-07dh,...) is ?1?. = 1: enable the interrupt on the int pin when the slipi bit (b0, t1/j1-07dh,...) is ?1?. t1/j1 elst interrupt indication (07dh, 17dh, 27dh, 37dh) slipi: = 0: no slip occurs. = 1: a slip occurs. this bit will be cleared if a ?1? is written to it. t1/j1 elst trunk code (07eh, 17eh, 27eh, 37eh) trkcode[7:0]: in receive clock slave mode and receive multiplexed mode, if it is out of synchronization and the trken bit (b2, t1/j1-07ch,... ) is ?1?, these bits are the trunk code to replace the received data stream. bit no. 7 6 5 4 3 2 1 0 bit name reserved trken slipd slipe type r/w r r/w default 000 bit no. 7 6 5 4 3 2 1 0 bit name reserved slipi type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name trkcode7 trkcode6 trkcode5 trkcode4 trkcode3 trkcode2 trkcode1 trkcode0 type r/w r/w r/w r/w r/w r/w r/w r/w default 11 1 1 1 1 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 175 march 22, 2004 t1/j1 aprm control (07fh, 17fh, 27fh, 37fh) lbbit: this bit is valid in esf format when the autoprm bit (b0, t1/j 1-07fh,...) is ?1?. the value in this bit will be transmitted in the lb bit position of the aprm. u2bit: this bit is valid in esf format when the autoprm bit (b0, t1/j1-07fh,...) is ?1?. t he value in this bit will be transmitted in the u2 bit position of the aprm. u1bit: this bit is valid in esf format when the autoprm bit (b0, t1/j1-07fh,...) is ?1?. t he value in this bit will be transmitted in the u1 bit position of the aprm. rbit: this bit is valid in esf format when the autoprm bit (b0, t1/j 1-07fh,...) is ?1?. the value in this bit will be transmitted in the r bit position of the aprm. crbit: this bit is valid in esf format when the autoprm bit (b0, t1/j 1-07fh,...) is ?1?. the value in this bit will be transmitted in the cr bit position of the aprm. autoprm: this bit is only valid in esf format. = 0: disable the aprm transmission. = 1: the automatic performance report message (aprm) is gener ated every one second and transmi tted on the dl bit positions. bit no. 7 6 5 4 3 2 1 0 bit name reserved lbbit u2bit u1bit rbit crbit autoprm type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 176 march 22, 2004 t1/j1 xboc code (080h, 180h, 280h, 380h) xboc[5:0]: these bits are only valid in the esf format. when the xboc[5:0] bits are written with any 6-bit code other than the ? 111111?, the c ode will be transmitted as the bit oriented message (bom). the bom pattern is ?111111110xboc[0]xboc[1]xboc[2]xboc[3]xboc[4]xboc[5]0? which occupies the dl of the f-bit position. t1/j1 boc control (081h, 181h, 281h, 381h) avc: this bit selects the validation criteria used to declare the bit oriented message (bom) in the received data stream. it is only valid in esf format. = 0: the bom is declared when the pattern is matched and the re ceived message is identical 8 out of 10 consecutive times and di ffers from the previous message. = 1: the bom is declared when the pattern is matched and the rece ived message is identical 4 out of 5 consecutive times and dif fers from the previous message. boce: = 0: disable the interrupt on the int pin when the boci bit ( b0, t1/j1-082h,...) is ?1?. = 1: enable the interrupt on the int pin when the boci bit (b0, t1/j1-082h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved xboc5 xboc4 xboc3 xboc2 xboc1 xboc0 type r/w r/w r/w r/w r/w r/w default 11 1 1 1 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved avc boce type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 177 march 22, 2004 t1/j1 boc interrupt indication (082h, 182h, 282h, 382h) boci: = 0: the boc[5:0] bits (b5~ 0, t1/j1-083h,...) are not updated. = 1: the boc[5:0] bits ( b5~0, t1/j1-083h,...) are updated. this bit will be cleared if a ?1? is written to it. t1/j1 rboc code (083h, 183h, 283h, 383h) boc[5:0]: when the received bom is declared, the message is loaded into t hese bits. the boc[5] bit corresponds to the msb of the message. bit no. 7 6 5 4 3 2 1 0 bit name reserved boci type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved boc5 boc4 boc3 boc2 boc1 boc0 type rr r r r r default 11 1 1 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 178 march 22, 2004 t1/j1 thdlc enable control (084h, 184h, 284h, 384h) tdlen3: = 0: all the functions of the hdlc transmitter #3 is disabled. = 1: all the functions of t he hdlc transmitter #3 is enabled. tdlen2: = 0: all the functions of the hdlc transmitter #2 is disabled. = 1: all the functions of t he hdlc transmitter #2 is enabled. tdlen1: this bit is only valid in t1/j1 mode esf & t1 dm formats. = 0: all the functions of the hdlc transmitter #1 is disabled. = 1: all the functions of t he hdlc transmitter #1 is enabled. bit no. 7 6 5 4 3 2 1 0 bit name reserved tdlen3 tdlen2 tdlen1 type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 179 march 22, 2004 t1/j1 thdlc2 assignment (086h, 186h, 286h, 386h) t1/j1 thdlc3 assignment (087h, 187h, 287h, 387h) the function of the above two sets of registers are the same. however, they correspond to different thdlc. even: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. odd: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. ts[4:0]: these bits binary define one channel of even and/or odd frames to insert the data to. ?00000? corresponds to ch 1 and ?10111? c orresponds to ch 24. the value above ?10111? is meanl ess. these bits are invalid when t he even bit and the odd bit are both ?0?. bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 180 march 22, 2004 t1/j1 thdlc2 bit select (089h, 189h, 289h, 389h) t1/j1 thdlc3 bit select (08ah, 18ah, 28ah, 38ah) the function of the above two sets of registers are the same. however, they correspond to different thdlc. bitenn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned channel. these bits are invalid when the even bit and the odd bit are both logic 0. the biten[7] bit corresponds to the fi rst bit (msb) of the selected channel. bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 181 march 22, 2004 t1/j1 rhdlc enable control (08bh, 18bh, 28bh, 38bh) rdlen3: = 0: all the functions of the hdlc receiver #3 is disabled. = 1: all the functions of the hdlc receiver #3 is enabled. rdlen2: = 0: all the functions of the hdlc receiver #2 is disabled. = 1: all the functions of the hdlc receiver #2 is enabled. rdlen1: this bit is only valid in t1/j1 mode esf & t1 dm formats. = 0: all the functions of the hdlc receiver #1 is disabled. = 1: all the functions of the hdlc receiver #1 is enabled. bit no. 7 6 5 4 3 2 1 0 bit name reserved rdlen3 rdlen2 rdlen1 type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 182 march 22, 2004 t1/j1 rhdlc2 assignment (08dh, 18dh, 28dh, 38dh) t1/j1 rhdlc3 assignment (08eh, 18eh, 28eh, 38eh) the function of the above two sets of registers are the same. however, they correspond to different rhdlc. even: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. odd: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. ts[4:0]: these bits binary define one channel of even and/or odd frames to extract the data fr om. ?00000? corresponds to ch 1 and ?10111 ? corresponds to ch 24. the value above ?10111? is meanless. these bits are invalid when the even bit and the odd bit are both ?0?. bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 183 march 22, 2004 t1/j1 rhdlc2 bit select (090h, 190h, 290h, 390h) t1/j1 rhdlc3 bit select (091h, 191h, 291h, 391h) the function of the above two sets of registers are the same. however, they correspond to different rhdlc. bitenn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from t he corresponding bit of the assigned channel. these bits are invalid when the even bit and the odd bit are both logic 0. the biten[7] bit corresponds to the fi rst bit (msb) of the selected channel. bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 184 march 22, 2004 t1/j1 rhdlc1 control register (092h, 192h, 292h, 392h) t1/j1 rhdlc2 control register (093h, 193h, 293h, 393h) t1/j1 rhdlc3 control register (094h, 194h, 294h, 394h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. lssufil: this bit is valid when the ss7 packet is lssu. = 0: the current lssu is not compared with the previous one. = 1: the current lssu is compared with the previous one. the current lssu will be discar ded if it is the same with the previous lssu. fisufil: this bit is valid when the ss7 packet is fisu. = 0: the current fisu is not compared with the previous one. = 1: the current fisu is compared with the previous one. the current fisu will be discarded if it is the same with the previous fisu. adrm[1:0]: these two bits select the addres s comparison mode in hdlc mode. = 00: no address is compared. = 01: high byte address is compared. = 10: low byte address is compared. = 11: both high byte address and low byte address are compared. rhdlcm: = 0: hdlc mode is selected. = 1: ss7 mode is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 185 march 22, 2004 rrst: a transition from ?0? to ?1? on this bit resets the corresponding hdlc receiver. the reset will clear the fifo, the pack bit (b 0, t1/j1-095h,... / 096h,... / 097h,...) and the emp bit (b1, t1/j1-095h,... / 096h,... / 097h,...). t1/j1 rhdlc1 rf ifo access status (095h, 195h, 295h, 395h) t1/j1 rhdlc2 rf ifo access status (096h, 196h, 296h, 396h) t1/j1 rhdlc3 rf ifo access status (097h, 197h, 297h, 397h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. emp: = 0: all valid hdlc/ss7 blocks are pushed into the fifo. = 1: the fifo is empty, i.e., all the blocks are read from the fifo. the corresponding hdlc receiver reset will clear this bit. pack: = 0: the byte read from the fifo is not an overhead byte. = 1: the byte read from the fifo is an overhead byte. the corresponding hdlc receiver reset will clear this bit. bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10 bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10 bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 186 march 22, 2004 t1/j1 rhdlc1 data (098h, 198h, 298h, 398h) t1/j1 rhdlc2 data (099h, 199h, 299h, 399h) t1/j1 rhdlc3 data (09ah, 19ah, 29ah, 39ah) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. dat[7:0]: these bits represent the bytes read from t he fifo. the dat[0] bit corresponds to the first bit of the serial received data from the fifo. bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 187 march 22, 2004 t1/j1 rhdlc1 interrupt control (09bh, 19bh, 29bh, 39bh) t1/j1 rhdlc2 interrupt control (09ch, 19ch, 29ch, 39ch) t1/j1 rhdlc3 interrupt control (09dh, 19dh, 29dh, 39dh) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ovfle: = 0: disable the interrupt on the int pin when the ovfli bit (b1, t1/j1-09eh,... / 09fh,... / 0a0h,...) is ?1?. = 1: enable the interrupt on the int pin when the ovfli bit (b1, t1/j 1-09eh,... / 09fh,... / 0a0h,...) is ?1?. rmbee: = 0: disable the interrupt on the int pin when the rmbei bit (b0, t1/j 1-09eh,... / 09fh,... / 0a0h,...) is ?1?. = 1: enable the interrupt on the int pin when the rmbei bit (b0, t1/j 1-09eh,... / 09fh,... / 0a0h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 188 march 22, 2004 t1/j1 rhdlc1 interrupt indication (09eh, 19eh, 29eh, 39eh) t1/j1 rhdlc2 interrupt indication (09fh, 19fh, 29fh, 39fh) t1/j1 rhdlc3 interrupt indication (0a0h, 1a0h, 2a0h, 3a0h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ovfli: the overwritten condition will occur if data is still attempted to write into the fifo when the fifo has already been full (128 bytes). = 0: no overwriting occurs. = 1: the overwriting occurs. this bit will be cleared if a ?1? is written to it. rmbei: = 0: no block is pushed into the fifo. = 1: a block of the hdlc/ss7 packet is pushed into the fifo. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 189 march 22, 2004 t1/j1 rhdlc1 high address (0a1h, 1a1h, 2a1h, 3a1h) t1/j1 rhdlc2 high address (0a2h, 1a2h, 2a2h, 3a2h) t1/j1 rhdlc3 high address (0a3h, 1a3h, 2a3h, 3a3h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ha[7:0]: in hdlc mode, when high byte address comparison or both bytes address comparison is required, t he high byte address position (t he byte fol- lowing the opening flag) is compared with the va lue in these bits, or with ?0xfc? or ?0xfe?. the ha[1] bit (the ?c/r? bit posit ion) is excluded to compare. bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 190 march 22, 2004 t1/j1 rhdlc1 low address (0a4h, 1a4h, 2a4h, 3a4h) t1/j1 rhdlc2 low address (0a5h, 1a5h, 2a5h, 3a5h) t1/j1 rhdlc3 low address (0a6h, 1a6h, 2a6h, 3a6h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. la[7:0]: in hdlc mode, when low byte address compar ison is required, the high byte address pos ition (the byte following the opening flag ) is compared with the value in these bits. when both bytes address comparison is required, the low byte address position (the byte following the high byte address position) is compared with the value in these bits. bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 191 march 22, 2004 t1/j1 thdlc1 control (0a7h, 1a7h, 2a7h, 3a7h) t1/j1 thdlc2 control (0a8h, 1a8h, 2a8h, 3a8h) t1/j1 thdlc3 control (0a9h, 1a9h, 2a9h, 3a9h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. autofisu: this bit is valid in ss7 mode when there is no data in the fifo to be transmitted. = 0: normal operation. = 1: the 7e (hex) flags is transmitted n times (the ?n? is determined by the fl[1:0 ] bits (b5~4, t1/j1-0aah,... / 0abh,... / 0a ch,...)), then the fisu packet is transmitted with the bsn and fsn the same with the last transmitted packet. eom: a transition from ?0? to ?1? on this bit i ndicates an entire hdlc/ss7 packet is stored in the fifo and starts the packet transm ission. xrep: in ss7 mode, when the fifo is empty, if less than 16 bytes are written into the fifo, these by tes can be transmitted repeatedly with the opening flag, fcs and closing flag. this bit determines if this cyclic transmission can be implemented. = 0: disable the cyclic transmission. = 1: enable the cyclic transmission. abort: = 0: disable the manual abort sequence insertion. = 1: the abort sequence (?0 1111111?) is m anually inserted to the current hdlc/ss7 packet. this bit is self-cleared after the abortion. thdlcm: = 0: hdlc mode is selected. = 1: ss7 mode is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 192 march 22, 2004 trst: a transition from ?0? to ?1? on the this bit resets the corresponding hdlc transmitter. the reset will clear the fifo.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 193 march 22, 2004 t1/j1 tfifo1 threshold (0aah, 1aah, 2aah, 3aah) t1/j1 tfifo2 threshold (0abh, 1abh, 2abh, 3abh) t1/j1 tfifo3 threshold (0ach, 1ach, 2ach, 3ach) the function of the above three sets of registers are the same. however, they correspond to different thdlc. fl[1:0]: these bits are valid in ss7 mode when there is no data in the fifo to be transmitted and the autofisu bit (b5, t1/j1-0a7h,... / 0a8h,... / 0a9h,...) is ?1?. they define how many times the 7e (hex ) flags are transmitted before the fisu packet transmission. = 00: 8 flags = 01: 16 flags = 10: 32 flags = 11: 64 flags ll[1:0]: these 2 bits set the lower threshold of the fifo. if the fill level is below the lower threshold, an interrupt may be generated . = 00: 16 bytes = 01: 32 bytes = 10: 64 bytes = 11: 96 bytes hl[1:0]: these 2 bits set the upper threshold of the fifo. once the fill level exceeds the upper threshold, the data stored in the fifo will start to be trans- mitted. = 00: 16 bytes = 01: 32 bytes = 10: 64 bytes = 11: 128 bytes bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 194 march 22, 2004 t1/j1 thdlc1 data (0adh, 1adh, 2adh, 3adh) t1/j1 thdlc2 data (0aeh, 1aeh, 2aeh, 3aeh) t1/j1 thdlc3 data (0afh, 1afh, 2afh, 3afh) the function of the above three sets of registers are the same. however, they correspond to different thdlc. dat[7:0]: the bytes to be stored in the fifo. the dat[0] bit corresponds to the first bit of the serial data in the fifo to be transmitte d. bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 195 march 22, 2004 t1/j1 tfifo1 status (0b0h, 1b0h, 2b0h, 3b0h) t1/j1 tfifo2 status (0b1h, 1b1h, 2b1h, 3b1h) t1/j1 tfifo3 status (0b2h, 1b2h, 2b2h, 3b2h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. ful: = 0: the fifo is not full. = 1: the fifo is full of 128 bytes. emp: = 0: the fifo is not empty. = 1: the fifo is empty. rdy: = 0: the fill level of the fifo is not below the lower thres hold set by the ll[1:0] bits (b3~2, t1/j1-0aah,... / 0abh,... / 0ac h,...). = 1: the fill level of the fifo is below the lower threshol d set by the ll[1:0] bits (b3~2, t1/j1-0aah,... / 0abh,... / 0ach,.. .). bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011 bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011 bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 196 march 22, 2004 t1/j1 thdlc1 interrupt control (0b3h, 1b3h, 2b3h, 3b3h) t1/j1 thdlc2 interrupt control (0b4h, 1b4h, 2b4h, 3b4h) t1/j1 thdlc3 interrupt control (0b5h, 1b5h, 2b5h, 3b5h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. udrune: = 0: disable the interrupt on the int pin when the udruni bit (b1, t1/j 1-0b6h,... / 0b7h,... / 0b8h,...) is ?1?. = 1: enable the interrupt on the int pin when the udruni bit (b1, t1/j 1-0b6h,... / 0b7h,... / 0b8h,...) is ?1?. rdye: = 0: disable the interrupt on the int pin when the rdyi bit (b0, t1/j1- 0b6h,... / 0b7h,... / 0b8h,...) is ?1?. = 1: enable the interrupt on the int pin when the rdyi bit (b0, t1/j 1-0b6h,... / 0b7h,... / 0b8h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 197 march 22, 2004 t1/j1 thdlc1 interrupt indication (0b6h, 1b6h, 2b6h, 3b6h) t1/j1 thdlc2 interrupt indication (0b7h, 1b7h, 2b7h, 3b7h) t1/j1 thdlc3 interrupt indication (0b8h, 1b8h, 2b8h, 3b8h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. udruni: when the fifo is empty and the last transmitted byte is not t he end of the current hdlc/ss7 packet, the under-run occurs. this bit indicates whether the under-run occurs. = 0: no under-run occurs. = 1: under-run occurs. this bit will be cleared if a ?1? is written to it. rdyi: = 0: there is no status change on the rdy bit (b0, t1/j1-0b0h,... / 0b1h,... / 0b2h,...). = 1: there is a transition (from ?0? to ?1?) on the rdy bit (b0, t1/j1-0b0h,... / 0b1h,... / 0b2h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 198 march 22, 2004 t1/j1 alarm status (0b9h, 1b9h, 2b9h, 3b9h) ais: = 0: more than 60 zeros are detected in a 40ms fixed window and this status persists for mx40ms. he re ?m? is decided by the ais cth[7:0] bits (b7~0, t1/j1-0c1h,...). = 1: less than 61 zeros are detected in a 40ms fixed window and this status persists for nx40ms. here ?n? is decided by the ais dth[7:0] bits (b7~0, t1/j1-0c0h,...). yel: the yellow alarm is detected w hen the frame is synchronized. in t1 sf / slc-96 format: = 0: more than 76 ?one?s are detected on the bit 2 of each channel during a 40ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bi ts (b7~0, t1/j1-0bfh,...). = 1: less than 77 ?one?s are detected on the bit 2 of each channel during a 40ms fixed window and th is status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bi ts (b7~0, t1/j1-0beh,...). in t1 esf format: = 0: less than 8 ?0xff00? (msb first) are detected on the dl bi ts during a 40ms fixed window and this status persists for mx40m s. here ?m? is decided by the yelcth[7:0] bi ts (b7~0, t1/j1-0bfh,...). = 1: more than 7 ?0xff00? (msb first) are detected on the dl bi ts during a 40ms fixed window and this status persists for nx40m s. here ?n? is decided by the yeldth[7:0] bi ts (b7~0, t1/j1-0beh,...). in t1 dm format: = 0: more than 3 ?one?s are detected on the y bit (bit 6 in eac h ch 24) during a 40ms fixed window and this status persists for mx40ms. here ?m? is decided by the yelcth[7:0] bits (b7~0, t1/j1-0bfh,...). = 1: less than 4 ?one?s are detected on the y bit (bit 6 in each ch 24) during a 40ms fixed window and this status persists for nx40ms. here ?n? is decided by the yeldth[7:0] bits (b7~0, t1/j1-0beh,...). in j1 sf format: = 0: more than 3 zeros are detected on the f-bit of the 12nd fr ame during a 40ms fixed window and this status persists for mx40 ms. here ?m? is decided by the yelcth[7:0] bi ts (b7~0, t1/j1-0bfh,...). = 1: less than 4 zeros are detected on the f-bit of the 12nd fr ame during a 40ms fixed window and this status persists for nx40 ms. here ?n? is decided by the yeldth[7:0] bi ts (b7~0, t1/j1-0beh,...). in j1 esf format: = 0: more than 2 zeros are detected on the dl bits during a 40 ms fixed window and this status persists for mx40 ms. here ?m? i s decided by the yelcth[7:0] bits (b7~0, t1/j1-0bfh,...). = 1: less than 3 zeros are detected on the dl bits during a 40 ms fixed window and this status persists for nx40 ms. here ?n? i s decided by the yeldth[7:0] bits (b7~0, t1/j1-0beh,...). red: = 0: the in sf / esf / t1 dm / slc-96 synchronization status pe rsists for mx120ms. here ?m? is decided by the redcth[7:0] bits (b7~0, t1/j1- 0bdh,...). = 1: the out of sf / esf / t1 dm / slc-96 synchronization status persists for nx40ms. here ?n? is decided by the reddth[7:0] bi ts (b7~0, t1/ j1-0bch,...). bit no. 7 6 5 4 3 2 1 0 bit name reserved ais yel red type rrr default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 199 march 22, 2004 t1/j1 alarm control (0bah, 1bah, 2bah, 3bah) aise: = 0: disable the interrupt on the int pin when the aisi bit (b3, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the aisi bit (b3, t1/j1-05dh,...) is ?1?. yele: = 0: disable the interrupt on the int pin when the yeli bit (b3, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the yeli bit (b3, t1/j1-05dh,...) is ?1?. rede: = 0: disable the interrupt on the int pin when the redi bit (b3, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the redi bit (b3, t1/j1-05dh,...) is ?1?. t1/j1 alarm indication (0bbh, 1bbh, 2bbh, 3bbh) aisi: = 0: there is no status change on the ais bit (b1, t1/j1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the ais bit (b1, t1/j1-04fh,...). this bit will be cleared if a ?1? is written to it. yeli: = 0: there is no status change on the yel bit (b1, t1/j1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the yel bit (b1, t1/j1-04fh,...). this bit will be cleared if a ?1? is written to it. redi: = 0: there is no status change on the red bit (b1, t1/j1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the red bit (b1, t1/j1-04fh,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved aise yele rede type r/w r/w r/w default 000 bit no. 7 6 5 4 3 2 1 0 bit name reserved aisi yeli redi type rrr default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 200 march 22, 2004 t1/j1 red declare threshold (0bch, 1bch, 2bch, 3bch) reddth[7:0]: the red alarm is declared when the out of sf/esf/t1 dm/slc-96 synchroni zation status persists for nx40ms. the value of the ?n? is decided by these bits. t1/j1 red clear threshold (0bdh, 1bdh, 2bdh, 3bdh) redcth[7:0]: the red alarm is cleared when the in sf/esf/t 1 dm/slc-96 synchronization status persist s for mx120ms. the value of the ?m? is d ecided by these bits. bit no. 7 6 5 4 3 2 1 0 bit name reddth7 reddth6 reddth5 reddth4 reddth3 reddth2 reddth1 reddth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 1 1 1 1 1 1 bit no. 7 6 5 4 3 2 1 0 bit name redcth7 redcth6 redcth5 redcth4 redcth3 redcth2 redcth1 redcth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 01 1 1 1 1 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 201 march 22, 2004 t1/j1 yellow declare threshold (0beh, 1beh, 2beh, 3beh) yeldth[7:0]: in t1 sf/slc-96 format, the yellow alarm is declared when le ss than 77 ?one?s are detected on the bit 2 of each channel during a 40ms fixed window and this status persists for nx40ms; in t1 esf format, t he yellow alarm is declared when more than 7 ?0xff00? (msb first ) are detected on the sliding dl bits during a 40ms fix ed window and this status persists for nx40ms; in t1 dm format, the yellow alarm is declared w hen less than 77 ?one?s are detected on the y bit (bit 6 in each ch 24) during a 40m s fixed window and this status persists for nx40ms; in j1 sf format, the yellow alarm is declared when less than 4 ?one?s are detected on the f- bit of the 12nd frame during a 40m s fixed window and this statu s persists for nx40ms; in j1 esf format, the yellow alarm is declared when less than 3 zeros are detected on the dl bits during a 40ms fixed window an d this status persists for nx40ms. the value of the ?n? are all decided by these bits. t1/j1 yellow clear threshold (0bfh, 1bfh, 2bfh, 3bfh) yelcth[7:0]: in t1 sf/slc-96 format, the yellow alar m is cleared when more than 76 ?one?s are det ected on the bit 2 of each channel during a 40ms fixed window and this status persists for mx40ms; in t1 esf format, t he yellow alarm is cleared when le ss than 8 ?0xff00? (msb first) are detected on the sliding dl bits during a 40ms fi xed window and this status persists for mx40ms; in t1 dm format, the yellow alarm is cleared wh en more than 76 ?one?s are detected on the y bit (bit 6 in each ch 24) during a 40ms fixed window and this status persists for mx40ms; in j1 sf format, the yellow alarm is cleared when more than 3 ?one?s are detected on the f- bit of the 12nd frame during a 40ms fixed window and this status persists for mx40ms; in j1 esf format, the yellow alarm is cleared when more than 2 zeros are detected on the dl bits during a 40ms fixed window and this status persists for mx40ms. the value of the ?m ? are all decided by these bits. bit no. 7 6 5 4 3 2 1 0 bit name yeldth7 yeldth6 yeldth5 yeldth4 yeldth3 yeldth2 yeldth1 yeldth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 1 0 1 0 bit no. 7 6 5 4 3 2 1 0 bit name yelcth7 yelcth6 yelcth5 yelcth4 yelcth3 yelcth2 yelcth1 yelcth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 1 0 1 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 202 march 22, 2004 t1/j1 ais declare threshold (0c0h, 1c0h, 2c0h, 3c0h) aisdth[7:0]: the blue alarm is declared when less than 61 zeros are detected in a 40ms fixed window and this st atus persists for nx40ms. the value of the ?n? is decided by these bits. t1/j1 ais clear threshold (0c1h, 1c1h, 2c1h, 3c1h) aiscth[7:0]: the blue alarm is cleared when more than 60 zeros are detected in a 40ms fix ed window and this status persists for mx40ms. the value of the ?m? is decided by these bits. bit no. 7 6 5 4 3 2 1 0 bit name aisdth7 aisdth6 aisdth5 aisdth4 aisdth3 aisdth2 aisdth1 aisdth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 1 1 1 1 1 1 bit no. 7 6 5 4 3 2 1 0 bit name aiscth7 aiscth6 aiscth5 aiscth4 aiscth3 aiscth2 aiscth1 aiscth0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 1 1 1 1 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 203 march 22, 2004 t1/j1 pmon control (0c2h, 1c2h, 2c2h, 3c2h) updat: a transition from ?0? to ?1? on this bit updates all the pmon indirect registers. autoupd: = 0: disable the automatic update functi on of the pmon indirect registers. = 1: all the pmon indirect register s are updated every one second automatically. bit no. 7 6 5 4 3 2 1 0 bit name reserved updat autoupd type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 204 march 22, 2004 t1/j1 pmon interrupt control 0 (0c3h, 1c3h, 2c3h, 3c3h) prdgove: = 0: disable the interrupt on the int pin when the prdgovi bit ( b7, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the prdgovi bit (b7, t1/j1-0c5h,...) is ?1?. ddsove: = 0: disable the interrupt on the int pin when the ddsovi bit (b4, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the ddsovi bit (b4, t1/j1-0c5h,...) is ?1?. cofaove: = 0: disable the interrupt on the int pin when the cofaovi bit (b3, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the cofaovi bit (b3, t1/j1-0c5h,...) is ?1?. oofove: = 0: disable the interrupt on the int pin when the oofovi bit (b2, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the oofovi bit (b2, t1/j1-0c5h,...) is ?1?. ferove: = 0: disable the interrupt on the int pin when the ferovi bit (b1, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the ferovi bit (b1, t1/j1-0c5h,...) is ?1?. crcove: = 0: disable the interrupt on the int pin when the crcovi bit (b0, t1/j1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the crcovi bit (b0, t1/j1-0c5h,...) is ?1?. t1/j1 pmon interrupt control 1 (0c4h, 1c4h, 2c4h, 3c4h) lcvove: = 0: disable the interrupt on the int pin when the lcvovi bit (b0, t1/j1-0c6h,...) is ?1?. = 1: enable the interrupt on the int pin when the lcvovi bit ( b0, t1/j1-0c6h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name prdgove reserved ddsove cofaove oofove ferove crcove type r/w r/w r/w r/w r/w r/w default 000000 bit no. 7 6 5 4 3 2 1 0 bit name reserved lcvove type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 205 march 22, 2004 t1/j1 pmon interrupt indication 0 (0c5h, 1c5h, 2c5h, 3c5h) prdgovi: = 0: the pmon indirect prgd counter mapping registers have not overflowed. = 1: the pmon indirect prgd count er mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. ddsovi: = 0: the pmon indirect ddse counter mapping registers have not overflowed. = 1: the pmon indirect ddse counter mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. cofaovi: = 0: the pmon indirect cofa counter mapping register has not overflowed. = 1: the pmon indirect cofa count er mapping register has overflowed. this bit will be cleared if a ?1? is written to it. oofovi: = 0: the pmon indirect oof counter mapping register has not overflowed. = 1: the pmon indirect oof counter mapping register has overflowed. this bit will be cleared if a ?1? is written to it. ferovi: = 0: the pmon indirect fer counter mapping registers have not overflowed. = 1: the pmon indirect fer counter mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. crcovi: = 0: the pmon indirect crce counter mapping registers have not overflowed. = 1: the pmon indirect crce count er mapping register s have overflowed. this bit will be cleared if a ?1? is written to it. t1/j1 pmon interrupt indication 1 (0c6h, 1c6h, 2c6h, 3c6h) lcvovi: = 0: the pmon indirect lcv counter mapping registers have not overflowed. = 1: the pmon indirect lcv count er mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name prdgovi reserved ddsovi cofaovi oofo vi ferovi crcovi type rrrrrr default 000000 bit no. 7 6 5 4 3 2 1 0 bit name reserved lcvovi type r default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 206 march 22, 2004 t1/j1 tplc / rplc / prgd test configuration (0c7h, 1c7h, 2c7h, 3c7h) prbsmode[1:0]: these two bits select one mode to extract/repl ace the data for the prbs generator/detector. = 00: the unframed mode is selected. all 24 channels are extrac ted/replaced and the per-channel conf iguration in the test bit ( b6, t1/j1-id- 41~58h) is ignored. = 01: the 8-bit-based mode is selected. the received data wi ll only be extracted/replaced on th e channel configured by the test bit (b6, t1/j1- id-41~58h). = 10: the 7-bit-based mode is selected. the received data will onl y be extracted/replaced on the 7 msb of the channel configure d by the test bit (b6, t1/j1-id-41~58h). = 11: reserved. prbsdir: = 0: the pattern in the prbs generator/detector is generat ed in the transmit path and is detected in the receive path. = 1: the pattern in the prbs generator/detector is generated in the receive path and is detected in the transmit path. testen: a transition from ?0? to ?1? on this bi t initiates the prbs generator/detector. bit no. 7 6 5 4 3 2 1 0 bit name reserved prbsmode1 prbsmode0 prbsdir testen type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 207 march 22, 2004 t1/j1 tplc access status (0c8h, 1c8h, 2c8h, 3c8h) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. t1/j1 tplc access control (0c9h, 1c9h, 2c9h, 3c9h) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of the indire ct register (from 01h to 18h & from 21h to 38h & from 41h to 58h) for the microproc essor access. t1/j1 tplc access data (0cah, 1cah, 2cah, 3cah) d[7:0]: this register holds the value which will be read from or written into the indirect r egisters (from 01h to 18h & from 21h to 38h & from 41h to 58h). if data is to be written into the indirect register, this regi ster must be written before the ta rget indirect register?s addres s and rwn=0 is written into the tplc access control register. if data is to be read from the i ndirect register, the target indirect register?s address and rwn= 1 must be written into the tplc access control register first, then this register will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 208 march 22, 2004 t1/j1 tplc configuration (0cbh, 1cbh, 2cbh, 3cbh) sigsnap: this bit is valid in sf, esf or slc-96 format. = 0: disable the signaling snapshot. = 1: enable the signaling snapshot. that is, the signaling bits of the first frame are locked and input on the tsign/mtsiga(mts igb) pin as the signaling bits of the current whole sf, esf or slc-96 frame. gstrken: = 0: the replacement is performed on a per -channel basis by setting the strken bit ( b4, t1/j1-id-41~58h) in the corresponding c hannel. = 1: the signaling bits (abcd) of all c hannels are replaced by the signaling trunk c onditioning code in the a,b,c,d bits (b3~0, t1/j1-id-41~58h). zcs[2:0]: these bits select one type of zero code suppressi on. (bit 1 is the msb in the following table). gsubst[2:0]: these bits select the repl acement of all the channels. bit no. 7 6 5 4 3 2 1 0 bit name sigsnap gstrken zcs2 zcs1 zcs0 gsubst2 gsubst1 gsubst0 type r/w r/w r/w r/w r/w r/w r/w r/w default 10 0 0 0 0 0 0 zcs[2:0] zero code suppression 0 0 0 no zero code suppression. 0 0 1 gte zero code suppression. bit 8 of an all-zero channel is replaced by a ?1?, except in signaling frames where bit 7 is fo rced to be a ?1?. 0 1 0 jammed bit 8 zero code suppression. bit 8 of all channels are replaced by a ?1?. 0 1 1 bell zero code suppression. bit 7 of an all-zero channel is replaced by a ?1?. 1 0 0 dds zero code suppression. an all-zero channel is replaced with ?10011000?. others reserved. gsubst[2:0] replacement selection 0 0 0 the replacement is performed on a per-channel basis by setti ng the subst[2:0] bits (b7~5, t1/j1-id-01~18h) in the correspo nding channel. 0 0 1 the data of all channels is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, t1/j1-id-21~38h). 0 1 0 the data of all channels is replaced by the a-law digital milliwatt pattern. 0 1 1 the data of all channels is replaced by the -law digital milliwatt pattern. 1 0 0 the data of all channels is replaced by the payload loopback code extracted from the elastic store buffer in the receive p ath. others reserved.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 209 march 22, 2004 t1/j1 tplc control enable (0cch, 1cch, 2cch, 3cch) abxx: this bit is valid in esf & slc-96 format. = 0: the signaling bits are valid in the lower nibble of each channel. = 1: the signaling bits are valid in the upper 2-bit positions of the lower nibble of each channel. the other bits of the chann el are don?t care con- ditions. pcce: = 0: disable all the functions in the transmit payload control. = 1: enable all the functions in the transmit payload control. bit no. 7 6 5 4 3 2 1 0 bit name reserved abxx reserved pcce type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 210 march 22, 2004 t1/j1 rplc access status (0cdh, 1cdh, 2cdh, 3cdh) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. t1/j1 rplc access control (0ceh, 1ceh, 2ceh, 3ceh) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of the indire ct register (from 01h to 18h & from 21h to 38h & from 41h to 58h) for the microproc essor access. t1/j1 rplc access data (0cfh, 1cfh, 2cfh, 3cfh) d[7:0]: this register holds the value which will be read from or written into the indirect r egisters (from 01h to 18h & from 21h to 38h & from 41h to 58h). if data is to be written into the indirect register, this regi ster must be written before the ta rget indirect register?s addres s and rwn=0 is written into the rplc access control register. if data is to be read from the indirect register, the target indirect register?s address and rwn= 1 must be written into the rplc access control register first, then this register will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 211 march 22, 2004 t1/j1 rplc configuration (0d0h, 1d0h, 2d0h, 3d0h) sigsnap: this bit is valid when sf, esf or slc-96 frame is in synchronization. = 0: disable the signaling snapshot. = 1: enable the signaling snapshot. that is, the signaling bits of the first frame are locked and output on the rsign/mrsiga(mr sigb) pin as the signaling bits of the current whole sf, esf or slc-96 frame. gstrken: = 0: the replacement is performed on a per -channel basis by setting the strken bit ( b4, t1/j1-id-41~58h) in the corresponding c hannel. = 1: the signaling bits (abcd) of all c hannels are replaced by the signaling trunk c onditioning code in the a,b,c,d bits (b3~0, t1/j1-id-41~58h). gsubst[2:0]: these bits select the repl acement of all the channels. bit no. 7 6 5 4 3 2 1 0 bit name sigsnap gstrken reserved gsubst2 gsubst1 gsubst0 type r/w r/w r/w r/w r/w default 10 0 0 0 gsubst[2:0] replacement selection 000 the replacement is performed on a per-channel basis by setting the subst[2:0] bits (b7~5, t1/j1-id-01~18h) in the correspond ing channel. 001 the data of all channels is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, t1/j1-id-21~38h). 010 the data of all channels is replaced by the a-law digital milliwatt pattern. 011 the data of all channels is replaced by the -law digital milliwatt pattern. the others reserved.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 212 march 22, 2004 t1/j1 rplc control enable (0d1h, 1d1h, 2d1h, 3d1h) abxx: this bit is valid in esf & slc-96 format. = 0: the signaling bits are valid in the lower nibble of each channel. = 1: the signaling bits are valid in the upper 2-bit positions of the lower nibble of each channel. the other bits of the chann el are don?t care con- ditions. sigfix: this bit is only valid in the sf, esf and slc-96 formats. = 0: disable the signali ng bits fixing function. = 1: the signaling bits (abcd) are fixed to t he value set in the pol bit (b1, t1/j1-0d1h,...). pol: this bit is only valid when the sigfix bit is ?1?. = 0: the signaling bits (abc d) are fixed to logic 0. = 1: the signaling bits (abc d) are fixed to logic 1. pcce: = 0: disable all the functions in the receive payload control. = 1: enable all the functions in the receive payload control. bit no. 7 6 5 4 3 2 1 0 bit name reserved abxx sigfix pol pcce type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 213 march 22, 2004 t1/j1 rcrb configuration (0d2h, 1d2h, 2d2h, 3d2h) freeze: = 0: disable the manual signaling freezing. = 1: manually freeze the signaling data in the a,b,c,d bits (b3~0, t1/j1-id- 01~18h) as the previous valid value. deb: = 0: disable the signaling de-bounce. = 1: enable the signaling de-bounce. that is, the a,b,c,d bits (b3~0, t1/j1-id-01~18h) are updat ed only if 2 consecutive receiv ed ab/abcd codewords of the same channel are identical. sige: = 0: disable the interrupt on the int pin when any of the cosi bits (t1/j1-0d8 h,... & t1/j1-0d7h,... & t1/j1-0d6h,...) is ?1?. = 1: enable the interrupt on the int pin when any of the cosi bits (t1/j1-0d8 h,... & t1/j1-0d7h,... & t1 /j1-0d6h,...) is ?1?. sigf: this bit is valid only in the esf and slc-96 format. = 0: the extracted signaling bits are in 4 states signaling, i.e., the signaling bits on framer 6 & 18 of a signaling multi-fra me are recognized as ?a? and the signaling bits on framer 12 & 24 are re cognized as ?b?. only the signaling bits a & b are saved in the extracted signal ing data/extract enable register. the c & d bits in the extracted signali ng data/extract enable register are not cared. = 1: the extracted signaling bits are in 16 states signaling, i.e., four signaling bits a, b, c & d are all saved in the extrac ted signaling data/ extract enable register. bit no. 7 6 5 4 3 2 1 0 bit name reserved freeze deb sige sigf type r/w r/w r/w r/w default 0001
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 214 march 22, 2004 t1/j1 rcrb access status (0d3h, 1d3h, 2d3h, 3d3h) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. t1/j1 rcrb access control (0d4h, 1d4h, 2d4h, 3d4h) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of t he indirect register (from 01h to 18h) for the microprocessor access. t1/j1 rcrb access data (0d5h, 1d5h, 2d5h, 3d5h) d[7:0]: this register holds the value which will be read from or written into the indirect r egisters (from 01h to 18h). if data is to b e written into the indirect register, this register must be written before the target indirect register?s addres s and rwn=0 is written into the rcrb access control register. if data is to be read from the indirect register, the target indirect register?s address and rw n=1 must be written into the rcrb access control register first, then this register will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name d7 d6 d5 d4 d3 d2 d1 d1 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 215 march 22, 2004 t1/j1 rcrb state change indication 0 (0d6h, 1d6h, 2d6h, 3d6h) cosi[x]: = 0: the signaling bits in it s corresponding channel is not changed. = 1: the signaling bits in its corresponding channel is changed. the corresponding bit will be cleared if a ?1? is written to i t. the cosi[8:1] bits correspond to channel 8 ~ 1 respectively. t1/j1 rcrb state change indication 1 (0d7h, 1d7h, 2d7h, 3d7h) cosi[x]: = 0: the signaling bits in it s corresponding channel is not changed. = 1: the signaling bits in its corresponding channel is changed. the corresponding bit will be cleared if a ?1? is written to it. the cosi[16:9] bits correspond to channel 16 ~ 9 respectively. t1/j1 rcrb state change indication 2 (0d8h, 1d8h, 2d8h, 3d8h) cosi[x]: = 0: the signaling bits in it s corresponding channel is not changed. = 1: the signaling bits in its corresponding channel is changed. the corresponding bit will be cleared if a ?1? is written to i t. the cosi[24:17] bits corres pond to channel 24 ~ 17 respectivel y. bit no. 7 6 5 4 3 2 1 0 bit name cosi8 cosi7 cosi6 cosi5 cosi4 cosi3 cosi2 cosi1 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name cosi16 cosi15 cosi14 cosi13 cosi12 cosi11 cosi10 cosi9 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name cosi24 cosi23 cosi22 cosi21 cosi20 cosi19 cosi18 cosi17 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 216 march 22, 2004 5.2.1.2 indirect register pmon: the pmon counter mapping registers (00h ~ 0bh) of a link are updated as a group in the following three ways: 1. a transition from ?0? to ?1? on the updat bi t (b1, t1/j1-0c2h,...) updat es all the registers; 2. if the autoupd bit (b0, t1/j1-0c2h,...) is set to ?1?, the registers will be updated every one second; t1/j1 crce counter mapping 0 (00h) crce[7:0]: in esf format, these bits together with the crce[9:8] bits count the crc-6 error numbers. the crce[0] bit is the lsb. t1/j1 crce counter mapping 1 (01h) crce[9:8]: in esf format, these bits together with the crce[7:0] bits count the crc-6 error numbers. the crce[9] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name crce7 crce6 crce5 crce4 crce3 crce2 crce1 crce0 type rr r r r r r r r 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved crce9 crce8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 217 march 22, 2004 t1/j1 fer counter mapping 0 (02h) fer[7:0]: in sf / t1 dm / slc-96 format, these bits together with the fer[ 11:8] bits count the f bit error numbers. the fer[0] bit is the lsb. in esf format, these bits together with the fer[11:8] bits count the frame alignment bit error numbers. the fer[0] bit is the l sb. t1/j1 fer counter mapping 1 (03h) fer[11:8]: in sf / t1 dm / slc-96 format, these bits together with the fer[ 7:0] bits count the f bit error numbers. the fer[11] bit is the msb. in esf format, these bits together with t he fer[7:0] bits count the frame alignment bit error numbers. the fer[11] bit is the m sb. bit no. 7 6 5 4 3 2 1 0 bit name fer7 fer6 fer5 fer4 fer3 fer2 fer1 fer0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved fer11 fer10 fer9 fer8 type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 218 march 22, 2004 t1/j1 cofa counter mapping (04h) cofa[2:0]: these bits count the times of the new-found f bit pos ition being different from the previous one events. t1/j1 oof counter mapping (05h) oof[4:0]: in sf / esf / t1 dm / slc-96 format, these bits count the ti mes of out of sf / esf / t1 dm / slc-96 synchronization events. bit no. 7 6 5 4 3 2 1 0 bit name reserved cofa2 cofa1 cofa0 type rrr default 000 bit no. 7 6 5 4 3 2 1 0 bit name reserved oof4 oof3 oof2 oof1 oof0 type rrrrr default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 219 march 22, 2004 t1/j1 prgd counter mapping 0 (06h) prgd[7:0]: these bits together with the prgd[15:8] bits count t he prgd bit error numbers. t he prgd[0] bit is the lsb. t1/j1 prgd counter mapping 1 (07h) prgd[15:8]: these bits together with the prgd[7:0] bits count the prgd bit error numbers. the prgd[15] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name prgd7 prgd6 prgd5 prgd4 prgd3 prgd2 prgd1 prgd0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name prgd15 prgd14 prgd13 prgd12 prgd11 prgd10 prgd9 prgd8 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 220 march 22, 2004 t1/j1 lcv counter mapping 0 (08h) lcv[7:0]: these bits together with the lcv[15:8] bits count the bipolar violation (bpv) error (in ami decoding) or b8zs code violation (c v) error (in b8zs decoding) numbers. the lcv[0] bit is the lsb. t1/j1 lcv counter mapping 1 (09h) lcv[15:8]: these bits together with the lcv[7:0] bits count the bipolar violation (bpv) error (i n ami decoding) or b8zs code violation (cv ) error (in b8zs decoding) numbers. the lcv[15] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 221 march 22, 2004 t1/j1 ddse counter mapping 0 (0ah) ddse[7:0]: in t1 dm format, these bits together with the ddse[9:8] bits count the dds pattern error numbers. the ddse[0] bit is the lsb. t1/j1 ddse counter mapping 1 (0bh) ddse[9:8]: in t1 dm format, these bits together with the ddse[7:0] bits count the dds pattern error numbers. the ddse[9] bit is the msb bit no. 7 6 5 4 3 2 1 0 bit name ddse7 ddse6 ddse5 ddse4 ddse3 ddse2 ddse1 ddse0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved ddse9 ddse8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 222 march 22, 2004 rcrb: the indirect registers of rcrb addressed from 01h to 18h are the extracted si gnaling data / extract enable registers for ch1 to ch24. each address corresponds to one channel. t1/j1 extracted signaling data/extract enable register (01h ~ 18h) extract: this bit is valid when the sf/e sf/slc-96 frame is synchronized. = 0: disable the signal ing bits extraction. = 1: the signaling bits are extracted to the a,b,c,d bits (b3~0, t1/j1-id-01~18h). in t1-dm format, there is no signaling bits. the extract bit of all the channels should be set to ?0?. a, b, c, d: these bits are valid when the extract bit (b4, t1/j1-id-01~18h) is enabled. these bits are the extracted signaling bits . in sf format, the c, d bits are t he repetition of the signaling bits a & b. bit no. 7 6 5 4 3 2 1 0 bit name reserved extract a b c d type r/w r r r r default 10000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 223 march 22, 2004 rplc: the indirect registers of rplc addressed fr om 01h to 18h are the channel control regi sters for ch1 to ch24. each address corres ponds to one channel. the indirect registers of rplc addressed fr om 21h to 38h are the data trunk conditioni ng code registers for ch1 to ch24. each a ddress cor- responds to one channel. the indirect registers of rplc addressed from 41h to 58h are the signaling trunk conditioning code registers for ch1 to ch24. e ach address corresponds to one channel. t1/j1 channel control register (01h ~ 18h) subst[2:0]: when the gsubst[2:0] bits (b2~0, t1/j1-0d0h,...) are ?000? , these bits select the r eplacement on a per-channel basis. sinv, oinv, einv: these three bits select how to invert the bits in the corresponding channel. bit no. 7 6 5 4 3 2 1 0 bit name subst2 subst1 subst0 sinv oinv einv g56k gap type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 subst[2:0] replacement selection 000 no operation. 001 the data of the corresponding channel is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, t1/j1-id-21~38h). 010 the data of the corresponding channel is replaced by the a-law digital milliwatt pattern. 011 the data of the corresponding channel is replaced by the -law digital milliwatt pattern. the others reserved. sinv oinv einv bit inversion 0 0 0 no inversion. 0 0 1 invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the msb). 0 1 0 invert the odd bits (bit 3, 5, 7) except the msb of the corresponding channel (bit 1 is the msb). 0 1 1 invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the msb). 1 0 0 invert the msb (bit 1) of the corresponding channel. 1 0 1 invert the msb (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel. 1 1 0 invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the msb). 1 1 1 invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the msb).
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 224 march 22, 2004 g56k, gap: these bits are valid in receive clock master mo de when the pcce bit (b0, t1/j1-0d1h,...) is ?1?. t1/j1 data trunk conditioning code register (21h ~ 38h) dtrk[7:0]: these bits are the data trunk code that can replace the data of the channel selected by the gsubst[2:0] bits (b2~0, t1/j1-0d0h, ...) or the subst[2:0] bits (b7~5, t1/j1-id-01~18h). g56k gap gap mode 0 0 the corresponding channel is not gapped. 1 0 bit 8 (lsb) of the corresponding channel is gapped (no clock signal during the bit 8). x 1 the corresponding channel is gapped (no clock signal during the channel). bit no. 7 6 5 4 3 2 1 0 bit name dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 225 march 22, 2004 t1/j1 signaling trunk cond itioning code register (41h ~ 58h) test: this bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the pr bsmode[1:0] bits (b3~2, t1/j1-0c7h,...). = 0: disable the data in the corresponding channel to be tested by the prbs generator/detector. = 1: enable the data in the corresponding c hannel to be extracted to the prbs generator /detector for test (when the prbsdir bit (b1, t1/j1- 0c7h,...) is ?0?); or enable the test pattern from the prbs g enerator/detector to replace the data in the corresponding channel for test (when the prb- sdir bit (b1, t1/j1-0c7h,...) is ?1?). in 8-bit-based mode, the data refers to all 8 bits. in 7-bit-based mode, the data refers to the 7 msb. all the channels that are extracted to t he prbs generator/detector are concatenated and treated as a continuous stream in which pseudo ran- dom are searched for. similarly, all the channels set to be replaced with the prbs generator/detector test pattern data are con catenated replaced by the prbs. strken: = 0: no operation. = 1: the data of the corresponding channel is replaced by the signali ng trunk code set in the a, b, c, d bits (b3~0, t1/j1-id-4 1~58h). a, b, c, d: these bits are the signaling trunk code that can replace the signaling bits of the c hannel selected by the gstrken bit (b6, t1/ j1-0d0h,...) or the strken bit (b4, t1/j1-id-41~58h). bit no. 7 6 5 4 3 2 1 0 bit name reserved test reserved strken a b c d type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 226 march 22, 2004 tplc: the indirect registers of tplc addressed from 01h to 18h are t he channel control registers for ch1 to ch24. each address corres ponds to one channel. the indirect registers of tplc addressed from 21h to 38h are the data trunk c onditioning code registers for ch1 to ch24. each a ddress cor- responds to one channel. the indirect registers of tplc addressed from 41h to 58h are the signaling trunk c onditioning code registers for ch1 to ch24. e ach address corresponds to one channel. t1/j1 channel control register (01h ~ 18h) subst[2:0]: when the gsubst[2:0] bits (b2~0, t1/j1-0cbh,...) are ?000? , these bits select the replacement on a per-channel basis. sinv, oinv, einv: these three bits select how to invert the bits in the corresponding channel. bit no. 7 6 5 4 3 2 1 0 bit name subst2 subst1 subst0 sinv oinv einv g56k gap type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 subst[2:0] replacement selection 0 0 0 no operation. 0 0 1 the data of the corresponding channel is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, t1/j1-id-21~38h) . 0 1 0 the data of the corresponding channel is replaced by the a-law digital milliwatt pattern. 0 1 1 the data of the corresponding channel is replaced by the -law digital milliwatt pattern. 1 0 0 the data of the corresponding channel is replaced by the payload loopback code extracted from the elastic store buffer in the receive path. others reserved. sinv oinv einv bit inversion 0 0 0 no inversion. 0 0 1 invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the msb). 0 1 0 invert the odd bits (bit 3, 5, 7) except the msb of the corresponding channel (bit 1 is the msb). 0 1 1 invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the msb). 1 0 0 invert the msb (bit 1) of the corresponding channel. 1 0 1 invert the msb (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel. 1 1 0 invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the msb). 1 1 1 invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the msb).
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 227 march 22, 2004 g56k, gap: these bits are valid in transmit clock master mode when the pcce bi t (b0, t1/j1-0cch,...) is ?1?. t1/j1 data trunk conditioning code register (21h ~ 38h) dtrk[7:0]: these bits are the data trunk code that can replace the data of the channel selected by the gsubst[2:0] bits (b2~0, t1/j1-0cbh, ...) or the subst[2:0] bits (b7~5, t1/j1-id-01~18h). g56k gap gap mode 0 0 the corresponding channel is not gapped. 1 0 bit 8 (lsb) of the corresponding channel is gapped (no clock signal during the bit 8). x 1 the corresponding channel is gapped (no clock signal during the channel). bit no. 7 6 5 4 3 2 1 0 bit name dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 228 march 22, 2004 t1/j1 signaling trunk cond itioning code register (41h ~ 58h) test: this bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the pr bsmode[1:0] bits (b3~2, t1/j1-0c7h,...). = 0: disable the data in the corresponding channel to be tested by the prbs generator/detector. = 1: enable the data in the corresponding c hannel to be extracted to the prbs generator /detector for test (when the prbsdir bit (b1, t1/j1- 0c7h,...) is ?1?); or enable the test pattern from the prbs g enerator/detector to replace the data in the corresponding channel for test (when the prb- sdir bit (b1, t1/j1-0c7h,...) is ?0?). in 8-bit-based mode, the data refers to all 8 bits. in 7-bit-based mode, the data refers to the 7 msb. all the channels that are extracted to t he prbs generator/detector are concatenated and treated as a continuous stream in which pseudo ran- dom are searched for. similarly, all the channels set to be replaced with the prbs generator/detector test pattern data are con catenated replaced by the prbs. sigins: = 0: the signaling insertion is not allowed. = 1: the signaling bits are inserted into the data stream to be transmitted. the signaling source is selected by the strken bit (b4, t1/j1-id- 41~58h). strken: = 0: no operation. = 1: the data of the corresponding channel is replaced by the signali ng trunk code set in the a, b, c, d bits (b3~0, t1/j1-id-4 1~58h). a, b, c, d: these bits are the signaling trunk code that can replace the signaling bits of t he channel selected by the gstrken bit (b6, t1/ j1-0cbh,...) or the strken bit (b4, t1/j1-id-41~58h). bit no. 7 6 5 4 3 2 1 0 bit name reserved test sigins strken a b c d type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 229 march 22, 2004 5.2.2 e1 mode 5.2.2.1 direct register e1 chip id for quad transceiver (001h) id[7:0]: the id[7:0] bits are pre-set. the id[7:4] bits represent the IDT82P2284 device. the id [3:0] bits represent the current version number (?0001? is for the first version). e1 software reset (004h) a write operation to this register will generate a software reset. the software reset will set all the register s except the t1/j1 or e1 mode register (020h,...) to their default values. if the s etting is changed in the t1/j1 or e1 mode register (020h,...), a software reset must be applied. bit no. 7 6 5 4 3 2 1 0 bit name id7 id6 id5 id4 id3 id2 id1 id0 type rrrrrrrr default 0010xxxx bit no. 7 6 5 4 3 2 1 0 bit name x type default
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 230 march 22, 2004 e1 g.772 monitor control (005h) mon[3:0]: these bits determine whether the g.772 monitor is implemented. when the g.772 monito r is implemented, these bits select one tra nsmitter or receiver to be monitored by the link 1. bit no. 7 6 5 4 3 2 1 0 bit name reserved mon3 mon2 mon1 mon0 type r/w r/w r/w r/w default 0000 mon[3:0] monitored path mon[3:0] monitored path 0000 no transmitter or receiver is monitored. 1000 no transmitter or receiver is monitored. 0001 the receiver of the link 2 is monitored. 1001 the transmitter of the link 2 is monitored. 0010 the receiver of the link 3 is monitored. 1010 the transmitter of the link 3 is monitored. 0011 the receiver of the link 4 is monitored. 1011 the transmitter of the link 4 is monitored. 0100 reserved 1100 reserved 0101 1101 0110 1110 0111 1111
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 231 march 22, 2004 e1 gpio control (006h) level[1]: when the gpio[1] pin is defined as an output port, this bit can be read and written: = 0: the gpio[1] pin outputs low level. = 1: the gpio[1] pin outputs high level. when the gpio[1] pin is defined as an input port, this bit can only be read: = 0: low level is input on the gpio[1] pin. = 1: high level is input on the gpio[1] pin. level[0]: when the gpio[0] pin is defined as an output port, this bit can be read and written: = 0: the gpio[0] pin outputs low level. = 1: the gpio[0] pin outputs high level. when the gpio[0] pin is defined as an input port, this bit can only be read: = 0: low level is input on the gpio[0] pin. = 1: high level is input on the gpio[0] pin. dir[1]: = 0: the gpio[1] pin is used as an output port. = 1: the gpio[1] pin is used as an input port. dir[0]: = 0: the gpio[0] pin is used as an output port. = 1: the gpio[0] pin is used as an input port. bit no. 7 6 5 4 3 2 1 0 bit name reserved level1 level0 dir1 dir0 type r/w r/w r/w r/w default 001 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 232 march 22, 2004 e1 reference clock output select (007h) ro2[1:0]: when no los is detected, the refb_out pin out puts a recovered clock from the clock and data recovery function block of one of t he four links. the link is selected by these bits: when los is detected, the refb_out pin outputs mclk or high leve l, as selected by the refh_los bit (b0, e1-03eh,...). (this fea ture is available in zb revision only). ro1[1:0]: when no los is detected, the refa_out pin outputs a recovered cl ock from the clock and data recovery function block of one of t he four links. the link is selected by these bits: when los is detected, the refa_out pin outputs mclk or high leve l, as selected by the refh_los bit (b0, e1-03eh,...). (this fea ture is available in zb revision only). bit no. 7 6 5 4 3 2 1 0 bit name reserved ro21 ro20 reserved ro11 ro10 type r/w r/w r/w r/w default 00 00 ro2[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4 ro2[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 233 march 22, 2004 e1 interrupt requisition link id (009h) intn: = 0: no interrupt is generated in the corresponding link. = 1: at least one interrupt is generated in the corresponding link. e1 timer interrupt control (00ah) tmove: = 0: disable the interrupt on the int pin when the tmovi bit (b0, e1-00bh) is ?1?. = 1: enable the interrupt on the int pin when the tmovi bit (b0, e1-00bh) is ?1?. e1 timer interrupt indication (00bh) tmovi: the device times every one second. = 0: one second timer is not over. = 1: one second timer is over. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved int4 int3 int2 int1 type rrr r default 000 0 bit no.7 6 543210 bit name reserved tmove type r/w default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved tmovi type r default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 234 march 22, 2004 e1 pmon access port (00eh) linksel[1:0]: these bits select one of the four links. one of the pmon indire ct registers of the selected li nk can be accessed by the micropr ocessor. addr[3:0]: these bits select one of the pmon indirect registers of the selected link to be accessed by the microprocessor. e1 pmon access data (00fh) dat[7:0]: these bits hold the value which is read fr om the selected pmon indirect register. bit no. 7 6 5 4 3 2 1 0 bit name reserved linksel1 linksel0 reserved addr3 addr2 addr1 addr0 type r/w r/w r/w r/w r/w r/w default 00 0000 linksel[1:0] selected link 00 link 1 01 link 2 10 link 3 11 link 4 address pmon indirect register address pmon indirect register 00h crce counter mapping 0 08h lcv counter mapping 0 01h crce counter mapping 1 09h lcv counter mapping 1 02h fer counter mapping 0 0ah tcrce counter mapping 0 03h fer counter mapping 1 0bh tcrce counter mapping 1 04h cofa counter mapping 0ch febe counter mapping 0 05h oof counter mapping 0dh febe counter mapping 1 06h prgd counter mapping 0 0eh tfebe counter mapping 0 07h prgd counter mapping 1 0fh tfebe counter mapping 1 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r r r r rrrr default 00000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 235 march 22, 2004 e1 backplane global configuration (010h) rslvck: this bit is valid when all four link s are in the receive clock slave mode. = 0: each link uses its own clock signal on t he rsckn pin and framing pulse on the rsfsn pin. = 1: all four links use the clock signal on the rs ck[1] pin and the framing pulse on the rsfs[1] pin. rmux: = 0: the receive system interface of the device is operated in the non-multiplexed mode. = 1: the receive system interface of the device is operated in the multiplexed mode. mtsda: this bit is valid in transmit multiplexed mode. it selects one mu ltiplexed bus for the transmit system interface of the device. = 0: the multiplexed bus b is selected. the data and si gnaling bits are de-multiplexed from multiplexed bus b. = 1: the multiplexed bus a is selected. the data and si gnaling bits are de-multiplexed from multiplexed bus a. tslvck: this bit is valid when all four links are in the transmit clock slave mode. = 0: each link uses its own timing signal on t he tsckn pin and framing pulse on the tsfsn pin. = 1: all four links use the timing signal on the ts ck[1] pin and the framing pulse on the tsfs[1] pin. tmux: = 0: the transmit system interface of the dev ice is operated in the non-multiplexed mode. = 1: the transmit system interface of the device is operated in the multiplexed mode. bit no. 7 6 5 4 3 2 1 0 bit name reserved rslvck rmux mtsda tslvck tmux type r/w r/w r/w r/w r/w default 10110
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 236 march 22, 2004 e1 transmit jitter at tenuation configuration (021h, 121h, 221h, 321h) tjitt_test: = 0: the real time interval between the re ad and write pointer of the fifo is indicate d in the tjitt[6:0] bits (b6~0, e1-038h,. ..). that is, the cur- rent interval between the read and write pointer of the fifo will be written into the tjitt[ 6:0] bits (b6~0, e1-038h,...). = 1: the peak-peak interval between the read and write pointer of the fifo is indicated in the tjitt[6:0] bits (b6~0, e1-038h,. ..). that is, the cur- rent interval is compared with the old one in the tjitt[6:0] bits (b6~0, e1-038h,...) and the larger one will be indicated by t he tjitt[6:0] bits (b6~0, e1-038h,...); otherwise, the value in the tjitt[ 6:0] bits (b6~0, e1-038h,...) is not changed. tja_limt: when the read and write pointer of the fifo are within 2/3/4 bi ts (corresponding to the fifo dept h) of overflowing or underflow ing, the bandwidth of the ja can be widened to track the short term input jitter, t hereby avoiding data corruption. th is bit selects whether the b andwidth is normal or wid- ened. = 0: normal bandwidth is selected. = 1: widen bandwidth is selected. in this case, the ja will not attenuate the input jitter until the read/write pointer?s posit ion is outside the 2/3/4 bits window. tja_e: = 0: disable the transmit jitter attenuator. = 1: enable the transmit jitter attenuator. tja_dp[1:0]: these two bits select the jitter attenuation depth. = 00: the jitter attenuation depth is 128-bit. = 01: the jitter attenuation depth is 64-bit. = 10 / 11: the jitter attenuation depth is 32-bit. tja_bw: this bit select the jitter transfer function bandwidth. = 0: 6.77 hz. = 1: 0.87 hz. bit no. 7 6 5 4 3 2 1 0 bit name reserved tjitt_test tja_limt tja_ e tja_dp1 tja_dp0 tja_bw type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 237 march 22, 2004 e1 transmit configuration 0 (022h, 122h, 222h, 322h) t_off: = 0: the transmit path is power up. = 1: the transmit path is power down. the line driver is in high impedance. t_md: this bit selects the line code rule to encode the data stream to be transmitted. = 0: the hdb3 encoder is selected. = 1: the ami encoder is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved t_off reserved t_md type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 238 march 22, 2004 e1 transmit configuration 1 (023h, 123h, 223h, 323h) dfm_on: = 0: the driver failur e monitor is disabled. = 1: the driver failure monitor is enabled. t_hz: = 0: the line driver works normally. = 1: set the line driver high-z . (the other parts of the transmit path still work normally.) puls[3:0]: these bits determine the template shapes for short/long haul transmission: bit no. 7 6 5 4 3 2 1 0 bit name reserved dfm_on t_hz puls3 puls2 puls1 puls0 type r/w r/w r/w r/w r/w r/w default 010000 puls[3:0] transmit clock cable impedance 0000 2.048 mhz 75 ? (in internal impedance matching mode) / reserved (in external impedance matching mode) 0001 2.048 mhz 120 ? (in internal impedance matching mode) / 75 ? & 120 ? (in external impedance matching mode) 0010 reserved 0011 0100 0101 0110 0111 1000 1001 1010 1011 11xx arbitrary waveform setting.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 239 march 22, 2004 e1 transmit configuration 2 (024h, 124h, 224h, 324h) scal[5:0]: the following setting lists the standard val ue of normal amplitude in different operat ing modes. each step change (one increasi ng or decreasing from the standard value) will scale the am plitude of the d/a output by a certain offs et. these bits are only effective when use r programmable arbitrary waveform is used. = 100001: normal amplitude in e1 - 75 ? & 120 ? operating modes. each step change scales about 3% offset. bit no. 7 6 5 4 3 2 1 0 bit name reserved scal5 scal4 scal3 scal2 scal1 scal0 type r/w r/w r/w r/w r/w r/w default 100001
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 240 march 22, 2004 e1 transmit configuration 3 (025h, 125h, 225h, 325h) this register is valid when the puls[3:0] bits (b3~0, e1-023h,...) are set to ?11xx?. done: = 0: disable the read/write operat ion to the pulse template ram. = 1: enable the read/write operation to the pulse template ram. rw: = 0: write the data to the pulse template ram. = 1: read the data to the pulse template ram. ui[1:0]: these bits specify one unit interval (ui) address. = 00: ui addressed 0 is specified. = 01: ui addressed 1 is specified. = 10: ui addressed 2 is specified. = 11: ui addressed 3 is specified. samp[3:0]: there bits specify one sample address. there are 16 samples in each ui. bit no. 7 6 5 4 3 2 1 0 bit name done rw ui1 ui0 samp3 samp2 samp1 samp0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 samp[3:0] specified sample address sa mp[3:0] specified sample address 0000 0 1000 8 0001 1 1001 9 0010 2 1010 10 0011 3 1011 11 0100 4 1100 12 0101 5 1101 13 0110 6 1110 14 0111 7 1111 15
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 241 march 22, 2004 e1 transmit configuration 4 (026h, 126h, 226h, 326h) wdat[6:0]: these bits contain the data to be stored in the pulse template ra m which is addressed by the ui[1 :0] bits (b5~4, e1-025h,...) a nd the samp[3:0] bits (b3~0, e1-025h,...). bit no. 7 6 5 4 3 2 1 0 bit name reserved wdat6 wdat5 wdat4 wdat3 wdat2 wdat1 wdat0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 242 march 22, 2004 e1 receive jitter atte nuation configuration (027h, 127h, 227h, 327h) rjitt_test: = 0: the real time interval between the read and write pointer of th e fifo is indicated in the rjit t[6:0] bits (b6~0, e1-039h,. ..). that is, the cur- rent interval between the read and write pointer of the fifo will be written into the rjitt[6:0] bits (b6~0, e1-039h,...). = 1: the peak-peak interval between the read and write pointer of the fifo is indicated in the rjitt[6:0] bits (b6~0, e1-039h,. ..). that is, the cur- rent interval is compared with the old o ne in the rjitt[6:0] bits (b6~0, e1-039h,...) and the larger one will be indicated by t he rjitt[6:0] bits (b6~0, e1-039h,...); otherwise, the value in the rjitt[ 6:0] bits (b6~0, e1-039h,...) is not changed. rja_limt: when the read and write pointer of the fifo are within 2/3/4 bi ts (corresponding to the fifo dept h) of overflowing or underflow ing, the bandwidth of the ja can be widened to track the short term input jitter, t hereby avoiding data corruption. th is bit selects whether the b andwidth is normal or wid- ened. = 0: normal bandwidth is selected. = 1: widen bandwidth is selected. in this case, the ja will not attenuate the input jitter until the read/write pointer?s posit ion is outside the 2/3/4 bits window. rja_e: = 0: disable the receive jitter attenuator. = 1: enable the receive jitter attenuator. rja_dp[1:0]: these two bits select the jitter attenuation depth. = 00: the jitter attenuation depth is 128-bit. = 01: the jitter attenuation depth is 64-bit. = 10 / 11: the jitter attenuation depth is 32-bit. rja_bw: this bit select the jitter transfer function bandwidth. = 0: 6.77 hz. = 1: 0.87 hz. bit no. 7 6 5 4 3 2 1 0 bit name reserved rjitt_test rja_limt rja_e rja_dp1 rja_dp0 rja_bw type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 243 march 22, 2004 e1 receive configuration 0 (028h, 128h, 228h, 328h) r_off: = 0: the receive path is power up. = 1: the receive path is power down. r_md: this bit selects the line code rule to decode the received data stream. = 0: the hdb3 decoder is selected. = 1: the ami decoder is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved r_off reserved r_md type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 244 march 22, 2004 e1 receive configuration 1 (029h, 129h, 229h, 329h) eq_on: = 0: the equalizer is off in short haul applications. = 1: the equalizer is on in long haul applications. los[4:0]: a los is detected when the incoming signals has ?no transitions?, i.e., when the signal level is less than q db below nominal f or n consecutive pulse intervals. in long haul applications, t hese bits select the los declare threshold (q). these bits are invalid in short ha ul applications. bit no. 7 6 5 4 3 2 1 0 bit name reserved eq_on reserved los4 los3 los2 los1 los0 type r/w r/w r/w r/w r/w r/w default 010101 los[4:0] los declare threshold (q) l os[4:0] los declare threshold (q) 00000 -4 db 01100 -28 db 00001 -6 db 01101 -30 db 00010 -8 db 01110 -32 db 00011 -10 db 01111 -34 db 00100 -12 db 10000 -36 db 00101 -14 db 10001 -38 db 00110 -16 db 10010 -40 db 00111 -18 db 10011 -42 db 01000 -20 db 10100 -44 db 01001 -22 db 10101 -46 db 01010 -24 db 10110 - 11111 -48 db 01011 -26 db
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 245 march 22, 2004 e1 receive configuration 2 (02ah, 12ah, 22ah, 32ah) slice[1:0]: these two bits define the data slicer threshold. = 00: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 40% of the peak amplitude. = 01: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 50% of the peak amplitude. = 10: the data slicer generates a mark if the voltage on the rtipn/rringn pins exceeds 60% of the peak amplitude. = 11: the data slicer generates a mark if the voltage on the rtipn/rringn pins exc eeds 70% of the peak amplitude. updw[1:0]: these two bits select the observation period, during wh ich the peak value of the incoming signals are measured. = 00: the observation period is 32 bits. = 01: the observation period is 64 bits. = 10: the observation period is 128 bits. = 11: the observation period is 256 bits. mg[1:0]: these two bits select the monitor gain. = 00: the monitor gain is 0 db. = 01: the monitor gain is 22 db. = 10: the monitor gain is 26 db. = 11: the monitor gain is 32 db. bit no. 7 6 5 4 3 2 1 0 bit name reserved slice1 slice0 updw1 updw0 mg1 mg0 type r/w r/w r/w r/w r/w r/w default 01 1 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 246 march 22, 2004 e1 maintenance function control 0 (02bh, 12bh, 22bh, 32bh) dllp: = 0: disable the loc al digital loopback 1. = 1: enable the local digital loopback 1. sllp: = 0: disable the system local loopback. = 1: enable the system local loopback. srlp: = 0: disable the system remote loopback. = 1: enable the system remote loopback. rlp: = 0: disable the remote loopback. = 1: enable the remote loopback. alp: = 0: disable the analog loopback. = 1: enable the analog loopback. dlp: = 0: disable the loc al digital loopback 2. = 1: enable the local digital loopback 2. bit no. 7 6 5 4 3 2 1 0 bit name reserved dllp sllp srlp reserved rlp alp dlp type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 247 march 22, 2004 e1 maintenance function control 1 (02ch, 12ch, 22ch, 32ch) lac: this bit selects the los criteria. = 0: the g.775 is selected. in short haul application, the los is declared when t he incoming signal level is less than 800 mvpp for 32 consecu- tive bit intervals and is cleared when the incoming signal level is greater than 1 v pp and has an average mark density of at le ast 12.5% and less than 16 consecutive zeros in 32 consecutive bit periods. in long haul application, the los is declared when the incoming signal leve l is less than q db below nominal (set in the los[4:0] bits (b4~0, e1-029h,...) ) for 32 consecutive bit interval s and is cleared when the incoming signal level is greater than (q + 4 db) and has an average mark density of at least 12.5% and less than 16 consecutive zeros in 32 consecutive bit peri ods. = 1: the i.431/etsi is selected. in short haul application, t he los is declared when the incoming signal level is less than 800 mvpp for 2048 con- secutive bit intervals and is cleared when the incoming signal level is greater than 1 vpp and has an average mark density of a t least 12.5% and less than 16 consecutive zeros in 32 consecutive bit periods. in l ong haul application, the los is declared when the incoming signal level is less than q db below nominal (set in the los[4:0] bits (b4~0, e1-029h,...)) for 2048 consecutive bit interval s and is cleared when the incomin g signal level is greater than (q + 4 db) and has an average mark density of at least 12.5% and less than 16 consecutive zeros in 32 consecutive bit peri ods. raise: this bit determines whether all ?one?s can be inse rted in the receive path when the los is detected. = 0: disable the insertion. = 1: enable the insertion. atao: this bit determines whether all ?one?s can be inserted in the transmit path when the los is detected in the receive path. = 0: disable the insertion. = 1: enable the insertion. bit no. 7 6 5 4 3 2 1 0 bit name reserved lac raise atao type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 248 march 22, 2004 e1 maintenance function control 2 (031h, 131h, 231h, 331h) bpv_ins: a transition from ?0? to ?1? on this bit gener ates a single bipolar violation (bpv) erro r to be inserted to the data stream to be transmitted. this bit must be cleared and set again for the next bpv error insertion. exz_def: this bit selects the excessive zero (exz) error criteria. = 0: the ansi is selected. in ami line code rule, the exz erro r is defined as more than 15 consecutive zeros in the data stream . in hdb3 line code rule, the exz error is defined as more th an 3 consecutive zeros in the data stream. = 1: the fcc is selected. in ami line code rule, the exz error is defined as more than 80 consecutive zeros in the data stream. in hdb3 line code rule, the exz error is defined as more th an 3 consecutive zeros in the data stream. exz_err[1:0]: these bits must be set to ?01? to enable the excessive zero ( exz) error event to be counted in an internal 16-bit exz counter. cnt_md: = 0: the manual report mode is selected. t he internal 16-bit exz counter transfers its content to the exz error counter l-byte & h-byte regis- ters when there is a transition fr om ?0? to ?1? on the cnt_trf bit. = 1: the auto report mode is selected. the internal 16-bit exz counter transfers its c ontent to the exz error counter l-byte & h-byte registers every one second automatically. cnt_trf: this bit is valid when the cnt_md bit is ?0?. a transition from ?0? to ?1? on this bit updates the content in t he exz error counter l-byte & h- byte registers with the value in the internal 16-bit exz counter. this bit must be cleared and set again for the next updating. bit no. 7 6 5 4 3 2 1 0 bit name reserved bpv_ins reserved exz_def exz_err1 exz_err0 cnt_md cnt_trf type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 249 march 22, 2004 e1 transmit and receive te rmination configuration (032h, 132h, 232h, 332h) t_term[2:0]: these bits select the internal impedance of the transmit path to match the cable impedance: = 000: the 75 ? internal impedance matching is selected. = 001: the 120 ? internal impedance matching is selected. (the above two values are the standard value for e1 mode). = 010: the 100 ? internal impedance matching is selected. = 011: the 110 ? internal impedance matching is selected. = 1xx: the internal impedance matching is bypa ssed, and external impedance circuit should be used. r_term[2:0]: these bits select the internal impedance of the receive path to match the cable impedance: = 000: the 75 ? internal impedance matching is selected. = 001: the 120 ? internal impedance matching is selected. (the above two values are the standard values for e1 mode). = 010: the 100 ? internal impedance matching is selected. = 011: the 110 ? internal impedance matching is selected. = 1xx: the internal impedance matching is bypa ssed, and external impedance circuit should be used. e1 interrupt enable control 0 (033h, 133h, 233h, 333h) df_ie: = 0: disable the interrupt on the int pin when the df_is bit (b2, e1-03ah,...) is ?1?. = 1: enable the interrupt on the int pin when the df_is bit (b2, e1-03ah,...) is ?1?. los_ie: = 0: disable the interrupt on the int pin when the los_is bit (b0, e1-03ah,...) is ?1?. = 1: enable the interrupt on the int pin when the los_is bit (b0, e1-03ah,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved t_term2 t_term1 t_term0 r _term2 r_term1 r_term0 type r/w r/w r/w r/w r/w r/w default 00 0 1 1 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved df_ie reserved los_ie type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 250 march 22, 2004 e1 interrupt enable control 1 (034h, 134h, 234h, 334h) dac_ie: = 0: disable the interrupt on the int pin when the dac_is bit (b6, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the dac_is bit (b6, e1-03bh,...) is ?1?. tja_ie: = 0: disable the interrupt on the int pin when the tja_is bit (b5, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the tja_is bit (b5, e1-03bh,...) is ?1?. rja_ie: = 0: disable the interrupt on the int pin when the rja_is bit (b4, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the rja_is bit (b4, e1-03bh,...) is ?1?. exz_ie: = 0: disable the interrupt on the int pin when the exz_is bit (b2, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the exz_is bit (b2, e1-03bh,...) is ?1?. cv_ie: = 0: disable the interrupt on the int pin when the cv_is bit (b1, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the cv_is bit (b1, e1-03bh,...) is ?1?. cnt_ie: = 0: disable the interrupt on the int pin when the cntov_is bit (b0, e1-03bh,...) is ?1?. = 1: enable the interrupt on the int pin when the cntov_is bit (b0, e1-03bh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved dac_ie tja_ie rja_ie reserved exz_ie cv_ie cnt_ie type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 251 march 22, 2004 e1 interrupt trigger edges select (035h, 135h, 235h, 335h) df_ies: = 0: the df_is bit (b2, e1-03ah,...) will be set to ?1? when there is a transition from ?0? to ?1? on the df_s bit (b2, e1-036h ,...). = 1: the df_is bit (b2, e1-03ah,...) will be set to ?1? when there is any transition fr om ?0? to ?1? or from ?1? to ?0? on the df_s bit (b2, e1-036h,...). los_ies: = 0: the los_is bit (b0, e1-03ah,...) will be set to ?1? when t here is a transition from ?0? to ?1? on the los_s bit (b0, e1-03 6h,...). = 1: the los_is bit (b0, e1-03ah,...) will be set to ?1? when ther e is any transition from ?0? to ?1? or from ?1? to ?0? on the los_s bit (b0, e1- 036h,...). e1 line status register 0 (036h, 136h, 236h, 336h) df_s: = 0: no transmit driver failure is detected. = 1: transmit driver failure is detected. los_s: = 0: no los is detected. = 1: loss of signal (los) is detected. bit no. 7 6 5 4 3 2 1 0 bit name reserved df_ies reserved los_ies type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved df_s reserved los_s type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 252 march 22, 2004 e1 line status register 1 (037h, 137h, 237h, 337h) latt[4:0]: these bits indicate the current gain of the vga relative to 3 v peak pulse level. bit no. 7 6 5 4 3 2 1 0 bit name reserved latt4 latt3 latt2 latt1 latt0 type rrr r r default 000 0 0 latt[4:0] gain (db) latt[4:0] gain (db) 00000 0 - 2 01011 22 - 24 00001 2 - 4 01100 24 - 26 00010 4 - 6 01101 26 - 28 00011 6 - 8 01110 28 - 30 00100 8 - 10 01111 30 - 32 00101 10 - 12 10000 32 - 34 00110 12 - 14 10001 34 - 36 00111 14 - 16 10010 36 - 38 01000 16 - 18 10011 38 - 40 01001 18 - 20 10100 40 - 42 01010 20 - 22 10101 ~ 11111 42 - 44
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 253 march 22, 2004 e1 transmit jitter measure value indication (038h, 138h, 238h, 338h) tjitt[6:0]: when the tjitt_test bit (b5, e1-021h,...) is ?0?, these bits represent the current interval between the read and write pointer of the fifo. when the tjitt_test bit (b5, e1-021h,...) is ?1?, these bits represent the p-p inte rval between the read and write pointer of t he fifo since last read. these bits will be cleared if a ?1 ? is written to the register. e1 receive jitter measure value indication (039h, 139h, 239h, 339h) rjitt[6:0]: when the rjitt_test bit (b5, e1-027h,...) is ?0?, these bits represent the current interval between the read and write pointer of the fifo. when the rjitt_test bit (b5, e1-027h,...) is ?1?, these bits represent the p-p inte rval between the read and write pointer of t he fifo since last read. these bits will be cleared if a ?1 ? is written to the register. bit no. 7 6 5 4 3 2 1 0 bit name reserved tjitt6 tjitt5 tjitt4 tjitt3 tjitt2 tjitt1 tjitt0 type rr r r r r r default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved rjitt6 rjitt5 rjitt4 rjitt3 rjitt2 rjitt1 rjitt0 type rr r r r r r default 00 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 254 march 22, 2004 e1 interrupt status 0 (03ah, 13ah, 23ah, 33ah) df_is: = 0: there is no status change on the df_s bit (b2, e1-036h,...). = 1: when the df_ies bit (b2, e1-035h,...) is ?0?, the ?1? on this bit indicates there is a transition from ?0? to ?1? on the d f_s bit (b2, e1-036h,...); when the df_ies bit (b2, e1-035h,...) is ?1?, the ?1? on this bit indicates there is a transition fr om ?0? to ?1? or from ?1? t o ?0? on the df_s bit (b2, e1- 036h,...). this bit will be cleared if a ?1? is written to it. los_is: = 0: there is no status change on the los_s bit (b0, e1-036h,...). = 1: when the los_ies bit (b0, e1-035h,...) is ?0?, the ?1? on th is bit indicates there is a transition from ?0? to ?1? on the los_s bit (b0, e1- 036h,...); when the los_ies bit (b0, e1-035h,...) is ?1?, the ?1? on this bit indicates there is a transition from ?0? to ?1? o r from ?1? to ?0? on the los_s bit (b0, e1-036h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved df_is reserved los_is type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 255 march 22, 2004 e1 interrupt status 1 (03bh, 13bh, 23bh, 33bh) dac_is: = 0: the sum of a pulse template does not exceed the d/a limitation (+ 63) when more than one ui is used to compose the arbitrary pulse tem- plate. = 1: the sum of a pulse template exceeds the d/a limitation (+ 63) when more than one ui is used to compose the arbitrary pulse template. this bit will be cleared if a ?1? is written to it. tja_is: = 0: the transmit ja fifo has not overflowed or underflowed. = 1: the transmit ja fifo has overflowed or underflowed. this bit will be cleared if a ?1? is written to it. rja_is: = 0: the receive ja fifo has not overflowed or underflowed. = 1: the receive ja fifo has overflowed or underflowed. this bit will be cleared if a ?1? is written to it. exz_is: = 0: no excessive zero (exz) error is detected. = 1: the excessive zero (exz) error is detected. this bit will be cleared if a ?1? is written to it. cv_is: = 0: no bipolar violation (bpv) error or hdb3 code violation (cv) error is detected. = 1: the bipolar violation (bpv) error or hd b3 code violation (cv) error is detected. this bit will be cleared if a ?1? is written to it. cntov_is: = 0: the internal 16-bit exz counter has not overflowed. = 1: the internal 16-bit exz counter has overflowed. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved dac_is tja_is rja_is reserved exz_is cv_is cntov_is type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 256 march 22, 2004 e1 exz error counter h-byte (03ch, 13ch, 23ch, 33ch) cnth[7:0]: these bits, together with the cntl[7:0] bits, reflec t the content in the internal 16-bit exz counter. e1 exz error counter l-byte (03dh, 13dh, 23dh, 33dh) cntl[7:0]: these bits, together with the cnth[7 :0] bits, reflect the content in the internal 16-bit exz counter. e1 reference clock output control (03eh, 13eh, 23eh, 33eh) refh_los: in case of los, this bit determines t he outputs on the refa_out and refb_out pins. = 0: output mclk. = 1: output high level. bit no. 7 6 5 4 3 2 1 0 bit name cnth[7] cnth[6] cnth[5] cnth[4] cnth[3] cnth[2] cnth[1] cnth[0] type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name cntl[7] cntl[6] cntl[5] cntl[4] cntl[3] cntl[2] cntl[1] cntl[0] type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved refh_los type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 257 march 22, 2004 e1 interrupt module indication 2 (03fh, 13fh, 23fh, 33fh) liu: = 0: no interrupt is generated in the receive / transmit internal termination, adaptive equalizer, data slicer, clk&data recove ry, receive / transmit jitter attenuator, b8zs/hdb3/ami decoder / encoder, waveform shaper / line build out or line driver block. = 1: interrupt is generated in the receive / transmit internal termination, adaptive equalizer, data slicer, clk&data recovery, receive / trans- mit jitter attenuator, b8zs/hdb3/ami decoder / encoder, wavefo rm shaper / line build out or line driver function block. e1 interrupt module indication 0 (040h, 140h, 240h, 340h) alarm: = 0: no interrupt is generated in the alarm detector function block. = 1: interrupt is generated in t he alarm detector function block. pmon: = 0: no interrupt is generated in t he performance monitor function block. = 1: interrupt is generated in the performance monitor function block. prgd: = 0: no interrupt is generated in the pr bs generator / detector function block. = 1: interrupt is generated in the prbs generator / detector function block. rcrb: = 0: no interrupt is generated in the receive cas/rbs buffer function block. = 1: interrupt is generated in the re ceive cas/rbs buffer function block. fgen: = 0: no interrupt is generated in the frame generator function block. = 1: interrupt is generated in t he frame generator function block. frmr: = 0: no interrupt is generated in the frame processor function block. = 1: interrupt is generated in t he frame processor function block. bit no. 7 6 5 4 3 2 1 0 bit name reserved liu type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved alarm pmon prgd rcrb fgen frmr type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 258 march 22, 2004 e1 interrupt module indication 1 (041h, 141h, 241h, 341h) thdlc3: = 0: no interrupt is generated in t he hdlc transmitter #3 function block. = 1: interrupt is generated in the hdlc transmitter #3 function block. thdlc2: = 0: no interrupt is generated in t he hdlc transmitter #2 function block. = 1: interrupt is generated in the hdlc transmitter #2 function block. thdlc1: = 0: no interrupt is generated in t he hdlc transmitter #1 function block. = 1: interrupt is generated in the hdlc transmitter #1 function block. rhdlc3: = 0: no interrupt is generated in the hdlc receiver #3 function block. = 1: interrupt is generated in the hdlc receiver #3 function block. rhdlc2: = 0: no interrupt is generated in the hdlc receiver #2 function block. = 1: interrupt is generated in the hdlc receiver #2 function block. rhdlc1: = 0: no interrupt is generated in the hdlc receiver #1 function block. = 1: interrupt is generated in the hdlc receiver #1 function block. elst: = 0: no interrupt is generated in the elastic store buffer function block. = 1: interrupt is generated in the elastic store buffer function block. trsi/resi: = 0: no interrupt is generated in the transmi t / receive system interface function block. = 1: interrupt is generated in the transmit / receive system interface function block. bit no. 7 6 5 4 3 2 1 0 bit name thdlc3 thdlc2 thdlc1 rhdlc3 rhdlc2 rhdlc1 elst trsi/resi type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 259 march 22, 2004 e1 tbif option register (042h, 142h, 242h, 342h) de: this bit selects the active edge of tsckn to sample the data on tsdn and tsign and the active edge of mtsck to sample the data on mtsda (mtsdb) and mtsiga (mtsigb). = 0: the falling edge is selected. = 1: the rising edge is selected. in transmit multiplexed mode, the bit of the four links should be set to the same value. fe: this bit selects the active edge of tsckn to update/sample the pulse on tsfsn and the active edge of mtsck to sample the pulse on mtsfs. = 0: the falling edge is selected. = 1: the rising edge is selected. in transmit multiplexed mode, the bit of the four links should be set to the same value. cms: this bit is valid in transmit clock slave mode and transmit multiplexed mode. = 0: the speed of tsckn/mtsck is the same as the data rate on the system side (2.048 mb/s / 8.192 mb/s). = 1: the speed of tsckn/mtsck is double the data rate on the system side (4.096 mb/s / 16.384 mb/s). in transmit clock slave mode, if all four links use tsck[1] and tsfs[1] to input the data (i.e., the tslvck bit (b, t1/j1-01h) is set to ?1?), the bit of the four links should be set to the same value. in transmit multiplexed mode, the bit of the four links should be set to the same value. fsinv: = 0: the transmit framing pul se tsfsn is active high. = 1: the transmit framing pulse tsfsn is active low. in transmit multiplexed mode, this bit of the four links should be set to the same value. fstyp: = 0: in transmit non-multiplexed mode, tsfsn pulses during the fi rst bit of each basic frame. in transmit multiplexed mode, mts fs pulses dur- ing the first bit of each basi c frame of the first link. = 1: in transmit non-multiplexed mode, if the crc multi-frame is to be generated, tsfsn pulses during the first bit of each crc multi-frame; if the signaling multi-frame is to be generated, tsfsn pulses during the first bit of each signaling multi-frame; if both the crc multi-frame and the sig- naling multi-frame are to be generated, tsfsn goes high/low duri ng the first bit of each signaling multi-frame and goes the opp osite during the sec- ond bit of each crc multi-frame. in transmit multiplexed mode, if the crc multi-frame is to be generated, mtsfs pulses during t he first bit of each crc multi-frame of the first link; if t he signaling multi-frame is to be generated, mt sfs pulses during the first bit of each s ignaling multi-frame of the first link; if both the crc multi-frame and the signaling multi-frame are to be generat ed, mtsfs goes high/low during the first bit of each signaling multi-frame and goes the opposite during the second bi t of each crc multi-frame of the first link. in transmit multiplexed mode, this bit of t he four links should be set to the same value. bit no. 7 6 5 4 3 2 1 0 bit name reserved de fe cms fsinv fstyp type r/w r/w r/w r/w r/w default 000 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 260 march 22, 2004 e1 tbif operating mode (043h, 143h, 243h, 343h) tmode: in transmit non-multiplexed mode, this bit selects the sub-mode. = 0: the transmit system interface is oper ated in transmit clock master mode. the timing signal for clocking the data and the f raming pulse to align the data input on the tsdn pin are prov ided from the processed data from the device. = 1: the transmit system interface is operated in transmit cl ock slave mode. the timing signal for clocking the data and the fr aming pulse to align the data input on the tsdn pin are provided by the system side. bit no. 7 6 5 4 3 2 1 0 bit name reserved tmode type r/w default 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 261 march 22, 2004 e1 tbif ts offset (044h, 144h, 244h, 344h) tsoff[6:0]: these bits give a binary number to define the timeslot offset. the timeslot offset is between the framing pulse on the tsfsn/mt sfs pin and the start of the corresponding frame input on the tsdn/mtsda(mtsdb) pin. the signaling bits on the tsig n/mtsiga(mtsigb) pin are alw ays per- timeslot aligned with the data on the tsdn/mtsda(mtsdb) pin. in non-multiplexed mode, the timeslot offs et can be configured from 0 to 31 timeslot s (0 & 31 are included). in multiplexed mod e, the timeslot off- set can be configured from 0 to 127 timeslots (0 & 127 are included). e1 tbif bit offset (045h, 145h, 245h, 345h) edge: this bit is valid when the cm s bit (b2, e1-042h,...) is ?1?. = 0: the first active edge of tsckn/mtsck is selected to sample the data on the tsdn/mtsda(mtsdb) and tsign/mtsiga(mtsigb) pins . = 1: the second active edge of tsckn/mtsck is selected to sa mple the data on the tsdn/mtsda(mtsdb) and tsign/mtsiga(mtsigb) pins. boff[2:0]: these bits give a binary number to define the bit offset. the bit offset is between the framing pulse on the tsfsn/mtsfs pin an d the start of the corresponding frame input on the tsdn/mtsda(mts db) pin. the signaling bits on the tsign/ mtsiga(mtsigb) pin are always per-times lot aligned with the data on the tsdn/mtsda(mtsdb) pin. bit no. 7 6 5 4 3 2 1 0 bit name reserved tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved edge boff2 boff1 boff0 type r/w r/w r/w r/w default 000 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 262 march 22, 2004 e1 rbif option register (046h, 146h, 246h, 346h) de: this bit selects the active edge of rsckn to update the data on rsdn and rsign and the active edge of mrsck to update the data on mrsda(mrsdb) and mrsiga(mrsigb). = 0: the falling edge is selected. = 1: the rising edge is selected. in receive multiplexed mode, the bit of the four links should be set to the same value. fe: this bit selects the active edge of rsckn to update/sample the pulse on rsfsn and the active edge of mrsck to sample the pulse on mrsfs. = 0: the falling edge is selected. = 1: the rising edge is selected. in receive multiplexed mode, the bit of the four links should be set to the same value. cms: this bit is valid in receive clock slave mode and receive multiplexed mode. = 0: the speed of rsckn/mrsck is the same as the data rate on the system side (2.048 mb/s / 8.192 mb/s). = 1: the speed of rsckn/mrsck is double the data ra te on the system side (4.096 mb/s / 16.384 mb/s). in receive clock slave mode, if all four links use the rsck[1] and rsfs[1] to output the data (i.e., the rslvck bit (b, e1-01h) is set to ?1?), the bit of the four links should be set to the same value. in receive multiplexed mode, the bit of the four links should be set to the same value. tri: = 0: the processed data and signaling bits are output on the rsdn/mrsda(mrsdb) and rsign/mrsiga(mrsigb) pins respectively. = 1: the output on the rsdn/mrsda(mrsdb) and rs ign/mrsiga(mrsigb) pins are in high impedance. bit no. 7 6 5 4 3 2 1 0 bit name reserved de fe cms tri type r/w r/w r/w r/w default 110 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 263 march 22, 2004 e1 rbif mode (047h, 147h, 247h, 347h) rmode: in receive non-multiplexed mode, this bit selects the sub-mode. = 0: the receive system interface is oper ated in receive clock master mode. the ti ming signal for clocking the data and the fra ming pulse to align the data output on the rsdn pin are received from each line side. = 1: the receive system interface is operated in receive cloc k slave mode. the timing signal fo r clocking the data and the fram ing pulse to align the data output on the rsdn pin are provided by the system side. e1 rbif frame pulse (048h, 148h, 248h, 348h) fsinv: = 0: the receive framing pulse rsfsn is active high. = 1: the receive framing pulse rsfsn is active low. in receive multiplexed mode, this bit of the four links should be set to the same value. ohd, smfs, cmfs: in receive clock master mode, these bits select what the pulse on rsfsn indicates. bit no. 7 6 5 4 3 2 1 0 bit name reserved rmode type r/w default 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved fsinv ohd smfs cmfs reserved type r/w r/w r/w r/w default 0000 ohd smfs cmfs rsfsn indication 0 0 0 the rsfsn pulses during the first bit of each basic frame. 0 0 1 the rsfsn pulses during the first bit of each crc multi-frame. 0 1 0 the rsfsn pulses during the first bit of each signaling multi-frame. 0 1 1 the rsfsn goes high/low during the first bit of each signaling multi-frame and goes the opposite during the sec- ond bit of each crc multi-frame. 1 0 0 the rsfsn pulses during the ts0 and ts16.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 264 march 22, 2004 e1 rbif ts offset (049h, 149h, 249h, 349h) tsoff[6:0]: except that in the receive master mode, when the ohd bit (b3, e1-048h,...), the smfs bit (b2, e1-048h,...) and the cmfs bit (b1 , e1-048h,...) are set to ts1 and ts16 overhead indication, the timeslot offset is supported in all the other conditions. these bits give a binary number to define t he timeslot offset. the timeslot offset is between the framing pulse on the rsfsn/mr sfs pin and the start of the corresponding frame output on the rsdn/mrsda(mrsdb) pin. the signaling bits on the rs ign/mrsiga(mrsigb) pin are al ways per- timeslot aligned with the data on the rsdn/mrsda(mrsdb) pin. in non-multiplexed mode, the timeslot offs et can be configured from 0 to 31 timeslot s (0 & 31 are included). in multiplexed mod e, the timeslot off- set can be configured from 0 to 127 timeslots (0 & 127 are included). e1 rbif bit offset (04ah, 14ah, 24ah, 34ah) edge: this bit is valid when the cm s bit (b1, e1-046h,...) is ?1?. = 0: the first active edge of rsckn/mrsck is selected to update the data on the rsdn/mrsda(mrsdb) and rsign/mrsiga(mrsigb) pins . = 1: the second active edge of rsckn/mrsck is selected to updat e the data on the rsdn/mrsda(mrsdb) and rsign/mrsiga(mrsigb) pins. boff[2:0]: except that in the receive master mode, when the ohd bit (b3, e1-048h,...), the smfs bit (b2, e1-048h,...) and the cmfs bit (b1 , e1-048h,...) are set to ts1 and ts16 overhead indication, the bit offset is supported in all the other conditions. these bits give a binary number to define the bit offset. the bi t offset is between the framing pulse on the rsfsn/mrsfs pin an d the start of the corresponding frame output on the rsdn/mrsda(m rsdb) pin. the signaling bits on the rsig n/mrsiga(mrsigb) pin are always per-chan nel aligned with the data on the rsdn/mrsda(mrsdb) pin. bit no. 7 6 5 4 3 2 1 0 bit name reserved tsoff6 tsoff5 tsoff4 tsoff3 tsoff2 tsoff1 tsoff0 type r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved edge boff2 boff1 boff0 type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 265 march 22, 2004 e1 rtsfs change indication (04bh, 14bh, 24bh, 34bh) rcofai: this bit is valid in receive clock slave mode and receive multiplexed mode. = 0: the interval of the pulses on the rsfs n/mrsfs pin is an integer multiple of 125 s. = 1: the interval of the pulses on the rsfsn/mr sfs pin is not an integer multiple of 125 s. this bit will be cleared if a ?1? is written to it. tcofai: this bit is valid in transmit clock slave mode and transmit multiplexed mode. = 0: the pulse on the tsfsn/mtsfs pin is an integer multiple of 125 s. = 1: the pulse on the tsfsn/mtsfs pin is not an integer multiple of 125 s. this bit will be cleared if a ?1? is written to it. e1 rtsfs interrupt control (04ch, 14ch, 24ch, 34ch) rcofae: = 0: disable the interrupt on the int pin when the rcofai bit (b1, e1-04bh,...) is ?1?. = 1: enable the interrupt on the int pin when the rcofai bit (b1, e1-04bh,...) is ?1?. tcofae: = 0: disable the interrupt on the int pin when the tcofai bit (b0, e1-04bh,...) is ?1?. = 1: enable the interrupt on the int pin when the tcofai bit (b0, e1-04bh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved rcofai tcofai type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved rcofae tcofae type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 266 march 22, 2004 e1 frmr mode 0 (04dh, 14dh, 24dh, 34dh) unfm: = 0: the data stream is received in framed mode and is processed by the frame processor. = 1: the data stream is received in unfra med mode and the frame processor is bypassed. refcrce: = 0: disable from re-searching for synchroni zation when the excessive crc-4 error occurs. = 1: search for synchronization again when the excessive crc-4 er ror occurs. this function can only be implemented only if the refen bit is logic 1. refen: = 0: ?locked in frame?. once the previous basic frame synchronization is acquired, and no errors can lead to reframe except for manually setting by the refr bit. = 1: search for basic frame synchronizati on again when it is out of synchronization. refr: a transition from logic 0 to logi c 1 forces to re-search for a new basic frame synchronization. bit no. 7 6 5 4 3 2 1 0 bit name reserved unfm refcrce refen refr type r/w r/w r/w r/w default 0110
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 267 march 22, 2004 e1 frmr mode 1 (04eh, 14eh, 24eh, 34eh) bit2c: this bit determines the criteria of out of basic frame synchronization. = 0: 3 consecutive fas pattern errors l ead to out of basic frame synchronization. = 1: 3 consecutive fas pattern errors or 3 consecutiv e nfas errors lead to out of basic frame synchronization. casen: = 0: disable searching for the channel associated signaling (cas) multi-frame. = 1: enable searching for the channel asso ciated signaling (cas) multi-frame after t he basic frame synchronization is acquired. crcen: = 0: disable searching for the crc multi-frame. = 1: enable searching for the crc multi-frame after the basic frame syn chronization is acquired. cntnfas & worderr: these two bits determine the criteria of fas/nfas bit/pattern error generation: ts16c & smfasc: these two bits determine the cr iteria of out of cas signali ng multi-frame synchronization: c2nciwck: = 0: stop searching for crc multi-frame alignm ent pattern in crc to non-crc interworking mode. = 1: enable searching for crc multi-frame alignment pa ttern even if crc to non-crc interworking has been declared. bit no. 7 6 5 4 3 2 1 0 bit name bit2c casen crcen cntnfas word err ts16c smfasc c2nciwck type r/w r/w r/w r/w r/w r/w r/w r/w default 11 1 0 0 0 0 0 worderr cntnfas error generation 0 0 each bit error in fas is counted as an error event. 1 0 a fas pattern error is counted as an error event. 0 1 each bit error in fas or nfas error is counted as an error event. 1 1 a fas pattern error or nfas erro r is counted as an error event. ts16c smfasc out of cas signaling multi-frame synchronization criteria x 0 2 consecutive cas signaling multi-frame alignment pattern errors occur. 0 1 2 consecutive cas signaling multi-frame alignment pattern errors occur or all the contents in ts16 are zeros for one signaling multi-frame. 1 1 2 consecutive cas signaling multi-frame alignment pattern er rors occur or all the contents in ts16 are zeros for two consecutive signaling multi-frames.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 268 march 22, 2004 e1 frmr status (04fh, 14fh, 24fh, 34fh) c2nciwv: = 0: the frame processor does not operat e in crc to non-crc interworking mode. = 1: the frame processor operates in crc to non-crc interworking mode. oosmfv: = 0: the cas signaling multi- frame is in synchronization. = 1: the cas signaling multi-fr ame is out of synchronization. oocmfv: = 0: the crc multi-frame is in synchronization. = 1: the crc multi-frame is out of synchronization. ooofv: = 0: the offline basic fr ame is in synchronization. = 1: the offline basic fram e is out of synchronization. oofv: = 0: the basic frame is in synchronization. = 1: the basic frame is out of synchronization. bit no. 7 6 5 4 3 2 1 0 bit name reserved c2nciwv oosmfv oocmfv ooofv oofv type rrrrr default 01101
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 269 march 22, 2004 e1 frmr interru pt control 0 (050h, 150h, 250h, 350h) c2nciwe: = 0: disable the interrupt on the int pin when the c2nciwi bit (b4, e1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the c2nciwi bit (b4, e1-052h,...) is ?1?. oosmfe: = 0: disable the interrupt on the int pin when the oosmfi bit (b3, e1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the oosmfi bit (b3, e1-052h,...) is ?1?. oocmfe: = 0: disable the interrupt on the int pin when the oocmfi bit (b2, e1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the oocmfi bit (b2, e1-052h,...) is ?1?. ooofe: = 0: disable the interrupt on the int pin when the ooofi bit (b1, e1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the ooofi bit (b1, e1-052h,...) is ?1?. oofe: = 0: disable the interrupt on the int pin when the oofi bit (b0, e1-052h,...) is ?1?. = 1: enable the interrupt on the int pin when the oofi bit (b0, e1-052h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved c2nciwe oosmfe oocmfe ooofe oofe type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 270 march 22, 2004 e1 frmr interru pt control 1 (051h, 151h, 251h, 351h) ismfpe: = 0: disable the interrupt on the int pin when the ismfpi bit (b4, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the ismfpi bit (b4, t1/j1-053h,...) is ?1?. icsmfpe: = 0: disable the interrupt on the int pin when the icsmfpi bit ( b3, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the icsmfpi bit (b3, t1/j1-053h,...) is ?1?. smfere: = 0: disable the interrupt on the int pin when the smferi bit (b2, e1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the smferi bit (b2, e1-053h,...) is ?1?. icmfpe: = 0: disable the interrupt on the int pin when the icmfpi bit (b2, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the icmfpi bit (b2, t1/j1-053h,...) is ?1?. cmfere: = 0: disable the interrupt on the int pin when the cmferi bit (b2, e1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the cmferi bit (b2, e1-053h,...) is ?1?. crcee: = 0: disable the interrupt on the int pin when the crcei bit ( b2, t1/j1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the crcei bit (b2, t1/j1-053h,...) is ?1?. fere: = 0: disable the interrupt on the int pin when the feri bit (b1, e1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the feri bit (b1, e1-053h,...) is ?1?. cofae: = 0: disable the interrupt on the int pin when the cofai bit (b0, e1-053h,...) is ?1?. = 1: enable the interrupt on the int pin when the cofai bit (b0, e1-053h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name ismfpe icsmfpe smfere icmfpe cmfere crcee fere cofae type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 271 march 22, 2004 e1 frmr interrupt indication 0 (052h, 152h, 252h, 352h) excrceri: when crc multi-frame is synchronized, once the ac cumulated crc-4 errors are not less than 915 ( 915) in a 1 second fixed window, an excessive crc-4 error event is generated. du ring out of crc multi-frame synchronization state, the excessive crc-4 error detect ion is suspended. = 0: no excessive crc-4 error event is detected. = 1: the excessive crc-4 error event is detected. this bit will be cleared if a ?1? is written to it. c2nciwi: = 0: there is no status change on the c2nciwv bit (b4, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the c2nciwv bit (b4, e1-04fh,...). this bit will be cleared if a ?1? is written to it. oosmfi: = 0: there is no status change on the oosmfv bit (b3, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the oosmfv bit (b3, e1-04fh,...). this bit will be cleared if a ?1? is written to it. oocmfi: = 0: there is no status change on the oocmfv bit (b2, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the oocmfv bit (b2, e1-04fh,...). this bit will be cleared if a ?1? is written to it. ooofi: = 0: there is no status change on the ooofv bit (b1, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the ooofv bit (b1, e1-04fh,...). this bit will be cleared if a ?1? is written to it. oofi: = 0: there is no status change on the oofv bit (b0, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the oofv bit (b0, e1-04fh,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved excrceri c2nciwi oosm fi oocmfi ooofi oofi type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 272 march 22, 2004 e1 frmr interrupt indication 1 (053h, 153h, 253h, 353h) ismfpi: = 0: the received bit is not the firs t bit of each cas signaling multi-frame. = 1: the first bit of each cas signaling multi-frame is received. this bit will be cleared if a ?1? is written to it. it can not be updated during out of cas si gnaling multi-frame synchronizati on state icsmfpi: = 0: the received bit is not the fi rst bit of each crc sub multi-frame. = 1: the first bit of each crc sub multi-frame is received. this bit will be cleared if a ?1? is written to it. it can not be updated during out of crc multi-frame synchronization state. smferi: when signaling multi-frame is sync hronized, the received signaling multi-frame ali gnment signals are compared with the expected one (?0000?). when one or more bits do not match, a singl e cas signaling multi-frame alignment pattern error event is generated. during out o f cas signaling multi-frame synchronization state, the cas signaling multi-frame alignm ent pattern error detection is suspended. = 0: no cas signaling multi-frame ali gnment pattern error event is detected. = 1: the cas signaling multi-frame ali gnment pattern error event is detected. this bit will be cleared if a ?1? is written to it. icmfpi: = 0: the received bit is not the first bit of each crc multi-frame. = 1: the first bit of each crc multi-frame is received. this bit will be cleared if a ?1? is written to it. it can not be updated during out of crc multi-frame synchronization state. cmferi: when crc multi-frame is synchronized, the received crc multi- frame alignment signals are com pared with the expected one (?00101 1?). if one or more bits do not match, a single crc multi-frame alignment pattern error event is generated. during out of crc multi-frame s ynchronization state, the crc multi-frame alignmen t pattern error detection is suspended. = 0: no crc multi-frame alignment pattern error event is detected. = 1: the crc multi-frame alignmen t pattern error event is detected. this bit will be cleared if a ?1? is written to it. crcei: when crc multi-frame is synchronized and the local calculated crc-4 of the current rece ived crc sub multi-frame does not match the received crc-4 of the next received crc sub multi-frame, a single crc-4 error event is generated. during out of crc multi-frame synchronization state, the crc-4 error detection is suspended. = 0: no crc-4 error event is detected. = 1: the crc-4 error event is detected. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name ismfpi icsmfpi smferi icmfpi cmferi crcei feri cofai type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 273 march 22, 2004 feri: when basic frame is synchronized and the criteria set by the wo rderr bit (b3, e1-04eh,...) and the cntnfas bit (b4, e1-04eh,... ) are met, a fas/nfas bit/pattern error event is generated. during out of ba sic frame synchronization state, the fas/nfas bit/pattern error detection is sus- pended. = 0: no fas/nfas bit/pattern error event is detected. = 1: the fas/nfas bit/pattern error event is detected. this bit will be cleared if a ?1? is written to it. cofai: = 0: the basic frame alignment pattern position is not changed. = 1: the new-found basic frame alignment patte rn position differs fr om the previous one. this bit will be cleared if a ?1? is written to it. e1 ts0 international / national (054h, 154h, 254h, 354h) si0: this bit reflects the content in the international bit of the latest received nfas frame. it is updated on the boundary of the associated nfas frame and is held during out of basic frame state. si1: this bit reflects the content in the international bit of the latest received fas frame. it is updated on the boundary of the a ssociated fas frame and is held during out of basic frame state. a: this bit reflects the content in the remote alarm indicati on bit of the latest received nfas frame. it is updated on the bounda ry of the associated nfas frame and is held during out of basic frame state. sa[4:8]: these bits reflect the content in the nati onal bit of the latest received nfas frame. they are updated on the boundary of the a ssociated nfas frame and are held during out of basic frame state. bit no. 7 6 5 4 3 2 1 0 bit name si0 si1 a sa4 sa5 sa6 sa7 sa8 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 274 march 22, 2004 e1 ts16 spare (055h, 155h, 255h, 355h) x[0:2]: these bits reflect the content in the ex tra bits. they are updated at the first bit of the next cas signaling multi-frame and a re held during out of cas signaling multi-frame state. y: this bit reflects the content in the remote signaling multi-fr ame alarm indication bit. it is updated at the first bit of the n ext cas signaling multi- frame and is held during out of cas signaling multi-frame state. e1 sa4 codeword (056h, 156h, 256h, 356h) sa4[1:4]: these bits reflect the content in the sa4 national bit codeword. if de-bounce is enabled by the sadeb bit (b6, e1-05ch,...), they are updated when the re ceived sa4 national bit codeword is the same for 2 consecutive crc sub multi-frames. if de-bounce is disabled, they are updated every crc sub multi-frame. these bits are held dur ing out of crc multi-frame synchronization state. bit no. 7 6 5 4 3 2 1 0 bit name reserved x0 y x1 x2 type rrrr default 0000 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa41 sa42 sa43 sa44 type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 275 march 22, 2004 e1 sa5 codewo3rd (057h, 157h, 257h, 357h) sa5[1:4]: these bits reflect the content in the sa5 national bit codeword. if de-bounce is enabled by the sadeb bit (b6, e1-05ch,...), they are updated when the re ceived sa5 national bit codeword is the same for 2 consecutive crc sub multi-frames. if de-bounce is disabled, they are updated every crc sub multi-frame. these bits are held dur ing out of crc multi-frame synchronization state. e1 sa6 codeword (058h, 158h, 258h, 358h) sa6[1:4]: these bits reflect the content in the sa6 national bit codeword. if de-bounce is enabled by the sadeb bit (b6, e1-05ch,...), they are updated when the re ceived sa6 national bit codeword is the same for 2 consecutive crc sub multi-frames. if de-bounce is disabled, they are updated every crc sub multi-frame. these bits are held dur ing out of crc multi-frame synchronization state. bit no. 7 6 5 4 3 2 1 0 bit name reserved sa51 sa52 sa53 sa54 type rrrr default 0000 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa61 sa62 sa63 sa64 type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 276 march 22, 2004 e1 sa7 codeword (059h, 159h, 259h, 359h) sa7[1:4]: these bits reflect the content in the sa7 national bit codeword. if de-bounce is enabled by the sadeb bit (b6, e1-05ch,...), they are updated when the re ceived sa7 national bit codeword is the same for 2 consecutive crc sub multi-frames. if de-bounce is disabled, they are updated every crc sub multi-frame. these bits are held dur ing out of crc multi-frame synchronization state. e1 sa8 codeword (05ah, 15ah, 25ah, 35ah) sa8[1:4]: these bits reflect the content in the sa8 national bit codeword. if de-bounce is enabled by the sadeb bit (b6, e1-05ch,...), they are updated when the re ceived sa8 national bit codeword is the same for 2 consecutive crc sub multi-frames. if de-bounce is disabled, they are updated every crc sub multi-frame. these bits are held dur ing out of crc multi-frame synchronization state. bit no. 7 6 5 4 3 2 1 0 bit name reserved sa71 sa72 sa73 sa74 type rrrr default 0000 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa81 sa82 sa83 sa84 type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 277 march 22, 2004 e1 sa6 codeword indication (05bh, 15bh, 25bh, 35bh) sa6-fi: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame are not matched with 0xfff . = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame ar e matched with 0xfff. sa6-ei: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame are not matched with 0xeee . = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame ar e matched with 0xeee. sa6-ci: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the c rc sub multi-frame are not matched with 0xccc . = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame ar e matched with 0xccc. sa6-ai: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame are not matched with 0xaaa . = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame ar e matched with 0xaaa. sa6-8i: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the c rc sub multi-frame are not matched with 0x888 . = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the crc sub multi-frame are matched with 0x888. bit no. 7 6 5 4 3 2 1 0 bit name reserved sa6-fi sa6-ei sa6-ci sa6-ai sa6-8i type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 278 march 22, 2004 e1 sa codeword interrupt control (05ch, 15ch, 25ch, 35ch) sa6syn: = 0: any 12 consecutive sa6 bits are com pared with 0x888, 0xaaa, 0xccc, 0xeee and 0x fff when crc multi-fr ame is synchronized. = 1: any 3 consecutive 4-bit sa6 codewords in the crc sub mu lti-frame are compared with 0x888, 0xaaa, 0xccc, 0xeee and 0xfff wh en crc multi-frame is synchronized. sadeb: = 0: disable the de-bounce function of the national bit codeword extraction. = 1: enable the de-dounce function of the national bit codeword extraction. sa6sce: = 0: disable the interrupt on the int pin when the scai bit (b3, t1/j1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the scai bit (b3, t1/j1-05dh,...) is ?1?. sa4e: = 0: disable the interrupt on the int pin when the sa4i bit (b2, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the sa4i bit (b2, e1-05dh,...) is ?1?. sa5e: = 0: disable the interrupt on the int pin when the sa5i bit (b2, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the sa5i bit (b2, e1-05dh,...) is ?1?. sa6e: = 0: disable the interrupt on the int pin when the sa6i bit (b2, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the sa6i bit (b2, e1-05dh,...) is ?1?. sa7e: = 0: disable the interrupt on the int pin when the sa7i bit (b2, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the sa7i bit (b2, e1-05dh,...) is ?1?. sa8e: = 0: disable the interrupt on the int pin when the sa8i bit (b2, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the sa8i bit (b2, e1-05dh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name sa6syn sadeb sa6sce sa4e sa5e sa6e sa7e sa8e type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 279 march 22, 2004 e1 sa codeword interrupt indication (05dh, 15dh, 25dh, 35dh) sa6sci: = 0: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the c rc sub multi-frame are not matched with 0x888 , 0xaaa, 0xccc, 0xeee or 0xfff. = 1: any 12 consecutive sa6 bits or any 3 consecutive 4-bit sa6 codewords in the cr c sub multi-frame are matched with 0x888, 0x aaa, 0xccc, 0xeee or 0xfff. sa4i: = 0: the value in the sa4[1:4] bits is not changed. = 1: the value in the sa4[1:4] bits is changed. sa5i: = 0: the value in the sa5[1:4] bits is not changed. = 1: the value in the sa5[1:4] bits is changed. sa6i: = 0: the value in the sa6[1:4] bits is not changed. = 1: the value in the sa6[1:4] bits is changed. sa7i: = 0: the value in the sa7[1:4] bits is not changed. = 1: the value in the sa7[1:4] bits is changed. sa8i: = 0: the value in the sa8[1:4] bits is not changed. = 1: the value in the sa8[1:4] bits is changed. bit no. 7 6 5 4 3 2 1 0 bit name reserved sa6sci sa4i sa5i sa6i sa7i sa8i type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 280 march 22, 2004 e1 overhead error status (05fh, 15fh, 25fh, 35fh) raicrcv: the continuous rai & febe error event is detect ed on the base of crc multi-frame synchronization. = 0: no continuous rai & febe error event is detected. = 1: the continuous rai & febe error event is detected, i.e., a logic 1 is received in the a bit and a logic 0 is received in a ny of the e1 and e2 bits for 10ms. cfebev: the continuous febe error event is detected on the base of crc multi-frame synchronization. = 0: no continuous febe error event is detected. = 1: the continuous febe error event is detected, i.e., a logic 0 is received in any of the e1 or e2 bit on 990 occasions per second for the lat- est 5 consecutive seconds. v52linkv: the v5.2 link id signal can be received on the base of basic frame synchronization. = 0: the v5.2 link id signal is not received. = 1: the v5.2 link id signal is received, i.e ., 2 out of 3 sliding sa7 bits are logic 0s. bit no. 7 6 5 4 3 2 1 0 bit name reserved raicrcv cfebev v52linkv type rrr default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 281 march 22, 2004 e1 overhead interrupt control (060h, 160h, 260h, 360h) tcrcee: = 0: disable the interrupt on the int pin when the tcrcei bit (b3, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the tcrcei bit (b3, e1-05dh,...) is ?1?. tfebee: = 0: disable the interrupt on the int pin when the tfebei bit (b3, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the tfebei bit (b3, e1-05dh,...) is ?1?. febee: = 0: disable the interrupt on the int pin when the febei bit (b3, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the febei bit (b3, e1-05dh,...) is ?1?. raicrce: = 0: disable the interrupt on the int pin when the raicrci bit (b3, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the raicrci bit (b3, e1-05dh,...) is ?1?. cfebee: = 0: disable the interrupt on the int pin when the cfebei bit (b3, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the cfebei bit (b3, e1-05dh,...) is ?1?. v52linke: = 0: disable the interrupt on the int pin when the v52linki bit (b0, e1-05dh,...) is ?1?. = 1: enable the interrupt on the int pin when the v52linki bit (b0, e1-05dh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved tcrcee tfebee febee raicrce cfebee v52linke type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 282 march 22, 2004 e1 overhead interrupt indication (061h, 161h, 261h, 361h) tcrcei: if the 4-bit sa6 codeword of a crc sub mult i-frame is matched with ?0010? or ?0011?, the network terminal crc error event is ge nerated. = 0: no nt crc error event is detected. = 1: the nt crc error event is detected. this bit will be cleared if a ?1? is written to it. tfebei: if the 4-bit sa6 codeword of a crc sub multi- frame is matched with ?0001? or ?0011?, the network terminal far end block error e vent is gener- ated. = 0: no nt febe error event is detected. = 1: the nt febe error event is detected. this bit will be cleared if a ?1? is written to it. febei: when crc multi-frame is synchronized and any of the crc error indication (e1 or e2) bi ts is received as a logic 0, a far end bl ock error event is generated. during out of crc multi-frame synchronization state, the far end block error (febe) detection is suspended. = 0: no far end block error (febe) event is detected. = 1: the far end block error (febe) event is detected. this bit will be cleared if a ?1? is written to it. raicrci: = 0: there is no status change on the raicrcv bit (b, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the raicrcv bit (b2, e1-04fh,...). this bit will be cleared if a ?1? is written to it. cfebei: = 0: there is no status change on the cfebev bit (b, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the cfebev bit (b, e1-04fh,...). this bit will be cleared if a ?1? is written to it. v52linki: = 0: there is no status change on the v52linkv bit (b, e1-04fh,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the v52linkv bit (b, e1-04fh,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved tcrcei tfebei febei raicrci cfebei v52linki type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 283 march 22, 2004 e1 mode (062h, 162h, 262h, 362h) xdis: this bit is valid when the si gnaling multi-frame is generated. = 0: the extra bits (the bit 5, 7 & 8 of ts16 of frame 0 of t he signaling multi-frame) are replaced by the value set in the x[0 :2] bits (b3 & b1~0, e1-06ah,...). = 1: disable the extra bits to be replaced by the value set in the x[0:2] bits (b3 & b1~0, e1-06ah,...). sidis: when the basic frame is generated, this bit deter mines how to replace the international bit. = 0: the international bit (bit 1) of fas frame and nfas frame are replaced by the value set in the si[1] (b0, e1-063h,...) and si[0] bits (b1, e1- 063h,...) respectively. = 1: disable the international bit (bit 1) of fas frame and nfas frame to be replaced by the value set in the si[1] (b0, e1-063 h,...) and si[0] bits (b1, e1-063h,...) respectively. when the crc multi-frame is generated, this bit, together with th e febedis bit (b4, e1-062h,...) and the oocmfv bit (b2, e1-04f h,...), deter- mines how to replace the e bit (refer to the description of the febedis bit). . febedis: when the crc multi-frame is generated, this bit, together with the sidis bit (b5, e1 -062h,...) and the oocmfv bit (b2, e1-04fh, ...), determines how to replace the e bit. bit no. 7 6 5 4 3 2 1 0 bit name reserved xdis sidis febedis crcm sigen gencrc fdis type r/w r/w r/w r/w r/w r/w r/w default 000 0 1 1 0 febedis (b4, e1-062h,...) oocmfv (b2, e1-04fh,...) sidis (b5, e1-062h,...) e bits insertion 00x a single zero is inserted into the e bit when a crc-4 error event is detected in the receive path. (the e1 bit corresponds to smfi and the e2 bit corresponds to smfii) 01x the value in the si[1] bit (b0, e1-063h,...) is inserted into the e1 bit posi- tion. the value in the si[0] bit (b1, e1-063h,...) is inserted into the e2 bit position. 1x0 the value in the si[1] bit (b0, e1-063h,...) is inserted into the e1 bit posi- tion. the value in the si[0] bit (b1, e1-063h,...) is inserted into the e2 bit position. 1 x 1 the e bit positions are unchanged.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 284 march 22, 2004 crcm, sigen, gencrc: these bits are valid when the fdis bit (b0, e1-062h,...) is 0. they control what kind of frame is generated: fdis: = 0: enable the generation of the basic frame, crc mu lti-frame and channel associated signaling (cas) multi-frame. = 1: disable the generation of the ba sic frame, crc multi-frame and channel associated signaling (cas) multi-frame. e1 fgen international bit (063h, 163h, 263h, 363h) si0: when the basic frame is generated and the sidis bit (b5, e1-062h,...) is ?0?, it contains the value to replace the internationa l bit (bit 1) of the nfas frame. when the crc multi-frame is generated, contro lled by the febedis bit (b4, e1-062h,...), the oocmfv bit (b2, e1-04fh,...) bit an d the sidis bit (b5, e1-062h,...), it contains th e value to replace the e2 bit. si1: when the basic frame is generated and the sidis bit (b5, e1-062h,...) is ?0?, it contains the value to replace the internationa l bit (bit 1) of the fas frame. when the crc multi-frame is generated, contro lled by the febedis bit (b4, e1-062h,...), the oocmfv bit (b2, e1-04fh,...) bit an d the sidis bit (b5, e1-062h,...), it contains th e value to replace the e1 bit. desired frame type gencrc (b1, e1-062h,...) crcm (b3, e1-062h,...) sigen (b2, e1-062h,...) basic frame 0 x x 10x crc multi-frame 1 0 x modified crc multi-frame 1 1 x channel associated signaling (cas) multi-frame 0 x 1 101 bit no. 7 6 5 4 3 2 1 0 bit name reserved si0 si1 type r/w r/w default 11
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 285 march 22, 2004 e1 fgen sa control (064h, 164h, 264h, 364h) sa4en: this bit is valid when t he basic frame is generated. = 0: disable the sa4[1:4] bits to be replaced by t he value set in the sa4[1:4] bits (b3~0, e1-065h,...). = 1: the sa4[1:4] bits are replaced by the val ue set in the sa4[1:4] bits (b3~0, e1-065h,...). sa5en: this bit is valid when t he basic frame is generated. = 0: disable the sa5[1:4] bits to be replaced by t he value set in the sa5[1:4] bits (b3~0, e1-066h,...). = 1: the sa5[1:4] bits are replaced by the val ue set in the sa5[1:4] bits (b3~0, e1-066h,...). sa6en: this bit is valid when t he basic frame is generated. = 0: disable the sa6[1:4] bits to be replaced by t he value set in the sa6[1:4] bits (b3~0, e1-067h,...). = 1: the sa6[1:4] bits are replaced by the val ue set in the sa6[1:4] bits (b3~0, e1-067h,...). sa7en: this bit is valid when t he basic frame is generated. = 0: disable the sa7[1:4] bits to be replaced by t he value set in the sa7[1:4] bits (b3~0, e1-068h,...). = 1: the sa7[1:4] bits are replaced by the val ue set in the sa7[1:4] bits (b3~0, e1-068h,...). sa8en: this bit is valid when t he basic frame is generated. = 0: disable the sa8[1:4] bits to be replaced by t he value set in the sa8[1:4] bits (b3~0, e1-069h,...). = 1: the sa8[1:4] bits are replaced by the val ue set in the sa8[1:4] bits (b3~0, e1-069h,...). bit no. 7 6 5 4 3 2 1 0 bit name reserved sa4en sa5en sa6en sa7en sa8en type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 286 march 22, 2004 e1 sa4 code-word (065h, 165h, 265h, 365h) sa4[1:4]: these bits are valid when the basic fram e is generated and the sa4en bit (b4, e1-064h ,...) is ?1?. when only the basic frame is generated, the value in the sa4[1] bit replaces the sa4 bit. when the crc mult i-frame is generated, they contai n the value to replace the sa4[ 1:4] bits. e1 sa5 code-word (066h, 166h, 266h, 366h) sa5[1:4]: these bits are valid when the basic fram e is generated and the sa5en bit (b3, e1-064h ,...) is ?1?. when only the basic frame is generated, the value in the sa5[1] bit replaces the sa5 bit. when the crc mult i-frame is generated, they contai n the value to replace the sa5[ 1:4] bits. e1 sa6 code-word (067h, 167h, 267h, 367h) sa6[1:4]: these bits are valid when the basic fram e is generated and the sa6en bit (b2, e1-064h ,...) is ?1?. when only the basic frame is generated, the value in the sa6[1] bit replaces the sa6 bit. when the crc mult i-frame is generated, they contai n the value to replace the sa6[ 1:4] bits. bit no. 7 6 5 4 3 2 1 0 bit name reserved sa41 sa42 sa43 sa44 type r/w r/w r/w r/w default 1111 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa51 sa52 sa53 sa54 type r/w r/w r/w r/w default 1111 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa61 sa62 sa63 sa64 type r/w r/w r/w r/w default 1111
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 287 march 22, 2004 e1 sa7 code-word (068h, 168h, 268h, 368h) sa7[1:4]: these bits are valid when the basic fram e is generated and the sa7en bit (b1, e1-064h ,...) is ?1?. when only the basic frame is generated, the value in the sa7[1] bit replaces the sa7 bit. when the crc mult i-frame is generated, they contai n the value to replace the sa7[ 1:4] bits. e1 sa8 code-word (069h, 169h, 269h, 369h) sa8[1:4]: these bits are valid when the basic fram e is generated and the sa8en bit (b0, e1-064h ,...) is ?1?. when only the basic frame is generated, the value in the sa8[1] bit replaces the sa8 bit. when the crc mult i-frame is generated, they contai n the value to replace the sa8[ 1:4] bits. e1 fgen extra (06ah, 16ah, 26ah, 36ah) x[0:2]: these bits are valid when the signaling mult i-frame is generated and the xdis bit (b6, e1-062h,...) is ?0?. they contain the va lue to replace the extra bits (the bit 5, 7 & 8 of ts16 of frame 0 of the signaling multi-frame). bit no. 7 6 5 4 3 2 1 0 bit name reserved sa71 sa72 sa73 sa74 type r/w r/w r/w r/w default 1111 bit no. 7 6 5 4 3 2 1 0 bit name reserved sa81 sa82 sa83 sa84 type r/w r/w r/w r/w default 1111 bit no. 7 6 5 4 3 2 1 0 bit name reserved x0 reserved x1 x2 type r/w r/w r/w default 111
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 288 march 22, 2004 e1 fgen maintenance 0 (06bh, 16bh, 26bh, 36bh) ts16los: = 0: normal operation. = 1: the data stream to be transmitted on ts16 is overwritten with all zeros. ts16ais: = 0: normal operation. = 1: the data stream to be transmitted on ts16 is overwritten with all ?one?s. mfais: this bit is valid when the signaling multi-frame is generated. t he value in this bit will be continuously transmitted in the y bit position (the bit 6 of ts16 of frame 0 of the signaling multi-frame). g706rai: this bit is valid when the basic fr ame is generated. it selects the crit eria for automatic rai transmission. = 0: the rai is transmitted automatically when: 1). out of basi c frame sync is declared in the receive path; 2). the receive pa th is operated in crc-4 to non-crc-4 inter-working mode; 3). t he offline searching in the receive path is out of basic frame sync; 4). the remais bit (b0, e1-06bh,...) is 1. = 1: the rai is transmitted automatically w hen: 1). out of basic frame sync is declared in the receive path; 2). the remais bit (b0, e1-06bh,...) is 1. autoyellow: this bit is valid when t he basic frame is generated. = 0: disable the autom atic rai transmission. = 1: the remote alarm indication (rai) is automatically transmitted as logic 1 in t he a bit position when conditions meet the c riteria selected by the g706rai bit (b2, e1-06bh,...). remais: this bit is valid when t he basic frame is generated. = 0: disable the manual rai transmission. = 1: the remote alarm indication (rai) is manual ly transmitted as logic 1 in the a bit position. bit no. 7 6 5 4 3 2 1 0 bit name reserved ts16los ts16ais mfais g706rai autoyellow remais type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 289 march 22, 2004 e1 fgen maintenance 1 (06ch, 16ch, 26ch, 36ch) cofaen: any transition (from ?0? to ?1? or from ?1? to ?0?) on this bit will lead to one bit deletion or one bit repetition in the data stream to be transmitted, that is, to change the frame alignment position. t he one bit deletion or repetition occurs randomly. txdis: = 0: normal operation. = 1: the data stream to be transmitt ed is overwritten with all ?zero?s. tais: = 0: normal operation. = 1: the data stream to be transmitt ed is overwritten with all ?one?s. bit no. 7 6 5 4 3 2 1 0 bit name reserved cofaen txdis tais type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 290 march 22, 2004 e1 fgen interrupt control (06dh, 16dh, 26dh, 36dh) smfe: = 0: disable the interrupt on the int pin when the smfi bit (b4, e1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the smfi bit (b4, e1-06eh,...) is ?1?. fase: = 0: disable the interrupt on the int pin when the fasi bit (b3, e1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the fasi bit (b3, e1-06eh,...) is ?1?. sigmfe: = 0: disable the interrupt on the int pin when the sigmfi bit (b2, e1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the sigmfi bit (b2, e1-06eh,...) is ?1?. mfe: = 0: disable the interrupt on the int pin when the mfi bit (b1, e1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the mfi bit (b1, e1-06eh,...) is ?1?. bfe: = 0: disable the interrupt on the int pin when the bfi bit (b0, e1-06eh,...) is ?1?. = 1: enable the interrupt on the int pin when the bfi bit (b0, e1-06eh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved smfe fase sigmfe mfe bfe type r/w r/w r/w r/w r/w default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 291 march 22, 2004 e1 fgen interrupt indication (06eh, 16eh, 26eh, 36eh) smfi: = 0: the bit input to the frame generator is not the first bit of eac h crc sub multi-frame. = 1: the first bit of each crc sub multi- frame is input to the frame generator. this bit will be cleared if a ?1? is written to it. fasi: = 0: the bit input to the frame generat or is not the first bit of each fas. = 1: the first bit of each fas is input to the frame generator. this bit will be cleared if a ?1? is written to it. sigmfi: = 0: the bit input to the frame generator is not the first bit of each signaling multi-frame. = 1: the first bit of each signaling multi- frame is input to the frame generator. this bit will be cleared if a ?1? is written to it. mfi: = 0: the bit input to the frame generator is not the first bit of each crc multi-frame. = 1: the first bit of each crc multi-fr ame is input to the frame generator. this bit will be cleared if a ?1? is written to it. bfi: = 0: the bit input to the frame generator is not the first bit of each basic frame. = 1: the first bit of each basic fram e is input to the frame generator. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved smfi fasi sigmfi mfi bfi type rrrrr default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 292 march 22, 2004 e1 error insertion (06fh, 16fh, 26fh, 36fh) crcinv: this bit is valid when the crc multi-frame or the modified crc multi-frame is generated. a transition from ?0? to ?1? on this bit will inve rt all 4 calculated crc bits in one sub-multi-frame. this bit is cleared when the inversion is completed. crcpinv: this bit is valid when the crc multi-frame is generated. a transition from ?0? to ?1? on this bit will invert one 6-bit crc multi-frame alignment pattern (?001011?). this bit is cleared when the inversion is completed. caspinv: this bit is valid when the cas multi-frame is generated. a transition from ?0? to ?1? on this bit will invert on e 4-bit signaling multi-fram e alignment pattern (?0000?). this bit is cleared when the inversion is completed. nfasinv: this bit is valid when t he basic frame is generated. a transition from ?0? to ?1? on this bit will invert one nfas bit (the bit 2 of ts0 of each odd frame). this bit is cleared when the inversion is completed. fasallinv: this bit is valid when t he basic frame is generated. a transition from ?0? to ?1? on this bit will invert one 7- bit fas pattern (the bit 2 ~ bit 8 of ts0 of each even frame). this bit is cleared when the inversion is completed. fas1inv: this bit is valid when t he basic frame is generated. a transition from ?0? to ?1? on this bit will invert on e fas bit (the bit 2 ~ bit 8 of ts0 of each even frame). this bit is cleared when the inversion is completed. bit no. 7 6 5 4 3 2 1 0 bit name reserved crcinv crcpinv caspinv nfasinv fasallinv fas1inv type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 293 march 22, 2004 e1 transmit timing option (070h, 170h, 270h, 370h) xts: in transmit clock master mode: = 0: the source of the transmit clock is selected from t he clock generated by the internal clock generator (2.048 mhz). = 1: the source of the transmit clock is select ed from the recovered clock from the line side. in transmit clock master mode, the trans mit buffer is bypassed automatically. in transmit clock slave mode and in transmit multiplexed mode: = 0: the source of the transmit clock is selected from t he clock from the backplane. t he transmit buffer is bypassed. = 1: the source of the transmit clock is selected from the clock generated by the inter nal clock generator (2.048 mhz). the tra nsmit buffer is not bypassed. e1 prgd control (071h, 171h, 271h, 371h) rinv: = 0: the data is not inverted before extracted to the pattern detector. = 1: the data is inverted before extracted to the pattern detector. tinv: = 0: the generated pattern is not inverted. = 1: the generated pattern is inverted. pats[1:0]: these bits select the prbs generated and detected pattern. = 00: the 2 15 -1 pattern per o.152 is selected. = 01: the 2 20 -1 pattern per o.150-4.5 is selected. = 10: the 2 11 -1 pattern per o.150 is selected. = 11: reserved. bit no. 7 6 5 4 3 2 1 0 bit name reserved xts type r/w default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved rinv tinv pats1 pats0 type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 294 march 22, 2004 e1 prgd status/error control (072h, 172h, 272h, 372h) bere: = 0: disable the interrupt on the int pin when the beri bit (b3, e1-073h,...) is ?1?. = 1: enable the interrupt on the int pin when the beri bit (b3, e1-073h,...) is ?1?. inv: = 0: no bit error is inserted to the generated pattern. = 1: a single bit error is inserted to the generated pattern. this bit is cleared after the single bit error insertion is completed. syncv: = 0: the pattern is out of synchronization (the pattern detector has detected 10 or more bit errors in a fixed 48-bit window). = 1: the pattern is in synchronization (the pattern detector has detected at leas t 48 consecutive erro r-free bit periods). synce: = 0: disable the interrupt on the int pin when the synci bit (b0, e1-073h,...) is ?1?. = 1: enable the interrupt on the int pin when the synci bit (b0, e1-073h,...) is ?1?. e1 prgd interrupt indication (073h, 173h, 273h, 373h) beri: = 0: no bit is mismatched with the prgd pattern when the extracted data is in synchronization state. = 1: at least one bit is mismatched with the prgd patte rn when the extracted data is in synchronization state. this bit will be cleared if a ?1? is written to it. synci: = 0: there is no status change on the syncv bit (b1, e1-072h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the syncv bit (b1, e1-072h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved bere inv syncv synce type r/w r/w r r/w default 0000 bit no. 7 6 5 4 3 2 1 0 bit name reserved beri reserved synci type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 295 march 22, 2004 e1 elst configuration (07ch, 17ch, 27ch, 37ch) trken: in receive clock slave mode and receive multiplexed mode, if it is out of synchronization, the trunk code programmed in the trk code[7:0] bits (b7~0, e1-07eh,...) can be set to replace the data or not. = 0: disable the replacement. = 1: enable the replacement. slipd: this bit makes sense only when the slipi bit (b0, e1-07dh,...) is ?1?. = 0: the latest slip is due to the elastic store buffer being empty. = 1: the latest slip is due to the elastic store buffer being full. slipe: = 0: disable the interrupt on the int pin when the slipi bit (b0, e1-07dh,...) is ?1?. = 1: enable the interrupt on the int pin when the slipi bit (b0, e1-07dh,...) is ?1?. e1 elst interrupt indication (07dh, 17dh, 27dh, 37dh) slipi: = 0: no slip occurs. = 1: a slip occurs. this bit will be cleared if a ?1? is written to it. e1 elst trunk code (07eh, 17eh, 27eh, 37eh) trkcode[7:0]: in receive clock slave mode and receive multiplexed mode, if it is out of synchronization and the trken bit (b2, e1-07ch,...) i s ?1?, these bits are the trunk codes to replace the received data stream. bit no. 7 6 5 4 3 2 1 0 bit name reserved trken slipd slipe type r/w r r/w default 000 bit no. 7 6 5 4 3 2 1 0 bit name reserved slipi type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name trkcode7 trkcode6 trkcode5 trkcode4 trkcode3 trkcode2 trkcode1 trkcode0 type r/w r/w r/w r/w r/w r/w r/w r/w default 11 1 1 1 1 1 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 296 march 22, 2004 e1 thdlc enable control (084h, 184h, 284h, 384h) tdlen3: = 0: all the functions of the hdlc transmitter #3 is disabled. = 1: all the functions of t he hdlc transmitter #3 is enabled. tdlen2: = 0: all the functions of the hdlc transmitter #2 is disabled. = 1: all the functions of t he hdlc transmitter #2 is enabled. tdlen1: = 0: all the functions of the hdlc transmitter #1 is disabled. = 1: all the functions of t he hdlc transmitter #1 is enabled. bit no. 7 6 5 4 3 2 1 0 bit name reserved tdlen3 tdlen2 tdlen1 type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 297 march 22, 2004 e1 thdlc1 assignment (085h, 185h, 285h, 385h) e1 thdlc2 assignment (086h, 186h, 286h, 386h) e1 thdlc3 assignment (087h, 187h, 287h, 387h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. even: = 0: the data is not inserted to the even frames. = 1: the data is inserted to the even frames. odd: = 0: the data is not inserted to the odd frames. = 1: the data is inserted to the odd frames. ts[4:0]: these bits binary define one timeslot of ev en and/or odd frames to insert the data to . they are invalid when the even bit and t he odd bit are both ?0?. bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 298 march 22, 2004 e1 thdlc1 bit select (088h, 188h, 288h, 388h) e1 thdlc2 bit select (089h, 189h, 289h, 389h) e1 thdlc3 bit select (08ah, 18ah, 28ah, 38ah) the function of the above three sets of registers are the same. however, they correspond to different thdlc. bitenn: = 0: the data is not inserted to the corresponding bit. = 1: the data is inserted to the corresponding bit of the assigned timeslot. these bits are invalid when the even bit and the odd bit are both logic 0. the biten[7] bit corresponds to the firs t bit (msb) of the selected timeslot. bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 299 march 22, 2004 e1 rhdlc enable control (08bh, 18bh, 28bh, 38bh) rdlen3: = 0: all the functions of the hdlc receiver #3 is disabled. = 1: all the functions of the hdlc receiver #3 is enabled. rdlen2: = 0: all the functions of the hdlc receiver #2 is disabled. = 1: all the functions of the hdlc receiver #2 is enabled. rdlen1: = 0: all the functions of the hdlc receiver #1 is disabled. = 1: all the functions of the hdlc receiver #1 is enabled. bit no. 7 6 5 4 3 2 1 0 bit name reserved rdlen3 rdlen2 rdlen1 type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 300 march 22, 2004 e1 rhdlc1 assignment (08ch, 18ch, 28ch, 38ch) e1 rhdlc2 assignment (08dh, 18dh, 28dh, 38dh) e1 rhdlc3 assignment (08eh, 18eh, 28eh, 38eh) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. even: = 0: the data is not extracted from the even frames. = 1: the data is extracted from the even frames. the even frames are fas frames. odd: = 0: the data is not extracted from the odd frames. = 1: the data is extracted from the odd frames. the odd frames are nfas frames. ts[4:0]: these bits binary define one timeslot of even and/or odd frames to extract the data fr om. they are invalid when the even bit an d the odd bit are both ?0?. bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved even odd ts4 ts3 ts2 ts1 ts0 type r/w r/w r/w r/w r/w r/w r/w default 000 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 301 march 22, 2004 e1 rhdlc1 bit select (08fh, 18fh, 28fh, 38fh) e1 rhdlc2 bit select (090h, 190h, 290h, 390h) e1 rhdlc3 bit select (091h, 191h, 291h, 391h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. bitenn: = 0: the data is not extracted from the corresponding bit. = 1: the data is extracted from t he corresponding bit of the assigned channel. these bits are invalid when the even bit and the odd bit are both logic 0. the biten[7] bit corresponds to the fi rst bit (msb) of the selected channel. bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name biten7 biten6 biten5 biten4 biten3 biten2 biten1 biten0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 302 march 22, 2004 e1 rhdlc1 control register (092h, 192h, 292h, 392h) e1 rhdlc2 control register (093h, 193h, 293h, 393h) e1 rhdlc3 control register (094h, 194h, 294h, 394h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. lssufil: this bit is valid when the ss7 packet is lssu. = 0: the current lssu is not compared with the previous one. = 1: the current lssu is compared with the previous one. the current lssu will be discar ded if it is the same with the previous lssu. fisufil: this bit is valid when the ss7 packet is fisu. = 0: the current fisu is not compared with the previous one. = 1: the current fisu is compared with the previous one. the current fisu will be discarded if it is the same with the previous fisu. adrm[1:0]: these two bits select the addres s comparison mode in hdlc mode. = 00: no address is compared. = 01: high byte address is compared. = 10: low byte address is compared. = 11: both high byte address and low byte address are compared. rhdlcm: = 0: hdlc mode is selected. = 1: ss7 mode is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved lssufil fisufil adrm1 adrm0 rhdlcm rrst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 303 march 22, 2004 rrst: a transition from ?0? to ?1? on the this bit will reset the co rresponding hdlc receiver. the reset will clear the fifo, the pac k bit (b0, e1-095h,... / 096h,... / 097h,...) and the emp bit (b1, e1-095h,... / 096h,... / 097h,...). e1 rhdlc1 rfifo access status (095h, 195h, 295h, 395h) e1 rhdlc2 rfifo access status (096h, 196h, 296h, 396h) e1 rhdlc3 rfifo access status (097h, 197h, 297h, 397h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. emp: = 0: all valid hdlc/ss7 blocks are pushed into the fifo. = 1: the fifo is empty, i.e., all the blocks are read from the fifo. the corresponding hdlc receiver reset will clear this bit. pack: = 0: the byte read from the fifo is not an overhead byte. = 1: the byte read from the fifo is an overhead byte. the corresponding hdlc receiver reset will clear this bit. bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10 bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10 bit no. 7 6 5 4 3 2 1 0 bit name reserved emp pack type rr default 10
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 304 march 22, 2004 e1 rhdlc1 data (098h, 198h, 298h, 398h) e1 rhdlc2 data (099h, 199h, 299h, 399h) e1 rhdlc3 data (09ah, 19ah, 29ah, 39ah) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. dat[7:0]: these bits represent the bytes read from t he fifo. the dat[0] bit corresponds to the first bit of the serial received data from the fifo. bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 305 march 22, 2004 e1 rhdlc1 interrupt control (09bh, 19bh, 29bh, 39bh) e1 rhdlc2 interrupt control (09ch, 19ch, 29ch, 39ch) e1 rhdlc3 interrupt control (09dh, 19dh, 29dh, 39dh) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ovfle: = 0: disable the interrupt on the int pin when the ovfli bit (b1, e1- 09eh,... / 09fh,... / 0a0h,...) is ?1?. = 1: enable the interrupt on the int pin when the ovfli bit (b1, e1-0 9eh,... / 09fh,... / 0a0h,...) is ?1?. rmbee: = 0: disable the interrupt on the int pin when the rmbei bit (b0, e1-0 9eh,... / 09fh,... / 0a0h,...) is ?1?. = 1: enable the interrupt on the int pin when the rmbei bit (b0, e1-09eh,... / 09fh,... / 0a0h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfle rmbee type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 306 march 22, 2004 e1 rhdlc1 interrupt indication (09eh, 19eh, 29eh, 39eh) e1 rhdlc2 interrupt indication (09fh, 19fh, 29fh, 39fh) e1 rhdlc3 interrupt indication (0a0h, 1a0h, 2a0h, 3a0h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ovfli: the overwritten condition will occur if data is still attempted to write into the fifo when the fifo has already been full (128 bytes). = 0: no overwriting occurs. = 1: the overwriting occurs. this bit will be cleared if a ?1? is written to it. rmbei: = 0: no block is pushed into the fifo. = 1: a block of the hdlc/ss7 packet is pushed into the fifo. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved ovfli rmbei type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 307 march 22, 2004 e1 rhdlc1 high address (0a1h, 1a1h, 2a1h, 3a1h) e1 rhdlc2 high address (0a2h, 1a2h, 2a2h, 3a2h) e1 rhdlc3 high address (0a3h, 1a3h, 2a3h, 3a3h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. ha[7:0]: in hdlc mode, when high byte address comparison or both bytes address comparison is required, t he high byte address position (t he byte fol- lowing the opening flag) is compared with the va lue in these bits, or with ?0xfc? or ?0xfe?. the ha[1] bit (the ?c/r? bit posit ion) is excluded to compare. bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name ha7 ha6 ha5 ha4 ha3 ha2 ha1 ha0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 308 march 22, 2004 e1 rhdlc1 low address (0a4h, 1a4h, 2a4h, 3a4h) e1 rhdlc2 low address (0a5h, 1a5h, 2a5h, 3a5h) e1 rhdlc3 low address (0a6h, 1a6h, 2a6h, 3a6h) the function of the above three sets of registers are the same. however, they correspond to different rhdlc. la[7:0]: in hdlc mode, when low byte address compar ison is required, the high byte address pos ition (the byte following the opening flag ) is compared with the value in these bits. when both bytes address comparison is required, the low byte address position (the byte following the high byte address position) is compared with the value in these bits. bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name la7 la6 la5 la4 la3 la2 la1 la0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 309 march 22, 2004 e1 thdlc1 control (0a7h, 1a7h, 2a7h, 3a7h) e1 thdlc2 control (0a8h, 1a8h, 2a8h, 3a8h) e1 thdlc3 control (0a9h, 1a9h, 2a9h, 3a9h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. autofisu: this bit is valid in ss7 mode when there is no data in the fifo to be transmitted. = 0: normal operation. = 1: the 7e (hex) flags is transmitted n times (the ?n? is deter mined by the fl[1:0] bits (b5~4, e1-0aah,... / 0abh,... / 0ach, ...)), then the fisu packet is transmitted with the bsn and fsn the same with the last transmitted packet. eom: a transition from ?0? to ?1? on this bit i ndicates an entire hdlc/ss7 packet is stored in the fifo and starts the packet transm ission. xrep: in ss7 mode, when the fifo is empty and less than 16 bytes ar e written into the fifo, these bytes can be transmitted repeatedly with the open- ing flag, fcs and closing flag. this bit determines whether this cyc lic transmission can be implemented. = 0: disable the cyclic transmission. = 1: enable the cyclic transmission. abort: = 0: disable the manual abort sequence insertion. = 1: the abort sequence (?0 1111111?) is m anually inserted to the current hdlc/ss7 packet. this bit is self-cleared after the abortion. thdlcm: = 0: hdlc mode is selected. = 1: ss7 mode is selected. bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved autofisu eom xrep abort thdlcm trst type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 310 march 22, 2004 trst: a transition from ?0? to ?1? on the this bit resets the corresponding hdlc transmitter. the reset will clear the fifo.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 311 march 22, 2004 e1 tfifo1 threshold (0aah, 1aah, 2aah, 3aah) e1 tfifo2 threshold (0abh, 1abh, 2abh, 3abh) e1 tfifo3 threshold (0ach, 1ach, 2ach, 3ach) the function of the above three sets of registers are the same. however, they correspond to different thdlc. fl[1:0]: these bits are valid in ss7 mode when there is no data in the fifo to be transmitted and the autofisu bit (b5, e1-0a7h,... / 0a 8h,... / 0a9h,...) is ?1?. they define how many times the 7e (hex ) flags is transmitted before the fisu packet transmission. = 00: 8 flags = 01: 16 flags = 10: 32 flags = 11: 64 flags ll[1:0]: these 2 bits set the lower threshold of the fifo. if the fill level is below the lower threshold, an interrupt may be generated . = 00: 16 bytes = 01: 32 bytes = 10: 64 bytes = 11: 96 bytes hl[1:0]: these 2 bits set the upper threshold of the fifo. once the fill level exceeds the upper threshold, the data stored in the fifo will start to be trans- mitted. = 00: 16 bytes = 01: 32 bytes = 10: 64 bytes = 11: 128 bytes bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1 bit no. 7 6 5 4 3 2 1 0 bit name reserved fl1 fl0 ll1 ll0 hl1 hl0 type r/w r/w r/w r/w r/w r/w default 10 0 0 0 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 312 march 22, 2004 e1 thdlc1 data (0adh, 1adh, 2adh, 3adh) e1 thdlc2 data (0aeh, 1aeh, 2aeh, 3aeh) e1 thdlc3 data (0afh, 1afh, 2afh, 3afh) the function of the above three sets of registers are the same. however, they correspond to different thdlc. dat[7:0]: the bytes are to be stored in the fifo. the dat[0] bit corresponds to the first bit of the serial data in the fifo to be transm itted. bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 313 march 22, 2004 e1 tfifo1 status (0b0h, 1b0h, 2b0h, 3b0h) e1 tfifo2 status (0b1h, 1b1h, 2b1h, 3b1h) e1 tfifo3 status (0b2h, 1b2h, 2b2h, 3b2h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. ful: = 0: the fifo is not full. = 1: the fifo is full of 128 bytes. emp: = 0: the fifo is not empty. = 1: the fifo is empty. rdy: = 0: the fill level of the fifo is not below the lower thre shold set by the ll[1:0] bits (b3~2, e1-0aah,... / 0ab,... / 0ach,.. .). = 1: the fill level of the fifo is below the lower threshol d set by the ll[1:0] bits (b3~2, e1-0aah,... / 0abh,... / 0ach,...). bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011 bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011 bit no. 7 6 5 4 3 2 1 0 bit name reserved ful emp rdy type rrr default 011
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 314 march 22, 2004 e1 thdlc1 interrupt control (0b3h, 1b3h, 2b3h, 3b3h) e1 thdlc2 interrupt control (0b4h, 1b4h, 2b4h, 3b4h) e1 thdlc3 interrupt control (0b5h, 1b5h, 2b5h, 3b5h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. udrune: = 0: disable the interrupt on the int pin when the udruni bit (b1, e1-0b6h,... / 0b7h,... / 0b8h,...) is ?1?. = 1: enable the interrupt on the int pin when the udruni bit (b1, e1-0 b6h,... / 0b7h,... / 0b8h,...) is ?1?. rdye: = 0: disable the interrupt on the int pin when the rdyi bit (b0, e1-0b6h,... / 0b7h,... / 0b8h,...) is ?1?. = 1: enable the interrupt on the int pin when the rdyi bit (b0, e1-0 b6h,... / 0b7h,... / 0b8h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udrune rdye type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 315 march 22, 2004 e1 thdlc1 interrupt indication (0b6h, 1b6h, 2b6h, 3b6h) e1 thdlc2 interrupt indication (0b7h, 1b7h, 2b7h, 3b7h) e1 thdlc3 interrupt indication (0b8h, 1b8h, 2b8h, 3b8h) the function of the above three sets of registers are the same. however, they correspond to different thdlc. udruni: when the fifo is empty and the last transmitted byte is not t he end of the current hdlc/ss7 packet, the under-run occurs. this bit indicates whether the under-run occurs. = 0: no under-run occurs. = 1: under-run occurs. this bit will be cleared if a ?1? is written to it. rdyi: = 0: there is no status change on the rd y bit (b0, e1-0b0h,... / 0b1h,... / 0b2h,...). = 1: there is a transition (from ?0? to ?1?) on the rdy bit (b0, e1-0b0h,... / 0b1h,... / 0b2h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved udruni rdyi type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 316 march 22, 2004 e1 alarm status (0b9h, 1b9h, 2b9h, 3b9h) ts16losv: the los in ts16 is detected on the bas e of basic frame synchronization. = 0: the los in ts16 is cleared when 16 c onsecutive ts16 are not all received as ?0?. = 1: the los in ts16 is detected when 16 consecutive ts16 are all received as ?0?. ts16aisv: the ais in ts16 is detected on the ba se of basic frame synchronization. = 0: the ais in ts16 is cleared when ts16 contains more than 3 zeros in a 16-cons ecutive-basic-frame period. = 1: the ais in ts16 is detected when ts16 contains less t han 4 zeros in each of two 16-c onsecutive-basic-frame periods. rmaiv: the remote signaling multi-frame al arm is detected on the base of cas signaling multi-fram e synchronization. = 0: the remote signaling multi-frame alarm is cleared when a single y bit is received as ?0?. = 1: the remote signaling multi-frame alarm is detec ted when 3 consecutive y bits are received as ?1?. ais: = 0: the ais alarm is cleared. that is, w hen the aisc bit (b1, e1-0bch,...) is ?0?, more than 2 zeros are detected in a 512-bit fixed window; when the aisc bit (b1, e1-0bch,...) is ?1?, more than 2 zero s are detected in each of 2 consecutive 512-bit fixed window. = 1: the ais alarm is detected. that is, when the aisc bit (b1, e1-0bch,...) is ?0 ?, less than 3 zeros are detected in a 512-bi t fixed window and it is out of basic frame synchronization; when the aisc bit (b1, e1-0bch,...) is ?1?, less than 3 zeros are detected in each of 2 consecutive 512-bit fixed window. raiv: the remote alarm is detected on t he base of basic frame synchronization. = 0: the remote alarm is cleared. that is, when the raic bit (b0, e1-0bch,...) is ?0?, a single a bit is received as ?0?; when the raic bit (b0, e1- 0bch,...) is ?1?, a single a bit is received as ?0?. = 1: the remote alarm is detected. that is , when the raic bit (b0, e1-0bch,...) is ?0 ?, 4 consecutive a bits are received as ?1 ?; when the raic bit (b0, e1-0bch,...) is ?1?, a single a bit is received as ?1?. red: = 0: the red alarm is cleared when in ba sic frame synchronization persists for 100ms. = 1: the red alarm is detected when out of basic frame synchroniza tion persists for 100ms. bit no. 7 6 5 4 3 2 1 0 bit name reserved ts16losv ts16aisv rmaiv ais raiv red type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 317 march 22, 2004 e1 alarm control (0bah, 1bah, 2bah, 3bah) ts16lose: = 0: disable the interrupt on the int pin when the ts16losi bit (b5, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the ts16losi bit (b5, e1-0bbh,...) is ?1?. ts16aise: = 0: disable the interrupt on the int pin when the ts16aisi bit (b4, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the ts16aisi bit (b4, e1-0bbh,...) is ?1?. rmaie: = 0: disable the interrupt on the int pin when the rmaii bit (b3, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the rmaii bit (b3, e1-0bbh,...) is ?1?. aise: = 0: disable the interrupt on the int pin when the aisi bit (b2, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the aisi bit (b2, e1-0bbh,...) is ?1?. raie: = 0: disable the interrupt on the int pin when the raii bit (b1, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the raii bit (b1, e1-0bbh,...) is ?1?. rede: = 0: disable the interrupt on the int pin when the redi bit (b0, e1-0bbh,...) is ?1?. = 1: enable the interrupt on the int pin when the redi bit (b0, e1-0bbh,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved ts16lose ts16aise rmaie aise raie rede type r/w r/w r/w r/w r/w r/w default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 318 march 22, 2004 e1 alarm indication (0bbh, 1bbh, 2bbh, 3bbh) ts16losi: = 0: there is no status change on the ts16losv bit (b5, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the ts16losv bit (b5, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. ts16aisi: = 0: there is no status change on the ts16aisv bit (b4, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or from ?1? to ?0?) on the ts16aisv bit (b4, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. rmaii: = 0: there is no status change on the rmaiv bit (b3, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the rmaiv bit (b3, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. aisi: = 0: there is no status change on the ais bit (b2, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the ais bit (b2, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. raii: = 0: there is no status change on the raiv bit (b1, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the raiv bit (b1, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. redi: = 0: there is no status change on the red bit (b0, e1-0b9h,...). = 1: there is a transition (from ?0? to ?1? or fr om ?1? to ?0?) on the red bit (b0, e1-0b9h,...). this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name reserved ts16losi ts16aisi rmaii aisi raii redi type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 319 march 22, 2004 e1 alarm criteria control (0bch, 1bch, 2bch, 3bch) aisc: this bit selects the ais alarm detection criteria. = 0: the criterion meets i.431. the ais alarm will be declared when less than 3 zero s are detected in a 512-bit fixed window an d it is out of basic frame synchronization, and the ais alarm will be cleared when more than 2 zeros are detected in a 512-bit fixed window. = 1: the criterion meets g.775. the ais al arm will be declared when less than 3 zeros are detected in each of 2 consecutive 512 -bit fixed win- dow, and the ais alarm will be cleared when more than 2 zeros are detected in each of 2 c onsecutive 512-bit fixed window. raic: this bit selects the remote alarm detection criterion. = 0: the remote alarm will be declared when 4 consecutive a bits are received as ?1?, and the remote alarm will be cleared when a single a bit is received as ?0?. = 1: the remote alarm will be declared when a single a bit is re ceived as ?1?, and the remote alarm will be cl eared when a sing le a bit is received as ?0?. e1 pmon control (0c2h, 1c2h, 2c2h, 3c2h) updat: a transition from ?0? to ?1? on this bit updates all the pmon indirect registers. autoupd: = 0: disable the automatic update functi on of the pmon indirect registers. = 1: all the pmon indirect register s are updated every one second automatically. bit no. 7 6 5 4 3 2 1 0 bit name reserved aisc raic type r/w r/w default 00 bit no. 7 6 5 4 3 2 1 0 bit name reserved updat autoupd type r/w r/w default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 320 march 22, 2004 e1 pmon interrupt control 0 (0c3h, 1c3h, 2c3h, 3c3h) prdgove: = 0: disable the interrupt on the int pin when the prdgovi bit (b7, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the prdgovi bit (b7, e1-0c5h,...) is ?1?. tfebeove: = 0: disable the interrupt on the int pin when the tfebeovi bit (b6, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the tfebeovi bit ( b6, e1-0c5h,...) is ?1?. febeove: = 0: disable the interrupt on the int pin when the febeovi bit (b5, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the febeovi bit (b5, e1-0c5h,...) is ?1?. tcrcove: = 0: disable the interrupt on the int pin when the tcrcovi bit (b4, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the tcrcovi bit (b4, e1-0c5h,...) is ?1?. cofaove: = 0: disable the interrupt on the int pin when the cofaovi bit (b3, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the cofaovi bit (b3, e1-0c5h,...) is ?1?. oofove: = 0: disable the interrupt on the int pin when the oofovi bit (b2, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the oofovi bit (b2, e1-0c5h,...) is ?1?. ferove: = 0: disable the interrupt on the int pin when the ferovi bit (b1, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the ferovi bit (b1, e1-0c5h,...) is ?1?. crcove: = 0: disable the interrupt on the int pin when the crcovi bit (b0, e1-0c5h,...) is ?1?. = 1: enable the interrupt on the int pin when the crcovi bit (b0, e1-0c5h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name prdgove tfebeove febeove tcrcove cofaove oofove ferove crcove type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 321 march 22, 2004 e1 pmon interrupt control 1 (0c4h, 1c4h, 2c4h, 3c4h) lcvove: = 0: disable the interrupt on the int pin when the lcvovi bit (b0, e1-0c6h,...) is ?1?. = 1: enable the interrupt on the int pin when the lcvovi bit (b0, e1-0c6h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved lcvove type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 322 march 22, 2004 e1 pmon interrupt indication 0 (0c5h, 1c5h, 2c5h, 3c5h) prdgovi: = 0: the pmon indirect prgd counter mapping registers have not overflowed. = 1: the pmon indirect prgd count er mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. tfebeovi: = 0: the pmon indirect tfebe counter mapping registers have not overflowed. = 1: the pmon indirect tfebe count er mapping register s have overflowed. this bit will be cleared if a ?1? is written to it. febeovi: = 0: the pmon indirect febe counter mapping registers have not overflowed. = 1: the pmon indirect febe count er mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. tcrcovi: = 0: the pmon indirect ddse counter mapping registers have not overflowed. = 1: the pmon indirect ddse counter mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. cofaovi: = 0: the pmon indirect cofa counter mapping register has not overflowed. = 1: the pmon indirect cofa count er mapping register has overflowed. this bit will be cleared if a ?1? is written to it. oofovi: = 0: the pmon indirect oof counter mapping register has not overflowed. = 1: the pmon indirect oof counter mapping register has overflowed. this bit will be cleared if a ?1? is written to it. ferovi: = 0: the pmon indirect fer counter mapping registers have not overflowed. = 1: the pmon indirect fer counter mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. crcovi: = 0: the pmon indirect crce counter mapping registers have not overflowed. = 1: the pmon indirect crce count er mapping register s have overflowed. this bit will be cleared if a ?1? is written to it. bit no. 7 6 5 4 3 2 1 0 bit name prdgovi tfebeovi febeovi tcrcovi cofaovi oofovi ferovi crcovi type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 323 march 22, 2004 e1 pmon interrupt indication 1 (0c6h, 1c6h, 2c6h, 3c6h) lcvovi: = 0: the pmon indirect lcv counter mapping registers have not overflowed. = 1: the pmon indirect lcv count er mapping registers have overflowed. this bit will be cleared if a ?1? is written to it. e1 tplc / rplc / prgd test configuration (0c7h, 1c7h, 2c7h, 3c7h) prbsmode[1:0]: these two bits select one mode to extract/repl ace the data for the prbs generator/detector. = 00: the unframed mode is selected. all 32 timeslots are extrac ted/replaced and the per-timeslot co nfiguration in the test bit (b6, e1-id- 41~4fh & 51~5fh) is ignored. = 01: the 8-bit-based mode is selected. the received data will onl y be extracted/replaced on the timeslot configured by the tes t bit (b6, e1-id- 41~4fh & 51~5fh). = 10: the 7-bit-based mode is selected. the received data will onl y be extracted/replaced on the 7 msb of the timeslot configur ed by the test bit (b6, e1-id-41~4fh & 51~5fh). = 11: reserved. prbsdir: = 0: the pattern in the prbs generator/detector is generat ed in the transmit path and is detected in the receive path. = 1: the pattern in the prbs generator/detector is generated in the receive path and is detected in the transmit path. testen: a transition from ?0? to ?1? on this bi t initiates the prbs generator/detector. bit no. 7 6 5 4 3 2 1 0 bit name reserved lcvovi type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved prbsmode1 prbsmode0 prbsdir testen type r/w r/w r/w r/w default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 324 march 22, 2004 e1 tplc access status (0c8h, 1c8h, 2c8h, 3c8h) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. e1 tplc access control (0c9h, 1c9h, 2c9h, 3c9h) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of the indirect register (from 00h to 3fh & from 41h to 4fh & from 51h to 5fh) for the microproc essor access. e1 tplc access data (0cah, 1cah, 2cah, 3cah) d[7:0]: this register holds the value wh ich will be read from or written into the indirect registers (fro m 00h to 3fh & from 41h to 4fh & from 51h to 5fh). if data is to be written into the indirect register, this regi ster must be written before the ta rget indirect register?s addres s and rwn=0 is written into the tplc access control register. if data is to be read from the i ndirect register, the target indirect register?s address and rwn= 1 must be written into the tplc access control register first, then this register will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 325 march 22, 2004 e1 tplc configuration (0cbh, 1cbh, 2cbh, 3cbh) sigsnap: this bit is valid when the si gnaling multi-frame is generated. = 0: disable the signaling snapshot. = 1: enable the signaling snapshot. that is, the signaling bits of the first basic frame are locked and input on the tsign/mtsi ga(mtsigb) pin as the signaling bits of the curr ent whole signaling multi-frame. gstrken: = 0: the replacement is perform ed on a per-timeslot basis by setting the strken bi t (b4, e1-id-41~4fh & 51~5fh) in the correspo nding timeslot. = 1: the signaling bits (abcd) of all ti meslots are replaced by the signaling trunk conditioning code in the a,b,c,d bits (b3~0 , e1-id-41~4fh & 51~5fh). gsubst[2:0]: these bits select the repl acement of all the channels. e1 tplc control enable (0cch, 1cch, 2cch, 3cch) pcce: = 0: disable all the functions in the transmit payload control. = 1: enable all the functions in the transmit payload control. bit no. 7 6 5 4 3 2 1 0 bit name sigsnap gstrken reserved gsubst2 gsubst1 gsubst0 type r/w r/w r/w r/w r/w default 10 0 0 0 gsubst[2:0] replacement selection 0 0 0 the replacement is performed on a per-timeslot basis by setting the subst[2:0] bits (b7~5, e1-id-00~1fh) in the correspond ing timeslot. 0 0 1 the data of all timeslots is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, e1-id-20~3fh). 0 1 0 the data of all timeslots is replaced by the a-law digital milliwatt pattern. 0 1 1 the data of all timeslots is replaced by the -law digital milliwatt pattern. 1 0 0 the data of all timeslots is replaced by the payload loopback code extracted from the elastic store buffer in the receive path. others reserved. bit no. 7 6 5 4 3 2 1 0 bit name reserved pcce type r/w default 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 326 march 22, 2004 e1 rplc access status (0cdh, 1cdh, 2cdh, 3cdh) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. e1 rplc access control (0ceh, 1ceh, 2ceh, 3ceh) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of the indirect register (from 00h to 3fh & from 41h to 4fh & from 51h to 5fh) for the microproc essor access. e1 rplc access data (0cfh, 1cfh, 2cfh, 3cfh) d[7:0]: this register holds the value wh ich will be read from or written into the indirect registers (fro m 00h to 3fh & from 41h to 4fh & from 51h to 5fh). if data is to be written into the indirect register, this regi ster must be written before the ta rget indirect register?s addres s and rwn=0 is written into the rplc access control register. if data is to be read from the indirect register, the target indirect register?s address and rwn= 1 must be written into the rplc access control register first, then this register will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name d7 d6 d5 d4 d3 d2 d1 d0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 327 march 22, 2004 e1 rplc configuration (0d0h, 1d0h, 2d0h, 3d0h) sigsnap: this bit is valid when signaling mu lti-frame is in synchronization. = 0: disable the signaling snapshot. = 1: enable the signaling snapshot. that is, the signaling bits of the first basic fr ame are locked and output on the rsign/mrs iga(mrsigb) pin as the signaling bits of the cu rrent whole signaling multi-frame. gstrken: = 0: the replacement is perform ed on a per-timeslot basis by setting the strken bi t (b4, e1-id-41~4fh & 51~5fh) in the correspo nding timeslot. = 1: the signaling bits (abcd) of all ti meslots are replaced by the signaling trunk conditioning code in the a,b,c,d bits (b3~0 , e1-id-41~4fh & 51~5fh). gsubst[2:0]: these bits select the replac ement of all the timeslots. bit no. 7 6 5 4 3 2 1 0 bit name sigsnap gstrken reserved gsubst2 gsubst1 gsubst0 type r/w r/w r/w r/w r/w default 00 0 0 0 gsubst[2:0] replacement selection 000 the replacement is performed on a per-timeslot basis by setting the subst[2:0] bits (b7~5, e1-id-00~1fh) in the correspondin g timeslot. 001 the data of all timeslots is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, e1-id-20~3fh). 010 the data of all timeslots is replaced by the a-law digital milliwatt pattern. 011 the data of all timeslots is replaced by the -law digital milliwatt pattern. the others reserved.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 328 march 22, 2004 e1 rplc control enable (0d1h, 1d1h, 2d1h, 3d1h) pcce: = 0: disable all the functions in the receive payload control. = 1: enable all the functions in the receive payload control. e1 rcrb configuration (0d2h, 1d2h, 2d2h, 3d2h) freeze: = 0: disable the manual signaling freezing. = 1: manually freeze the signaling data in the a,b,c,d bits (b3~0, e1-id-01~0fh & 11~1fh) as the previous valid value. deb: = 0: disable the signaling de-bounce. = 1: enable the signaling de-bounce. that is, the a,b,c,d bits (b3~0, e1-id-01~0fh & 11~1fh) are updated only if 2 consecutive received abcd codeword of the same timeslot are identical. sige: = 0: disable the interrupt on the int pin when any of the cosi bits (e1-0d9h,... & e1-0d8h,... & e1-0d7h,... & e1-0d6h,...) is ?1?. = 1: enable the interrupt on the int pin when any of the cosi bits (e1-0d9h,... & e1-0d8h,... & e1-0d7h,... & e1-0d6h,...) is ?1?. bit no. 7 6 5 4 3 2 1 0 bit name reserved pcce type r/w default 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved freeze deb sige reserved type r/w r/w r/w default 000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 329 march 22, 2004 e1 rcrb access status (0d3h, 1d3h, 2d3h, 3d3h) busy: = 0: no reading or writing operat ion on the indirect registers. = 1: an internal indirect register is being accessed. any new operation on the inte rnal indirect register is not allowed. e1 rcrb access control (0d4h, 1d4h, 2d4h, 3d4h) rwn: = 0: write the data to the specified indirect register. = 1: read the data to the specified indirect register. address[6:0]: these bits specify the address of the indire ct register (from 01h to 0fh & from 11 h to 1fh) for the mi croprocessor access. e1 rcrb access data (0d5h, 1d5h, 2d5h, 3d5h) dat[7:0]: this register holds the value which will be read from or written into the indirect regi sters (from 01h to 0fh & from 11h to 1fh ). if data is to be writ- ten into the indirect register, this regi ster must be written before the target indi rect register?s address and rwn=0 is writte n into the rcrb access control register. if data is to be read from the indirect register, the target indi rect register?s address and rwn=1 must be wr itten into the rcrb access control register first, then this regist er will contain the requested data byte. bit no. 7 6 5 4 3 2 1 0 bit name reserved busy type r default 0 bit no. 7 6 5 4 3 2 1 0 bit name rwn address6 address5 address4 a ddress3 address2 address1 address0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name dat7 dat6 dat5 dat4 dat3 dat2 dat1 dat0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 330 march 22, 2004 e1 rcrb state change indication 0 (0d6h, 1d6h, 2d6h, 3d6h) cosi[x]: = 0: the signaling bits in its corresponding timeslot is not changed. = 1: the signaling bits in it s corresponding timeslot is changed. the corresponding bit will be cleared if a ?1? is written to it. the cosi[8:1] bits correspond to timeslot 8 ~ 1 respectively. e1 rcrb state change indication 1 (0d7h, 1d7h, 2d7h, 3d7h) cosi[x]: = 0: the signaling bits in its corresponding timeslot is not changed. = 1: the signaling bits in it s corresponding timeslot is changed. the corresponding bit will be cleared if a ?1? is written to it. the cosi[16] bit corr esponds to timeslot 17. the cosi[15:9] bi ts correspond to timeslot 15 ~ 9 respectively. bit no. 7 6 5 4 3 2 1 0 bit name cosi8 cosi7 cosi6 cosi5 cosi4 cosi3 cosi2 cosi1 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name cosi16 cosi15 cosi14 cosi13 cosi12 cosi11 cosi10 cosi9 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 331 march 22, 2004 e1 rcrb state change indication 2 (0d8h, 1d8h, 2d8h, 3d8h) cosi[x]: = 0: the signaling bits in its corresponding timeslot is not changed. = 1: the signaling bits in it s corresponding timeslot is changed. the corresponding bit will be cleared if a ?1? is written to it. the cosi[24:17] bits correspond to timeslot 25 ~ 18 respective ly. e1 rcrb state change indication 3 (0d9h, 1d9h, 2d9h, 3d9h) cosi[x]: = 0: the signaling bits in its corresponding timeslot is not changed. = 1: the signaling bits in it s corresponding timeslot is changed. the corresponding bit will be cleared if a ?1? is written to it. the cosi[30:25] bits correspond to timeslot 31 ~ 26 respective ly. bit no. 7 6 5 4 3 2 1 0 bit name cosi24 cosi23 cosi22 cosi21 cosi20 cosi19 cosi18 cosi17 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved cosi30 cosi29 cosi28 cosi27 cosi26 cosi25 type rr r r r r default 00 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 332 march 22, 2004 5.2.2.2 indirect register pmon: the pmon counter mapping registers (00h ~ 0fh) of a link are updated as a group in the following three ways: 1. a transition from ?0? to ?1? on the updat bit (b1, e1-0c2h,...) updates all the registers; 2. if the autoupd bit (b0, e1-0c2h,...) is set to ?1?, the registers will be updated every one second; e1 crce counter mapping 0 (00h) crce[7:0]: these bits together with the crce[9 :8] bits count the crc-4 error num bers. the crce[0] bit is the lsb. e1 crce counter mapping 1 (01h) crce[9:8]: these bits together with the crce[7 :0] bits count the crc-4 error num bers. the crce[9] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name crce7 crce6 crce5 crce4 crce3 crce2 crce1 crce0 type rr r r r r r r r 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved crce9 crce8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 333 march 22, 2004 e1 fer counter mapping 0 (02h) fer[7:0]: these bits together with the fer[11:8] bits count the fas/ nfas bit/pattern error numbers. the fer[0] bit is the lsb. e1 fer counter mapping 1 (03h) fer[11:8]: these bits together with the fer[7:0] bits count the fas/ nfas bit/pattern error numbers. the fer[11] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name fer7 fer6 fer5 fer4 fer3 fer2 fer1 fer0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved fer11 fer10 fer9 fer8 type rrrr default 0000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 334 march 22, 2004 e1 cofa counter mapping (04h) cofa[2:0]: these bits count the times of the new-found basic frame alignment pattern position bei ng different from the previous one events . e1 oof counter mapping (05h) oof[4:0]: these bits count the times of out of basic frame synchronization events. bit no. 7 6 5 4 3 2 1 0 bit name reserved cofa2 cofa1 cofa0 type rrr default 000 bit no. 7 6 5 4 3 2 1 0 bit name reserved oof4 oof3 oof2 oof1 oof0 type rrrrr default 00000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 335 march 22, 2004 e1 prgd counter mapping 0 (06h) prgd[7:0]: these bits together with the prgd[15:8] bits count t he prgd bit error numbers. t he prgd[0] bit is the lsb. e1 prgd counter mapping 1 (07h) prgd[15:8]: these bits together with the prgd[7:0] bits count the prgd bit error numbers. the prgd[15] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name prgd7 prgd6 prgd5 prgd4 prgd3 prgd2 prgd1 prgd0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name prgd15 prgd14 prgd13 prgd12 prgd11 prgd10 prgd9 prgd8 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 336 march 22, 2004 e1 lcv counter mapping 0 (08h) lcv[7:0]: these bits together with the lcv[15:8] bits count the bipolar violation (bpv) error (in ami dec oding) or hdb3 code violation (c v) error (in hdb3 decoding) numbers. the lcv[0] bit is the lsb. e1 lcv counter mapping 1 (09h) lcv[15:8]: these bits together with the lcv[7:0] bits count the bipolar violation (bpv) error (in ami decoding) or hdb3 code violation (cv ) error (in hdb3 decoding) numbers. the lcv[15] bit is the msb. bit no. 7 6 5 4 3 2 1 0 bit name lcv7 lcv6 lcv5 lcv4 lcv3 lcv2 lcv1 lcv0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name lcv15 lcv14 lcv13 lcv12 lcv11 lcv10 lcv9 lcv8 type rr r r r r r r default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 337 march 22, 2004 e1 tcrce counter mapping 0 (0ah) tcrce[7:0]: these bits together with the tcrce[9: 8] bits count the nt crc error num bers. the tcrce[0] bit is the lsb. e1 tcrce counter mapping 1 (0bh) tcrce[9:8]: these bits together with the tcrce[7: 0] bits count the nt crc error num bers. the tcrce[9] bit is the msb bit no. 7 6 5 4 3 2 1 0 bit name tcrce7 tcrce6 tcrce5 tcrce4 tcrce3 tcrce2 tcrce1 tcrce0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved tcrce9 tcrce8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 338 march 22, 2004 e1 febe counter mapping 0 (0ch) febe[7:0]: these bits together with the febe[9:8 ] bits count the far end block error numbers. the febe[0] bit is the lsb. e1 febe counter mapping 1 (0dh) febe[9:8]: these bits together with the febe[7:0 ] bits count the far end block error numbers. the febe[9] bit is the msb bit no. 7 6 5 4 3 2 1 0 bit name febe7 febe6 febe5 febe4 febe3 febe2 febe1 febe0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved febe9 febe8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 339 march 22, 2004 e1 tfebe counter mapping 0 (0eh) tfebe[7:0]: these bits together with the tfebe[9:8] bits count t he nt febe error numbers. the tfebe[0] bit is the lsb. e1 tfebe counter mapping 1 (0fh) tfebe[9:8]: these bits together with the tfebe[7:0] bits count t he nt febe error numbers. the tfebe[9] bit is the msb bit no. 7 6 5 4 3 2 1 0 bit name tfebe7 tfebe6 tfebe5 tfebe4 tfebe3 tfebe2 tfebe1 tfebe0 type rr r r r r r r default 00 0 0 0 0 0 0 bit no. 7 6 5 4 3 2 1 0 bit name reserved tfebe9 tfebe8 type rr default 00
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 340 march 22, 2004 rcrb: the indirect registers of rcrb addressed from 01h to 0fh & from 11h to 1fh ar e the extracted signaling data / extract enable re gisters for ts1 to ts15 & ts17 to ts31. each address corresponds to one timeslot. e1 extracted signaling data/extract enable register (01h ~ 0fh & 11h ~ 1fh) extract: this bit is valid when the signal ing multi-frame is synchronized. = 0: disable the signal ing bits extraction. = 1: the signaling bits are extracted to the a,b,c,d bits (b3~0, e1-id-01~0fh & 11~1fh). a, b, c, d: these bits are valid when the extract bit is enabled. these bits are the extracted signaling bits. bit no. 7 6 5 4 3 2 1 0 bit name reserved extract a b c d type r/w r r r r default 10000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 341 march 22, 2004 rplc: the indirect registers of rplc addressed fr om 00h to 1fh are the timeslot control r egisters for ts0 to ts31. each address corre sponds to one timeslot. the indirect registers of rplc addressed fr om 20h to 3fh are the data trunk conditioni ng code registers for ts0 to ts31. each a ddress cor- responds to one timeslot. the indirect registers of rplc addressed from 41h to 4fh and from 51h to 5fh are the signaling trunk conditioning code register s for ts1 to ts15 and ts17 to ts31 respectively. each address corresponds to one timeslot. e1 timeslot control register (00h ~ 1fh) subst[2:0]: when the gsubst[2:0] bits (b2~0, e1-0d0h,...) are ?000?, t hese bits select the replacement on a per-timeslot basis. sinv, oinv, einv: these three bits select how to invert the bits in the corresponding timeslot. bit no. 7 6 5 4 3 2 1 0 bit name subst2 subst1 subst0 sinv oinv einv g56k gap type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 subst[2:0] replacement selection 000 no operation. 001 the data of the corresponding timeslot is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, e1-id-20~3fh). 010 the data of the corresponding timeslot is replaced by the a-law digital milliwatt pattern. 011 the data of the corresponding timeslot is replaced by the -law digital milliwatt pattern. the others reserved. sinv oinv einv bit inversion 0 0 0 no inversion. 0 0 1 invert the even bits (bit 2, 4, 6, 8) of the corresponding timeslot (bit 1 is the msb). 0 1 0 invert the odd bits (bit 3, 5, 7) except the msb of the corresponding timeslot (bit 1 is the msb). 0 1 1 invert the bits from bit 2 to bit 8 of the corresponding timeslot (bit 1 is the msb). 1 0 0 invert the msb (bit 1) of the corresponding timeslot. 1 0 1 invert the msb (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding timeslot. 1 1 0 invert all the odd bits (bit 1, 3, 5, 7) of the corresponding timeslot (bit 1 is the msb). 1 1 1 invert all the bits (bit 1 ~ bit 8) of the corresponding timeslot (bit 1 is the msb).
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 342 march 22, 2004 g56k, gap: these bits are valid in receive clock master mode when the pcce bit (b0, e1-0d1h,...) is ?1?. e1 data trunk conditioning code register (20h ~ 3fh) dtrk[7:0]: these bits are the data trunk codes that c an replace the data of the timeslot selected by the gsubst[2:0] bits (b2~0, e1-0d0h,. ..) or the subst[2:0] bits (b7~5, e1-id-00~1fh). g56k gap gap mode 0 0 the corresponding timeslot is not gapped. 1 0 bit 8 (lsb) of the corresponding timeslot is gapped (no clock signal during the bit 8). x 1 the corresponding timeslot is gapped (no clock signal during the timeslot). bit no. 7 6 5 4 3 2 1 0 bit name dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 343 march 22, 2004 e1 signaling trunk conditioning code register (41h ~ 4fh & 51h ~ 5fh) test: this bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the pr bsmode[1:0] bits (b3~2, e1-0c7h,...). = 0: disable the data in the corresponding timesl ot to be tested by the prbs generator/detector. = 1: enable the data in the corresponding timeslot to be extract ed to the prbs generator/detector for test (when the prbsdir bi t (b1, e1- 0c7h,...) is ?0?); or enable the test pattern from the prbs g enerator/detector to replace the data in the corresponding timeslo t for test (when the prb- sdir bit (b1, e1-0c7h,...) is ?1?). in 8- bit-based mode, the data refers to all 8 bi ts. in 7-bit-based mode, the data refers to the 7 msb. all the timeslots that are extracted to the prbs generator/d etector are concatenated and treated as a continuous stream in whic h pseudo ran- dom are searched for. similarly, all the timeslots set to be replaced with the prbs generator/detector test pattern data are co ncatenated replaced by the prbs. strken: = 0: no operation. = 1: the data of the corresponding timeslot is replaced by the signaling trunk code set in the a, b, c, d bits (b3~0, e1-id-41~ 4fh & 51~5fh). a, b, c, d: these bits are the signaling trunk codes that can replace the signaling bits of the timeslot selected by the gstrken bit (b6, e 1-0d0h,...) or the strken bit (b4, e1 -id-41~4fh & 51~5fh). bit no. 7 6 5 4 3 2 1 0 bit name reserved test reserved strken a b c d type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 344 march 22, 2004 tplc: the indirect registers of tplc addressed fr om 00h to 1fh are the timeslot control r egisters for ts0 to ts31. each address corre sponds to one timeslot. the indirect registers of tplc addressed from 20h to 3fh are the data trunk c onditioning code registers for ts0 to ts31. each a ddress cor- responds to one timeslot. the indirect registers of tplc addressed from 41h to 4fh and from 51h to 5f h are the signaling trunk conditioning code register s for ts1 to ts15 and ts17 to ts31 respectively. each address corresponds to one timeslot. e1 timeslot control register (00h ~ 1fh) subst[2:0]: when the gsubst[2:0] bits(b2~0, e1-0cbh,...) are ?000?, these bits select the repl acement on a per-channel basis. sinv, oinv, einv: these three bits select how to invert the bits in the corresponding channel. bit no. 7 6 5 4 3 2 1 0 bit name subst2 subst1 subst0 sinv oinv einv g56k gap type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0 subst[2:0] replacement selection 0 0 0 no operation. 0 0 1 the data of the corresponding timeslot is replaced by the data trunk code set in the dtrk[7:0] bits (b7~0, t1/j1-id-21~38h ). 0 1 0 the data of the corresponding timeslot is replaced by the a-law digital milliwatt pattern. 0 1 1 the data of the corresponding timeslot is replaced by the -law digital milliwatt pattern. 1 0 0 the data of the corresponding timeslot is replaced by the payload loopback code extracted from the elastic store buffer in the receive path. others reserved. sinv oinv einv bit inversion 0 0 0 no inversion. 0 0 1 invert the even bits (bit 2, 4, 6, 8) of the corresponding channel (bit 1 is the msb). 0 1 0 invert the odd bits (bit 3, 5, 7) except the msb of the corresponding channel (bit 1 is the msb). 0 1 1 invert the bits from bit 2 to bit 8 of the corresponding channel (bit 1 is the msb). 1 0 0 invert the msb (bit 1) of the corresponding channel. 1 0 1 invert the msb (bit 1) and the even bits (bit 2, 4, 6, 8) of the corresponding channel. 1 1 0 invert all the odd bits (bit 1, 3, 5, 7) of the corresponding channel (bit 1 is the msb). 1 1 1 invert all the bits (bit 1 ~ bit 8) of the corresponding channel (bit 1 is the msb).
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 345 march 22, 2004 g56k, gap: these bits are valid in transmi t clock master mode when the pcce bit (b0, e1-0cch,...) is ?1?. e1 data trunk conditioning code register (20h ~ 3fh) dtrk[7:0]: these bits are the data trunk codes that c an replace the data of the channel selected by the gsubst[2:0] bits (b2~0, t1/j1-0cbh ,...) or the subst[2:0] bits (b7~5, t1/j1-id-01~18h). g56k gap gap mode 0 0 the corresponding timeslot is not gapped. 1 0 bit 8 (lsb) of the corresponding timeslot is gapped (no clock signal during the bit 8). x 1 the corresponding timeslot is gapped (no clock signal during the timeslot). bit no. 7 6 5 4 3 2 1 0 bit name dtrk7 dtrk6 dtrk5 dtrk4 dtrk3 dtrk2 dtrk1 dtrk0 type r/w r/w r/w r/w r/w r/w r/w r/w default 00 0 0 0 0 0 0
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver programming information 346 march 22, 2004 e1 signaling trunk conditioning code register (41h ~ 4fh & 51h ~ 5fh) test: this bit is valid in 8-bit-based mode or in 7-bit-based mode selected by the pr bsmode[1:0] bits (b3~2, t1/j1-0c7h,...). = 0: disable the data in the corresponding channel to be tested by the prbs generator/detector. = 1: enable the data in the corresponding channel to be extracted to the prbs generator/detector for test (when the prbsdir bit (b1, e1- 0c7h,...) is ?0?); or enable the test pattern from the prbs g enerator/detector to replace the data in the corresponding channel for test (when the prb- sdir bit (b1, e1-0c7h,...) is ?1?). in 8- bit-based mode, the data refers to all 8 bi ts. in 7-bit-based mode, the data refers to the 7 msb. all the channels that are extracted to t he prbs generator/detector are concatenated and treated as a continuous stream in which pseudo ran- dom are searched for. similarly, all the channels set to be replaced with the prbs generator/detector test pattern data are con catenated replaced by the prbs. strken: = 0: no operation. = 1: the data of the corresponding channel is replaced by the signali ng trunk code set in the a, b, c, d bits (b3~0, t1/j1-id-4 1~58h). a, b, c, d: these bits are the signaling trunk codes that can replace the signaling bits of the channel selected by the gstrken bit (b6, t1 /j1-0cbh,...) or the strken bit (b4, t1/j1-id-41~58h). bit no. 7 6 5 4 3 2 1 0 bit name reserved test reserved strken a b c d type r/w r/w r/w r/w r/w r/w default 000000
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 347 mar ch 22, 2004 6 ieee std 1149.1 jtag test access port the IDT82P2284 supports the digi tal boundary scan specification as described in the ieee 1149.1 standards. the boundary scan architecture cons ists of data and instruction registers plus a test access port (t ap) controller. control of the tap is achieved through signals applied to the test mode select (tms) and test clock (tck) input pins. data is shifted into the registers via the test data input (tdi) pin, and shifted out of the registers via the test data output (tdo) pin. both tdi and td o are clocked at a rate determined by tck. the jtag boundary scan regist ers include bsr (boundary scan register), dir (device identificati on register), br (bypass register) and ir (instruction register). these will be described in the following pages. refer to figure - 40 for architecture. figure 40. jtag architecture bsr (boundary scan register) dir (device identification register) br (bypass register) ir (instruction register) mux tdo tdi tck tms trst control<6:0> mux select output enable tap (test access port) controller
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 348 mar ch 22, 2004 6.1 jtag instructions and instruction reg- ister (ir) the ir (instruction register) with instruction decode block is used to select the test to be executed or the data register to be accessed or both. the instructions are shifted in lsb first to this 3-bit register. see table 82 for details of the codes and the instructions related. table 82: ir code ir code instruction comment 0 0 0 extest the external test instruction allows testing of the interconnection to other devices. when the current instruction i s the extest instruction, the boundary scan register is placed between tdi and tdo. the signal on the input pins can be sampled by loading the boundary s can register using the capture-dr state. the sampled values can then be viewed by shifting the boundary scan register using the shi ft-dr state. the signal on the output pins can be controlled by loading patterns shifted in through input tdi into the boundary scan register using the update-dr state. 0 1 0 sample / preload the sample/preload instruction is used to allow scanning of the boundary-scan register without causing interference to the norm al opera- tion of the on-chip system logic. data received at system input pins is supplied without modification to the on-chip system log ic; data from the on-chip system logic is driven without modification through the system output pins. sample allows a snapshot to be taken of the data flowing from the system pins to the on-chip system logic or vice versa, without interfering with the normal operation of the as sembled board. preload allows an initial data pattern to be placed at the latched parallel outputs of boundary-scan register cells prio r to selection of another boundary-scan test operation. 0 0 1 idcode the identification instruction is used to connect the identification register between tdi and tdo. the device?s iden tification code can then be shifted out using the shift-dr state. 1 1 1 bypass the bypass instruction shifts data from input tdi to output tdo with one tc k clock period delay. the instruction is used to bypass the device. 0 1 1 clamp this instruction allows the state of the signals driven from device pins to be determined from the boundary-scan regi ster while the bypass register is selected as the serial path between tdi and tdo. the signals driven from the device pins will not change while the clamp instruction is selected. 0 1 0 highz use of the highz instruction places the device in a state in which all of its system logic outputs are placed in an i nactive drive state (e.g., high impedance). in this state, and in-circuit test system may drive signals onto the connections normally driven by a device o utput without incurring the risk of damage to the device. 1 0 1 - (for ic manufactory test)
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 349 mar ch 22, 2004 6.2 jtag data register 6.2.1 device identification register (idr) the idr can be set to define the vision, the part number, the man- ufacturer identity and a fixed bit. t he idr is 32 bits long and is parti- tioned as in table 83. data from the idr is shifted out to the tdo lsb first. 6.2.2 bypass register (byp) the byr consists of a single bi t. it can provide a serial path between the tdi input and tdo output, bypassing the byr to reduce test access times. 6.2.3 boundary scan register (bsr) the bidirectional ports inte rface to 2 boundary scan cells: - in cell: the input cell is observable only (bc_4). - out cell: the output cell is c ontrollable and observable (bc_1). the boundary scan (bs) sequence is illustrated in table 84. table 83: idr bit no. comments 0 set to ?1? 1 ~ 11 manufacturer identity (033h) 12 ~ 27 part number (04d8h) 28 ~ 31 version number table 84: boundary scan (bs) sequence bs-cell name bs no. bs-cell type thz 173 in-cell cle_gen_2.048 172 out-cell cle_gen_1.544 171 out-cell refb_out 170 out-cell refa_out 169 out-cell ic 168 in-cell ic 167 in-cell clk_sel[0] 166 in-cell clk_sel[1] 165 in-cell clk_sel[2] 164 in-cell gpio[0]_out 163 out-cell gpio[0]_in 162 in-cell gpio[0]_oe 161 out-cell gpio[1]_out 160 out-cell gpio[1]_in 159 in-cell gpio[1]_oe 158 out-cell reset 157 in-cell osci 156 in-cell (internal) 155 in-cell (internal) 154 in-cell (internal) 153 in-cell (internal) 152 in-cell (internal) 151 in-cell (internal) 150 in-cell (internal) 149 in-cell (internal) 148 in-cell tsig[4] 147 in-cell tsd[4] 146 in-cell tsig[3] 145 in-cell tsd[3] 144 in-cell tsig[2] 143 in-cell tsd[2] 142 in-cell tsig[1] 141 in-cell tsd[1] 140 in-cell (internal) 139 out-cell (internal) 138 in-cell (internal) 137 out-cell (internal) 136 in-cell (internal) 135 out-cell (internal) 134 out-cell (internal) 133 in-cell
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 350 mar ch 22, 2004 (internal) 132 out-cell (internal) 131 in-cell (internal) 130 out-cell (internal) 129 out-cell (internal) 128 in-cell (internal) 127 out-cell (internal) 126 in-cell (internal) 125 out-cell (internal) 124 out-cell (internal) 123 in-cell (internal) 122 out-cell (internal) 121 in-cell (internal) 120 out-cell tsfs4_out 119 out-cell tsfs4_in 118 in-cell tsck4_out 117 out-cell tsck4_in 116 in-cell tsck_fs4_oe 115 out-cell tsfs3_out 114 out-cell tsfs3_in 113 in-cell tsck3_out 112 out-cell tsck3_in 111 in-cell tsck_fs3_oe 110 out-cell tsfs2_out 109 out-cell tsfs2_in 108 in-cell tsck2_out 107 out-cell tsck2_in 106 in-cell tsck_fs2_oe 105 out-cell tsfs1_out 104 out-cell tsfs1_in 103 in-cell tsck1_out 102 out-cell tsck1_in 101 in-cell tsck_fs1_oe 100 out-cell (internal) 99 out-cell (internal) 98 out-cell (internal) 97 out-cell (internal) 96 out-cell (internal) 95 out-cell (internal) 94 out-cell (internal) 93 out-cell (internal) 92 out-cell (internal) 91 out-cell (internal) 90 out-cell (internal) 89 out-cell (internal) 88 out-cell rsig[4] 87 out-cell rsd[4] 86 out-cell table 84: boundary scan (bs) sequence (continued) bs-cell name bs no. bs-cell type rsd_rsig4_en 85 out-cell rsig[3] 84 out-cell rsd[3] 83 out-cell rsd_rsig3_en 82 out-cell rsig[2] 81 out-cell rsd[2] 80 out-cell rsd_rsig2_en 79 out-cell rsig[1] 78 out-cell rsd[1] 77 out-cell rsd_rsig1_en 76 out-cell (internal) 75 out-cell (internal) 74 in-cell (internal) 73 out-cell (internal) 72 in-cell (internal) 71 out-cell (internal) 70 out-cell (internal) 69 in-cell (internal) 68 out-cell (internal) 67 in-cell (internal) 66 out-cell (internal) 65 out-cell (internal) 64 in-cell (internal) 63 out-cell (internal) 62 in-cell (internal) 61 out-cell (internal) 60 out-cell (internal) 59 in-cell (internal) 58 out-cell (internal) 57 in-cell (internal) 56 out-cell rsfs4_out 55 out-cell rsfs4_in 54 in-cell rsck4_out 53 out-cell rsck4_in 52 in-cell rsck_fs4_en 51 out-cell rsfs3_out 50 out-cell rsfs3_in 49 in-cell rsck3_out 48 out-cell rsck3_in 47 in-cell rsck_fs3_en 46 out-cell rsfs2_out 45 out-cell rsfs2_in 44 in-cell rsck2_out 43 out-cell rsck2_in 42 in-cell rsck_fs2_en 41 out-cell rsfs1_out 40 out-cell rsfs1_in 39 in-cell table 84: boundary scan (bs) sequence (continued) bs-cell name bs no. bs-cell type
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 351 mar ch 22, 2004 rsck1_out 38 out-cell rsck1_in 37 in-cell rsck_fs1_en 36 out-cell int _out 35 out-cell int _oe 34 out-cell spien 33 in-cell mpm 32 in-cell ds / rd /sclk 31 in-cell wr /r w /sdi 30 in-cell cs 29 in-cell d0_out 28 out-cell d0_in 27 in-cell d1_out 26 out-cell d1_in 25 in-cell d2_out 24 out-cell d2_in 23 in-cell d3_out 22 out-cell d3_in 21 in-cell d4_out 20 out-cell d4_in 19 in-cell d5_out 18 out-cell d5_in 17 in-cell d6_out 16 out-cell d6_in 15 in-cell d7_out 14 out-cell d7_in 13 in-cell d_oen 12 out-cell a[0] 11 in-cell a[1] 10 in-cell a[2] 9 in-cell a[3] 8 in-cell a[4] 7 in-cell a[5] 6 in-cell a[6] 5 in-cell a[7] 4 in-cell a[8] 3 in-cell a[9] 2 in-cell (internal) 1 in-cell table 84: boundary scan (bs) sequence (continued) bs-cell name bs no. bs-cell type
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 352 mar ch 22, 2004 6.3 test access po rt controller the tap controller is a 16-state synchronous state machine. figure - 41 shows its state diagram. a description of each state is listed in table 85. note that the figure c ontains two main branches to access either the data or instruction regi sters. the value shown next to each state transition in this figure states the value present at tms at each ris- ing edge of tck. table 85: tap controller state description state description test logic reset in this state, the test logic is disabled to continue normal operation of the device. during initialization, the device initial izes the instruction register with the idcode instruction. regardless of the original state of the controller, the controller enters the test-logic-reset state when the tms input is held high for at least 5 rising edges of tck. the controller remains in this state while tms is high. run-test/ idle this is a controller state between scan operations. once in this state, the controller remains in the state as long as tms is h eld low. the instruction reg- ister and all test data registers retain their previous state. when tms is high and a rising edge is applied to tck, the contro ller moves to the select-dr state. select-dr- scan this is a temporary controller state and the instruction does not change in this state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves into the captur e-dr state and a scan sequence for the selected test data register is initiated. if tms is held high and a rising edge applied to tck, the controller moves to the select-ir-scan state. capture- dr in this state, the boundary scan register captures input pin dat a if the current instruction is extest or sample/preload. the i nstruction does not change in this state. the other test data registers, which do not have parallel input, are not changed. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or the shift-dr state if tms is low. shift-dr in this controller state, the test data register connected between tdi and tdo as a result of the current instruction s hifts data on stage toward its serial output on each rising edge of tck. the instruction does not change in this state. when the tap controller is in this state and a rising edge is applied to tck, the controller enters the exit1-dr state if tms is high or remains in the shift-dr state if tms is low. exit1-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-dr sta te. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. pause-dr the pause state allows the test controller to temporarily halt the shifting of data through the test data register in t he serial path between tdi and tdo. for example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test sequence. the test data reg- ister selected by the current instruction retains its previous value and the instruction does not change during this state. the controller remains in this state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-dr state . exit2-dr this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-dr state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-dr sta te. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. update-dr the boundary scan register is provided with a latched parallel output to prevent changes while data is shifted in resp onse to the extest and sam- ple/preload instructions. when the tap controller is in this state and the boundary scan register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of tck. the data held at the latched parallel output changes only in this state. all shift-reg- ister stages in the test data register selected by the current instruction retain their previous value and the instruction does not change during this state. select-ir- scan this is a temporary controller state. the test data register selected by the current instruction retains its previous state. if tms is held low and a rising edge is applied to tck when in this state, the controller moves into the capture-ir state, and a scan sequence for the instruct ion register is initiated. if tms is held high and a rising edge is applied to tck, the controller moves to the test-logic-reset state. the instruction does not change during this state. capture-ir in this controller state, the shift register contained in the instruction register loads a fixed value of '100' on th e rising edge of tck. this supports fault-iso- lation of the board-level serial test data path. data registers selected by the current instruction retain their value and the instruction does not change dur- ing this state. when the controller is in this state and a rising edge is applied to tck, the controller enters the exit1-ir st ate if tms is held high, or the shift-ir state if tms is held low. shift-ir in this state, the shift register contained in the instru ction register is connected between tdi and tdo and shifts dat a one stage towards its serial output on each rising edge of tck. the test data register selected by the current instruction retains its previous value and the instr uction does not change dur- ing this state. when the controller is in this state and a rising edge is applied to tck, the controller enters the exit1-ir st ate if tms is held high, or remains in the shift-ir state if tms is held low. exit1-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the pause-ir sta te. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 353 mar ch 22, 2004 pause-ir the pause state allows the test controller to temporarily halt the shifting of data through the instruction register. t he test data register selected by the cur- rent instruction retains its previous value and the instruction does not change during this state. the controller remains in th is state as long as tms is low. when tms goes high and a rising edge is applied to tck, the controller moves to the exit2-ir state. exit2-ir this is a temporary state. while in this state, if tms is held high, a rising edge applied to tck causes the controller to enter the update-ir state, which terminates the scanning process. if tms is held low and a rising edge is applied to tck, the controller enters the shift-ir sta te. the test data register selected by the current instruction retains its previous value and the instruction does not change during this state. update-ir the instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of tck. when the new instruction has been latched, it becomes the current instruction. the test data registers selected by the current instruction r etain their previous value. table 85: tap controller state description (continued) state description
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ieee std 1149.1 jtag test a ccess port 354 mar ch 22, 2004 figure 41. jtag state diagram test-logic reset run test/idle select-dr select-ir capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 0 1 1 1 00 00 0 0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 0 1
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 355 march 22, 2004 7 physical and electrical specifications 7.1 absolute maximum ratings caution: long-term exposure to absolute maximum ratings may affect the device?s reliability, and permanent damage may occur if the rating is exceeded during operation. functional operati on under these conditions is not impli ed. the device should be operated under reco mmended operating conditions. 7.2 recommended oper ating conditions min max storage temperature -65 c +150 c voltage on vddar/vddat/vddax/vd dab/vddap w.r.t. gnd -0.5 v 4.6 v voltage on vdddio w.r.t. gnd -0.5 v 4.6 v voltage on vdddc w.r.t. gnd -0.5 v 2.2 v voltage on any input digital pin -0.5 v 6 v voltage on any input analog pin -0.5 v vddar/vddat/vddax/ vddab/vddap + 0.5 esd performance (hbm) 2000 v latch-up current on any pin 1.5 x inormal * maximum junction temperature 150 maximum allowed power dissipation (package) 2.63w note: * inormal is the total curr ent in normal operation mode. parameter description min. typ. max unit top operating temperature range -40 25 85 c vdddio digital io power supply 3.0 3.3 3.6 v vddar/vddat/vddax/vddab/vddap ana log io power supply 3.13 3.3 3.47 v vdddc digital core power 1.68 1.8 1.98 v vil input low voltage 0 0.8 v vih input high voltage 2.0 3.3 v
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 356 march 22, 2004 7.3 d.c. characteristics @ ta = -40 to +85 c, vdddio = 3.3 v + 0.3 v, vdddc = 1.8 + 10% parameter description min. typ. max unit test conditions vol output low voltage 0.40 v vdddio = min, iol = 4 ma, 8 ma voh output high voltage 2.4 v vdddio = min, ioh = 4 ma, 8 ma vt+ schmitt trigger input low to high threshold point for ios with schmitt trigger 1.35 v vt- schmitt trigger input high to low threshold point for ios with schmitt trigger 1.02 v r pu pullup resistor in pull-up ios 50 70 115 k ? iil input low current -1 0 +1 a vil = gndd iih input high current -1 0 +1 a vih = vdddio iol d output low current 8 ma vo = vol, d7 - d0 ioh d output high current 8 ma vo = voh, d7 - d0 iol output low current 4 ma vo = vol, except d7 - d0 ioh output high current 4 ma vo = voh, except d7 - d0 c in input digital pin capacitance 10 pf i zl leakage current of digital output in high-impedance mode -10 10 a gnd < vo < vdddio p power dissipation 450 mw with the prbs pattern, excluding loading dissipation p33 power dissipation in 3.3 v domain 350 mw p18 power dissipation in 1.8 v domain 100 mw
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 357 march 22, 2004 7.4 digital i/o timing characteristics the capacitive loading for timing measurement is: 100 pf for bus: d[7:0], 50 pf for other pins. the timing can be applied to both clock edges as defined by active clock edge selection. delays are measured according to the cr oss of 50% of the rising/falling edge. the duty cycle for tsckn/mtsck & rsckn/mrsck is from 40% to 60%. the system input / output timing in is listed as below: figure 42. i/o timing in mode 7.5 clock freque ncy requirement - relative to nominal rate symbol parameter min. typ. max unit tprop propagation delay -10 / 0 * 20 ns ts set up time 10 ns thold hold time 10 ns note: * the ?-10? applies to the case that t he clock is input and the ?0? applies to the case that the clock is output. min max unit tsck -100 +100 ppm rsck -100 +100 ppm osci -32 +32 ppm rsck inputs tprop outputs thold ts tsck
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 358 march 22, 2004 7.6 t1/j1 line receiver el ectrical characteristics parameter min. typ. max unit test conditions receiver sensitivity short haul with cable loss @ 772 khz: long haul with cable loss @ 772 khz: 10 36 db with nominal pulse amplitude of 3.0 v for 100 ? termina- tion analog los level short haul: long haul: 4 800 48 mvp-p db a los level is programmable for long haul. allowable consecutive zeros before los t1.231 - 1993: i.431: 175 1544 los reset 12.5 % ?one?s g.775, etsi 300233 receive intrinsic jitter 10 hz - 8 khz 10 hz - 40 khz 8 khz - 40 khz wide band 0.02 0.025 0.025 0.05 u.i. u.i. u.i. u.i. ja is enabled input jitter tolerance 0.1 hz - 1 hz: 4.9 hz - 300 hz: 10 khz - 100 khz: 138.0 28.0 0.4 u.i. u.i. u.i. at&t62411 receiver differential input impedance 20 k ? input termination resistor tolerance 1% receive return loss 39 khz - 77 khz: 77 khz - 1.544 mhz: 1.544 mhz - 2.316 mhz 20 20 20 db db db g.703 internal termination
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 359 march 22, 2004 7.7 e1 line receiver el ectrical characteristics parameter min. typ. max unit test conditions receiver sensitivity short haul with cable loss @ 1024 khz: long haul with cable loss @ 1024 khz: 10 43 db with nominal pulse amplitude of 3.0 v for 120 ? and 2.37 v for 75 ? termination analog los level short haul: long haul: 4 800 48 mvp-p db a los level is programmable for long haul. allowable consecutive zeros before los g.775: i.431 / etsi300233: 32 2048 los reset 12.5 % ?one?s g.775, etsi 300233 receive intrinsic jitter 0.05 u.i. ja is enabled; wide band input jitter tolerance 1 hz - 20 hz: 20 hz - 2.4 khz: 18 khz - 100 khz: 37 5 2 u.i. u.i. u.i. g.823, with 6 db cable attenuation receiver differential input impedance 20 k ? input termination resistor tolerance 1% receive return loss 51 khz - 102 khz: 102 khz - 2.048 mhz: 2.048 mhz - 3.072 mhz 20 20 20 db db db g.703 internal termination
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 360 march 22, 2004 7.8 t1/j1 line transmitter electrical characteristics parameter min. typ. max unit output pulse amplitudes 2.4 3.0 3.6 v zero (space) level -0.15 0.15 v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv output pulse width at 50% of nominal amplitude 338 350 362 ns pulse width variation at the half amplitude (t1.102) 20 ns imbalance between positive and negative pulses amplitude (t1.102) 0.95 1.05 transmit return loss 39 khz - 77 khz: 77 khz - 1.544 mhz: 1.544 mhz - 2.316 mhz: 20 15 12 db db db intrinsic transmit jitter (tsck is jitter free) 10 hz - 8 khz: 8 khz - 40 khz: 10 hz - 40 khz: wide band: 0.020 0.025 0.025 0.050 u.i.p-p u.i.p-p u.i.p-p u.i.p-p line short circuit current 110 ma ip-p
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 361 march 22, 2004 7.9 e1 line transmitter el ectrical characteristics parameter min. typ. max unit output pulse amplitudes e1, 75 ? load: e1, 120 ? load: 2.14 2.7 2.37 3.0 2.60 3.3 v v zero (space) level e1, 75 ? load: e1, 120 ? load: -0.237 -0.3 0.237 0.3 v v transmit amplitude variation with supply -1 +1 % difference between pulse sequences for 17 consecutive pulses (t1.102) 200 mv output pulse width at 50% of nominal amplitude 232 244 256 ns ratio of the amplitudes of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 ratio of the width of positive and negative pulses at the center of the pulse interval (g.703) 0.95 1.05 transmit return loss (g.703) e1, 75 ? / 120 ? 51 khz - 102 khz: 102 khz - 2.048 mhz: 2.048 mhz - 3.072 mhz: 20 15 12 db db db intrinsic transmit jitter (tsck is jitter free) 20 hz - 100 khz 0.050 u.i. line short circuit current 110 ma ip-p
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 362 march 22, 2004 7.10 jitter tolerance 7.10.1 t1/j1 mode figure 43. t1/j1 jitter tolerance performance requirement jitter tolerance min. typ. max unit standard 1 hz 138.0 u.i. at&t 62411 4.9 hz - 300 hz 28.0 u.i. 10 khz - 100 khz 0.4 u.i.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 363 march 22, 2004 7.10.2 e1 mode figure 44. e1 jitter tole rance performa nce requirement jitter tolerance min. typ. max unit standard 1 hz 37 u.i. g.823 cable attenuation is 6 db 20 hz - 2.4 khz 1.5 u.i. 18 khz - 100 khz 0.2 u.i.
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 364 march 22, 2004 7.11 jitter transfer 7.11.1 t1/j1 mode t1/j1 jitter transfer performance is required by at&t pub.62411. figure 45. t1/j1 jitter transfer performance requirement (at&t62411 / gr-253-core / tr-tsy-000009) parameter min. typ. max unit jitter attenuator latency delay 32-bit fifo: 64-bit fifo: 128-bit fifo: 16 32 64 u.i. u.i. u.i. input jitter tolerance before fifo overflow or underflow 32-bit fifo: 64-bit fifo: 128-bit fifo: 28 58 120 u.i. u.i. u.i. parameter min. typ. max unit @ 1 hz 0 db @ 20 hz 0 @ 1 khz +33.3 @ 1.4 khz 40 @ 70 khz 40
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 365 march 22, 2004 7.11.2 e1 mode e1 jitter transfer performance is required by g.736. figure 46. e1 jitter transfer performance requirement (g.736) parameter min. typ. max unit @ 3 hz -0.5 db @ 40 hz -0.5 @ 400 hz +19.5 @ 100 khz +19.5
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 366 march 22, 2004 7.12 microprocessor timing specification 7.12.1 motorola non-multiplexed mode 7.12.1.1 read cycle specification figure 47. motorola non-multiplexed mode read cycle symbol parameter min max units trc read cycle time 237 ns tdw valid ds width 232 ns trwv delay from ds to valid read signal 21 ns trwh r w to ds hold time 134 ns tav delay from ds to valid address 21 ns tadh address to ds hold time 134 ns tprd ds to valid read data propagation delay 206 ns tdaz delay from read data active to high z 5 20 ns trecovery recovery time from read cycle 5 ns a[x:0] valid address ds + cs r w read d[7:0] trwv valid data tdaz tadh trwh tprd trc tdw tav trecovery
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 367 march 22, 2004 7.12.1.2 write cycle specification figure 48. motorola non-multiplexed mode write cycle symbol parameter min max units twc write cycle time 237 ns tdw valid ds width 232 ns trwv delay from ds to valid write signal 21 ns trwh r w to ds hold time 165 ns tav delay from ds to valid address 21 ns tah address to ds hold time 165 ns tdv delay from ds to valid write data 83 ns tdhw write data to ds hold time 165 ns trecovery recovery time from write cycle 5 ns a[x:0] valid address ds + cs r w write d[7:0] trwv tdhw tah trwh twc tdw tav valid data tdv trecovery
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 368 march 22, 2004 7.12.2 intel non-multiplexed mode 7.12.2.1 read cycle specification figure 49. intel non-multiplexed mode read cycle symbol parameter min max units trc read cycle time 237 ns trdw valid rd width 232 ns tav delay from rd to valid address 21 ns tah address to rd hold time 134 ns tprd rd to valid read data propagation delay 206 ns tdaz delay from read data active to high z 5 20 ns trecovery recovery time from read cycle 5 ns a[x:0] valid address cs + rd read d[7:0] valid data tdaz tah tprd trdw tav note: the wr pin should be tied to high. trecovery trc
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 369 march 22, 2004 7.12.2.2 write cycle specification figure 50. intel non-multiplexed mode write cycle symbol parameter min max units twc write cycle time 237 ns twrw valid wr width 232 ns tav delay from wr to valid address 21 ns tah address to wr hold time 165 ns tdv delay from wr to valid write data 83 ns tdhw write data to wr hold time 165 ns trecovery recovery time from write cycle 5 ns a[x:0] valid address wr + cs write d[7:0] tdhw tah twc twrw tav valid data tdv note: the rd pin should be tied to high. trecovery
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 370 march 22, 2004 7.12.3 spi mode the maximum spi data transfer clock is 2 mhz. figure 51. spi timing diagram symbol description min. max units f op sclk frequency 2.0 mhz t csh min. cs high time 100 ns t css cs setup time 50 ns t csd cs hold time 100 ns t cld clock disable time 50 ns t clh clock high time 205 ns t cll clock low time 205 ns t dis data setup time 50 ns t dih data hold time 150 ns t pd output delay 150 ns t df output disable time 50 ns cs sclk sdi sdo t csh t css high impedance high impedance t csd t clh t cll t dis t dih t pd t df valid input valid output t cld
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 371 march 22, 2004
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver physical and electrical specifications 372 march 22, 2004
IDT82P2284 quad t1/e1/j1 long haul / short haul transceiver ordering information 373 march 22, 2004 corporate headquarters for sales: for tech support: 2975 stender way800-345-7015 or 408-727-5116408-330-1552 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. ordering information idt xxxxxxx xx x device type package process/temperature range blank industrial (-40 c to +85 c) bb plastic ball grid array (pbga, bb208) 82p2284 quad t1/e1/j1 long / short haul transceiver

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