1/5 ESDA25DB3 ? august 2001 - ed : 2 n 18 bidirectional transil functions n low capacitanc e:c= 30pf @ v rm n 500 w peak pulse power (8/20 m s) features so-20 i 1 2 o functional diagram the ESDA25DB3 is a dual monolithic voltage suppressor designed to protect components which are connected to data and transmission lines against esd. description transil array for esd protection application specific discretes a.s.d.? where transient overvoltage protection in esd sensitive equipment is required, such as : - computers - printers - communication systems it is particulary recommended for rs232 i/o port protection where the line interface withstands 2 kv, esd surges. applications high esd protection level : up to 25 kv high integration suitable for high density boards benefits iec 1000-4-2 : level 4 mil std 883c-method 3015-6 : class 3 (human body model) complies with the following standards :
ESDA25DB3 2/5 symbol parameter v rm stand-off voltage v br breakdown voltage v cl clamping voltage i rm leakage current i pp peak pulse current a t voltage temperature coefficient c capacitance electrical characteristics (t amb = 25c) symbol parameter value unit v pp electrostatic discharge mil std 883c - method 3015-6 25 kv p pp peak pulse power (8/20 m s) 500 w t stg t j storage temperature range maximum junction temperature -55to+150 125 c c t l maximum lead temperature for soldering during 10s 260 c absolute maximum ratings (t amb = 25c) types v br @ i r i rm @v rm rd a tc min. max. max. typ. max. typ. note1 note1 note 2 note 3 0v bias vvma m av w 10 -4 /c pf ESDA25DB3 25 30 1 2 24 0.5 9.7 50 note 1 : betwenn any i/o pin groung note 2 : square pulse, ipp = 25a, tp=2.5 m s. note 3 : d v br = a t* (tamb -25c) * v br (25c)
ESDA25DB3 3/5 the esda family has been designed to clamp fast spikes like esd. generally the pcb designers need to calculate easily the clamping voltage v cl . this is why we give the dynamic resistance in addition to the classical parameters. the voltage across the protection cell can be calculated with the following formula: v cl =v br +rdi pp where ipp is the peak current through the esda cell. dynamic resistance measurement the short duration of the esd has led us to prefer a more adapted test wave, as below defined, to the classical 8/20 m s and 10/1000 m s surges. 2.5 m s duration measurement wave. as the value of the dynamic resistance remains stable for a surge duration lower than 20 m s, the 2.5 m s rectangular surge is well adapted. in addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of rd. calculation of the clamping voltage use of the dynamic resistance 2s tp = 2.5s t i ipp
ESDA25DB3 4/5 0 25 50 75 100 125 150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 ppp[tj initial]/ppp[tj initial=25c] tj initial(c) fig. 1 : peak power dissipation versus initial junction tempearature. 20 25 30 35 40 45 50 55 60 0.1 1.0 10.0 50.0 ipp(a) tp=2.5s v (v) cl fig. 3 : clamping voltage versus peak pulse current (tj initial = 25 c). rectangular waveform tp = 2.5 m s. 110100 100 1000 5000 ppp(w) tp(s) fig. 2 : peak pulse power versus exponential pulse duration (tj initial = 25 c). 12 510 30 10 20 50 100 c(pf) f=1mhz vosc=30mv v (v) r fig. 4 : capacitance versus reverse applied voltage (typical values). 25 50 75 100 125 1 10 100 200 i [tj] / i [tj=25c] rr tj(c) fig. 5 : relative variation of leakage current versus junction temperature (typical values).
ESDA25DB3 5/5 package mechanical data so-20 plastic marking: logo, date code, e25db3 packaging : preferred packaging is tape and reel. weight: 0.55g. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap- proval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com ref. dimensions millimetres inches min. typ. max. min. typ. max. a 2.65 0.104 a1 0.10 0.20 0.004 0.008 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13.0 0.484 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.50 0.020 l 0.50 1.27 0.020 0.050 k 8 (max) k hx45 c l a a1 b e d eh esda 25 d b 3 rl esd array v min br bidirectionel packaging: rl = tape & reel = tube package so-20 order code
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