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ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 1 g574 global mixed-mode technology inc. dual-slot pcmcia/cardbus power controller features ? backward compatible with g570 ? fully integrated v cc and v pp switching for dual slot pc card tm interface ? 3-lead serial interface compatible with cardbus tm controllers ? 3.3v low voltage mode ? meets pc card standards ? reset for system initia lization of pc cards ? 12v supply can be disabled except during 12v flash programming ? short circuit and thermal protection ? 30 pin ssop ? compatible with 3.3v, 5v and 12v pc cards ? low r ds(on) (180-m 5v v cc switch; 130 m 3.3v v cc switch) ? break-before-make switching ? internal power-on reset ? standby mode: 60ma current limit (typ) application ? notebook pc ? electronic dictionary ? pos description the g574 pc card power-interface switch provides an integrated power-management solution for two pc cards. all of the discrete power mosfets, a logic sec- tion, current limiting, and thermal protection for pc card control are combined on a single integrated circuit (ic). the circuit allows the distribution of 3.3v, 5v, and/or 12v card power by means of the serial interface. the current-limiting feature eliminates the need for fuses, which reduces component count and improves reliabil- ity. the g574 features a 3.3v low voltage mode that allows for 3.3v switching without the need for 5v supply. this facilitates low power system designs such as sleep mode and pager mode where only 3.3v is available. the g574 incorporates a reset function, selectable by one of two inputs, to help alleviate system errors. the reset function enables pc card initialization concurrent with host platform initialization, allowing a system reset. reset is accomplished by grounding the v cc and v pp (flash-memory programming voltage) outputs, which discharges residual card voltage. this device also has the ability to program the xvpp outputs independent of the xvcc outputs. a standby mode that changes all output-current limits to 50ma (typical) has been incorporated. end equipment for the g574 includes notebook com- puters, desktop computers, personal digital assistants (pdas), digital cameras and bar-code scanners . the g574 is backward-compatible with the g570. ordering information order number order number (pb free) temp. range package g574sa G574SAF -40 c to +85 c ssop-30 pin configuration mode nc nc 12v bvpp bvcc bvcc bvcc stby oc 3.3v 3.3v 5v data clock latch reset 12v avpp avcc avcc avcc gnd nc reset 3.3v g574 5v ssop-30 5 6 7 8 9 10 11 12 13 14 26 27 28 25 24 23 22 21 20 19 18 17 16 15 1 4 3 2 5v 30 29 nc nc mode nc nc 12v bvpp bvcc bvcc bvcc stby oc 3.3v 3.3v 5v data clock latch reset 12v avpp avcc avcc avcc gnd nc reset 3.3v g574 5v ssop-30 5 6 7 8 9 10 11 12 13 14 26 27 28 25 24 23 22 21 20 19 18 17 16 15 1 4 3 2 5v 30 29 nc nc
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 2 g574 global mixed-mode technology inc. absolute maximum ratings over operating free-air temperature (unless otherwise noted)* input voltage range for card power: v i(3.3v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v v i(5v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6v v i(12v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3v to 14v logic input voltage. . . . . . . . . . . . . . . . . . . -0.3v to 6v output current (each card): i o (xvcc) . . . . . . . . . . . . . . . . . . . . . . . . internally limited i o(xvpp) . . . . . . . . . . . . . . . . . . . . . . . . .internally limited operating virtual junction temperature range, t j . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 c to 125 c operating free-air temperature range, t a . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .-40 c to 85 c storage temperature range, t stg . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55 c to 150 c thermal resistance ja ssop-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 c/w power dissipation p d (t a +25 c) ssop-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1024mw esd. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .note1 *stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress rating only, and functional operation of the device at thes e or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute- maximum-rated conditions for extended periods may a ffect device reliability. note 1: esd (electrostatic discharge) s ensitive device. proper esd precautions ar e recommended to avoid performance degradation or less of functionality. recommended operating conditions min max unit v i (5v) 2.7 5.25 v v i (3.3v) 2.7 5.25 v input voltage range, v i v i (12v) --- 13.5 v i o (xvcc) at 25 c --- 1 a output current i o (xvpp) at 25 c --- 150 ma clock frequency 0 2.5 mhz operating virtual junction temperature, t j -40 125 c typical pc card power-distribution application 0.1 f 0.1 f 12v 12v avcc avcc avcc bvcc bvcc bvcc avpp bvpp data clock latch reset reset oc system voltage supervisor or pci bus reset 0.1 f 0.1 f v cc v cc pc card connector a v pp1 v pp2 pc card connector b v pp2 v pp1 v cc v cc data clock latch pcmcia controller 5v 3.3v 33 f 0.1 f 33 f 0.1 f 5v 5v 5v 3.3v 3.3v 3.3v gnd g574 0.1 f 10 f 12v (ceramic) (ceramic) (ceramic) stby mode gpi/o 0.1 f 0.1 f 12v 12v avcc avcc avcc bvcc bvcc bvcc avpp bvpp data clock latch reset reset oc system voltage supervisor or pci bus reset 0.1 f 0.1 f v cc v cc pc card connector a v pp1 v pp2 pc card connector b v pp2 v pp1 v cc v cc data clock latch pcmcia controller 5v 3.3v 33 f 0.1 f 33 f 0.1 f 5v 5v 5v 3.3v 3.3v 3.3v gnd g574 0.1 f 10 f 12v (ceramic) (ceramic) (ceramic) stby mode gpi/o
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 3 g574 global mixed-mode technology inc. terminal functions terminal name no. i/o description 3.3v 15,16,17 i 3.3v v cc input for card power 5v 1,2,30 i 5v v cc input for card power and/or chip power 12v 7,24 i 12v v pp input for card power avcc 9,10,11 o switched output t hat delivers 0v, 3.3v, 5v or high impedance to card avpp 8 o switched output that delivers 0v, 3. 3v, 5v, 12v or high impedance to card bvcc 20,21,22 o switched output that delivers 0v, 3.3v, 5v or high impedance bvpp 23 o switch output that delivers 0v, 3.3v, 5v, 12v or high impedance gnd 12 ground mode 29 i g570 operation when floating or pulled low; must be pulled high exter nally for g574 operation. mode is internally pulled low with a 150k pulldown resistor. oc 18 o logic-level overcurrent. reports output that goes low when an overcurrent condition exists reset 6 i logic-level reset input active high. do not connect if reset pin is used. reset is internally pulled low with a 150k pulldown resistor. reset 14 i logic-level reset input active low. do not connect if reset pin is used. the pin is internally pulled high with a 150k pullup resistor to 5v, if 5v v cc exists. and pulled to 3.3v, if 3.3v v cc exists only. stby 19 logic-level active low input sets the g574 to standby mode and sets all current limits to 50ma. the pin is internally pulled high with a 150k pullup resistor to 5v, if 5v v cc exists. and pulled to 3.3v, if 3.3v v cc exists only. clock 4 i logic level clock for serial data word data 3 i logic level serial data word latch 5 i logic level latch for serial data word nc 13,25,26, 27,28 no internal connection
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 4 g574 global mixed-mode technology inc. electrical characteristics (t a =t j =25 c , v i(5v) =5v, v i(3.3v) =3.3v, v i(12v) =12v, stby floating, all outputs unloaded (unless otherwise noted) dc characteristics parameter test conditions min typ max unit 5v to xvcc --- 150 180 3.3v to xvcc v i(5v) = 5v, v i(3.3v) =3.3v --- 100 130 3.3v to xvcc v i(5v) = 0v, v i(3.3v) =3.3v --- 110 150 m 5v to xvpp --- 3 4 3.3v to xvpp --- 2.9 4 12v to xvpp --- 1.3 2 3.3v/5v to xvcc --- 1.2 2 3.3v/5v to xvpp --- 12 12.5 switch resistance * 12v to xvpp stby = low, i o = 30ma --- 5 6.5 v o(xvpp) clamp low voltage i pp at 10ma --- 0.18 0.8 v v o(xvcc) clamp low voltage i cc at 10ma --- 0.13 0.8 v i pp high impedance state t a = 25 c --- 0.3 1 i ikg leakage current i cc high-impedance state t a = 25 c --- 0.3 1 a i i(3.3v) --- 6 15 i i(5v) --- 110 150 i i(12v) v o(xvcc) = v o(xvcc) = 5v --- 5 15 a i i(3.3v) --- 82 150 i i(5v) --- 0 normal operation and in reset mode i i(12v) v i(5v) = 0, v o(xvcc) = 3.3v v o(xvpp) = 12v --- 17 45 a i i(3.3v) --- --- 1 i i(5v) --- 2 10 i i input current shutdown mode i i(12v) v o(xvcc) = hi-z, v o(xvpp) = hi-z --- --- 1 a i o(xvcc) 0.8 --- 2.2 a i o(xvpp) output powered into a short to gnd 120 --- 450 ma standby mode, 3.3v to xvcc --- 55 120 standby mode, 5v to xvcc --- 70 120 standby mode, 3.3v to xvpp --- 44 120 standby mode, 5v to xvpp --- 78 120 i os short-circuit * output current limit standby mode, 12v to xvpp t j = 25 c output powered into a short to gnd stby =0v --- 60 110 ma trip point, tj --- 155 --- thermal shutdown hysteresis --- 10 --- c * pulse-testing techniques are used to main tain junction temperature close to ambient temperatures; thermal effects must be tak en into ac- count separately. input currents do not include logic input currents (presented in electrical characteristics for logic section); clock is inacti ve. specified by design, not tested in production. logic section parameter test condition min typ max unit v i(reset) = 5v or v i ( reset ) = 0v --- 35 50 i i (reset) or ( reset )* v i(reset) = 0v or v i ( reset ) = 5v --- --- 1 v i(mode) = 5v --- 35 50 i i (mode) * v i(mode) = 0v --- --- 1 v i ( stby ) = 5v --- --- 1 i i ( stby ) * v i ( stby ) = 0v --- 35 50 logic input cur- rent i i (clock) or i i (data) or i i (latch) --- --- 1 a logic input high level 2 --- --- v logic input low level 2 --- 0.8 v v i(5v) = 5v, i o = 1ma v i(5v) 0.4 --- --- logic output high level, oc v i(5v) = 0v, i o = 1ma v i(3.3v) 0.4 --- --- v logic output low level, oc i o = 1ma --- --- 0.4 v * reset and mode have internal 150k pulldown resistors; reset and stby have internal 150k pullup resistors.
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 5 g574 global mixed-mode technology inc. switching characteristics *, ** parameter test condition min typ max unit v o (xvcc) --- 2 --- v o (xvpp) (12v) --- 0.04 --- t r output rise time v o (xvpp) (3.3v or 5v) --- 0.4 --- ms v o (xvcc) --- 0.01 --- t f output fall time v o (xvpp) --- 0.01 --- ms t pd(on) --- 0.2 --- latch to v o(xvpp (12v) t pd(off) --- 1.8 --- ms t pd(on) --- 1.7 --- latch to v o(xvpp= xvcc) (3.3v), v i(5v) = 5v t pd(off) --- 2.2 --- ms t pd(on) --- 1.7 --- latch to v o(xvpp= xvcc) (5v) t pd(off) --- 2.2 --- ms t pd(on) --- 2.4 --- latch to v o(xvcc) (3.3v), v i(5v) = 5v t pd(off) --- 8.5 --- ms t pd(on) --- 1 --- latch to v o(xvcc) (5v) t pd(off) --- 8.5 --- ms t pd(on) --- 2.6 --- t pd propagation delay (see figure 1) latch to v o(xvcc) (3.3v), v i(5v) = 0v t pd(off) --- 8.2 --- ms * refer to parameter measurement information **switching characteristics are with c l = 0.1 f parameter measurement information figure 1. test circuits and voltage waveforms load circuit xvpp i o(xvpp) xvcc i o(xcc) v dd gnd 50% 90% t pd(off) t pd(on) 10% gnd latch v o(xvpp) propagation delay (xvpp) 90% 10% t r t f gnd rise/fall time (xvpp) v dd gnd 50% 90% t off t on 10% gnd latch v o(xvpp) turn on/off time (xvpp) v dd gnd 50% 90% t pd(off) t pd(on) 10% gnd latch v o(xvcc) propagation delay (xvcc) 90% 10% t r t f gnd rise/fall time (xvcc) v dd gnd 50% 90% t off t on 10% gnd latch v o(xvcc) turn on/off time (xvcc) voltage waveforms v o(xvpp) v o(xvcc) load circuit xvpp i o(xvpp) xvcc i o(xcc) v dd gnd 50% 90% t pd(off) t pd(on) 10% gnd latch v o(xvpp) propagation delay (xvpp) 90% 10% t r t f gnd rise/fall time (xvpp) v dd gnd 50% 90% t off t on 10% gnd latch v o(xvpp) turn on/off time (xvpp) v dd gnd 50% 90% t pd(off) t pd(on) 10% gnd latch v o(xvcc) propagation delay (xvcc) 90% 10% t r t f gnd rise/fall time (xvcc) v dd gnd 50% 90% t off t on 10% gnd latch v o(xvcc) turn on/off time (xvcc) voltage waveforms v o(xvpp) v o(xvcc)
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 6 g574 global mixed-mode technology inc. note:data is clocked in on the positive edge of the clock. the positive edge of the latch signal should occur before the next positive edge of the clock. for definition of d0 to d10, see the control logic table. figure 2. serial-interface timing for independe nt xvpp switching when mode=5v or 3.3v note:data is clocked in on the positive edge of the clock. the positive edge of the latch signal should occur before the next positive edge of the clock. for definition of d0 to d8, see the control logic table. figure 3. serial-interface timing when mode = 0v or floating data latch clock d7 d8 d6 d5 d4 d3 d2 d1 d0 d9 d10 data setup time data hold time latch delay time clock delay time data latch clock d7 d8 d6 d5 d4 d3 d2 d1 d0 d9 d10 data setup time data hold time latch delay time clock delay time data latch clock d7 d8 d6 d5 d4 d3 d2 d1 d0 data setup time data hold time latch delay time clock delay time data latch clock d7 d8 d6 d5 d4 d3 d2 d1 d0 data setup time data hold time latch delay time clock delay time
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 7 g574 global mixed-mode technology inc. switching characteristics switching characteristics
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 8 g574 global mixed-mode technology inc. switching characteristics
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 9 g574 global mixed-mode technology inc. switching characteristics switching characteristics
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ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 11 g574 global mixed-mode technology inc. application information overview pc cards were initially introduced as a means to add eeprom (flash memory) to portable computers with limited on-board memory. the idea of add-in cards quickly took hold; modems, wireless lans, global positioning satellite (gps), multimedia, and hard-disk versions were soon available. as the number of pc card applications grew, the engineering community quickly recognized the need for a standard to ensure compatibility across platforms. to this end, the pcmcia was established, comprised of members from leading computer, software, pc card, and semi- conductor manufactures. one key goal was to realize the ? plug-and play ? concept. cards and hosts from different vendors should be compatible ? able to com- municate with one another transparently. pc card power specification system compatibility also means power compatibility. the most current set of specifications (pc card stan- dard) set forth by the pcmcia committee states that power is to be transferred between the host and the card through eight of the 68 terminals of the pc card connector. this power interface consists of two v cc , two v pp , and four ground terminals. multiple v cc and ground terminals minimize connector-terminal and line resistance. the two v pp terminals were originally specified as separate signals but are commonly tied together in the host to form a single node to minimize voltage losses. card primary power is supplied through the v cc terminals; flash-memory programming and erase voltage is supplied through the v pp termi- nals. overcurrent and over-temperature protection pc cards are inherently subject to damage that can result from mishandling. host systems require protec- tion against short-circuited cards that could lead to power supply or pcb-trace damage. even systems robust enough to withstand a short circuit would still undergo rapid battery discharge into the damaged pc card, resulting in the rather sudden and unacceptable loss of system power. most hosts include fuses for protection. however, the reliability of fused systems is poor, as blown fuses require troubleshooting and re- pair, usually by the manufacturer. the g574 takes a two-pronged approach to overcur- rent protection. first, instead of fuses, sense fets monitor each of the power outputs. excessive current generates an error signal that linearly limits the output current, preventing host damage or failure. sense fets, unlike sense resistors or polyfuses, have an added advantage in that they do not add to the series resistance of the switch and thus produce no addi- tional voltage losses. second, when an overcurrent condition is detected, the g574 asserts a signal at oc that can be monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. in the event that an overcurrent condition persists, causing the ic to exceed its maximum junc- tion temperature, thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe operating region. 12v supply not required most pc card switches use the externally supplied 12v v pp power for switch-gate drive and other chip functions, which requires that power be present at all times. the g574 offers considerable power savings by using an internal charge pump to generate the re- quired higher voltages from 5v or 3.3v input; therefore, the external 12v supply can be disable except when needed for flash-memory functions, thereby extending battery lifetime. do not ground the 12v input if the 12v input is not used. additional power savings are real- ized by the g574 during a software shutdown in which quiescent current drops to a typical of 2 a. 3.3v low voltage mode the g574 operates in 3.3v low voltage mode when 3.3v is the only available input voltage (v i(5v) =0, v i(12v) =0).this allows host and pc cards to be oper- ated in low power 3.3v only modes such as sleep modes or pager modes. note that in this operation mode, the g574 derives its bias current from the 3.3v input pin and only 3.3v can be delivered to the card. the 3.3v switch resistance increases, but the added switch resistance should not be critical, because only a small amount of current is delivered in this mode. voltage transitioning requirement pc cards, like portables, are migrating from 5v to 3.3v to minimize power consumption, optimize board space, and increase logic speeds. the g574 is de- signed to meet all combinations of power delivery as currently defined in the pcmcia standard. the latest protocol accommodates mixed 3.3v/5v systems by first powering the card with 5v, then polling it to de- termine its 3.3v compatibility. the pcmcia specifica- tion requires that the capacitors on 3.3v compatible cards be discharged to below 0.8 v before applying 3.3v power. this ensures that sensitive 3.3v circuitry is not subjected to any residual 5v charge and func- tions as a power reset. the g574 offer a selectable v cc and v pp ground state, in accordance with pcmcia 3.3v/5v switching specifications, to fully discharge the card capacitors while switching between v cc voltage.
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 12 g574 global mixed-mode technology inc. shutdown mode in the shutdown mode, which can be controlled by bit d8 of the input serial data word, each of he xvcc and xvpp outputs is forced to a high-inpedance state. in this mode, the chip quiescent current is limited to 2 a or less to conserve battery power. standby mode the g574 can be put in standby mode by pulling stby low to conserve power during low-power opera- tion. in this mode, all of the power outputs (xvcc and xvpp) will have a nominal current limit of 50ma. stby has an internal 150k pullup resistor. the out- put-switch status of the device must be set, allowing the output capacitors to charge, prior to enabling the standby mode. changing the setting of the output switches with the device in standby mode may cause an overcurrent response to be generated. mode the mode pin programs the switches in either g574 or g570 mode. an internal 150 k pulldown resistor is connected to the pin. floating or pulling the mode pin low sets the switches in g570 mode; pulling the mode pin high sets the switches in g574 mode. in g570mode, xvpp outputs are dependent on xvcc outputs. in g574 mode, xvpp is programmed inde- pendent of xvcc. refer to g574 control-logic tables for more information. output ground switches several pcmcia power distribution switches on the market do not have an active grounding fet switch. these devices do not meet the pc card specification requiring a discharge of v cc within 100ms. pc card resistance can not be relied on to provide a discharge path for voltages stored on pc card capacitance be- cause of possible high impedance isolation by power management schemes. a method commonly shown to alleviate this problem is to add to the switch output an external 100k resistor in parallel with the pc card. considering that this is the only discharge path to ground, a timing analysis show that the rc time con- stant delays the required discharge time to more than 2 seconds. the only way to ensure timing compatibility with pc card standards is to use a power-distribution switch that has an internal ground switch, like that of the g574, or add an external ground fet to each of the output lines with the control logic necessary to se- lect it. in summary, the g574 is a complete single-chip dual-slot pc card power interface. it meets all cur- rently defined pcmcia specifications for power deliv- ery in 5v, 3.3v, and mixed systems, and offers a serial control interface. the g574 offers functionality, power savings, overcurrent and thermal protection, and fault reporting in one 30 pin ssop surface-mount package for maximum value added to new portable designs. power supply considerations the g574 has multiple pins for each of its 3.3v, 5v, and 12v power inputs and for switched v cc outputs. any individual pin can conduct the rated input or out- put current. unless all pins are connected in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost power. both 12v inputs must be connected for proper v pp switching; it is recommended that all input and output power pins be paralleled for optimum operation. although the g574 is fairly immune to power input fluctuations and noise, it is generally considered good design practice to bypass power supplies typically with a 1 f electrolytic or tantalum capacitor paralleled by a 0.047 f to 0.1 f ceramic capacitor. it is strongly re- commended that the switched v cc and v pp outputs be bypassed with a 0.1 f or larger capacitor; doing so improves the immunity of the g574 to electrostatic discharge (esd). care should be taken to minimize the inductance of pcb traces between the g574 and the load. high switching currents can produce large negative-voltage transients, which forward biases sub- strate diodes, resulting in unpredictable performance. similarly, no pin should be taken below ? 0.3v. reset or reset inputs to ensure that cards are in a known state after power brownouts or system initialization, the pc cards should be reset at the same time as the host by ap- plying a low impedance to the xv cc and xv pp terminals to ground. a low impedance output state allows dis- charging of residual voltage remaining on pc card filter capacitance, permitting the system (host and pc cards) to be powered up concurrently. the reset or reset input will closes internal switches s1, s4, s7, and s11 with all other switches left open (see g574 control logic table). the g574 remains in the low im- pedance output state until the signal is deasserted and further data is clocked in and latched. reset or reset are provided for direct compatibility with sys- tems that use either an active-low or active-high reset voltage supervisor. the unused pin is internally pulled up or down and should be left unconnected. overcurrent and thermal protection the g574 uses sense fets to check for overcurrent conditions in each of the v cc and v pp outputs. unlike sense resistors or polyfuses, these fets do not add to the series resistance of the switch; therefore, voltage and power losses are reduced. overcurrent sensing is applied to each output separately. when an overcur- rent condition is detected, only the power output af- fected is limited; all other power outputs continue to function normally. the oc indicator, normally a logic high, is a logic low when any overcurrent condition is detected, providing for initiation of system diagnostics and/or sending a warning message to the user.
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 13 g574 global mixed-mode technology inc. during power up, the g574 controls the rise time of the v cc and v pp outputs and limits the current into a faulty card or connector. if a short circuit is applied after power is established (e.g., hot insertion of a bad card), current is initially limited only by the impedance between the short and the power supply. in extreme cases, as much as 10a to 15a may flow into the short before the current limiting of the g574 engages. if the v cc or v pp outputs are driven below ground, the g574 may latch nondestructively in an off state. cycling power will reestablish normal operation. overcurrent limiting for the v cc outputs is designed to activate, if powered up, into a short in the range of 0.8a to 2.2a. the v pp outputs limit from 120ma to 450ma. the protection circuitry acts by linearly limiting the current passing through the switch rather than ini- tiating a full shutdown of the supply. shutdown occurs only during thermal limiting. thermal limiting prevents destruction of the ic from overheating if the package power-dissipation ratings are exceeded. thermal limiting disables all power outputs (both a and b slots) until the device has cooled. logic input and outputs the serial interface consists of data, clock, and latch leads. the data is clocked in on the positive leading edge of the clock (see figure 2 and 3 ). the bit (d0 through d10 serial data word is loaded during the positive edge of the latch signal. the latch signal should occur before the next positive leading edge of the block. the shutdown bit of the data word places all v cc and v pp outputs in a high-impedance state and reduces chip quiescent current to 2 a to conserve battery power. the g574 serial interface is designed to be compatible with serial-interface pcmcia controllers and current pcmcia and japan electronic industry development association (jeida) standards. an overcurrent output ( oc ) is provided to indicate an overcurrent condition in any of the v cc or v pp outputs as previously discussed. functional block diagram thermal internal current monitor reset reset data oc gnd 5v 5v 12v g574 clock latch stby mode cs cs cs cs cs cs cs cs cs cs both 12v pins must be connected together. 15 16 17 1 2 30 3.3v 3.3v 3.3v s1 s2 s3 5v 12v 7 24 29 19 3 4 5 6 14 18 s7 s8 s9 s10 9 10 11 8 20 21 22 23 12 s11 s12 s13 s14 s4 s5 s6 avcc avcc avcc avpp bvcc bvcc bvcc bvpp thermal internal current monitor reset reset data oc gnd 5v 5v 12v g574 clock latch stby mode cs cs cs cs cs cs cs cs cs cs cs cs cs both 12v pins must be connected together. 15 16 17 1 2 30 3.3v 3.3v 3.3v s1 s2 s3 5v 12v 7 24 29 19 3 4 5 6 14 18 s7 s8 s9 s10 9 10 11 8 20 21 22 23 12 s11 s12 s13 s14 s4 s5 s6 avcc avcc avcc avpp bvcc bvcc bvcc bvpp
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 14 g574 global mixed-mode technology inc. g574 control logic g574 mode (mode pulled high) xvpp avpp control signals bvpp control signals d8 ( shdn ) d0 d1 d9 output v_avpp d8 ( shdn ) d4 d5 d10 output v_bvpp 1 0 0 0v 1 0 0 0v 1 0 1 0 3.3v 1 0 1 0 3.3v 1 0 1 1 5v 1 0 1 1 5v 1 1 0 12v 1 1 0 12v 1 1 1 hi-z 1 1 1 hi-z 0 hi-z 0 hi-z xvcc avcc control signals bvcc control signals d8 ( shdn ) d3 d2 output v_avcc d8 ( shdn ) d6 d7 output v-bvcc 1 0 0 0v 1 0 0 0v 1 0 1 3.3v 1 0 1 3.3v 1 1 0 5v 1 1 0 5v 1 1 1 0v 1 1 1 0v 0 x hi-z 0 x hi-z g570 mode (mode floating or pulled low) xvpp avpp control signals bvpp control signals d8 ( shdn ) d0 d1 output v_avpp d8 ( shdn ) d4 d5 output v-bvpp 1 0 0 0v 1 0 0 0v 1 0 1 v_avcc 1 0 1 v_bvcc 1 1 0 12v 1 1 0 12v 1 1 1 hi-z 1 1 1 hi-z 0 x hi-z 0 x hi-z xvcc avcc control signals bvcc control signals d8 ( shdn ) d3 d2 output v_avcc d8 ( shdn ) d6 d7 output v-bvcc 1 0 0 0v 1 0 0 0v 1 0 1 3.3v 1 0 1 3.3v 1 1 0 5v 1 1 0 5v 1 1 1 0v 1 1 1 0v 0 x hi-z 0 x hi-z
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 15 g574 global mixed-mode technology inc. esd protection the xv cc and xv pp outputs can be exposed to poten- tially higher discharges from the external environment through the pc card connector. bypassing the outputs with 0.1 f capacitors protects the devices from dis- charges up to 10kv. figure 3. detailed interconnections and capacitor recommendations 0.1 f 0.1 f 12v 12v avcc avcc avcc bvcc bvcc bvcc avpp bvpp data clock latch reset reset oc system voltage supervisor or pci bus reset 0.1 f 0.1 f v cc v cc pc card connector a v pp1 v pp2 pc card connector b v pp2 v pp1 v cc v cc data clock latch pcmcia controller 5v 3.3v 33 f 0.1 f 33 f 0.1 f 5v 5v 5v 3.3v 3.3v 3.3v gnd g574 0.1 f 10 f 12v (ceramic) (ceramic) (ceramic) stby mode gpi/o 0.1 f 0.1 f 12v 12v avcc avcc avcc bvcc bvcc bvcc avpp bvpp data clock latch reset reset oc system voltage supervisor or pci bus reset 0.1 f 0.1 f v cc v cc pc card connector a v pp1 v pp2 pc card connector b v pp2 v pp1 v cc v cc data clock latch pcmcia controller 5v 3.3v 33 f 0.1 f 33 f 0.1 f 5v 5v 5v 3.3v 3.3v 3.3v gnd g574 0.1 f 10 f 12v (ceramic) (ceramic) (ceramic) stby mode gpi/o
ver: 1.2 jul 28, 2006 tel: 886-3-5788833 http://www.gmt.com.tw 16 g574 global mixed-mode technology inc. package information note: 1. dimensional tolerance 0.10mm 2. plating thickness 5~15 m 3. dimensions ? d ? does not include burrs, however dimensi on including protrusions or gate burrs shall be max. 0.20mm 4. dimension ? e1 ? does not include inter-lead flash or protrusion. inter-l ead flash or protrusion small not exceeds 0.25 per side. dimension in mm dimension in inch symbol min. nom. max. min. nom. max. a 1.80 1.90 2.00 0.071 0.075 0.079 a1 1.75 1.80 1.85 0.069 0.071 0.073 a2 0.05 0.10 0.15 0.002 0.004 .006 b 0.25 0.30 0.35 0.010 0.012 0.014 c 0.10 0.15 0.20 0.004 0.006 0.008 d 10.10 10.15 10.20 0.398 0.400 .402 e 7.50 ----- 7.90 0.295 ----- 0.311 e1 5.20 5.25 5.30 0.205 0.207 0.209 l1 0.53 0.68 0.83 0.021 0.027 0.033 l 1.10 1.20 1.30 0.043 0.047 0.051 e 0.65 bsc 0.026bsc 1 4 7 1 4 7 taping specification package q ? ty/reel ssop-30 2,000 ea gmt inc. does not assume any responsibility for use of any circui try described, no circuit patent licenses are implied and gmt inc. reserves the right at any time without notice to change said circuitry and specifications. d e 3.6 1.15 e1 e b a a1 a2 l1 c l feed direction typical ssop package orientation feed direction typical ssop package orientation

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