C6845 cr t controller megafunction gener a l descript ion the C6845 c a thod e ray tube controller (crtc) interfaces a micr oprocessor to a raster-sc a n crt displ a y. the C6845 is a synchr onou s, synthe sizable vhdl megafunction , fu ncti onally equ ivalent to the motorol a mC6845 crt controller . the micropr o cessor access 19 register s (1 address an d 18 data register s) withi n the C6845 in order to provide video timing, refresh memory addresses, cur s or , and light pen strob e si gnals. crt video timing si gnals include vertic al sync (vs ) , horizon t al sy nc (hs), and display en abl e (de) output signals. refr esh mem o ry addressing includes memor y address (ma[13:0 ]) and row addre s s (ra[4:0] ) out p ut buse s. the C6845 m i croprocessor interface c o n s ist of unidi rectional d a ta i n put (din[7:0]) and data output (dout[7:0]) buses and control sign als rs, rwn, cs n, an d e. opti onally, an av ailable bus wr apper converts the unidirecti o nal data buses into an 8-b i t bi-directional data bus (d[7:0]). this is the pin equ ivalent to the mC6845 . features ? fully-synchr onous, syn t hesizable vhdl megafunc ti on , function ally equivalent to motorol a mc6 845 ? capable of dri ving alphanumeric, semi-g raphic, or bit-mapped grap hics display s ? wide range of programmable alphanum eric screen f o rmats ? programm able register s controlling outp ut signal s vertical sync (vs ) , horizontal sync (hs), an d display en abl e (de) signal s ? programm able horizontal li ne rate and sync pulse wid t h ? programm able vertical frame rate ? programm able register s controlling mem o ry address (ma[13:0]) start address ? programm able start address register for hardwar e s c rolling ? programm able register s controlling row addre ss (ra[4:0]) size, yielding a character row ? programm able register c o n t rolling norm al sync (non -interlace), in terlace syn c , or interlac e s y nc & video mode ? programm able register s for control and format of cursor ? light pen reg i ster ? microprocessor 8-bit data bus and control interface cast, inc . marc h 2004 page 1
cast C6845 me gafunc ti on d a t a s h e e t symbol C6845 crt controller pdbtri rs rwn csn e lpstb resetn clk vs hs de ma[13..0] ra[4..0] cursor crt control refresh memory/ charactor generator addressing microprocessor interface light pen strobe cursor reset & clock pu_resetn din[7..0] dout[7..0] pin description name type polarity descrip t ion microprocessor interface din[7..0] in - data bus inp u t dout[7..0] out - data bus outp ut pdbtri out (see description) processor data bus tri-state control h= processor reads l= processor writes rs in low address register select h i g h d a t a r e g i s t e r s e l e c t rwn in low write to internal register h i g h r e a d i n t e r n a l r e g i s t e r c s n i n lo w c h i p s e l e c t high enable data bu s output durin g microprocessor reads e i n falling edge register data during microprocessor writes light pen str o be i n terface lps t b in rising edge light pen stro be reset and cl ock i n terface r e s e t n i n l o w r e s e t / t e s t m o d e cl k in fallin g edge s y n c h r on ou s cl ock (except for micro-processor interface) p u _ r e s e t n i n lo w asynchro n o u s po wer- u p r e s e t crt control interface d e o u t h i g h d i s p l a y enable h s o u t h i g h h o r i z o n t a l s y n c v s o u t h i g h verti c al s y n c refresh mem o ry/character generator address i ng interface ma[ 13. . 0 ] ou t - refresh memo r y address r a [ 4 . . 0 ] o u t - r o w a d d r e s s cursor interface c u r s o r o u t h i g h c u r s o r applications ? point- of-c ont a ct kio s k cast, in c. pa g e 2
cast C6845 me gafunc ti on d a t a s h e e t ? medical in stru mentati o n ? ? ? ? te st & me asu r ement ins t ru mentati o n industrial eq uipment avionics gaming & am usemen t mac h ines block diagram rwn a d dres s r e gist er and de c o de r csn rs e p d btr i di n[ 7 : 0 ] ho ri z o n t a l tota l r eg r0 hori z o n t al displaye d re g r1 h o r i zont al syn c widt h r e g r3 vertical total re g r4 vert ica l t o t a l a d just re g r5 vert ical d i s p l ayed reg r6 v e r t i c al sy nc po s i t i on re g r7 i n terlace mode re g r8 m a x sc an li ne a d dres s r eg r9 cursor start re g r10 cur s or e nd re g r11 st ar t addr e s s re g r1 2 r1 3 c u rsor a d d ress re g r1 4 r1 5 sync p o s i ti on re g r2 ligh t pen r eg r16 r17 lin ear a d d res s gen erator cur s or contr o l co m a ( 1 3:0) li ght p e n s y nc lp stb cl k vertical contr o l r a (4:0) co co co sc an lin e co unte r c h aracter row count e r co vs co horizon t al syn c wi dt h count e r co co co hori z o n t al count e r cu rs o r se t re se t re giste r hs co se t re se t re giste r cl k cl k de r e setn re s e t n dout [ 7 : 0 ] p u _ r es etn functional description this secti o n d e scribe s the b l ock diagra m above . a descri ption of each of th e blocks in the diagram is gi ven here. cast, in c. page 3
cast C6845 me gafunc ti on d a t a s h e e t horizontal timing the horizon t al timing section con s ist of the horiz o ntal counter , horizontal syn c width coun ter, registers r0 through r3 , and associ ated synchron ous set/r eset fli p -flops and c o incidence ci rcuits. the horizon t al counter c o unts from zer o until coincid e nce with re gister r0 syn c hronou sly re set s the c o un ter. this repr esen ts the h o rizon t al line rate and enabling of the display enable (d e) f o r a new lin e takes place. coincidence of the horiz o ntal counter wi th regi ster r1 marks th e end of the ac ti ve display por t ion of a horizontal line with display en able (d e) going inactiv e . coincidence of the horiz o ntal counter wi th regi ster r2 marks th e beginning of horizontal retr ace with horizon t al sy nc (hs) going active high. coincidence of the horiz o ntal sync width counter with register r3 marks th e en d of horizontal retrace wi th horizon t al sy nc (hs) going inactive low. vert ic a l ti m i ng the vertic al timing section consi s ts of th e scan line c o unter , char acter row cou n ter, register s r4 thr o ugh r9, th e ver t ic al contr o l logi c block, and as soci ated c o incidence circuits. the sc an lin e counter c o unts from zer o until coincid e nce with re gister r9 syn c hronou sly re set s the sc an line counter and synchron ou sly increments the character row c o unter . the scan li ne counter c o unts the sc an lines co mpo s ing a charac t e r row, and t h e charac ter row c o unter count s the ch aract e r row s comprising a vertical fram e. the char acter row c o unter coincidence with r4 and the re sidual s c an line coun t represen ted by r5 marks the end of a verti c al frame . the char acter row c o unter coincidence with regi ster r6 mark s the end of the active display portion of the vertical fram e measur ed in charac ter row s . the char acter row c o unter coincidence with regi ster r7 mark s the beginning of vertical retr ac e with ver t ical sync (vs) g o i n g active hig h . vs rem a in s high for a fixed period of 16 scan lines. register r8 , i n terlace mod e register, ef fects th e ver t ic al timing ac cording to its programming . normal syn c (non-interl a c e ) mode displ a ys th e same field each fr ame. interl ace sync mode splits a fram e into even and odd fields. vertical sync (vs) active high is delayed on e-half scan li ne at th e end of even field s. f o r interlace sync & vide o mode , in addi tion to the vs delay on eve n fields, th e row address c o unter seque n ces on even fields through 0,2,4 , ? c o un ter values wh ile on odd fiel d s, thr o ugh 1 , 3,5 , ? c o unter values. cursor the cursor section con s i s t of the cursor control , cursor start regi ster r10 , cursor end register r11, cur s or address regi ster s r14 and r15, and associated interl ac e m o de re gister s e tting s and r e fre s h memory add r ess and ro w add r ess bu se s a s well as assoc i ated coincid e nce circuits. as a first con d ition for ac ti vating the cur s or , cursor a ddress registers r14 and r15 signify th e charac ter in linear addre s s sp ace the c u rsor c a n be active . th en, cu rsor start register r10 and cursor end register r11 select the scan lines within the design ated character space the cur s or will be acti ve. in addition, c u rsor start register r10 contains a 2 - bi t field indicati ng whether the cursor is active or not, and, if so, wheth e r it should blin k or not, and , if blink, at 1/16 th or 1/32 nd the field rate. cast, in c. page 4
cast C6845 me gafunc ti on d a t a s h e e t start ad dress start address register r12 and r13 indi cate the first a ddress the l i near address generat o r puts on the refr esh memory addr ess bus at th e start of a v e rtical fram e. whenever t h e microproc e ssor writ es t o r12 and r1 3, the linear address generator i s updated at the st art of th e next ver t ical frame. light pe n registe r on the rising edge of the l p stb input, after synchr oni z ation by tw o clk cycles, t h e value of th e refre s h memory addr ess bus is cap t ured by the light pen reg i st er s r16 an d r17. the s e register s are readable by- w ay- of the microp rocessor inter f ace. linear ad d r ess ge nerator the line ar ad dress gen e rator gener a te s the refre s h memo ry addr ess. the linear address generator initi a lizes to the v a lue of the star t address regi ste r s r12 and r13 at the st ar t of eac h vert ical frame . th e linear addr es s generator remains active during horizontal and ver t ical retrac e, f o r refresh of d y namic ra ms. device utilization & performance supported device utilization performanc e family tested les memory memory bit s f max c y c l o n e e p 1 c 2 0 - 6 3 9 9 0 0 1 8 6 m h z strati x e p 1 s 2 0 - 5 3 9 9 0 0 1 9 4 m h z strati x - i i e p 2 s 6 0 - 3 3 3 0 0 0 2 2 1 m h z deliverables encrypte d netlist lic e nse ? ? ? ? ? ? ? pos t synth e si s edif netli s t assignment & configuration symbol & incl ude files te stbench vect ors f o r te sting the func tionality of th e megafuncti on place & rout e scripts documentation cast, in c. page 5
cast C6845 megafunction datasheet cast, inc. page 6 vhdl source license x x x x x x x vhdl rtl source code testbenches vectors for testing functionality expected results synthesis scripts simulation scripts documentation related information mC6845 crt controller contact: motorola semiconductors 3501 ed bluestein blvd. austin, texas 78721 phone: 512-933-6000 800-201-0399 (literature) url: www.motorola.com to obtain a copy of the mC6845 crt controller data sheet, contact cast. contact information cast, inc. 11 stonewall court woodcliff lake, new jersey 07677 usa phone: +1 201-391-8300 fax: +1 201-391-8694 e-mail: info@cast-inc.com url: www.cast-inc.com this core developed by the peripheral co ntroller experts at digital blocks, inc. copyright ? cast, inc. 2004, all ri ghts reserved. contents subjec t to change without notice.
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