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| rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7177/adv7178 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998 integrated digital ccir-601 to pal/ntsc video encoder features itu-r bt601/656 ycrcb to pal/ntsc video encoder high quality 9-bit video dacs integral nonlinearity <1 lsb at 9 bits ntsc-m, pal-m/n, pal-b/d/g/h/i single 27 mhz crystal/clock r equired ( 3 2 oversampling) 75 db video snr 32-bit direct digital synthesizer for color subcarrier multistandard video output support: composite (cvbs) component s-video (y/c) component yuv and rgb video input data port supports: ccir-656 4:2:2 8-bit parallel input format 4:2:2 16-bit parallel input format smpte 170m ntsc-compatible composite video itu-r bt.470 pal-compatible composite video full video output drive or low signal drive capability 34.7 ma max into 37.5 v (doubly-terminated 75r) 5 ma min with external buffers programmable simultaneous composite and s-vhs (vhs) y/c or rgb (scart)/yuv video outputs programmable luma filters (low-pass/notch/extended) programmable vbi (vertical blanking interval) programmable subcarrier frequency and phase programmable luma delay individual on/off control of each dac ccir and square pixel operation color signal control/burst signal control interlaced/noninterlaced operation complete on-chip video timing generator osd support (ad7177 only) programmable multimode master/slave operation macrovision antitaping rev 7.01 (adv7178 only)** closed captioning support onboard voltage reference 2-wire serial mpu interface (i 2 c ? compatible) single supply +5 v or +3 v operation small 44-lead pqfp package synchronous 27 mhz/13.5 mhz clock o/p applications mpeg-1 and mpeg-2 video, dvd, digital satellite/ cable systems (set top boxes/irds), digital tvs, cd video/karaoke, video games, pc video/multimedia general description the adv7177/adv7178 is an integrated digital video encoder that converts digital ccir-601 4:2:2 8- or 16-bit component video data into a standard analog baseband television signal functional block diagram osd_en osd_0 osd_1 osd_2 p7Cp0 p15Cp8 color data adv7177 only 4:2:2 to 4:4:4 inter- polator 8 8 8 8 add burst 8 inter- polator 8 v low-pass filter 9 9 9 9 9 sin/cos dds block yuv to rbg matrix m u l t i p l e x e r 9 9 9 9-bit dac 9-bit dac 9-bit dac dac c (pin 26) dac b (pin 27) dac a (pin 31) adv7177/adv7178 voltage reference circuit video timing generator i 2 c mpu port clock clock clock/2 reset sclock sdata alsb gnd v ref r set comp v aa hsync field/ vsync blank 8 add burst 8 inter- polator 8 u low-pass filter 8 add sync 8 inter- polator 8 y low-pass filter ycrcb to yuv matrix * protected by u.s. patent numbers 5,343,196 and 5,442,355 and other intellectual property rights. ** this device is protected by u.s. patent numbers 4,631,603, 4,577,216, 4,819,098 and other intellectual property rights. the mac rovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. please contact sales office for latest macrovision version available. note: itu-r and ccir are used interchangeably in this document (itu-r has replaced ccir recommendations). i 2 c is a registered trademark of philips corporation. (continued on page 11)
C2C rev. 0 adv7177/adv7178Cspecifications (v aa = +5 v 6 5% 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions 1 min typ max units static performance 3 resolution (each dac) 9 bits accuracy (each dac) integral nonlinearity 1.0 lsb differential nonlinearity guaranteed monotonic 1.0 lsb digital inputs 3 input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 4 v in = 0.4 v or 2.4 v 1 m a input current, i in 5 v in = 0.4 v or 2.4 v 50 m a input capacitance, c in 10 pf digital outputs 3 output high voltage, v oh i source = 400 m a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 10 m a three-state output capacitance 10 pf analog outputs 3 output current 6 r set = 300 w , r l = 75 w 16.5 17.35 18.5 ma output current 7 5ma dac-to-dac matching 0.6 5 % output compliance, v oc 0 +1.4 v output impedance, r out 15 k w output capacitance, c out i out = 0 ma 30 pf voltage reference 3 reference range, v ref i vrefout = 20 m a 1.112 1.235 1.359 v power requirements 3, 8 v aa 4.75 5.0 5.25 v low power mode i dac (max) 9 62 ma i dac (min) 9 25 ma i cct 10 100 150 ma power supply rejection ratio comp = 0.1 m f 0.01 0.5 %/% notes 1 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 1 2 temperature range t min to t max : 0 c to +70 c. 1 3 guaranteed by characterization. 1 4 all digital input pins except pins reset , osd0 and clock. 1 5 excluding all digital input pins except pins reset , osd0 and clock. 1 6 full drive into 75 w load. 1 7 minimum drive current (used with buffered/scaled output load). 1 8 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 1 9 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 18.5 ma output per dac) to drive all three da cs. turning off individual dacs reduces i dac correspondingly. 10 i cct (circuit current) is the continuous current required to drive the device. specifications subject to change without notice. 5 v specifications C3C rev. 0 adv7177/adv7178 parameter conditions 1 min typ max units static performance 3 resolution (each dac) 9 bits accuracy (each dac) integral nonlinearity 0.5 lsb differential nonlinearity guaranteed monotonic 0.5 lsb digital inputs input high voltage, v inh 2v input low voltage, v inl 0.8 v input current, i in 3, 4 v in = 0.4 v or 2.4 v 1 m a input current, i in 3, 5 v in = 0.4 v or 2.4 v 50 m a input capacitance, c in 10 pf digital outputs output high voltage, v oh i source = 400 m a 2.4 v output low voltage, v ol i sink = 3.2 ma 0.4 v three-state leakage current 3 10 m a three-state output capacitance 3 10 pf analog outputs 3 output current 6, 7 r set = 300 w , r l = 75 w 16.5 17.35 18.5 ma output current 8 5ma dac-to-dac matching 2.0 % output compliance, v oc 0 +1.4 v output impedance, r out 15 k w output capacitance, c out i out = 0 ma 30 pf power requirements 3, 9 v aa 3.0 3.3 3.6 v normal power mode i dac (max) 10 r set = 300 w , r l = 150 w 113 116 ma i dac (min) 10 15 ma i cct 9 45 ma low power mode i dac (max) 10 60 ma i dac (min) 10 25 ma i cct 11 45 ma power supply rejection ratio comp = 0.1 m f 0.01 0.5 %/% notes 1 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 1 2 temperature range t min to t max : 0 c to +70 c. 1 3 guaranteed by characterization. 1 4 all digital input pins except pins reset , osd0 and clock. 1 5 excluding all digital input pins except pins reset , osd0 and clock. 1 6 full drive into 75 w load. 1 7 dacs can output 35 ma typically at 3.3 v (r set = 150 w and r l = 75 w ), optimum performance obtained at 18 ma dac current (r set = 300 w and r l = 150 w ). 1 8 minimum drive current (used with buffered/scaled output load). 1 9 power measurements are taken with clock frequency = 27 mhz. max t j = 110 c. 10 i dac is the total current (min corresponds to 5 ma output per dac, max corresponds to 38 ma output per dac) to drive all three dacs . turning off individual dacs reduces i dac correspondingly. 11 i cct (circuit current) is the continuous current required to drive the device. specifications subject to change without notice. 3.3 v specifications (v aa = +3.0 vC3.6 v 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) C4C rev. 0 adv7177/adv7178Cspecifications parameter conditions 1 min typ max units filter characteristics luma bandwidth 3 (low-pass filter) ntsc mode stopband cutoff >54 db attenuation 7.0 mhz passband cutoff f 3 db >3 db attenuation 4.2 mhz chroma bandwidth ntsc mode stopband cutoff >40 db attenuation 3.2 mhz passband cutoff f 3 db >3 db attenuation 2.0 mhz luma bandwidth 3 (low-pass filter) pal mode stopband cutoff >50 db attenuation 7.4 mhz passband cutoff f 3 db >3 db attenuation 5.0 mhz chroma bandwidth pal mode stopband cutoff >40 db attenuation 4.0 mhz passband cutoff f 3 db >3 db attenuation 2.4 mhz differential gain 4 lower power mode 2.0 % differential phase 4 lower power mode 1.5 degrees snr 4 (pedestal) rms 75 db rms peak periodic 70 db p-p snr 4 (ramp) rms 57 db rms peak periodic 56 db p-p hue accuracy 4 1.2 degrees color saturation accuracy 4 1.4 % chroma nonlinear gain 4 referenced to 40 ire 1.0 % chroma nonlinear phase 4 ntsc 0.4 degrees pal 0.6 degrees chroma/luma intermod 4 referenced to 714 mv (ntsc) 0.2 % referenced to 700 mv (pal) 0.2 % chroma/luma gain ineq 4 0.6 % chroma/luma delay ineq 4 2.0 ns luminance nonlinearity 4 1.2 % chroma am noise 4 64 db chroma pm noise 4 62 db notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 4.75 v to 5.25 v. 2 temperature range t min to t max : 0 c to +70 c. 3 these specifications are for the low-pass filter only and guaranteed by design. for other internal filters, see figure 5. 4 guaranteed by characterization. specifications subject to change without notice. 5 v dynamic specifications 1 (v aa = +4.75 v C 5.25 v 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) C5C rev. 0 adv7177/adv7178 parameter conditions 1 min typ max units filter characteristics luma bandwidth 3 (low-pass filter) ntsc mode stopband cutoff >54 db attenuation 7.0 mhz passband cutoff f 3 db >3 db attenuation 4.2 mhz chroma bandwidth ntsc mode stopband cutoff >40 db attenuation 3.2 mhz passband cutoff f 3 db >3 db attenuation 2.0 mhz luma bandwidth 3 (low-pass filter) pal mode stopband cutoff >50 db attenuation 7.4 mhz passband cutoff f 3 db >3 db attenuation 5.0 mhz chroma bandwidth pal mode stopband cutoff >40 db attenuation 4.0 mhz passband cutoff f 3 db >3 db attenuation 2.4 mhz differential gain 4 normal power mode 1.0 % differential phase 4 normal power mode 1.0 degrees snr 4 (pedestal) rms 70 db rms peak periodic 64 db p-p snr 4 (ramp) rms 56 db rms peak periodic 54 db p-p hue accuracy 4 1.2 degrees color saturation accuracy 4 1.4 % luminance nonlinearity 4 1.4 % chroma am noise 4 ntsc 64 db chroma pm noise 4 ntsc 62 db chroma am noise 4 pal 64 db chroma pm noise 4 pal 62 db notes 1 the max/min specifications are guaranteed over this range. the max/min values are typical over 3.0 v to 3.6 v. 2 temperature range t min to t max : 0 c to +70 c. 3 these specifications are for the low-pass filter only and guaranteed by design. for other internal filters, see figure 5. 4 guaranteed by characterization. specifications subject to change without notice. 3.3 v dynamic specifications 1 (v aa = +3.0 v C 3.6 v 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) adv7177/adv7178 C6C rev. 0 5 v timing specifications (v aa = 4.75 v C 5.25 v 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max units mpu port 3, 4 sclock frequency 0 100 khz sclock high pulsewidth, t 1 4.0 m s sclock low pulsewidth, t 2 4.7 m s hold time (start condition), t 3 after this period the first clock is generated 4.0 m s setup time (start condition), t 4 relevant for repeated start condition 4.7 m s data setup time, t 5 250 ns sdata, sclock rise time, t 6 1 m s sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 4.7 m s analog outputs 3, 5 analog output delay 5ns dac analog output skew 0 ns clock control and pixel port 3, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 3.5 ns data hold time, t 12 4ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 24 ns digital output hold time, t 14 4ns pipeline delay, t 15 37 clock cycles reset control 3, 4 reset low time 6 ns internal clock control clock/2 rise time, t 16 7ns clock/2 fall time, t 17 7ns osd timing 4 osd setup time, t 18 6ns osd hold time, t 19 2ns notes 1 the max/min specifications are guaranteed over this range. 2 temperature range t min to t max : 0 c to +70 c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock specifications subject to change without notice. C7C rev. 0 adv7177/adv7178 3.3 v timing specifications (v aa = +3.0 vC3.6 v 1 , v ref = 1.235 v, r set = 300 v . all specifications t min to t max 2 unless otherwise noted.) parameter conditions min typ max units mpu port 3, 4 sclock frequency 0 100 khz sclock high pulsewidth, t 1 4.0 m s sclock low pulsewidth, t 2 4.7 m s hold time (start condition), t 3 after this period the first clock is generated 4.0 m s setup time (start condition), t 4 repeated for start condition 4.7 m s data setup time, t 5 250 ns sdata, sclock rise time, t 6 1 m s sdata, sclock fall time, t 7 300 ns setup time (stop condition), t 8 4.7 m s analog outputs 3, 5 analog output delay 7ns dac analog output skew 0 ns clock control and pixel port 3, 4, 6 f clock 27 mhz clock high time, t 9 8ns clock low time, t 10 8ns data setup time, t 11 3.5 ns data hold time, t 12 4ns control setup time, t 11 4ns control hold time, t 12 3ns digital output access time, t 13 24 ns digital output hold time, t 14 4ns pipeline delay, t 15 37 clock cycles reset control 3, 4 reset low time 6 ns internal clock control clock/2 rise time, t 16 10 ns clock/2 fall time, t 17 10 ns osd timing 4 osd setup time, t 18 10 ns osd hold time, t 19 2ns notes 1 the max/min specifications are guaranteed over this range. 2 temperature range t min to t max : 0 c to +70 c. 3 ttl input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. timing reference points at 50% for inputs and outputs. analog output load 10 pf. 4 guaranteed by characterization. 5 output delay measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 6 pixel port consists of the following: pixel inputs: p15Cp0 pixel controls: hsync , field/ vsync , blank clock input: clock specifications subject to change without notice. adv7177/adv7178 C8C rev. 0 t 3 t 2 t 6 t 1 t 7 t 5 t 3 t 4 t 8 sdata sclock figure 1. mpu port timing diagram t 9 t 11 clock pixel input data t 10 t 12 hsync , field/ vsync , blank cb y cr y cb y hsync , field/ vsync , blank t 13 t 14 control i/ps control o/ps figure 2. pixel and control data timing diagram t 16 t 17 t 17 t 16 clock/2 clock clock/2 clock figure 3. internal timing diagram t 18 clock osd en t 19 osd0C2 figure 4. osd timing diagram adv7177/adv7178 C9C rev. 0 absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital input pin . . gnd C 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . C65 c to +150 c junction temperature (t j ) . . . . . . . . . . . . . . . . . . . . . . +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +260 c analog outputs to gnd 2 . . . . . . . . . . . . . . gnd C 0.5 to v aa notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 analog output short circuit to any power supply or common can be of an indefinite duration. ordering guide temperature package package model range description option ADV7178KS 0 c to +70 c plastic quad flatpack s-44 adv7177ks 0 c to +70 c plastic quad flatpack s-44 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adv7177/adv7178 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, pr oper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configuration 12 13 14 15 16 17 18 19 20 21 22 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 27 28 25 26 23 24 33 pin 1 identifier r set v ref dac a v aa gnd v aa dac b blank p13 p14 p15 hsync field/ vsync alsb v aa clock/2 p5 p6 p7 p8 p9 p10 p11 p12 osd_en dac c comp sdata sclock gnd v aa gnd reset clock clock gnd p4 p3 p2 p1 p0 osd_2 osd_1 osd_0 adv7177/adv7178 pqfp top view (not to scale) package thermal performance the 44-lead pqfp package used for this device has a junction- to-ambient thermal resistance ( q ja ) in still air on a four-layer pcb of 53.2 c/w. the junction-to-case thermal resistance ( q jc ) is 18.8 c/w. care must be taken when operating the part in certain condi- tions to prevent overheating. table i illustrates what conditions are to be used when using the part. table i. allowable operating conditions for adv7177/ adv7178 in 44-lead pqfp package condition 5 v 3 v 3 dacs on, double 75r 1 no yes 3 dacs on, low power 2 yes yes 3 dacs on, buffered 3 yes yes 2 dacs on, double 75r no yes 2 dacs on, low power yes yes 2 dacs on, buffered yes yes notes 1 dac on, double 75r refers to a condition where the dacs are terminated into a double 75r load and low power mode is disabled. 2 dac on, low power refers to a condition where the dacs are terminated in a double 75r load and low power mode is enabled. 3 dac on, buffered refers to a condition where the dac current is reduced to 5 ma and external buffers are used to drive the video loads. warning! esd sensitive device adv7177/adv7178 C10C rev. 0 pin function descriptions pin input/ no. mnemonic output function 1, 20, 28, 30 v aa p +5 v supply. 2 clock/2 o synchronous clock output signal. can be either 27 mhz or 13.5 mhz; this can be controlled by mr32 and mr33 in mode register 3. 3C10, 12C14, p15Cp0 i 8-bit 4:2:2 multiplexed ycrcb pixel port (p7Cp0) or 16-bit ycrcb 37C41 pixel port (p15Cp0). p0 represents the lsb. 11 osd_en i enables osd input data on the video outputs. 15 hsync i/o hsync (modes 1 and 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) sync signals. 16 field/ vsync i/o dual function field (mode 1) and vsync (mode 2) control signal. this pin may be configured to output (master mode) or accept (slave mode) these control signals. 17 blank i/o video blanking control signal. the pixel inputs are ignored when this is logic level 0. this signal is optional. 18 alsb i ttl address input. this signal sets up the lsb of the mpu address. 19, 21, 29, 42 gnd g ground pin. 22 reset i the input resets the on-chip timing generator and sets the adv7177/adv7178 into default mode. this is ntsc operation, timing slave mode 0, 8-bit operation, 2 composite and s vhs out. 23 sclock i mpu port serial interface clock input. 24 sdata i/o mpu port serial data input/output. 25 comp o compensation pin. connect a 0.1 m f capacitor from comp to v aa . 26 dac c o dac c analog output. 27 dac b o dac b analog output. 31 dac a o dac a analog output. 32 v ref i/o voltage reference input for dacs or voltage reference output (1.2 v). 33 r set i a 300 w resistor connected from this pin to gnd is used to control full-scale amplitudes of the video signals. 34C36 osd_0C2 i on screen display inputs. 43 clock o crystal oscillator output (to crystal). leave unconnected if no crystal is used. 44 clock i crystal oscillator input. if no crystal is used this pin can be driven by an external ttl clock source; it requires a stable 27 mhz reference clock for standard operation. alternatively, a 24.52 mhz (ntsc) or 29.5 mhz (pal) can be used for square pixel operation. adv7177/adv7178 C11C rev. 0 compatible with worldwide standards. the 4:2:2 yuv video data is interpolated to two times the pixel rate. the color- differ ence components (uv) are quadrature modulated using a subcarrier frequency generated by an on-chip 32-bit digital synthesizer (also running at two times the pixel rate). the two times pixel rate sampling allows for better signal-to-noise ratio. a 32-bit dds with a 9-bit look-up table produces a superior subcarrier in terms of both frequency and phase. in addition to the composite output signal, there is the facility to output s-video (y/c) video, yuv or rgb video. each analog output is capable of driving the full video-level (34.7 ma) signal into an unbuffered, doubly terminated 75 w load. with external buffering, the user has the additional option to scale back the dac output current to 5 ma min, thereby signifi- cantly reducing the power dissipation of the device. the adv7177/adv7178 also supports both pal and ntsc square pixel operation. the output video frames are synchronized with the incoming data timing reference codes. optionally, the encoder accepts (and can generate) hsync , vsync and field timing signals. these timing signals can be adjusted to change pulsewidth and position while the part is in the master mode. the encoder requires a single two times pixel rate (27 mhz) clock for standard operation. alternatively, the encoder requires a 24.54 mhz clock for ntsc or 29.5 mhz clock for pal square pixel mode operation. all internal timing is generated on-chip. the adv7177/adv7178 modes are set up over a two-wire serial bidirectional port (i 2 c-compatible) with two slave addresses. functionally the adv7178 and adv7177 are the same with the exception that the adv7178 can output the macrovision anticopy algorithm, and osd is only supported on the adv7177. the adv7177/adv7178 is packaged in a 44-lead thermally enhanced pqfp package. data path description for pal b, d, g, h, i, m, n and ntsc m, n modes, ycrcb 4:2:2 data is input via the ccir-656 compatible pixel port at a 27 mhz data rate. the pixel data is demultiplexed to from three data paths. y typically has a range of 16 to 235, cr and cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both y, cb and cr. the adv7177/adv 7178 supports pal (b, d, g, h, i, n, m) and ntsc (with and without pedestal) standards. the appropri- ate s ync, blank and burst levels are added to the ycrcb data. macrovision antitaping (adv7178 only), closed caption ing, osd (adv7177 only), and teletext levels are also added to y, and the resultant data is interpolated to a rate of 27 mhz. the interpolated data is filtered and scaled by three digital fir filters. the u and v signals are modulated by the appropriate subcarrier sine/cosine phases and added together to make up the chromi- nance signal. the luma (y) signal can be delayed 1C3 luma cycles (each cycle is 74 ns) with respect to the chroma signal. the luma and chroma signals are then added together to make up the composite video signal. all edges are slew rate limited. the ycrcb data is also used to generate rgb data with appropriate sync and blank levels. the rgb data is in synchronization with the composite video output. alternatively analog yuv data can be generated instead of rgb. the three 9-bit dacs can be used to output: 1. rgb video. 2. yuv video 3. one composite video signal + luma and chroma 3. (s-video). alternatively, each dac can be individually powered off if not required. video output levels are illustrated in appendix 3, appendix 4 and appendix 5. internal filter response the y filter supports several different frequency responses, including two 4.5 mhz/5.0 mhz low-pass responses, pal/ ntsc subcarrier notch responses and a pal/ntsc extended response. the u and v filters have a 2/2.4 mhz low-pass response for ntsc/pal. these filter characteristics are illus- trated in figures 7 to 13. (continued from page 1) mr04 mr03 ntsc 0 0 2.3 0.026 7.0 > 54 4.2 pal 0 0 3.4 0.098 7.3 > 50 5.0 ntsc 0 1 1.0 0.085 3.57 > 27.6 2.1 pal 0 1 1.4 0.107 4.43 > 29.3 2.7 ntsc/pal 1 0 4.0 0.150 7.5 > 40 5.35 ntsc 1 1 2.3 0.054 7.0 > 54 4.2 pal 1 1 3.4 0.106 7.3 > 50.3 5.0 filter selection f 3 db passband cutoff (mhz) stopband cutoff (mhz) passband ripple (db) stopband attenuation (db) figure 5. luminance internal filter specifications ntsc 1.0 0.085 3.2 > 40 0.3 2.05 pal 1.3 0.04 4.0 > 40 0.02 2.45 filter selection f 3 db passband cutoff (mhz) stopband cutoff (mhz) passband ripple (db) stopband attenuation (db) attenuation @ 1.3mhz (db) figure 6. chrominance internal filter specifications adv7177/adv7178 C12C rev. 0 frequency C mhz 0 C60 C50 C40 C10 C20 C30 0 246 amplitude C db 812 10 type a type b figure 7. ntsc low-pass filter frequency C mhz 0 C60 C50 C40 C10 C20 C30 0 246 8 12 10 amplitude C db figure 8. ntsc notch filter frequency C mhz 0 C60 C50 C40 C10 C20 C30 0 246 8 12 10 amplitude C db type b type a figure 9. pal low-pass filter frequency C mhz 0 C60 C50 C40 C10 C20 C30 0 246 8 12 10 amplitude C db figure 10. pal notch filter frequency C mhz C60 C50 C40 C10 C20 C30 0 246 8 12 10 amplitude C db 0 figure 11. ntsc/pal extended mode filter frequency C mhz 0 C60 C50 C40 C10 C20 C30 0 246 8 12 10 amplitude C db figure 12. ntsc uv filter adv7177/adv7178 C13C rev. 0 frequency C mhz 0 C60 C50 C40 C10 C20 C30 02468 12 10 amplitude C db figure 13. pal uv filter color bar generation the adv7177/adv7178 can be configured to generate 75% amplitude, 75% saturation (75/7.5/75/7.5) for ntsc or 75% amplitude, 100% saturation (100/0/75/0) for pal color bars. these are enabled by setting mr17 of mode register 1 to logic 1. square pixel mode the adv7177/adv7178 can be used to operate in square pixel mode. for ntsc operation an input clock of 24.5454 mhz is required. alternatively an input clock of 29.5 mhz is required for pal operation. the internal timing logic adjusts accordingly for square pixel mode operation . color signal control the color information can be switched on and off the video output using bit mr24 of mode register 2. burst signal control the burst information can be switched on and off the video output using bit mr25 of mode register 2. ntsc pedestal control the pedestal on both odd and even fields can be controlled on a line-by-line basis using the ntsc pedestal control registers. this allows the pedestals to be controlled during the vertical blanking interval (lines 10 to 25 and lines 273 to 288). pixel timing description the adv7177/adv7178 can operate in either 8-bit or 16-bit ycrcb mode. 8-bit ycrcb mode this default mode accepts multiplexed ycrcb inputs through the p7Cp0 pixel inputs. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, etc. the y, cb and cr data are input on a rising clock edge. 16-bit ycrcb mode this mode accepts y inputs through the p7Cp0 pixel inputs and multiplexed crcb inputs through the p15Cp8 pixel inputs. the data is loaded on every second rising edge of clock. the inputs follow the sequence cb0, y0 cr0, y1 cb1, y2, etc. osd the adv7177 supports osd. there are twelve 8-bit osd registers, loaded with data from the four most significant bits of y, cb, cr input pixel data bytes. a choice of eight colors can, therefore, be selected via the osd_0, osd_1, osd_2 pins, each color being a combination of 12 bits of y, cb, cr pixel data. the display is under control of the osd_en pin. the osd window can be an entire screen or just one pixel, its size may change by using the osd_en signal to control the width on a line-by-line basis. figure 4 illustrates osd timing on the adv7177. subcarrier reset the adv7177/adv7178 can be used in subcarrier reset mode. the subcarrier will reset to field 0 at the start of the following field when a low to high transition occurs on this input pin. video timing description the adv7177/adv7178 is intended to interface to off- the-shelf mpeg1 and mpeg2 decoders. consequently, the adv7177/adv7178 accepts 4:2:2 ycrcb pixel data via a ccir-656 pixel port, and has several video timing modes of operation that allow it to be configured as either system master video timing generator or a slave to the system video timing generator. the adv7177/adv7178 generates all of the re- quired horizontal and vertical timing periods and levels for the analog video outputs. the adv7177/adv7178 calculates the width and placement of analog sync pulses, blanking levels and color burst envelopes. color bursts are disabled on appropriate lines, and serration and equalization pulses are inserted where required. in addition, the adv7177/adv7178 supports a pal or ntsc square pixel operation in slave mode. the part requires an input pixel clock of 24.5454 mhz for ntsc and an input pixel clock of 29.5 mhz for pal. the internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. the adv7177/adv7178 has four distinct master and four distinct slave timing configurations. timing control is estab- lished with the bidirectional sync , blank and field/ vsync pins. timing mode register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. adv7177/adv7178 C14C rev. 0 vertical blanking data insertion it is possible to allow encoding of incoming ycbcr data on those lines of vbi that do not bear line sync or pre-/post-equalizat ion pulses (see figures 14 to 25). this mode of operation is called partial blanking and is selected by setting mr31 to 1. it all ows the insertion of any vbi data (opened vbi) into the encoded output waveform. this data is present in digitized incoming ycbcr data stream (e.g., wss data, cgms, vps, etc.). alternatively, the entire vbi may be blanked (no vbi data inserted) on these lines by setting mr31 to 0. the complete vbi comprises of the following lines: 525/60 systems, lines 525 to 21 for field 1 and lines 262 to line 284 for field 2. 625/50 systems, lines 624 to line 22 and lines 311 to 335. the opened vbi consists of: 525/60 systems, lines 10 to 21 for field 1 and second half of line 273 to line 284 for field 2. 625/50 systems, line 7 to line 22 and lines 319 to 335. mode 0 (ccir-656): slave option (timing register 0 tr0 = x x x x x 0 0 0) the adv7177/adv7178 is controlled by the sav (start active video) and eav (end active video) time codes in the pixel data. all timing information is transmitted using a 4-byte synchronization pattern. a synchronization pattern is sent immediately bef ore and after each line during active picture and retrace. mode 0 is illustrated in figure 14. the hsync , field/ vsync and blank (if not used) pins should be tied high during this mode. y c r y f f 0 0 0 0 x y 8 0 1 0 8 0 1 0 f f 0 0 f f a b a b a b 8 0 1 0 8 0 1 0 f f 0 0 0 0 x y c b y c r c b y c b y c r eav code sav code ancillary data (hanc) 4 clock 4 clock 268 clock 1440 clock 4 clock 4 clock 280 clock 1440 clock end of active video line start of active video line analog video input pixels ntsc/pal m system (525 llnes/60hz) pal system (625 lines/50hz) y figure 14. timing mode 0 (slave mode) mode 0 (ccir-656): master option (timing register 0 tr0 = x x x x x 0 0 1) the adv7177/adv7178 generates h, v and f signals required for the sav (start active video) and eav (end active video) time codes in the ccir-656 standard. the h bit is output on the hsync pin, the v bit is output on the blank pin, and the f bit is output on the field/ vsync pin. mode 0 is illustrated in figure 15 (ntsc) and figure 16 (pal). the h, v and f transitions relative to the video waveform are illustrated in figure 17. adv7177/adv7178 C15C rev. 0 522 523 524 525 1 2 3 4 5 67 8 9 10 11 20 21 22 display display vertical blank odd field even field h v f 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank h v f figure 15. timing mode 0 (ntsc master mode) 622 623 624 625 1 2 3 4 5 67 21 22 23 display display vertical blank h v f odd field even field 309 310 311 312 314 315 316 317 318 319 320 334 335 336 display display vertical blank h v f odd field even field 313 figure 16. timing mode 0 (pal master mode) adv7177/adv7178 C16C rev. 0 analog video h f v figure 17. timing mode 0 data transitions (master mode) mode 1: slave option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 0) in this mode the adv7177/adv7178 accepts horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is dis- abled, the adv7177/adv7178 automatically blanks all normally blank lines. mode 1 is illustrated in figure 18 (ntsc) and figure 19 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 18. timing mode 1 (ntsc) adv7177/adv7178 C17C rev. 0 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 figure 19. timing mode 1 (pal) mode 1: master option hsync , blank , field (timing register 0 tr0 = x x x x x 0 1 1) in this mode the adv7177/adv7178 can generate horizontal sync and odd/even field signals. a transition of the field input when hsync is low indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7177/adv7178 automatically blanks all normally blank lines. pixel data is latched on the rising clock edge fol low- ing the timing signal transitions. mode 1 is illustrated in figure 18 (ntsc) and figure 19 (pal). figure 20 illustrates the hsync , blank and field for an odd or even field transition relative to the pixel data. field pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr y hsync blank figure 20. timing mode 1 odd/even field transitions master/slave adv7177/adv7178 C18C rev. 0 mode 2: slave option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 0) in this mode the adv7177/adv7178 accepts horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7177/adv7178 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 21 (ntsc) and figure 22 (pal). 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank vsync 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank vsync figure 21. timing mode 2 (ntsc) 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank vsync display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank display 320 vsync figure 22. timing mode 2 (pal) adv7177/adv7178 C19C rev. 0 mode 2: master option hsync , vsync , blank (timing register 0 tr0 = x x x x x 1 0 1) in this mode, the adv7177/adv7178 can generate horizontal and vertical sync signals. a coincident low transition of both hsync and vsync inputs indicates the start of an odd field. a vsync low transition when hsync is high indicates the start of an even field. the blank signal is optional. when the blank input is disabled, the adv7177/adv7178 automatically blanks all normally blank lines as per ccir-624. mode 2 is illustrated in figure 21 (ntsc) and figure 22 (pal). figure 23 illus- trates the hsync , blank and vsync for an even-to-odd field transition relative to the pixel data. figure 24 illustrates the hsync , blank and vsync for an odd-to-even field transition relative to the pixel data. pal = 12 * clock/2 ntsc = 16 * clock/2 hsync vsync blank pixel data pal = 132 * clock/2 ntsc = 122 * clock/2 cb y cr figure 23. timing mode 2 even-to-odd field transition master/slave pal = 864 * clock/2 ntsc = 858 * clock/2 pal = 132 * clock/2 ntsc = 122 * clock/2 hsync vsync blank pixel data pal = 12 * clock/2 ntsc = 16 * clock/2 cb y cr y cb figure 24. timing mode 2 odd-to-even field transition master/slave adv7177/adv7178 C20C rev. 0 mode 3: master/slave option hsync , blank , field (timing register 0 tr0 = x x x x x 1 1 0 or x x x x x 1 1 1) in this mode, the adv7177/adv7178 accepts or generates horizontal sync and odd/even field signals. a transition of the field input when hsync is high indicates a new frame, i.e., vertical retrace. the blank signal is optional. when the blank input is disabled, the adv7177/adv7178 automatically blanks all normally blank lines as per ccir-624. mode 3 is illustrated in figure 25 (ntsc) and figure 26 (pal). 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 odd field even field display display vertical blank hsync blank field 522 523 524 525 1234 5 678 9 10 11 20 21 22 display display vertical blank odd field even field hsync blank field figure 25. timing mode 3 (ntsc) 6226236246251234 5 67 21 22 23 display vertical blank odd field even field hsync blank field display 309 310 311 312 313 314 315 316 317 318 319 334 335 336 display vertical blank odd field even field hsync blank field display 320 figure 26. timing mode 3 (pal) adv7177/adv7178 C21C rev. 0 output video timing the video timing generator generates the appropriate sync, blank and burst sequence that controls the output analog waveforms. these sequences are summarized below. in slave modes, the following sequences are synchronized with the input timing control signals. in master modes, the timing generator free runs and generates the following sequences in addition to the output timing control signals. ntscCinterlaced: scan lines 1C9 and 264C272 are always blanked and vertical sync pulses are included. scan lines 525, 10C21 and 262, 263, 273C284 are also blanked and can be used for closed captioning data. burst is disabled on lines 1C6, 261C 269 and 523C525. ntscCnoninterlaced: scan lines 1C9 are always blanked, and vertical sync pulses are included. scan lines 10C21 are also blanked and can be used for closed captioning data. burst is disabled on lines 1C6, 261C262. palCinterlaced: scan lines 1C6, 311C318 and 624C625 are always blanked, and vertical sync pulses are included in fields 1, 2, 5 and 6. scan lines 1C5, 311C319 and 624C625 are al- ways blanked, and vertical sync pulses are included in fields 3, 4, 7 and 8. the remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. burst is disabled on lines 1C6, 311C318 and 623C625 in fields 1, 2, 5 and 6. burst is disabled on lines 1C5, 311C319 and 623C625 in fields 3, 4, 7 and 8. palCnoninterlaced: scan lines 1C6 and 311C312 are always blanked, and vertical sync pulses are included. the remaining scan lines in the vertical blanking interval are also blanked and can be used for teletext data. burst is disabled on lines 1C5, 310C312. power-on reset after power-up, it is necessary to execute a reset operation. a reset occurs on the falling edge of a high-to-low transition on the reset pin. this initializes the pixel port so that the pixel inputs, p7Cp0 are selected. after reset, the adv7177/ adv7178 is automatically set up to operate in ntsc mode. subcarrier frequency code 21f07c16hex is loaded into the subcarrier frequency registers. all other registers, with the exception of mode register 0, are set to 00h. all bits in mode register 0 are set to logic level 0 except bit mr02. bit mr02 of mode register 0 is set to logic level 1. this en- ables the 7.5 ire pedestal. sch phase mode the sch phase is configured in default mode to reset every four (ntsc) or eight (pal) fields to avoid an accumulation of sch phase error over time. in an ideal system, zero sch phase error would be maintained forever, but in reality, this is impos- sible to achieve due to clock frequency variations. this effect is reduced by the use of a 32-bit dds, which generates this sch. resetting the sch phase every four or eight fields avoids the accumulation of sch phase error, and results in very minor sch phase jumps at the start of the four or eight field sequence. resetting the sch phase should not be done if the video source does not have stable timing or the adv7177/adv7178 is con- figured in rtc mode (mr21 = 1 and mr22 = 1). under these conditions (unstable video) the subcarrier phase reset should be enabled mr22 = 0 and mr21 = 1) but no reset ap plied. in this configuration the sch phase will never be reset, which means that the output video will now track the unstable input video. the subcarrier phase reset, when applied, will reset the sch phase to field 0 at the start of the next field (e.g., subcarrier phase reset applied in field 5 [pal] on the start of the next field sch phase will be reset to field 0). mpu port description the adv7178 and adv7177 support a two-wire serial (i 2 c- compatible) microprocessor bus driving multiple peripherals. two inputs, serial data (sdata) and serial clock (sclock), carry information between any device connected to the bus. each slave device is recognized by a unique address. the adv7178 and adv7177 each have four possible slave ad- dresses for both read and write operations. these are unique addresses for each device and are illustrated in figure 27 and figure 28. the lsb sets either a read or write operation. logic level 1 corresponds to a read operation, while logic level 0 corresponds to a write operation. a1 is set by setting the alsb pin of the adv7177/adv7178 to logic level 0 or logic level 1. 0 x 0 0101a1 address control set up by alsb read/write control 0 write 1 read figure 27. adv7178 slave address 1 x 1 1 1 01a1 address control set up by alsb read/write control 0 write 1 read figure 28. adv7177 slave address to control the various devices on the bus, the following proto- col must be followed: first, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the start condition and shift the next eight bits (7-bit address + r/ w bit). the bits transfer from msb down to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices withdraw from the bus at this point and maintain an idle condition. the idle condition is where the device monitors the sdata and sclock lines waiting for the start condition and the correct transmitted address. the r/ w bit determines the direction of the data. a logic 0 on the lsb of the first byte means that the master will write information to the peripheral. a logic 1 on the lsb of the first byte means that the master will read informa- tion from the peripheral. adv7177/adv7178 C22C rev. 0 the adv7177/adv7178 acts as a standard slave device on the bus. the data on the sdata pin is 8 bits long, supporting the 7-bit addresses, plus the r/ w bit. the adv7178 has 36 subaddresses and the adv7177 has 31 subaddresses to enable access to the internal registers. it therefore interprets the first byte as the device address and the second byte as the starting subaddress. the subaddresses auto increment allows data to be written to or read from the starting subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. there is one excep- tion. the subcarrier frequency registers should be updated in sequence, starting with subcarrier frequency register 0. the auto increment function should then be used to increment and access subcarrier frequency registers 1, 2 and 3. the subcarrier frequency registers should not be accessed independently. stop and start conditions can be detected at any stage during the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. during a given sclock high pe- riod, the user should issue only one start condition, one stop condition or a single stop condition followed by a single start condition. if an invalid subaddress is issued by the user, the adv7177/adv7178 will not issue an acknowledge and will return to the idle condition. if, in auto-increment mode, the user exceeds the highest subaddress, the following action will be taken: 1. in read mode, the highest subaddress register contents will continue to be output until the master device issues a no- acknowledge. this indicates the end of a read. a no- acknowledge condition is where the sdata line is not pulled low on the ninth pulse. 2. in write mode, the data for the invalid byte will not be loaded into any subaddress register, a no-acknowledge will be issued by the adv7177/adv7178 and the part will re- turn to the idle condition. figure 29 illustrates an example of data transfer for a read se- quence and the start and stop conditions. 1-7 8 9 1-7 8 9 1-7 8 9 p s start addr r/ w ack subaddress ack data ack stop sdata sclock figure 29. bus data transfer figure 30 shows bus write and read sequences. register accesses the mpu can write to or read from all of the adv7177/ adv7178 registers except the subaddress register, which is a write-only register. the subaddress register determines which register the next read or write operation accesses. all communi- cations with the part through the bus start with an access to the subaddress register. a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register, including subaddress register, mode registers, subcarrier freque ncy registers, subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers and ntsc pedestal control registers in terms of its configuration. data a(s) s slave addr a(s) sub addr a(s) lsb = 0 lsb = 1 data a(s) p s slave addr a(s) sub addr a(s) s slave addr a(s) data a(m) a (m ) data p write sequence read sequence a (s) = no-acknowledge by slave a (m) = no-acknowledge by master a(s) = acknowledge by slave a(m) = acknowledge by master s = start bit p = stop bit figure 30. write and read sequences adv7177/adv7178 C23C rev. 0 subaddress register (sr7Csr0) the communications register is an 8-bit write-only register. after the part has been accessed over the bus, and a read/write operation is selected, the subaddress is set up. the subaddress register determines to/from which register the operation takes place. figure 31 shows the various operations under the control of the subaddress register. zero should always be written to sr7Csr6. register select (sr5Csr0) these bits are set up to point to the required starting address. mode register 0 mr0 (mr07Cmr00) (address [sr4Csr0] = 00h) figure 32 shows the various operations under the control of mode register 0. this register can be read from as well as written to. mr0 bit description encode mode control (mr01Cmr00) these bits are used to set up the encode mode. the adv7177/ adv7178 can be set up to output ntsc, pal (b, d, g, h, i) and pal (m) standard video. pedestal control (mr02) this bit specifies whether a pedestal is to be generated on the ntsc composite video signal. this bit is invalid if the adv71 77/adv7178 is configured in pal mode. luminance filter control (mr04Cmr03) the luminance filters are divided into two sets (ntsc/pal) of four filters, low-pass a, low-pass b, notch and extended. when pal is selected, bits mr03 and mr04 select one of four pal luminance filters; likewise, when ntsc is selected, bits mr03 and mr04 select one of four ntsc luminance filters. the filters are illustrated in figures 7 to 13. sr4 sr3 sr2 sr1 sr0 sr7 sr6 sr5 sr5 sr4 sr3 sr2 sr1 sr0 adv7178 subaddress register 0 0 0 0 0 0 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 subcarrier freq register 0 0 0 0 0 1 1 subcarrier freq register 1 0 0 0 1 0 0 subcarrier freq register 2 0 0 0 1 0 1 subcarrier freq register 3 0 0 0 1 1 0 subcarrier phase register 0 0 0 1 1 1 timing register 0 0 0 1 0 0 0 closed captioning extended data C byte 0 0 0 1 0 0 1 closed captioning extended data C byte 1 0 0 1 0 1 0 closed captioning data C byte 0 0 0 1 0 1 1 closed captioning data C byte 1 0 0 1 1 0 0 timing register 1 0 0 1 1 0 1 mode register 2 0 0 1 1 1 0 ntsc pedestal control reg 0 (field 1/3) 0 0 1 1 1 1 ntsc pedestal control reg 1 (field 1/3) 0 1 0 0 0 0 ntsc pedestal control reg 2 (field 2/4) 0 1 0 0 0 1 ntsc pedestal control reg 3 (field 2/4) 0 1 0 0 1 0 mode register 3 0 1 0 0 1 1 macrovision register ? ? ? ? ? ? " " ? ? ? ? ? ? " " 1 0 0 0 1 1 macrovision register zero should be written to these bits sr7Csr6 (00) sr5 sr4 sr3 sr2 sr1 sr0 adv7177 subaddress register 0 0 0 0 0 0 mode register 0 0 0 0 0 0 1 mode register 1 0 0 0 0 1 0 subcarrier freq register 0 0 0 0 0 1 1 subcarrier freq register 1 0 0 0 1 0 0 subcarrier freq register 2 0 0 0 1 0 1 subcarrier freq register 3 0 0 0 1 1 0 subcarrier phase register 0 0 0 1 1 1 timing register 0 0 0 1 0 0 0 closed captioning extended data C byte 0 0 0 1 0 0 1 closed captioning extended data C byte 1 0 0 1 0 1 0 closed captioning data C byte 0 0 0 1 0 1 1 closed captioning data C byte 1 0 0 1 1 0 0 timing register 1 0 0 1 1 0 1 mode register 2 0 0 1 1 1 0 ntsc pedestal control reg 0 (field 1/3) 0 0 1 1 1 1 ntsc pedestal control reg 1 (field 1/3) 0 1 0 0 0 0 ntsc pedestal control reg 2 (field 2/4) 0 1 0 0 0 1 ntsc pedestal control reg 3 (field 2/4) 0 1 0 0 1 0 mode register 3 0 1 0 0 1 1 osd register ? ? ?? ??" " ? ? ?? ??" " 0 1 1 1 1 0 osd register figure 31. subaddress register mr01 mr00 mr07 mr02 mr04 mr03 mr05 mr06 output video standard selection 0 0 ntsc 0 1 pal (b, d, g, h, i) 1 0 pal (m) 1 1 reserved mr01 mr00 mr07 (0) zero should be written to this bit output select 0 yc output 1 rgb/yuv output mr06 filter select 0 0 low-pass filter (a) 0 1 notch filter 1 0 extended mode 1 1 low-pass filter (b) mr04 mr03 rgb sync 0 disable 1 enable mr05 pedestal control 0 pedestal off 1 pedestal on mr02 figure 32. mode register 0 (mr0) adv7177/adv7178 C24C rev. 0 mr11 mr10 mr17 mr12 mr13 mr15 mr16 mr14 closed captioning field selection 0 0 no data out 0 1 odd field only 1 0 even field only 1 1 data out (both fields) mr12 mr11 mr16 (1) luma dac control mr14 chroma dac control mr13 composite dac control mr15 interlace control 0 interlaced 1 noninterlaced mr10 color bar control 0 disable 1 enable mr17 0 normal 1 power-down 0 normal 1 power-down 0 normal 1 power-down one should be written to this bit figure 33. mode register 1 (mr1) rgb sync (mr05) this bit is used to set up the rgb outputs with the sync infor- mation encoded on all rgb outputs. output control (mr06) this bit specifies if the part is in composite video or rgb/yuv mode. please note that the main composite signal is still avail- able in rgb/yuv mode. mode register 1 mr1 (mr17Cmr10) (address (sr4Csr0) = 01h) figure 33 shows the various operations under the control of mode register 1. this register can be read from as well as written to. mr1 bit description interlaced mode control (mr10) this bit is used to set up the output to interlaced or noninter- laced mode. this mode is only relevant when the part is in composite video mode. closed captioning field control (mr12Cmr11) these bits control the fields on which closed captioning data is displayed; closed captioning information can be displayed on an odd field, even field or both fields. dac control (mr15Cmr13) these bits can be used to power down the dacs. this can be used to reduce the power consumption of the adv7177/ adv7178 if any of the dacs are not required in the application. color bar control (mr17) this bit can be used to generate and output an internal color bar test pattern. the color bar configuration is 75/7.5/75/7.5 for ntsc and 100/0/75/0 for pal. it is important to note that when color bars are enabled the adv7177/adv7178 is config- ured in a master timing mode as per the one selected by bits tr01 and tr02. subcarrier frequency register 3-0 (fsc3Cfsc0) (address [sr4Csr0] = 05hC02h) these 8-bit-wide registers are used to set up the subcarrier frequency. the value of these registers are calculated by using the following equation: subcarrier frequency register = 2 32 1 f clk f scf i.e.: ntsc mode, f clk = 27 mhz, f scf = 3.5795454 mhz subcarrier frequency value = 21 27 10 3 5795454 10 32 6 6 . = 21f07c16 hex figure 34 shows how the frequency is set up by the four registers. subcarrier frequency reg 3 subcarrier frequency reg 2 subcarrier frequency reg 1 subcarrier frequency reg 0 fsc30 fsc29 fsc27 fsc25 fsc28 fsc24 fsc31 fsc26 fsc22 fsc21 fsc19 fsc17 fsc20 fsc16 fsc23 fsc18 fsc14 fsc13 fsc11 fsc9 fsc12 fsc8 fsc15 fsc10 fsc6 fsc5 fsc3 fsc1 fsc4 fsc0 fsc7 fsc2 figure 34. subcarrier frequency register subcarrier phase register (fp7Cfp0) (address [sr4Csr0] = 06h) this 8-bit-wide register is used to set up the subcarrier phase. each bit represents 1.41 degrees. timing register 0 (tr07Ctr00) (address [sr4Csr0] = 07h) figure 35 shows the various operations under the control of timing register 0. this register can be read from as well as written to. this register can be used to adjust the width and position of the master mode timing signals. tr0 bit description master/slave control (tr00) this bit controls whether the adv7177/adv7178 is in master or slave mode. this register can be used to adjust the width and position of the master timing signals. timing mode control (tr02Ctr01) these bits control the timing mode of the adv7177/adv7178. these modes are described in the timing and control section of the data sheet. blank control (tr03) this bit controls whether the blank input is used when the part is in slave mode adv7177/adv7178 C25C rev. 0 tr01 tr00 tr07 tr02 tr03 tr05 tr06 tr04 timing register reset tr07 black input control 0 enable 1 disable tr03 pixel port control 0 8-bit 1 16-bit tr06 master/slave control 0 slave timing 1 master timing tr00 luma delay 0 0 0ns delay 0 1 74ns delay 1 0 148ns delay 1 1 222ns delay tr05 tr04 timing mode selection 0 0 mode 0 0 1 mode 1 1 0 mode 2 1 1 mode 3 tr02 tr01 figure 35. timing register 0 tr11 tr10 tr17 tr12 tr13 tr15 tr16 tr14 hsync width 0 0 1 x t pclk 0 1 4 x t pclk 1 0 16 x t pclk 1 1 128 x t pclk tr11 tr10 t a hsync to field rising edge delay (mode 1 only) x0t b x1t b + 32 m s tr15 tr14 t c hsync to pixel data adjustment tr17 tr16 0 0 0 x t pclk 0 1 1 x t pclk 1 0 2 x t pclk 1 1 3 x t pclk hsync to field/ vsync delay tr13 tr12 0 0 0 x t pclk 0 1 4 x t pclk 1 0 8 x t pclk 1 1 16 x t pclk vsync width (mode 2 only) tr15 tr14 0 0 1 x t pclk 0 1 4 x t pclk 1 0 16 x t pclk 1 1 128 x t pclk line 313 line 314 line 1 t b timing mode 1 (master/pal) hsync field/ vsync t a t c t b figure 38. timing register 1 luma delay control (tr05Ctr04) these bits control the addition of a luminance delay. each bit represents a delay of 74 ns. pixel port select (tr06) this bit is used to set the pixel port to accept 8-bit or 16-bit data. if an 8-bit input is selected the data will be set up on pins p7Cp0. timing register reset (tr07) toggling tr07 from low to high and low again resets the inter- nal timing counters. this bit should be toggled after power-up, reset or changing to a new timing mode. closed captioning even field data register 1C0 (ced15Cced00) (address [sr4Csr0] = 09C08h) these 8-bit-wide registers are used to set up the closed captioning extended data bytes on even fields. figure 36 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ced6 ced5 ced3 ced1 ced4 ced2 ced0 ced7 ced14 ced13 ced11 ced9 ced12 ced10 ced8 ced15 figure 36. closed captioning extended data register closed captioning odd field data register 1C0 (ccd15Cccd00) (subaddress [sr4Csr0] = 0bC0ah) these 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. figure 37 shows how the high and low bytes are set up in the registers. byte 1 byte 0 ccd6 ccd5 ccd3 ccd1 ccd4 ccd2 ccd0 ccd7 ccd14 ccd13 ccd11 ccd9 ccd12 ccd10 ccd8 ccd15 figure 37. closed captioning data register adv7177/adv7178 C26C rev. 0 timing register 1 (tr17Ctr10) (address [sr4Csr0] = 0ch) timing register 1 is an 8-bit-wide register. figure 38 shows the various operations under the control of timing register 1. this register can be read from as well as written to. this register can be used to adjust the width and position of the master mode timing signals. tr1 bit description hsync width (tr11Ctr10) these bits adjust the hsync pulsewidth. hsync to vsync /field delay control (tr13Ctr12) these bits adjust the position of the hsync output relative to the field/ vsync output. hsync to field delay control (tr15Ctr14) when the adv7177/adv7178 is in timing mode 1, these bits adjust the position of the hsync output relative to the field output rising edge. vsync width (tr15Ctr14) when the adv7177/adv7178 is in timing mode 2, these bits adjust the vsync pulsewidth. hsync to pixel data adjust (tr17Ctr16) this enables the hsync to be adjusted with respect to the pixel data. this allows the cr and cb components to be swapped. this adjustment is available in both master and slave timing modes. mode register 2 mr2 (mr27Cmr20) (address [sr4-sr0] = 0dh) mode register 2 is an 8-bit-wide register. figure 39 shows the various operations under the control of mode register 2. this r egister can be read from as well as written to. mr2 bit description square pixel mode control (mr20) this bit is used to set up square pixel mode. this is available in slave mode only. for ntsc, a 24.54 mhz clock must be sup- plied. for pal, a 29.5 mhz clock must be supplied. active video line control (mr23) this bit switches between two active video line durations. a zero selects itu-r bt.470 (720 pixels pal/ntsc) and a one selects itu-r/smpte analog standard for active video dura- tion (710 pixels ntsc 702 pixels pal). chrominance control (mr24) this bit enables the color information to be switched on and off the video output. burst control (mr25) this bit enables the burst information to be switched on and off the video output. rgb/yuv control (mr26) this bit enables the output from the rgb dacs to be set to yuv output video standard. bit mr06 of mode register 0 must be set to logic level 1 before mr26 is set. table ii. dac output configuration matrix mr06 mr26 dac a dac b dac c 0 0 cvbs y c 0 1 cvbs y c 10bsr 11uyv cvbs: composite video baseband signal y: luminance component signal (for yuv or y/c mode) c: chrominance signal (for y/c mode) u: chrominance component signal (for yuv mode) v: chrominance component signal (for yuv mode) r: red component video (for rgb mode) g: green component video (for rgb mode) b: blue component video (for rgb mode) low power control (mr27) this bit enables the lower power mode of the adv7177/ adv7178. this will reduce dac current by 50%. mr21 mr27 mr22 mr23 mr26 mr25 mr24 mr20 chrominance control 0 enable color 1 disable color mr24 rgb/yuv control 0 rgb output 1 yuv output mr26 square pixel control 0 disable 1 enable mr20 burst control 0 enable burst 1 disable burst mr25 ccir624/ccir601 control 0 ccir624 output 1 ccir601 output mr23 mr22Cmr21 (00) zero should be written to these bits low power mode 0 disable 1 enable mr27 figure 39. mode register 2 adv7177/adv7178 C27C rev. 0 ntsc pedestal registers 3C0 (pce15C0, pco15C0) (subaddress [sr4Csr0] = 11C0eh) these 8-bit-wide registers are used to set up the ntsc pedestal on a line-by-line basis in the vertical blanking interval for both odd and even fields. figure 40 show the four control registers. a logic 1 in any of the bits of these registers has the effect of turning the pedestal off on the equivalent line when used in ntsc. field 1/3 pco6 pco5 pco3 pco1 pco4 pco2 pco0 pco7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pco14 pco13 pco11 pco9 pco12 pco10 pco8 pco15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 1/3 field 2/4 pce6 pce5 pce3 pce1 pce4 pce2 pce0 pce7 line 17 line 16 line 15 line 14 line 13 line 12 line 11 line 10 pce14 pce13 pce11 pce9 pce12 pce10 pce8 pce15 line 25 line 24 line 23 line 22 line 21 line 20 line 19 line 18 field 2/4 figure 40. pedestal control registers mode register 3 mr3 (mr37Cmr30) (address [sr4Csr0] = 12h) mode register 3 is an 8-bit-wide register. figure 41 shows the various operations under the control of mode register 3. mr3 bit description revision code (mr30) this bit is read only and indicates the revision of the device. vbi pass-through control (mr31) this bit determines whether or not data in the vertical blanking interval (vbi) is output to the analog outputs or blanked. clock output select (mr33Cmr32) these bits control the synchronous clock output signal. the clock can be 27 mhz, 13.5 mhz or disabled, depending on the values of these bits. osd enable (mr35) a logic one in mr35 will enable the osd function on the adv7177. reserved (mr36) these bits are reserved. input default color (mr36) this bit determines the default output color from the dacs for zero input data (or disconnected). a logical 0 means that the color corresponding to 00000000 will be displayed. a logical 1 forces the output color to black for 00000000 input video data. osd register 0C11 (address [sr4Csr0] = 12hC1dh) there are 12 osd registers as shown in figure 42. there are four bits for each y, cb and cr value, there are four zero added to give the complete byte for each value loaded interna lly. (y0 = [y0 3 , y0 2 , y0 1 , y0 0 , 0, 0, 0, 0], cb = [cb 3 , cb 2 , cb 1 , cb 0 , 0, 0, 0, 0,], cr = [cr 3 , cr 2 , cr 1 , cr 0 , 0, 0, 0, 0].) mr31 mr30 mr37 mr32 mr34 mr33 mr35 mr36 zero should be written to this bit mr34 input default color 0 input color 1 black mr36 vbi passthrough 0 disable 1 enable mr31 clock control 0 0 clock output off 0 1 13.5mhz output 1 0 27mhz output 1 1 clock output off mr33-32 mr30 rev code (read only) zero should be written to this bit mr37 osd enable 0 disable 1 enable mr35 figure 41. mode register 3 y0 cr0 cb0 y1 cr1 cb1 cr7 cb7 osd reg 0 osd reg 1 osd reg 2 osd reg 11 figure 42. osd registers adv7177/adv7178 C28C rev. 0 the adv7177/adv7178 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is imperative that these same design and layout techniques be applied to the system level design so that high speed, accurate performance is achieved. the recommended analog circuit layout shows the analog interface between the device and monitor. the layout should be optimized for lowest noise on the adv7177/ adv7178 power and ground lines by shielding the digital inputs and providing good decoupling. the lead length between groups of v aa and gnd pins should by minimized to minimize induc- tive ringing. ground planes the ground plane should encompass all adv7177/adv7178 ground pins, voltage reference circuitry, power supply bypass circuitry for the adv7177/adv7178, the analog output traces, and all the digital signal traces lea ding up to the adv7177/ adv7178. the ground plane is the boards common ground plane. this should be as substantial as possible to maximize heat spreading and power dissipation on the board. power planes the adv7177/adv7178 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (v aa ). this power plane should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the adv7177/adv7178. the metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7177/adv7178 power pins and voltage refer- ence circuitry. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane unless they can be arranged so that the plane-to-plane noise is common-mode. appendix 1 board design and layout considerations supply decoupling for optimum performance, bypass capacitors should be in- stalled using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. best performance is obtained with 0.1 m f ceramic capacitor decoupling. each group of v aa pins on the adv7177/adv7178 must have at least one 0.1 m f decoupling capacitor to gnd. these capacitors should be placed as close to the device as possible. it is important to note that while the adv7177/adv7178 con- tains circuitry to reject power supply noise, this rejection de- creases with frequency. if a high frequency switching power supply is used, the designer should pay close attention to reduc- ing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane. digital signal interconnect the digital inputs to the adv7177/adv7178 should be iso- lated as much as possible from the analog outputs and other analog circuitry. also, these input signals should not overlay the analog power plane. due to the high clock rates involved, long clock lines to the adv7177/adv7178 should be avoided to reduce noise pickup. any active termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not the analog power plane. analog signal interconnect the adv7177/adv7178 should be located as close to the output connectors as possible to minimize noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane, not the analog power plane, to maximize the high frequency power supply rejection. digital inputs, especially pixel data inputs and clocking signals, should never overlay any of the analog signal circuitry and should be kept as far away as possible. for best performance, the outputs should each have a 75 w load resistor connected to gnd. these resistors should be placed as close as possible to the adv7177/adv7178 as to minimize reflections. the adv7177/adv7178 should have no inputs left floating. any inputs that are not required should be tied to ground. adv7177/adv7178 C29C rev. 0 0.1 m f +5v (v aa ) 37C41, 3C10, 12C14 p15Cp0 32 5k v +5v (v cc ) 150 v 24 5k v +5v (v cc ) mpu bus 44 22 15 17 16 19, 21 29, 42 18 23 33 1, 20, 28, 30 0.1 m f 0.01 m f power supply decoupling for each power supply group 10 m f 33 m f gnd l1 (ferrite bead) +5v v aa +5v (v aa ) (v cc ) 10k v +5v (v aa ) 27mhz or 13.5mhz clock output 25 34 gnd alsb hsync field/ vsync blank reset clock r set sdata sclock luma v ref comp 75 v 75 v 75 v 35 adv7177/ adv7178 unused inputs should be grounded chroma 100 v 100 v 4k v +5v (v aa ) 100nf reset 0.1 m f +5v (v aa ) 11 36 osd_en osd_0 osd_1 osd_2 osd inputs 43 clock 2 clock/2 33pf 27mhz xtal 33pf 26 27 pixel data 31 cvbs figure 43. recommended analog circuit layout adv7177/adv7178 C30C rev. 0 the adv7177/adv7178 supports closed captioning, conform- ing to the standard television synchronizing waveform for color transmission. closed captioning is transmitted during the blanked active line time of line 21 of the odd fields and line 284 of even fields. closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. after the clock run-in signal, the blanking level is held for two d ata bits and is followed by a logic level 1 start bit. 16 b its of data follow the start bit. these consist of two 8-bit bytes, seven data bits and one odd parity bit. the data for these bytes is stored in closed captioning data registers 0 and 1. the adv7177/adv7178 also supports the extended closed captioning operation, which is active during even fields, and is encoded on scan line 284. the data for this operation is stored in closed captioning extended data registers 0 and 1. all clock run-in signals and timing to support closed captioning on lines 21 and 284 are generated automatically by the adv7177/ adv7178. all pixels inputs are ignored during lines 21 and 284. appendix 2 closed captioning fcc code of federal regulations (cfr) 47 section 15.119 and eia608 describe the closed captioning information for lines 21 and 284. the adv7177/adv7178 uses a single buffering method. this means that the closed captioning buffer is only one byte deep, therefore there will be no frame delay in outputting the closed captioning data unlike other 2-byte deep buffering systems. the data must be loaded at least one line before (line 20 or line 283) it is outputted on line 21 and line 284. a typical imple- mentation of this method is to use vsync to interrupt a micro- processor, which will in turn load the new data (two bytes) every field. if no new data is required for transmission you must insert zeros in both the data registers; this is called nulling. it is also important to load control codes, all of which are double bytes on line 21, or a tv will not recognize them. if you have a message like hello world, which has an odd num- ber of characters, it is important to pad it out to an even number to get end of caption 2-byte control code to land in the same field. 12.91 m s s t a r t p a r i t y p a r i t y d0Cd6 d0Cd6 10.003 m s 33.764 m s 50 ire 40 ire frequency = f sc = 3.579545mhz amplitude = 40 ire reference color burst (9 cycles) 7 cycles of 0.5035 mhz (clock run-in) 10.5 6 0.25 m s two 7-bit + parity ascii characters (data) 27.382 m s byte 0 byte 1 figure 44. closed captioning waveform (ntsc) adv7177/adv7178 C31C rev. 0 appendix 3 ntsc waveforms (with pedestal) 130.8 ire 100 ire 7.5 ire 0 ire C40 ire peak composite ref white black level sync level blank level 714.2mv 1268.1mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 45. ntsc composite video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 714.2mv 1048.4mv 387.6mv 334.2mv 48.3mv figure 46. ntsc luma video levels 650mv 232.2mv 1067.7mv 0mv peak chroma blank/black level 286mv (pk-pk) 835mv (pk-pk) peak chroma figure 47. ntsc chroma video levels 100 ire 7.5 ire 0 ire C40 ire ref white black level sync level blank level 720.8mv 1052.2mv 387.5mv 331.4mv 45.9mv figure 48. ntsc rgb video levels adv7177/adv7178 C32C rev. 0 ntsc waveforms (without pedestal) 130.8 ire 100 ire 0 ire C40 ire peak composite ref white sync level blank/black level 714.2mv 1289.8mv 1052.2mv 338mv 52.1mv figure 49. ntsc composite video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 714.2mv 1052.2mv 338mv 52.1mv figure 50. ntsc luma video levels 650mv 198.4mv 1101.6mv 0mv peak chroma blank/black level 307mv (pk-pk) 903.2mv (pk-pk) peak chroma figure 51. ntsc chroma video levels 100 ire 0 ire C40 ire ref white sync level blank/black level 715.7mv 1052.2mv 336.5mv 51mv figure 52. ntsc rgb video levels adv7177/adv7178 C33C rev. 0 pal waveforms 1284.2mv 1047.1mv 350.7mv 50.8mv peak composite ref white sync level blank/black level 696.4mv figure 53. pal composite video levels 1047mv 350.7mv 50.8mv ref white sync level blank/black level 696.4mv figure 54. pal luma video levels 650mv 207.5mv 1092.5mv 0mv peak chroma blank/black level 300mv (pk-pk) 885mv (pk-pk) peak chroma figure 55. pal chroma video levels 1050.2mv 351.8mv 51mv ref white sync level blank/black level 698.4mv figure 56. pal rgb video levels adv7177/adv7178 C34C rev. 0 betacam level 0mv 171mv 334mv 505mv 0mv 2 171mv 2 334mv 2 505mv white yellow cyan green magenta red blue black figure 57. ntsc 100% color bars no pedestal u levels betacam level 0mv 158mv 309mv 467mv 0mv C158mv C309mv C467mv white yellow cyan green magenta red blue black figure 58. ntsc 100% color bars with pedestal u levels smpte level 0mv 118mv 232mv 350mv 0mv C118mv C232mv C350mv white yellow cyan green magenta red blue black figure 59. pal 1005 color bars u levels uv waveforms betacam level 0mv 82mv 423mv 505mv 0mv C82mv C505mv C423mv white yellow cyan green magenta red blue black figure 60. ntsc 100% color bars no pedestal v levels betacam level 0mv 76mv 391mv 467mv 0mv C76mv C467mv C391mv white yellow cyan green magenta red blue black figure 61. ntsc 100% color bars with pedestal v levels smpte level 0mv 57mv 293mv 350mv 0mv C57mv C350mv C293mv white yellow cyan green magenta red blue black figure 62. pal 100% color bars v levels adv7177/adv7178 C35C rev. 0 appendix 4 register values the adv7177/adv7178 registers can be set depending on the user standard required. the following examples give the various register formats for several video standards. in each case the output is set to composite o/p with all dacs powered up and with the blank input control disabled. addi- tionally, the burst and color information are enabled on the output and the internal color bar generator is switched off. in the examples shown, the timing mode is set to mode 0 in slave format. tr02Ctr00 of the timing register 0 control the tim- ing modes. for a detailed explanation of each bit in the com- mand registers, please turn to the register programming section of the data sheet. tr07 should be toggled after setting up a new timing mode. timing register 1 provides additional control over the position and duration of the timing signals. in the examples, this register is programmed in default mode. ntsc (f sc = 3.5795454 mhz) address data 00hex mode register 0 04hex 01hex mode register 1 00hex 02hex subcarrier frequency register 0 16hex 03hex subcarrier frequency register 1 7chex 04hex subcarrier frequency register 2 f0hex 05hex subcarrier frequency register 3 21hex 06hex subcarrier phase register 00hex 07hex timing register 0 08hex 08hex closed captioning ext register 0 00hex 09hex closed captioning ext register 1 00hex 0ahex closed captioning register 0 00hex 0bhex closed captioning register 1 00hex 0chex timing register 1 00hex 0dhex mode register 2 80hex 0ehex pedestal control register 0 00hex 0fhex pedestal control register 1 00hex 10hex pedestal control register 2 00hex 11hex pedestal control register 3 00hex 12hex mode register 3 00hex pal b, d, g, h, i (f sc = 4.43361875 mhz) address data 00hex mode register 0 01hex 01hex mode register 1 00hex 02hex subcarrier frequency register 0 cbhex 03hex subcarrier frequency register 1 8ahex 04hex subcarrier frequency register 2 09hex 05hex subcarrier frequency register 3 2ahex 06hex subcarrier phase register 00hex 07hex timing register 0 08hex 08hex closed captioning ext register 0 00hex 09hex closed captioning ext register 1 00hex 0ahex closed captioning register 0 00hex 0bhex closed captioning register 1 00hex 0chex timing register 1 00hex 0dhex mode register 2 80hex address data 0ehex pedestal control register 0 00hex 0fhex pedestal control register 1 00hex 10hex pedestal control register 2 00hex 11hex pedestal control register 3 00hex 12hex mode register 3 00hex pal m (f sc = 3.57561149 mhz) address data 00hex mode register 0 06hex 01hex mode register 1 00hex 02hex subcarrier frequency register 0 a3hex 03hex subcarrier frequency register 1 efhex 04hex subcarrier frequency register 2 e6hex 05hex subcarrier frequency register 3 21hex 06hex subcarrier phase register 00hex 07hex timing register 0 08hex 08hex closed captioning ext register 0 00hex 09hex closed captioning ext register 1 00hex 0ahex closed captioning register 0 00hex 0bhex closed captioning register 1 00hex 0chex timing register 1 00hex 0dhex mode register 2 80hex 0ehex pedestal control register 0 00hex 0fhex pedestal control register 1 00hex 10hex pedestal control register 2 00hex 11hex pedestal control register 3 00hex 12hex mode register 3 00hex adv7177/adv7178 C36C rev. 0 if an output filter is required for the cvbs, y, uv, chroma and rgb outputs of the adv7177/adv7178, the following filter in figure 63 can be used. plots of the filter characteristics are shown in figures 64, 65 and 66. an output filter is not required if the outputs of the adv7177/adv7178 are connected to an analog monitor or an analog tv; however, if the output signals are applied to a system where sampling is used (e.g., digital tv), a filter is required to prevent aliasing. l 1 m h l 2.7 m h l 0.68 m h r 75 v r 75 v c 470pf c 330pf c 56pf in out figure 63. output filter frequency C hz 10k 100m 100k decibels 1m 10m 0 C5 C70 C10 C15 C20 C25 C30 C35 C40 C45 C50 C55 C60 C65 v db C op figure 64. output filter plot appendix 5 optional output filter frequency C mhz 1 100 decibels 10 0 C35 C5 C10 C15 C20 C25 C30 v db C op figure 65. output filter close up frequency C mhz 110 decibels 2 0.0 C3.5 C0.5 C1.0 C1.5 C2.0 C2.5 C3.0 v db C op 468 C4.5 C4.0 figure 66. output filter plot close up adv7177/adv7178 C37C rev. 0 for external buffering of the adv7177/adv7178 dac out- puts, the configuration in figure 67 is recommended. this configuration shows the dac outputs running at half (18 ma) their full current (34.7 ma) capability. this will allow the adv7177/adv7178 to dissipate less power, the analog current is reduced by 50% with a r set of 300 w and a r load of 75 w . this mode is recomm ended for 3.3 volt operation as optimum perfor- mance is obtained from the dac ou tputs at 18 ma with a v aa of 3.3 volts. this buffer also adds extra isolation on the video out- appendix 6 optional dac buffering puts, see buffer circuit in figure 68. when calculating absolute output full current and voltage, use the following equation: v out = i out r load i out = v ref k () r set k = 4.2146 constant , v ref = 1.235 v adv7177/adv7178 v ref digital core pixel port 300 v r set 75 v 75 v 75 v v aa output buffer dac a output buffer output buffer dac c dac b figure 67. output dac buffering configuration 2n2907 75 v 75 v output to tv/monitor 36 v input v cc figure 68. recommended output dac buffer adv7177/adv7178 C38C rev. 0 outline dimensions dimensions shown in inches and (mm). plastic quad flatpack (s-44) 0.548 (13.925) 0.546 (13.875) top view (pins down) 1 33 34 44 11 12 23 22 0.033 (0.84) 0.029 (0.74) 0.398 (10.11) 0.390 (9.91) 0.016 (0.41) 0.012 (0.30) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.040 (1.02) 0.032 (0.81) seating plane 0.096 (2.44) max 0.037 (0.94) 0.025 (0.64) 8 8 0.8 8 printed in u.s.a. c3314C2.5C8/98 |
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